Autoupdate FIT image : wrong dtb load address
Hello folks,
I'm trying to generate a autoupdate FIT-image.
I'm using u-boot 2010.12 / dtc 1.2.0. / Kernel 2.6.36.6 ;
Its work fine, but the load address of fdt-part is wrong.
Does anyone know what the problem is?
-- 8
Auto-update from TFTP: trying update file 'mxa.itb'
Using FEC device
TFTP from server 192.168.1.10; our IP address is 192.168.1.58
Filename 'mxa.itb'.
Load address: 0x10
Loading: #
#
#
done
Bytes transferred = 2210382 (21ba4e hex)
Processing update 'kernel@0' :sha1+
Erasing 0xff00 - 0xff13
.. done
Erased 10 sectors
Copying to flash...done
Processing update 'rootfs@0' :sha1+
Erasing 0xff20 - 0xff2b
.. done
Erased 6 sectors
Copying to flash...done
Processing update 'fpga@0' :sha1+
Erasing 0xfff6 - 0xfff9
.. done
Erased 2 sectors
Copying to flash...done
Processing update 'fdt@0' :sha1+
Error: end address (0x3c30c665) not in flash! - ??
Error: can't flash update, aborting
Hit any key to stop autoboot: 0
-- 8
Thanks in advance.
Andreas Friesen
PS : Hier is my its-source file and mkimage output :
-- 8
/dts-v1/;
/ {
description = Automatic Software Update: kernel, rootfs, FDT, FPGA ;
timestamp = 1300774787;
#address-cells = 1;
images {
kernel@0 {
description = linux kernel image;
data = /incbin/(./uImage);
arch = ppc;
type = firmware;
load = 0xFF00;
compression = none;
hash@1 {
algo = sha1;
};
};
rootfs@0 {
description = RootFS image;
data = /incbin/(./rootfs.img);
arch = ppc;
type = firmware;
load = 0xFF20;
compression = none;
hash@1 {
algo = sha1;
};
};
fpga@0 {
description = FPGA Firmware;
data = /incbin/(./fpga.bin);
arch = ppc;
compression = none;
type = firmware;
load = 0xFFF6;
hash@1 {
algo = sha1;
};
};
fdt@0 {
description = FDT binary;
data = /incbin/(./mxa.dtb);
arch = ppc;
compression = none;
type = firmware;
load = 0xFFFE; ---
!!
hash@1 {
algo = sha1;
};
};
};
};
8--
$ mkimage -f mxa_autoupdate.its mxa.itb
Registered Kirkwood Boot Image support
Registered Freescale i.MX 51 Boot Image support
Registered FIT Image support
Registered Default Image support
FIT format handling
Trying to execute dtc -I dts -O dtb -p 500 mxa_autoupdate.its
mxa_autoupdate.itb.tmp
DTC: dts-dtb on file mxa_autoupdate.its
Added timestamp successfully
FIT description: Automatic Software Update: kernel, rootfs, FDT, FPGA
Created: Tue Mar 22 07:19:47 2011
Image 0 (kernel@0)
Description: linux kernel image
Type: Firmware
Compression: uncompressed
Data Size:1222870 Bytes = 1194.21 kB = 1.17 MB
Architecture: PowerPC
Load Address: 0xff00
Hash node:'hash@1'
Hash algo:sha1
Hash value: e619b777d20246fe5b4f5b6ed2ad6ebe44c54fdf
Hash len: 20
Image 1 (rootfs@0)
Description: RootFS image
Type: Firmware
Compression: uncompressed
Data Size:753664 Bytes = 736.00 kB = 0.72 MB
Architecture: PowerPC
Load Address: 0xff20
Hash node:'hash@1'
Hash algo:sha1
Hash value: eaf7b46387c0a912b81cb1cd38f8af616ed746a6
Hash len: 20
Image 2 (fpga@0)
Description: FPGA Firmware
Type: Firmware
Compression: uncompressed
Data Size:212392 Bytes = 207.41 kB = 0.20 MB
Architecture: PowerPC
Load Address: 0xfff6
Hash node:'hash@1'
Hash algo:sha1
Hash value: 65a54dc977a7287c499816108bc18eb19989aa0e
Hash len: 20
Image 3 (fdt@0)
Description: FDT binary
Type: Firmware
Compression: uncompressed
Data Size:2 Bytes = 19.53 kB = 0.02 MB
Architecture: PowerPC
Load Address: 0x3c307846 -
[PATCH] hvc_console: Don't access hvc_task if not initialised
hvc_open() can be called without having any backing device. This
results in a call to hvc_kick() which calls wake_up_process on a NULL
pointer. Ensure hvc is initialised by checking for a non-NULL hvc_task
before waking up the hvc thread.
This was found by an autotest run for virtio_console without having a
console backend.
CC: sta...@kernel.org
Signed-off-by: Amit Shah amit.s...@redhat.com
---
drivers/tty/hvc/hvc_console.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
index e9cba13..b2cb5cc 100644
--- a/drivers/tty/hvc/hvc_console.c
+++ b/drivers/tty/hvc/hvc_console.c
@@ -286,6 +286,9 @@ EXPORT_SYMBOL_GPL(hvc_instantiate);
/* Wake the sleeping khvcd */
void hvc_kick(void)
{
+ if (!hvc_task)
+ return;
+
hvc_kicked = 1;
wake_up_process(hvc_task);
}
--
1.7.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: vmsplice bad address
On Monday 07 March 2011 10:35:44 Benjamin Herrenschmidt wrote: I'm not completely surprised ... I wouldn't expect vmsplice to work on /dev/mem ... No struct page backing the memory for example. So how would that work to do zero-copy ? Somebody gave me a hint of marking the memory regions as iomem, do a ioremap then mmap and vmsplice but that's a mouthful... -- Guillaume Dargaud http://www.gdargaud.net/ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: add clock_adjtime for powerpc
This patch adds the clock_adjtime system call to the powerpc architecture. The call was introduced in f1f1d5ebd10ffa4242bce7a90a56a222d6b7bc77 Signed-off-by: Richard Cochran richard.coch...@omicron.at --- arch/powerpc/include/asm/systbl.h |1 + arch/powerpc/include/asm/unistd.h |3 ++- 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index aa0f1eb..6a1152c 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h @@ -348,3 +348,4 @@ COMPAT_SYS_SPU(sendmsg) COMPAT_SYS_SPU(recvmsg) COMPAT_SYS_SPU(recvmmsg) SYSCALL_SPU(accept4) +COMPAT_SYS_SPU(clock_adjtime) diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 6151937..386de07 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h @@ -367,10 +367,11 @@ #define __NR_recvmsg 342 #define __NR_recvmmsg 343 #define __NR_accept4 344 +#define __NR_clock_adjtime 345 #ifdef __KERNEL__ -#define __NR_syscalls 345 +#define __NR_syscalls 346 #define __NR__exit __NR_exit #define NR_syscalls__NR_syscalls -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: hvc_console: Don't access hvc_task if not initialised
[removed stable list from discussion]
On Thu, 24 Mar 2011 07:29:58 -, Amit Shah wrote:
hvc_open() can be called without having any backing device. This
results in a call to hvc_kick() which calls wake_up_process on a NULL
pointer.
How is hvc_open called without a hvc_driver registered to the tty layer?
Ensure hvc is initialised by checking for a non-NULL hvc_task
before waking up the hvc thread.
No if the task is missing the subsystem is really stuck. Put a check
in open and refuse to open.
This was found by an autotest run for virtio_console without having a
console backend.
stack trace please
CC: sta...@kernel.org
Signed-off-by: Amit Shah amit.s...@redhat.com
---
drivers/tty/hvc/hvc_console.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
index e9cba13..b2cb5cc 100644
--- a/drivers/tty/hvc/hvc_console.c
+++ b/drivers/tty/hvc/hvc_console.c
@@ -286,6 +286,9 @@ EXPORT_SYMBOL_GPL(hvc_instantiate);
/* Wake the sleeping khvcd */
void hvc_kick(void)
{
+ if (!hvc_task)
+ return;
+
hvc_kicked = 1;
wake_up_process(hvc_task);
}
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: add clock_adjtime for powerpc
On Thu, Mar 24, 2011 at 04:05:17PM +0100, Richard Cochran wrote: This patch adds the clock_adjtime system call to the powerpc architecture. Never mind this patch. Stephen Rothwell already posted a patch on linuxppc-dev adding this syscall eariler today. Thanks, Richard ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
High load average (~2.0) on an idle PowerPC 64 machine
I there, I've this Quad G5 machine that's sitting pretty much idle with the latest Debian stable installed, and yet it's got an abnormaly high load average. I've detailed the situation over here, maybe you guys will find it interesting or have something to say : http://serverfault.com/questions/251299/high-load-average-over-2-0-on-an-idle-machine The machine doesn't seem to be actually slowed down, it looks more like an incorrect measurement. Thank you very much for any help ! - Romain ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/4] powerpc/mpic: parse 4-cell intspec types other than zero
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mpic.h |2 ++
arch/powerpc/sysdev/mpic.c | 37 -
2 files changed, 38 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 7005ee0..25a0cb3 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -371,6 +371,8 @@ struct mpic
* NOTE: This flag trumps MPIC_WANTS_RESET.
*/
#define MPIC_NO_RESET 0x4000
+/* Freescale MPIC (compatible includes fsl,mpic) */
+#define MPIC_FSL 0x8000
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf000
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0f7c671..69f96ec 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -6,6 +6,7 @@
* with various broken implementations of this HW.
*
* Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
@@ -1030,6 +1031,7 @@ static int mpic_host_xlate(struct irq_host *h, struct
device_node *ct,
irq_hw_number_t *out_hwirq, unsigned int *out_flags)
{
+ struct mpic *mpic = h-host_data;
static unsigned char map_mpic_senses[4] = {
IRQ_TYPE_EDGE_RISING,
IRQ_TYPE_LEVEL_LOW,
@@ -1038,7 +1040,38 @@ static int mpic_host_xlate(struct irq_host *h, struct
device_node *ct,
};
*out_hwirq = intspec[0];
- if (intsize 1) {
+ if (intsize = 4 (mpic-flags MPIC_FSL)) {
+ /*
+* Freescale MPIC with extended intspec:
+* First two cells are as usual. Third specifies
+* an interrupt type. Fourth is type-specific data.
+*
+* See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+*/
+ switch (intspec[2]) {
+ case 0:
+ case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
+ break;
+ case 2:
+ if (intspec[0] = ARRAY_SIZE(mpic-ipi_vecs))
+ return -EINVAL;
+
+ *out_hwirq = mpic-ipi_vecs[intspec[0]];
+ break;
+ case 3:
+ if (intspec[0] = ARRAY_SIZE(mpic-timer_vecs))
+ return -EINVAL;
+
+ *out_hwirq = mpic-timer_vecs[intspec[0]];
+ break;
+ default:
+ pr_debug(%s: unknown irq type %u\n,
+__func__, intspec[2]);
+ return -EINVAL;
+ }
+
+ *out_flags = map_mpic_senses[intspec[1] 3];
+ } else if (intsize 1) {
u32 mask = 0x3;
/* Apple invented a new race of encoding on machines with
@@ -1137,6 +1170,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
/* Check for big-endian in device-tree */
if (node of_get_property(node, big-endian, NULL) != NULL)
mpic-flags |= MPIC_BIG_ENDIAN;
+ if (node of_device_is_compatible(node, fsl,mpic))
+ mpic-flags |= MPIC_FSL;
/* Look for protected sources */
if (node) {
--
1.7.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/4] powerpc/mpic: add the mpic global timer support
Add support for MPIC timers as requestable interrupt sources.
Based on http://patchwork.ozlabs.org/patch/20941/ by Dave Liu.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mpic.h |3 +-
arch/powerpc/sysdev/mpic.c | 92 ---
2 files changed, 88 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 25a0cb3..664bee6 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -263,6 +263,7 @@ struct mpic
#ifdef CONFIG_SMP
struct irq_chip hc_ipi;
#endif
+ struct irq_chip hc_tm;
const char *name;
/* Flags */
unsigned intflags;
@@ -281,7 +282,7 @@ struct mpic
/* vector numbers used for internal sources (ipi/timers) */
unsigned intipi_vecs[4];
- unsigned inttimer_vecs[4];
+ unsigned inttimer_vecs[8];
/* Spurious vector to program into unused sources */
unsigned intspurious_vec;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 69f96ec..c173e67 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -219,6 +219,28 @@ static inline void _mpic_ipi_write(struct mpic *mpic,
unsigned int ipi, u32 valu
_mpic_write(mpic-reg_type, mpic-gregs, offset, value);
}
+static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
+{
+ unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
+ ((tm 3) * MPIC_INFO(TIMER_STRIDE));
+
+ if (tm = 4)
+ offset += 0x1000 / 4;
+
+ return _mpic_read(mpic-reg_type, mpic-tmregs, offset);
+}
+
+static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32
value)
+{
+ unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
+ ((tm 3) * MPIC_INFO(TIMER_STRIDE));
+
+ if (tm = 4)
+ offset += 0x1000 / 4;
+
+ _mpic_write(mpic-reg_type, mpic-tmregs, offset, value);
+}
+
static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
unsigned int cpu = mpic_processor_id(mpic);
@@ -269,6 +291,8 @@ static inline void _mpic_irq_write(struct mpic *mpic,
unsigned int src_no,
#define mpic_write(b,r,v) _mpic_write(mpic-reg_type,(b),(r),(v))
#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v)_mpic_ipi_write(mpic,(i),(v))
+#define mpic_tm_read(i)_mpic_tm_read(mpic,(i))
+#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v)_mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
@@ -628,6 +652,13 @@ static unsigned int mpic_is_ipi(struct mpic *mpic,
unsigned int irq)
return (src = mpic-ipi_vecs[0] src = mpic-ipi_vecs[3]);
}
+/* Determine if the linux irq is a timer */
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
+{
+ unsigned int src = mpic_irq_to_hw(irq);
+
+ return (src = mpic-timer_vecs[0] src = mpic-timer_vecs[7]);
+}
/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
@@ -814,6 +845,25 @@ static void mpic_end_ipi(struct irq_data *d)
#endif /* CONFIG_SMP */
+static void mpic_unmask_tm(struct irq_data *d)
+{
+ struct mpic *mpic = mpic_from_irq_data(d);
+ unsigned int src = mpic_irq_to_hw(d-irq) - mpic-timer_vecs[0];
+
+ DBG(%s: enable_tm: %d (tm %d)\n, mpic-name, irq, src);
+ mpic_tm_write(src, mpic_tm_read(src) ~MPIC_VECPRI_MASK);
+ mpic_tm_read(src);
+}
+
+static void mpic_mask_tm(struct irq_data *d)
+{
+ struct mpic *mpic = mpic_from_irq_data(d);
+ unsigned int src = mpic_irq_to_hw(d-irq) - mpic-timer_vecs[0];
+
+ mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
+ mpic_tm_read(src);
+}
+
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
bool force)
{
@@ -948,6 +998,12 @@ static struct irq_chip mpic_ipi_chip = {
};
#endif /* CONFIG_SMP */
+static struct irq_chip mpic_tm_chip = {
+ .irq_mask = mpic_mask_tm,
+ .irq_unmask = mpic_unmask_tm,
+ .irq_eoi= mpic_end_irq,
+};
+
#ifdef CONFIG_MPIC_U3_HT_IRQS
static struct irq_chip mpic_irq_ht_chip = {
.irq_startup= mpic_startup_ht_irq,
@@ -991,6 +1047,16 @@ static int mpic_host_map(struct irq_host *h, unsigned int
virq,
}
#endif /* CONFIG_SMP */
+ if (hw = mpic-timer_vecs[0] hw = mpic-timer_vecs[7]) {
+ WARN_ON(!(mpic-flags MPIC_PRIMARY));
+
+ DBG(mpic: mapping as timer\n);
+ set_irq_chip_data(virq, mpic);
+ set_irq_chip_and_handler(virq,
[PATCH 2/4] powerpc/p1022ds: fix broken mpic timer node
There is no hardware interrupt 0xf7. But now we can express the timer
interrupt using 4-cell interrupts. This requires converting all of the
other interrupt specifiers in the tree as well.
Also add the second timer group, and fix the reg property to only
describe the timer registers.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/boot/dts/p1022ds.dts | 106
1 files changed, 59 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1022ds.dts
b/arch/powerpc/boot/dts/p1022ds.dts
index 59ef405..4f685a7 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -52,7 +52,7 @@
#size-cells = 1;
compatible = fsl,p1022-elbc, fsl,elbc, simple-bus;
reg = 0 0xffe05000 0 0x1000;
- interrupts = 19 2;
+ interrupts = 19 2 0 0;
ranges = 0x0 0x0 0xf 0xe800 0x0800
0x1 0x0 0xf 0xe000 0x0800
@@ -157,7 +157,7 @@
* IRQ8 is generated if the EVENT switch is pressed
* and PX_CTL[EVESEL] is set to 00.
*/
- interrupts = 8 8;
+ interrupts = 8 8 0 0;
};
};
@@ -178,13 +178,13 @@
ecm@1000 {
compatible = fsl,p1022-ecm, fsl,ecm;
reg = 0x1000 0x1000;
- interrupts = 16 2;
+ interrupts = 16 2 0 0;
};
memory-controller@2000 {
compatible = fsl,p1022-memory-controller;
reg = 0x2000 0x1000;
- interrupts = 16 2;
+ interrupts = 16 2 0 0;
};
i2c@3000 {
@@ -193,7 +193,7 @@
cell-index = 0;
compatible = fsl-i2c;
reg = 0x3000 0x100;
- interrupts = 43 2;
+ interrupts = 43 2 0 0;
dfsrr;
};
@@ -203,7 +203,7 @@
cell-index = 1;
compatible = fsl-i2c;
reg = 0x3100 0x100;
- interrupts = 43 2;
+ interrupts = 43 2 0 0;
dfsrr;
wm8776:codec@1a {
@@ -220,7 +220,7 @@
compatible = ns16550;
reg = 0x4500 0x100;
clock-frequency = 0;
- interrupts = 42 2;
+ interrupts = 42 2 0 0;
};
serial1: serial@4600 {
@@ -229,7 +229,7 @@
compatible = ns16550;
reg = 0x4600 0x100;
clock-frequency = 0;
- interrupts = 42 2;
+ interrupts = 42 2 0 0;
};
spi@7000 {
@@ -238,7 +238,7 @@
#size-cells = 0;
compatible = fsl,espi;
reg = 0x7000 0x1000;
- interrupts = 59 0x2;
+ interrupts = 59 0x2 0 0;
espi,num-ss-bits = 4;
mode = cpu;
@@ -275,7 +275,7 @@
compatible = fsl,mpc8610-ssi;
cell-index = 0;
reg = 0x15000 0x100;
- interrupts = 75 2;
+ interrupts = 75 2 0 0;
fsl,mode = i2s-slave;
codec-handle = wm8776;
fsl,playback-dma = dma00;
@@ -294,25 +294,25 @@
compatible = fsl,ssi-dma-channel;
reg = 0x0 0x80;
cell-index = 0;
- interrupts = 76 2;
+ interrupts = 76 2 0 0;
};
dma01: dma-channel@80 {
compatible = fsl,ssi-dma-channel;
reg = 0x80 0x80;
cell-index = 1;
- interrupts = 77 2;
+ interrupts = 77 2 0 0;
};
dma-channel@100 {
compatible = fsl,eloplus-dma-channel;
reg = 0x100 0x80;
cell-index = 2;
- interrupts = 78 2;
+ interrupts = 78 2 0 0;
};
dma-channel@180 {
compatible = fsl,eloplus-dma-channel;
reg = 0x180 0x80;
[PATCH] powerpc/booke: Correct the SPRN_MAS5 definition.
From: Varun Sethi varun.se...@freescale.com 339 is the SPR number for MAS5 documented by Power ISA 2.06, and implemented by e500mc. It is not yet used anywhere in the kernel, so nothing should be relying on the wrong number. Signed-off-by: Varun Sethi varun.se...@freescale.com Signed-off-by: Scott Wood scottw...@freescale.com --- arch/powerpc/include/asm/reg_booke.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 86ad812..3b1a9b7 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -110,7 +110,7 @@ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS5 0x153 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27A /* Process ID Register 2 */ -- 1.7.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: ARCH_PFN_OFFSET should be unsigned long
pfns are unsigned long, but MEMORY_START is phys_addr_t. This leads to page_to_pfn() returning phys_addr_t, and thus type mismatches in a few print statements. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/powerpc/include/asm/page.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index da4b200..2cd664e 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h @@ -100,7 +100,7 @@ extern phys_addr_t kernstart_addr; #endif #ifdef CONFIG_FLATMEM -#define ARCH_PFN_OFFSET(MEMORY_START PAGE_SHIFT) +#define ARCH_PFN_OFFSET((unsigned long)(MEMORY_START PAGE_SHIFT)) #define pfn_valid(pfn) ((pfn) = ARCH_PFN_OFFSET (pfn) max_mapnr) #endif -- 1.7.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/4] powerpc: Add fsl mpic timer binding
Update the existing example in the general mpic binding to have a
separate TCRx region. Currently the example doesn't describe TCRx at
all. The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between. That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.
Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.
Add fsl,available-ranges, similar to msi-available-ranges.
Signed-off-by: Scott Wood scottw...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/mpic-timer.txt | 38
.../devicetree/bindings/powerpc/fsl/mpic.txt |2 +-
2 files changed, 39 insertions(+), 1 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
new file mode 100644
index 000..df41958
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
@@ -0,0 +1,38 @@
+* Freescale MPIC timers
+
+Required properties:
+- compatible: fsl,mpic-global-timer
+
+- reg : Contains two regions. The first is the main timer register bank
+ (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
+ register (TCRx) for the group.
+
+- fsl,available-ranges: use start count style section to define which
+ timer interrupts can be used. This property is optional; without this,
+ all timers within the group can be used.
+
+- interrupts: one interrupt per timer in the group, in order, starting
+ with timer zero. If timer-available-ranges is present, only the
+ interrupts that correspond to available timers shall be present.
+
+Example:
+ /* Note that this requires #interrupt-cells to be 4 */
+ timer0: timer@41100 {
+ compatible = fsl,mpic-global-timer;
+ reg = 0x41100 0x100 0x41300 4;
+
+ /* Another AMP partition is using timers 0 and 1 */
+ fsl,available-ranges = 2 2;
+
+ interrupts = 2 0 3 0
+ 3 0 3 0;
+ };
+
+ timer1: timer@42100 {
+ compatible = fsl,mpic-global-timer;
+ reg = 0x42100 0x100 0x42300 4;
+ interrupts = 4 0 3 0
+ 5 0 3 0
+ 6 0 3 0
+ 7 0 3 0;
+ };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index 8aa10f4..6af4b64 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -190,7 +190,7 @@ EXAMPLE 4
*/
timer0: timer@41100 {
compatible = fsl,mpic-global-timer;
- reg = 0x41100 0x100;
+ reg = 0x41100 0x100 0x41300 4;
interrupts = 0 0 3 0
1 0 3 0
2 0 3 0
--
1.7.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[BUG] pgprot_noncached() is -NOT- safe for mapping vmalloc buffers into userspace
Hi Takashi ! While working on endian-fixing xHCI with Matt (CC), we discovered the source of our problems with usb-audio on a board we were working on. c32d977b8157bf67cdf47729ce7dd054a26eb534 ALSA: pcm - Call pgprot_noncached() for vmalloc'ed buffers I'm afraid that this is totally bogus :-) I don't know on what arch it is safe to have the same memory be mapped cachable in the kernel (and accessed via this cached mapping) and non-cachable in userspace, but I can confidently say that wherever it works it does so by accident. In the case of usb-audio, what we observed is that the user application was writing samples using an uncached mapping, so directly to memory, which does -not- invalidate conflicting cache lines on the way, an the kernel would then memcpy those data to the USB buffers using a cached mapping (vmalloc) and essentially get stale stuff from the cache instead of the real samples. Worse, on some processors, it's actually -illegal- to create (and even more to -access-) a conflicting mapping of a page of memory, ie, have it mapped cached somewhere and uncached somewhere else. It will lockup some processors and afaik, some x86 as well. In fact, cache coherent architectures often don't support mapping memory uncached -at-all- so something like snd_pcm_lib_mmap_noncached() shouldn't exist, or at least be under arch control. There's no case where it's always safe. There will almost always be a cache alias in the linear mapping unless special arch specific sauce has been applied. Now, there's another problem on top of that, which is that snd_pcm_default_mmap() will not work properly the other way around on powerpc, where the mapping -needs- to be uncached bcs you are running on a non cache coherent embedded CPU and trying to mmap DMA memory, but that's something that needs fixing inside powerpc by properly defining dma_mmap_coherent() ARCH_HAS_DMA_MMAP_COHERENT (I thought we had added it a while back but it's not upstream, patch must have got lost). We must also make sure we don't go down that path for vmalloc memory though. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Query: PCIe range entry at pcie@0 in dts files
On Mar 23, 2011, at 10:20 PM, Kushwaha Prabhakar-B32579 wrote:
Hi all,
I have query about usage of range field at pcie@0 under PCIe controller.
Please find snap shot from mpc8536_36.dts..
pci3: pcie@fffe0b000 {
compatible = fsl,mpc8548-pcie;
device_type = pci;
#interrupt-cells = 1;
#size-cells = 2;
#address-cells = 3;
reg = 0xf 0xffe0b000 0 0x1000;
bus-range = 0 0xff;
ranges = 0x0200 0 0xe000 0xc 0x2000 0 0x2000
0x0100 0 0x 0xf 0xffc3 0 0x0001;
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 27 0x2;
interrupt-map-mask = 0xf800 0 0 7;
interrupt-map =
/* IDSEL 0x0 */
0 0 1 mpic 8 1
0 0 2 mpic 9 1
0 0 3 mpic 10 1
0 0 4 mpic 11 1
;
pcie@0 {
reg = 0 0 0 0 0;
#size-cells = 2;
#address-cells = 3;
device_type = pci;
ranges = 0x0200 0 0xe000 -- child/port start
address
0x0200 0 0xe000 -- Parent bus address
0 0x2000
0x0100 0 0x
0x0100 0 0x
0 0x0010;
};
};
Question:
A) is ranges filed of pcie@0 really required?
I just went through the code and found scan_OF_for_pci_dev() called
from pci_busdev_to_OF_node() touches pcie@0 node. But, It does not even uses
range filed.
static struct device_node *scan_OF_for_pci_dev(struct device_node
*parent,unsigned int devfn) {
---
---
for_each_child_of_node(parent, np) {
reg = of_get_property(np, reg, psize);
---
---
if (!strcmp(np-name, multifunc-device)) {
}
I also checked Power_ePAPR_APPROVED_v1.0.pdf. It never say range filed
required for child bus.
Part of the reason for the range is to match PCIe semantics of RC having a
transparent bridge.
B) if range field of pcie@0 required. why does child/port start address same
as Parent bus address? Range property provides mapping of port address to
parent address space.
So the value should be 0x. Means port's address starting from
0x to size 0x2000 is mapped parent's 0xe000.
ranges = 0x0200 0 0x -- Child/port's
start address
0x0200 0 0xe000-- Parent bus
address
0 0x2000
0x0100 0 0x
0x0100 0 0x
0 0x0010;
because the bridge is transparent.
- k
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/dts:Update PCIe memory maps to match u-boot of Px020RDB
PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Acked-by: Kumar Gala kumar.g...@freescale.com --- Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (Branch master) arch/powerpc/boot/dts/p1020rdb.dts| 12 ++-- arch/powerpc/boot/dts/p2020rdb.dts| 12 ++-- arch/powerpc/boot/dts/p2020rdb_camp_core0.dts |4 ++-- arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 10 +- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts index 22f64b6..e0668f8 100644 --- a/arch/powerpc/boot/dts/p1020rdb.dts +++ b/arch/powerpc/boot/dts/p1020rdb.dts @@ -1,7 +1,7 @@ /* * P1020 RDB Device Tree Source * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -553,7 +553,7 @@ reg = 0 0xffe09000 0 0x1000; bus-range = 0 255; ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000 - 0x100 0x0 0x 0 0xffc3 0x0 0x1; + 0x100 0x0 0x 0 0xffc1 0x0 0x1; clock-frequency = ; interrupt-parent = mpic; interrupts = 16 2; @@ -580,8 +580,8 @@ #address-cells = 3; reg = 0 0xffe0a000 0 0x1000; bus-range = 0 255; - ranges = 0x200 0x0 0xc000 0 0xc000 0x0 0x2000 - 0x100 0x0 0x 0 0xffc2 0x0 0x1; + ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000 + 0x100 0x0 0x 0 0xffc0 0x0 0x1; clock-frequency = ; interrupt-parent = mpic; interrupts = 16 2; @@ -590,8 +590,8 @@ #size-cells = 2; #address-cells = 3; device_type = pci; - ranges = 0x200 0x0 0xc000 - 0x200 0x0 0xc000 + ranges = 0x200 0x0 0x8000 + 0x200 0x0 0x8000 0x0 0x2000 0x100 0x0 0x0 diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts index da4cb0d..e2d48fd 100644 --- a/arch/powerpc/boot/dts/p2020rdb.dts +++ b/arch/powerpc/boot/dts/p2020rdb.dts @@ -1,7 +1,7 @@ /* * P2020 RDB Device Tree Source * - * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -537,7 +537,7 @@ reg = 0 0xffe09000 0 0x1000; bus-range = 0 255; ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000 - 0x100 0x0 0x 0 0xffc3 0x0 0x1; + 0x100 0x0 0x 0 0xffc1 0x0 0x1; clock-frequency = ; interrupt-parent = mpic; interrupts = 25 2; @@ -564,8 +564,8 @@ #address-cells = 3; reg = 0 0xffe0a000 0 0x1000; bus-range = 0 255; - ranges = 0x200 0x0 0xc000 0 0xc000 0x0 0x2000 - 0x100 0x0 0x 0 0xffc2 0x0 0x1; + ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000 + 0x100 0x0 0x 0 0xffc0 0x0 0x1; clock-frequency = ; interrupt-parent = mpic; interrupts = 26 2; @@ -574,8 +574,8 @@ #size-cells = 2; #address-cells = 3; device_type = pci; - ranges = 0x200 0x0 0xc000 - 0x200 0x0 0xc000 + ranges = 0x200 0x0 0x8000 + 0x200 0x0 0x8000 0x0 0x2000 0x100 0x0 0x0 diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts index 0fe93d0..b69c3a5 100644 --- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts @@ -6,7 +6,7 @@ * This dts file allows core0 to have
