RE: [RFC] Multi queue support in ethernet/freescale/ucc_geth.c
-Original Message- From: Paul Gortmaker [mailto:paul.gortma...@windriver.com] Sent: Friday, February 03, 2012 6:42 AM To: Li Yang-R58472 Cc: net...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: [RFC] Multi queue support in ethernet/freescale/ucc_geth.c Hi Li, Hi Paul, Sorry for the late response due to holidays. A while back DaveM mentioned that it would be good to break out the ring allocations[1] in this driver. I was looking at it, and in the process noticed this: $ grep 'numQueues.*=' drivers/net/ethernet/freescale/ucc_geth.c .numQueuesTx = 1, .numQueuesRx = 1, $ My interpretation of the above is that there is no way (aside from a code edit) to enable multi queue support. They are only ever assigned one time, to a value of one. Assuming I'm not missing something obvious, is the multi queue support functional and tested, or just old code that never got tested and subsequently enabled? Previously the device is only used on single core cpu, so we didn't have the incentive to enable multi-queue. It is not tested on Linux currently. The reason I ask, is that the ring allocation code gets rid of the loop wrapping it, if the driver is really only meant to ever have just single queues for Rx/Tx. And other areas of the driver can also be simplified accordingly as well. Well. I would prefer the other way which is to add the multi-queue support as we are using the QE in multi-core SoC and the current driver is having almost all the code needed for multi-queue except interface to the protocol layer. - Leo ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/dts: Removed fsl,msi property from dts.
From: Diana CRACIUN diana.crac...@freescale.com
The association in the decice tree between PCI and MSI
using fsl,msi property was an artificial one and it does
not reflect the actual hardware.
Signed-off-by: Diana CRACIUN diana.crac...@freescale.com
---
arch/powerpc/boot/dts/p2041rdb.dts |3 ---
arch/powerpc/boot/dts/p3041ds.dts |4
arch/powerpc/boot/dts/p3060qds.dts |2 --
arch/powerpc/boot/dts/p4080ds.dts |3 ---
arch/powerpc/boot/dts/p5020ds.dts |4
5 files changed, 0 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts
b/arch/powerpc/boot/dts/p2041rdb.dts
index 4f957db..2852139 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -135,7 +135,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -151,7 +150,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -167,7 +165,6 @@
reg = 0xf 0xfe202000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x4000 0 0x2000
0x0100 0 0x 0xf 0xf802 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p3041ds.dts
b/arch/powerpc/boot/dts/p3041ds.dts
index f469145..22a215e 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -173,7 +173,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -189,7 +188,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -205,7 +203,6 @@
reg = 0xf 0xfe202000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x4000 0 0x2000
0x0100 0 0x 0xf 0xf802 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -221,7 +218,6 @@
reg = 0xf 0xfe203000 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x6000 0 0x2000
0x0100 0 0x 0xf 0xf803 0 0x0001;
- fsl,msi = msi2;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p3060qds.dts
b/arch/powerpc/boot/dts/p3060qds.dts
index 529042e..9ae875c 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -212,7 +212,6 @@
reg = 0xf 0xfe20 0 0x1000;
ranges = 0x0200 0 0xe000 0xc 0x 0x0 0x2000
0x0100 0 0x 0xf 0xf800 0x0
0x0001;
- fsl,msi = msi0;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
@@ -228,7 +227,6 @@
reg = 0xf 0xfe201000 0 0x1000;
ranges = 0x0200 0x0 0xe000 0xc 0x2000 0x0
0x2000
0x0100 0x0 0x 0xf 0xf801 0x0
0x0001;
- fsl,msi = msi1;
pcie@0 {
ranges = 0x0200 0 0xe000
0x0200 0 0xe000
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 6d60e54..3e20460 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -141,7 +141,6 @@
reg = 0xf 0xfe20 0 0x1000;
Re: [PATCH] powerpc/dts: Removed fsl,msi property from dts.
On Thu, Feb 9, 2012 at 7:41 AM, Diana Craciun diana.crac...@freescale.com wrote: From: Diana CRACIUN diana.crac...@freescale.com The association in the decice tree between PCI and MSI using fsl,msi property was an artificial one and it does not reflect the actual hardware. Signed-off-by: Diana CRACIUN diana.crac...@freescale.com Acked-by: Timur Tabi ti...@freescale.com -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2 v4] powerpc/dts: Add dts for p1020rdb-pc board
On Wed, Feb 8, 2012 at 11:40 PM, Zhicheng Fan b32...@freescale.com wrote: arch/powerpc/boot/dts/p1020rdb-pc.dts | 90 arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++ arch/powerpc/boot/dts/p1020rdb-pc_36b.dts | 90 If we're going to support both 32-bit and 36-bit dts files, then we have to label both DTS files properly. Do not assume that 32-bit is the default, because on some platforms, 36-bit is the default. p1020rdb-pc.dts should be called p1020rdb-pc_32b.dts. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2 v4] powerpc/85xx: Add p1020rdb-pc platform support
On Wed, Feb 8, 2012 at 11:40 PM, Zhicheng Fan b32...@freescale.com wrote:
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
static int __init p1020_rdb_pc_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, fsl,P1020RDB-PC);
}
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [PATCH 1/2 v2] P1025RDB: Add Quicc Engine support
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(Could not find qe-ic node\n);
Since you have to use pr_err instead of dev_err, please add a prefix
to the message. Like this:
pr_err(mpc85xx-rdb: could not find qe-ic node\n);
or maybe something like this:
pr_err(%s: could not find qe-ic node\n, __func__);
+ if (machine_is(p1025_rdb)) {
+
+ __be32 __iomem *pmuxcr;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+
+ if (np) {
+ pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
Use the ccsr_guts_85xx structure instead of hard-coded offsets.
MPC85xx_PMUXCR_OFFSET should be deleted.
+
+ if (!pmuxcr)
+ pr_err(KERN_EMERG Error: Alternate function
+ signal multiplex control register
not
+ mapped!\n);
A missing node in the device tree is NOT an emergency. Also, the
KERN_xxx macros are not supposed to be used in a pr_xxx macro. Please
don't blindly copy/paste code from somewhere else without thinking
about it.
--
Timur Tabi
Linux kernel developer at Freescale
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Re: [PATCH v2] powerpc: Rework lazy-interrupt handling
Hi Ben, Small comment inline. On 02/09/2012 06:25 AM, Benjamin Herrenschmidt wrote: From 0ace17ba6960a8788b1bda3770df254cbbc6a244 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidtb...@kernel.crashing.org Date: Thu, 9 Feb 2012 15:25:04 +1100 Subject: [PATCH] powerpc: Rework lazy-interrupt handling The current implementation of lazy interrupts handling has some issues that this tries to address. Except on iSeries, we don't do the various workarounds we need to do on re-enable when returning from an interrupt, which can do an implicit re-enable, and thus we may still lose or get delayed decrementer or doorbell interrupts. The current scheme also makes it much harder to handle the external edge interrupts provided by some BookE processors when using the EPR facility (External Proxy) and the Freescale Hypervisor. We also hard mask on decrementer interrupts which is sub-optimal. This is an attempt at fixing it all in one go by reworking the way we do the lazy interrupt disabling. The base idea is to replace the hard_enabled field with a irq_happened field in which we store a bit mask of what interrupt occurred while soft-disabled. When re-enabling, either via arch_local_irq_restore() or when returning from an interrupt, we can now decide what to do by testing bits in that field. We then implement re-emitting of the lost interrupts via either a re-use of the existing exception frame (exception exit case) or via the creation of a new one from assembly code (arch_local_irq_enable), without the need to trigger a fake one using set_dec() or similar. In addition, this adds a few refinements: - We no longer hard disable decrementer interrupts that occur while soft-disabled. We now simply bump the decrementer back to max (on BookS) or leave it stopped (on BookE) and continue with hard interrupts enabled, which means that we'll potentially get better sample quality from performance monitor interrupts. - Timer, decrementer and doorbell interrupts now hard-enable shortly after removing the source of the interrupt, which means they no longer run entirely hard disabled. Again, this will improve perf sample quality. - On Book3E 64-bit, we now make the performance monitor interrupt act as an NMI like Book3S (the necessary C code for that to work appear to already be present in the FSL perf code, notably calling nmi_enter instead of irq_enter). There are additional refinements that we can do on top of this patch: - We could remove the ps3 workaround from arch_local_irq_enable(), I believe that it should no longer be necessary - We could make masked decrementer interrupts act as NMIs when doing timer-based perf sampling to improve the sample quality. - There are additional simplifications of the exception entry/exit path that I've spotted along the way, such as merging fast_exception_return with the normal code path. This patch needs a LOT more testing review than it had so far !!! Not-signed-off-by-yet: Benjamin Herrenschmidtb...@kernel.crashing.org --- v2: - Add hard-enable to decrementer, timer and doorbells - Fix CR clobber in masked irq handling on BookE - Make embedded perf interrupt act as an NMI - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want to retrigger an interrupt without preventing hard-enable Signed-off-by: Benjamin Herrenschmidtb...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h| 21 ++- arch/powerpc/include/asm/hw_irq.h | 51 +- arch/powerpc/include/asm/irqflags.h | 13 +- arch/powerpc/include/asm/paca.h |2 +- arch/powerpc/kernel/asm-offsets.c |2 +- arch/powerpc/kernel/dbell.c | 12 ++ arch/powerpc/kernel/entry_64.S | 96 ++- arch/powerpc/kernel/exceptions-64e.S| 210 --- arch/powerpc/kernel/exceptions-64s.S| 90 ++ arch/powerpc/kernel/head_64.S |9 - arch/powerpc/kernel/idle_book3e.S |8 +- arch/powerpc/kernel/idle_power4.S | 17 ++- arch/powerpc/kernel/idle_power7.S | 20 ++- arch/powerpc/kernel/irq.c | 187 ++-- arch/powerpc/kernel/time.c | 15 ++- arch/powerpc/platforms/iseries/Makefile |2 +- arch/powerpc/platforms/iseries/exception.S | 11 +- arch/powerpc/platforms/iseries/misc.S | 26 --- arch/powerpc/platforms/pseries/processor_idle.c | 24 +++- 19 files changed, 540 insertions(+), 276 deletions(-) delete mode 100644 arch/powerpc/platforms/iseries/misc.S [snip] diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 429983c..7fa4096 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -21,6 +21,7 @@ #includeasm/exception-64e.h #includeasm/bug.h #includeasm/irqflags.h
Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses
On Wed, Feb 8, 2012 at 2:02 PM, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Wed, 2012-02-08 at 07:58 -0800, Bjorn Helgaas wrote: The only architecture-specific thing here is discovering the range of bus numbers below a host bridge. The architecture should not have to mess around with pci_bus_update_busn_res_end() like this. It should be able to say here's my bus number range (and of course the PCI core can default to 0-255 if the arch doesn't supply a range) and the core should take care of the rest. So it's a bit messy in here because we deal with several things. What the firmware gives us is the range it assigned, but that isn't necessarily the HW limits (almost never is in fact). In some cases we honor it, for example when in probe only mode where we prevent any reassigning, and in some case, we ignore it and let the PCI core renumber things (typically because the FW forgot to set aside bus numbers for a cardbus slot for example, that sort of things). So it's a bit of a tricky situation. Off the top of my head, I'm pretty sure that most if not all of our PCI host bridges simply support a full 0...255 range and there is no sharing between bridges like on x86, they are just different domains. My point is that the interface between the arch and the PCI core should be simply the arch telling the core this is the range of bus numbers you can use. If the firmware doesn't give you the HW limits, that's the arch's problem. If you want to assume 0..255 are available, again, that's the arch's decision. But the answer to the question what bus numbers are available to me depends only on the host bridge HW configuration. It does not depend on what pci_scan_child_bus() found. Therefore, I think we can come up with a design where pci_bus_update_busn_res_end() is unnecessary. Bjorn ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc: Rework lazy-interrupt handling
On Thu, 2012-02-09 at 19:03 +0200, Tudor Laurentiu wrote: +masked_interrupt_book3e_0x900: + ACK_DEC(r11); + li r11,PACA_HAPPENED_DEC + b masked_interrupt_book3e_no_mask +masked_interrupt_book3e_0x980: + ACK_FIT(r11); + li r11,PACA_HAPPENED_DEC + b masked_interrupt_book3e_no_mask +masked_interrupt_book3e_0x280: +masked_interrupt_book3e_0x2c0: + li r11,PACA_HAPPENED_DBELL + b masked_interrupt_book3e_no_mask + +masked_interrupt_book3e_no_mask: + mtcrr10 + lbz r10,PACAIRQHAPPENED(r13) + ori r10,r10,r11 Shouldn't this be an 'or'? Yes, absolutely. This is a typo/thinko I do all the time ... oops. + stb r10,PACAIRQHAPPENED(r13) + b 1f +masked_interrupt_book3e_full_mask: mtcrr10 -masked_interrupt_book3e_common: - stb r11,PACAHARDIRQEN(r13) + lbz r10,PACAIRQHAPPENED(r13) + ori r10,r10,r11 Same comment. I'll respin and fix. Cheers, Ben + stb r10,PACAIRQHAPPENED(r13) mfspr r10,SPRN_SRR1 rldicl r11,r10,48,1/* clear MSR_EE */ rotldi r10,r11,16 mtspr SPRN_SRR1,r10 - ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */ +1: ld r10,PACA_EXGEN+EX_R10(r13); ld r11,PACA_EXGEN+EX_R11(r13); mfspr r13,SPRN_SPRG_GEN_SCRATCH; rfi b . /* + * Called from arch_local_irq_enable when an interrupt needs + * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 + * to indicate the kind of interrupt. MSR:EE is already off. + * We generate a stackframe like if a real interrupt had happened. + * + * Note: While MSR:EE is off, we need to make sure that _MSR + * in the generated frame has EE set to 1 or the exception + * handler will not properly re-enable them. + */ +_GLOBAL(__reemit_interrupt) + /* We are going to jump to the exception common code which +* will retrieve various register values from the PACA which +* we don't give a damn about. +*/ + mflrr10 + mfmsr r11 + mfcrr4; + mtspr SPRN_SPRG_GEN_SCRATCH,r13; + std r1,PACA_EXGEN+EX_R1(r13); + stw r4,PACA_EXGEN+EX_CR(r13); + ori r11,r11,MSR_EE + subir1,r1,INT_FRAME_SIZE; + cmpwi cr0,r3,0x500 + beq exc_0x500_common + cmpwi cr0,r3,0x900 + beq+exc_0x900_common + cmpwi cr0,r3,0x280 + beq+exc_0x280_common + blr + +/* * This is called from 0x300 and 0x400 handlers after the prologs with * r14 and r15 containing the fault address and error code, with the * original values stashed away in the PACA @@ -680,6 +762,8 @@ BAD_STACK_TRAMPOLINE(0x000) BAD_STACK_TRAMPOLINE(0x100) BAD_STACK_TRAMPOLINE(0x200) BAD_STACK_TRAMPOLINE(0x260) +BAD_STACK_TRAMPOLINE(0x280) +BAD_STACK_TRAMPOLINE(0x2a0) BAD_STACK_TRAMPOLINE(0x2c0) BAD_STACK_TRAMPOLINE(0x2e0) BAD_STACK_TRAMPOLINE(0x300) --- Best Regards, Laurentiu ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses
On Thu, 2012-02-09 at 11:24 -0800, Bjorn Helgaas wrote: My point is that the interface between the arch and the PCI core should be simply the arch telling the core this is the range of bus numbers you can use. If the firmware doesn't give you the HW limits, that's the arch's problem. If you want to assume 0..255 are available, again, that's the arch's decision. But the answer to the question what bus numbers are available to me depends only on the host bridge HW configuration. It does not depend on what pci_scan_child_bus() found. Therefore, I think we can come up with a design where pci_bus_update_busn_res_end() is unnecessary. In an ideal world yes. In a world where there are reverse engineered platforms on which we aren't 100% sure how thing actually work under the hood and have the code just adapt on what's there (and try to fix it up -sometimes-), thinks can get a bit murky :-) But yes, I see your point. As for what is the correct setting that needs to be done so that the patch doesn't end up a regression for us, I'll have to dig into some ancient HW to dbl check a few things. I hope 0...255 will just work but I can't guarantee it. What I'll probably do is constraint the core to the values in hose-min/max, and update selected platforms to put 0..255 in there when I know for sure they can cope. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Fix WARN_ON in decrementer_check_overflow
On Thu, 9 Feb 2012, Benjamin Herrenschmidt wrote:
We use __get_cpu_var() which triggers a false positive warning
in smp_processor_id() thinking interrupts are enabled (at this
point, they are soft-enabled but hard-disabled).
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
I was initially planning to fix that with a more in-depth rework
of how we do lazy irq disabling on powerpc, but that patch is
becoming too complex for this release so I'll apply this as a
stop-gap and leave the full rework for -next
Okay, thanks for the update, that's equivalent to the get_cpu_var
plus put_cpu_var patch I had generally been running with successfully.
(I was not at all confident that it was a sufficient fix, and have
to say generally above because one time I got something that looked
like recursive calls overflowing the stack, and IIRC something irq
did appear in each frame of the trace. But probably no connection,
never seen again, and I don't recall even which -rc or -next it was.)
Hugh
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 701d4ac..01e2877 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -118,10 +118,14 @@ static inline notrace void set_soft_enabled(unsigned
long enable)
static inline notrace void decrementer_check_overflow(void)
{
u64 now = get_tb_or_rtc();
- u64 *next_tb = __get_cpu_var(decrementers_next_tb);
+ u64 *next_tb;
+
+ preempt_disable();
+ next_tb = __get_cpu_var(decrementers_next_tb);
if (now = *next_tb)
set_dec(1);
+ preempt_enable();
}
notrace void arch_local_irq_restore(unsigned long en)
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Re: [PATCH] powerpc: Fix WARN_ON in decrementer_check_overflow
On Thu, 2012-02-09 at 14:25 -0800, Hugh Dickins wrote: Okay, thanks for the update, that's equivalent to the get_cpu_var plus put_cpu_var patch I had generally been running with successfully. (I was not at all confident that it was a sufficient fix, and have to say generally above because one time I got something that looked like recursive calls overflowing the stack, and IIRC something irq did appear in each frame of the trace. But probably no connection, never seen again, and I don't recall even which -rc or -next it was.) If you ever see that again, please shoot me the log ! Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH SDK1.2 1/3] powerpc/fsl-pci: Unify pci/pcie initialization code
Hi Kumar,
This series of patches have been pending for a long time.
I'd like to know whether they are look good or not so I can do the further work
on it.
It's kind of emergency things for me.
Thanks a lot for your attention.
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, January 10, 2012 3:31 PM
To: Gala Kumar-B11780
Cc: Li Yang-R58472; Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH SDK1.2 1/3] powerpc/fsl-pci: Unify pci/pcie initialization
code
Hi Kumar,
Do you have any idea on this series of patches?
Looking forward to your answer.
Thanks.
--Jia Hongtao.
-Original Message-
From: Jia Hongtao-B38951
Sent: Wednesday, December 21, 2011 3:11 PM
To: linuxppc-dev@lists.ozlabs.org
Cc: Li Yang-R58472; Gala Kumar-B11780; Jia Hongtao-B38951
Subject: [PATCH SDK1.2 1/3] powerpc/fsl-pci: Unify pci/pcie initialization code
We unified the Freescale pci/pcie initialization by changing the fsl_pci to a
platform driver.
In previous version pci/pcie initialization is in platform code which
Initialize pci bridge base on EP/RC or host/agent settings.
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/platforms/85xx/p1022_ds.c | 39 +++
arch/powerpc/sysdev/fsl_pci.c | 53
2 files changed, 65 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c
b/arch/powerpc/platforms/85xx/p1022_ds.c
index 2bf4342..41de2c1 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -277,32 +277,9 @@ void __init mpc85xx_smp_init(void);
*/
static void __init p1022_ds_setup_arch(void) { -#ifdef CONFIG_PCI
- struct device_node *np;
-#endif
- dma_addr_t max = 0x;
-
if (ppc_md.progress)
ppc_md.progress(p1022_ds_setup_arch(), 0);
-#ifdef CONFIG_PCI
- for_each_compatible_node(np, pci, fsl,p1022-pcie) {
- struct resource rsrc;
- struct pci_controller *hose;
-
- of_address_to_resource(np, 0, rsrc);
-
- if ((rsrc.start 0xf) == 0x8000)
- fsl_add_bridge(np, 1);
- else
- fsl_add_bridge(np, 0);
-
- hose = pci_find_hose_for_OF_device(np);
- max = min(max, hose-dma_window_base_cur +
- hose-dma_window_size);
- }
-#endif
-
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops.get_pixel_format= p1022ds_get_pixel_format;
diu_ops.set_gamma_table = p1022ds_set_gamma_table;
@@ -316,11 +293,8 @@ static void __init p1022_ds_setup_arch(void) #endif
#ifdef CONFIG_SWIOTLB
- if (memblock_end_of_DRAM() max) {
+ if (memblock_end_of_DRAM() 0x)
ppc_swiotlb_enable = 1;
- set_pci_dma_ops(swiotlb_dma_ops);
- ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
- }
#endif
pr_info(Freescale P1022 DS reference board\n); @@ -339,6 +313,17 @@
static int __init p1022_ds_publish_devices(void) }
machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+static struct of_device_id __initdata p1022_pci_ids[] = {
+ { .compatible = fsl,p1022-pcie, },
+ {},
+};
+
+static int __init p1022_ds_publish_pci_device(void) {
+ return of_platform_bus_probe(NULL, p1022_pci_ids, NULL); }
+machine_arch_initcall(p1022_ds, p1022_ds_publish_pci_device);
+
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
/*
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ce547e..a0f305d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -712,3 +712,56 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+
+static const struct of_device_id pci_ids[] = {
+ { .compatible = fsl,mpc8540-pci, },
+ { .compatible = fsl,mpc8548-pcie, },
+ { .compatible = fsl,p1022-pcie, },
+ {},
+};
+
+static int __devinit fsl_pci_probe(struct platform_device *pdev) {
+ struct pci_controller *hose;
+
+ if (of_match_node(pci_ids, pdev-dev.of_node)) {
+ struct resource rsrc;
+ of_address_to_resource(pdev-dev.of_node, 0, rsrc);
+ if ((rsrc.start 0xf) == 8000)
+ fsl_add_bridge(pdev-dev.of_node, 1);
+ else
+ fsl_add_bridge(pdev-dev.of_node, 0);
+
+#ifdef CONFIG_SWIOTLB
+ hose = pci_find_hose_for_OF_device(pdev-dev.of_node);
+ /*
+* if we couldn't map all of DRAM via the dma windows
+* we need SWIOTLB to handle buffers located outside of
+* dma capable memory region
+*/
+ if (memblock_end_of_DRAM() hose-dma_window_base_cur
+
[PATCH 2/2 V2] powerpc/85xx: Add p2020rdb-pc dts support
From: crazytyt tfor...@163.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Tang Yuantian b29...@freescale.com
---
V1 vs V2:
-rename dts from .dts to _32b.dts
-remove amp dts
arch/powerpc/boot/dts/p2020rdb-pc.dtsi| 241 +
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts | 96
arch/powerpc/boot/dts/p2020rdb-pc_36b.dts | 96
3 files changed, 433 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
create mode 100644 arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
new file mode 100644
index 000..c21d1c7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,241 @@
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR U-Boot Image;
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,p2020-fcm-nand,
+fsl,elbc-fcm-nand;
+ reg = 0x1 0x0 0x4;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = 0x0 0x0010;
+ label = NAND U-Boot Image;
+
[PATCH 1/2 V2] powerpc/85xx: Add P1024rdb dts support
From: crazytyt tfor...@163.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v1 vs v2:
-remove amp dts
-rename the dts from .dts to _32b.dts
-remove p1024si-pre.dtsi
arch/powerpc/boot/dts/p1024rdb.dtsi| 228
arch/powerpc/boot/dts/p1024rdb_32b.dts | 87
arch/powerpc/boot/dts/p1024rdb_36b.dts | 87
3 files changed, 402 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1024rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1024rdb_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1024rdb_36b.dts
diff --git a/arch/powerpc/boot/dts/p1024rdb.dtsi
b/arch/powerpc/boot/dts/p1024rdb.dtsi
new file mode 100644
index 000..eb3141d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb.dtsi
@@ -0,0 +1,228 @@
+/*
+ * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR U-Boot Image;
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,p1020-fcm-nand,
+fsl,elbc-fcm-nand;
+ reg = 0x1 0x0 0x4;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = 0x0 0x0010;
+ label = NAND U-Boot Image;
+ read-only;
+
[PATCH 05/60] powerpc: remove the second argument of k[un]map_atomic()
Signed-off-by: Cong Wang amw...@redhat.com
---
arch/powerpc/kvm/book3s_pr.c |4 ++--
arch/powerpc/mm/dma-noncoherent.c |5 ++---
arch/powerpc/mm/hugetlbpage.c |4 ++--
arch/powerpc/mm/mem.c |4 ++--
4 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index e2cfb9e..220fcdf 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -227,14 +227,14 @@ static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu,
struct kvmppc_pte *pte)
hpage_offset /= 4;
get_page(hpage);
- page = kmap_atomic(hpage, KM_USER0);
+ page = kmap_atomic(hpage);
/* patch dcbz into reserved instruction, so we trap */
for (i=hpage_offset; i hpage_offset + (HW_PAGE_SIZE / 4); i++)
if ((page[i] 0xff0007ff) == INS_DCBZ)
page[i] = 0xfff7;
- kunmap_atomic(page, KM_USER0);
+ kunmap_atomic(page);
put_page(hpage);
}
diff --git a/arch/powerpc/mm/dma-noncoherent.c
b/arch/powerpc/mm/dma-noncoherent.c
index 329be36..6747eec 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -365,12 +365,11 @@ static inline void __dma_sync_page_highmem(struct page
*page,
local_irq_save(flags);
do {
- start = (unsigned long)kmap_atomic(page + seg_nr,
- KM_PPC_SYNC_PAGE) + seg_offset;
+ start = (unsigned long)kmap_atomic(page + seg_nr) + seg_offset;
/* Sync this buffer segment */
__dma_sync((void *)start, seg_size, direction);
- kunmap_atomic((void *)start, KM_PPC_SYNC_PAGE);
+ kunmap_atomic((void *)start);
seg_nr++;
/* Calculate next buffer segment size */
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index a8b3cc7..57c7465 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -910,9 +910,9 @@ void flush_dcache_icache_hugepage(struct page *page)
if (!PageHighMem(page)) {
__flush_dcache_icache(page_address(page+i));
} else {
- start = kmap_atomic(page+i, KM_PPC_SYNC_ICACHE);
+ start = kmap_atomic(page+i);
__flush_dcache_icache(start);
- kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
+ kunmap_atomic(start);
}
}
}
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index d974b79..baaafde 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -458,9 +458,9 @@ void flush_dcache_icache_page(struct page *page)
#endif
#ifdef CONFIG_BOOKE
{
- void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE);
+ void *start = kmap_atomic(page);
__flush_dcache_icache(start);
- kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
+ kunmap_atomic(start);
}
#elif defined(CONFIG_8xx) || defined(CONFIG_PPC64)
/* On 8xx there is no need to kmap since highmem is not supported */
--
1.7.7.6
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 59/60] highmem: kill all __kmap_atomic() [swar...@nvidia.com: highmem: Fix ARM build break due to __kmap_atomic rename]
Signed-off-by: Stephen Warren swar...@nvidia.com
Signed-off-by: Cong Wang amw...@redhat.com
---
arch/arm/include/asm/highmem.h |2 +-
arch/arm/mm/highmem.c|4 ++--
arch/frv/include/asm/highmem.h |2 +-
arch/frv/mm/highmem.c|4 ++--
arch/mips/include/asm/highmem.h |2 +-
arch/mips/mm/highmem.c |4 ++--
arch/mn10300/include/asm/highmem.h |2 +-
arch/parisc/include/asm/cacheflush.h |2 +-
arch/powerpc/include/asm/highmem.h |2 +-
arch/sparc/include/asm/highmem.h |2 +-
arch/sparc/mm/highmem.c |4 ++--
arch/tile/include/asm/highmem.h |2 +-
arch/tile/mm/highmem.c |4 ++--
arch/x86/include/asm/highmem.h |2 +-
arch/x86/mm/highmem_32.c |4 ++--
include/linux/highmem.h | 11 +++
16 files changed, 24 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index a4edd19..8c5e828 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -57,7 +57,7 @@ static inline void *kmap_high_get(struct page *page)
#ifdef CONFIG_HIGHMEM
extern void *kmap(struct page *page);
extern void kunmap(struct page *page);
-extern void *__kmap_atomic(struct page *page);
+extern void *kmap_atomic(struct page *page);
extern void __kunmap_atomic(void *kvaddr);
extern void *kmap_atomic_pfn(unsigned long pfn);
extern struct page *kmap_atomic_to_page(const void *ptr);
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 807c057..5a21505 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -36,7 +36,7 @@ void kunmap(struct page *page)
}
EXPORT_SYMBOL(kunmap);
-void *__kmap_atomic(struct page *page)
+void *kmap_atomic(struct page *page)
{
unsigned int idx;
unsigned long vaddr;
@@ -81,7 +81,7 @@ void *__kmap_atomic(struct page *page)
return (void *)vaddr;
}
-EXPORT_SYMBOL(__kmap_atomic);
+EXPORT_SYMBOL(kmap_atomic);
void __kunmap_atomic(void *kvaddr)
{
diff --git a/arch/frv/include/asm/highmem.h b/arch/frv/include/asm/highmem.h
index a8d6565..716956a 100644
--- a/arch/frv/include/asm/highmem.h
+++ b/arch/frv/include/asm/highmem.h
@@ -157,7 +157,7 @@ static inline void kunmap_atomic_primary(void *kvaddr, enum
km_type type)
pagefault_enable();
}
-void *__kmap_atomic(struct page *page);
+void *kmap_atomic(struct page *page);
void __kunmap_atomic(void *kvaddr);
#endif /* !__ASSEMBLY__ */
diff --git a/arch/frv/mm/highmem.c b/arch/frv/mm/highmem.c
index fd7fcd4..31902c9 100644
--- a/arch/frv/mm/highmem.c
+++ b/arch/frv/mm/highmem.c
@@ -37,7 +37,7 @@ struct page *kmap_atomic_to_page(void *ptr)
return virt_to_page(ptr);
}
-void *__kmap_atomic(struct page *page)
+void *kmap_atomic(struct page *page)
{
unsigned long paddr;
int type;
@@ -64,7 +64,7 @@ void *__kmap_atomic(struct page *page)
return NULL;
}
}
-EXPORT_SYMBOL(__kmap_atomic);
+EXPORT_SYMBOL(kmap_atomic);
void __kunmap_atomic(void *kvaddr)
{
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index 77e6440..2d91888 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -47,7 +47,7 @@ extern void kunmap_high(struct page *page);
extern void *kmap(struct page *page);
extern void kunmap(struct page *page);
-extern void *__kmap_atomic(struct page *page);
+extern void *kmap_atomic(struct page *page);
extern void __kunmap_atomic(void *kvaddr);
extern void *kmap_atomic_pfn(unsigned long pfn);
extern struct page *kmap_atomic_to_page(void *ptr);
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 3634c7e..aff5705 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -41,7 +41,7 @@ EXPORT_SYMBOL(kunmap);
* kmaps are appropriate for short, tight code paths only.
*/
-void *__kmap_atomic(struct page *page)
+void *kmap_atomic(struct page *page)
{
unsigned long vaddr;
int idx, type;
@@ -62,7 +62,7 @@ void *__kmap_atomic(struct page *page)
return (void*) vaddr;
}
-EXPORT_SYMBOL(__kmap_atomic);
+EXPORT_SYMBOL(kmap_atomic);
void __kunmap_atomic(void *kvaddr)
{
diff --git a/arch/mn10300/include/asm/highmem.h
b/arch/mn10300/include/asm/highmem.h
index bfe2d88..7c137cd 100644
--- a/arch/mn10300/include/asm/highmem.h
+++ b/arch/mn10300/include/asm/highmem.h
@@ -70,7 +70,7 @@ static inline void kunmap(struct page *page)
* be used in IRQ contexts, so in some (very limited) cases we need
* it.
*/
-static inline unsigned long __kmap_atomic(struct page *page)
+static inline unsigned long kmap_atomic(struct page *page)
{
unsigned long vaddr;
int idx, type;
diff --git a/arch/parisc/include/asm/cacheflush.h
b/arch/parisc/include/asm/cacheflush.h
index da601dd..9f21ab0 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++
[PATCH 1/2 v5] powerpc/85xx: Add p1020rdb-pc platform support
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e..d54772e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -90,10 +90,18 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P1020RDB-PC);
+}
+
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -139,3 +147,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 2/2 v5] powerpc/dts: Add dts for p1020rdb-pc board
From: Zhicheng Fan b32...@freescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++
arch/powerpc/boot/dts/p1020rdb-pc_32b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 64 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 142 +
5 files changed, 633 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000..c952cd3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,247 @@
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+
