[PATCH 10/12] powerpc: Fix register clobbering when accumulating stolen time
When running under a hypervisor that supports stolen time accounting, we may call C code from the macro EXCEPTION_PROLOG_COMMON in the exception entry path, which clobbers CR0. However, the FPU and vector traps rely on CR0 indicating whether we are coming from userspace or kernel to decide what to do. So we need to restore that value after the C call Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/ppc_asm.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 368f72f..50f73aa 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -60,6 +60,8 @@ BEGIN_FW_FTR_SECTION; \ cmpdcr1,r11,r10;\ beq+cr1,33f;\ bl .accumulate_stolen_time;\ + ld r12,_MSR(r1); \ + andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 33:\ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 03/12] powerpc: Rework runlatch code
This moves the inlines into system.h and changes the runlatch
code to use the thread local flags (non-atomic) rather than
the TIF flags (atomic) to keep track of the latch state.
The code to turn it back on in an asynchronous interrupt is
now simplified and partially inlined.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/exception-64s.h | 50 --
arch/powerpc/include/asm/reg.h | 22 +
arch/powerpc/include/asm/system.h| 38 ++
arch/powerpc/include/asm/thread_info.h |9 +-
arch/powerpc/kernel/exceptions-64s.S |3 ++
arch/powerpc/kernel/process.c| 24 ++
6 files changed, 89 insertions(+), 57 deletions(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h
b/arch/powerpc/include/asm/exception-64s.h
index 041b222..bdc9eeb 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -284,35 +284,39 @@ label##_hv:
\
rlwimi r11,r12,0,MSR_EE; \
mtmsrd r11,1
-#define STD_EXCEPTION_COMMON(trap, label, hdlr)\
- .align 7; \
- .globl label##_common; \
-label##_common:\
- EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
- DISABLE_INTS; \
- bl .save_nvgprs; \
- addir3,r1,STACK_FRAME_OVERHEAD; \
- bl hdlr; \
- b .ret_from_except
+#define ADD_NVGPRS \
+ bl .save_nvgprs
+
+#define RUNLATCH_ON\
+BEGIN_FTR_SECTION \
+ clrrdi r3,r1,THREAD_SHIFT; \
+ ld r4,TI_LOCAL_FLAGS(r3); \
+ andi. r0,r4,_TLF_RUNLATCH;\
+ beqlppc64_runlatch_on_trampoline; \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+
+#define EXCEPTION_COMMON(trap, label, hdlr, ret, additions)\
+ .align 7; \
+ .globl label##_common; \
+label##_common:\
+ EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
+ additions; \
+ addir3,r1,STACK_FRAME_OVERHEAD; \
+ bl hdlr; \
+ b ret
+
+#define STD_EXCEPTION_COMMON(trap, label, hdlr)\
+ EXCEPTION_COMMON(trap, label, hdlr, ret_from_except,\
+ADD_NVGPRS;DISABLE_INTS)
/*
* Like STD_EXCEPTION_COMMON, but for exceptions that can occur
* in the idle task and therefore need the special idle handling
* (finish nap and runlatch)
*/
-#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
- .align 7; \
- .globl label##_common; \
-label##_common:\
- EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
- FINISH_NAP; \
- DISABLE_INTS; \
-BEGIN_FTR_SECTION \
- bl .ppc64_runlatch_on; \
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)\
- addir3,r1,STACK_FRAME_OVERHEAD; \
- bl hdlr; \
- b .ret_from_except_lite
+#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)\
+ EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
+FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
/*
* When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 7fdc2c0..b1a215e 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1079,30 +1079,12 @@
#define proc_trap()asm volatile(trap)
-#ifdef CONFIG_PPC64
-
-extern void ppc64_runlatch_on(void);
-extern void __ppc64_runlatch_off(void);
-
-#define ppc64_runlatch_off() \
- do {\
- if (cpu_has_feature(CPU_FTR_CTRL) \
- test_thread_flag(TIF_RUNLATCH)) \
- __ppc64_runlatch_off(); \
- } while (0)
+#define __get_SP() ({unsigned long sp; \
+ asm volatile(mr %0,1: =r (sp)); sp;})
extern unsigned long scom970_read(unsigned int address);
extern void
[PATCH 12/12] powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some issues that this tries to address. We don't do the various workarounds we need to do when re-enabling interrupts in some cases such as when returning from an interrupt and thus we may still lose or get delayed decrementer or doorbell interrupts. The current scheme also makes it much harder to handle the external edge interrupts provided by some BookE processors when using the EPR facility (External Proxy) and the Freescale Hypervisor. Additionally, we tend to keep interrupts hard disabled in a number of cases, such as decrementer interrupts, external interrupts, or when a masked decrementer interrupt is pending. This is sub-optimal. This is an attempt at fixing it all in one go by reworking the way we do the lazy interrupt disabling from the ground up. The base idea is to replace the hard_enabled field with a irq_happened field in which we store a bit mask of what interrupt occurred while soft-disabled. When re-enabling, either via arch_local_irq_restore() or when returning from an interrupt, we can now decide what to do by testing bits in that field. We then implement replaying of the missed interrupts either by re-using the existing exception frame (in exception exit case) or via the creation of a new one from an assembly trampoline (in the arch_local_irq_enable case). This removes the need to play with the decrementer to try to create fake interrupts, among others. In addition, this adds a few refinements: - We no longer hard disable decrementer interrupts that occur while soft-disabled. We now simply bump the decrementer back to max (on BookS) or leave it stopped (on BookE) and continue with hard interrupts enabled, which means that we'll potentially get better sample quality from performance monitor interrupts. - Timer, decrementer and doorbell interrupts now hard-enable shortly after removing the source of the interrupt, which means they no longer run entirely hard disabled. Again, this will improve perf sample quality. - On Book3E 64-bit, we now make the performance monitor interrupt act as an NMI like Book3S (the necessary C code for that to work appear to already be present in the FSL perf code, notably calling nmi_enter instead of irq_enter). (This also fixes a bug where BookE perfmon interrupts could clobber r14 ... oops) - We could make masked decrementer interrupts act as NMIs when doing timer-based perf sampling to improve the sample quality. Signed-off-by-yet: Benjamin Herrenschmidt b...@kernel.crashing.org --- v2: - Add hard-enable to decrementer, timer and doorbells - Fix CR clobber in masked irq handling on BookE - Make embedded perf interrupt act as an NMI - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want to retrigger an interrupt without preventing hard-enable v3: - Fix or vs. ori bug on Book3E - Fix enabling of interrupts for some exceptions on Book3E v4: - Fix resend of doorbells on return from interrupt on Book3E v5: - Rebased on top of my latest series, which involves some significant rework of some aspects of the patch. --- arch/powerpc/include/asm/exception-64s.h| 29 ++- arch/powerpc/include/asm/hw_irq.h | 49 +- arch/powerpc/include/asm/irqflags.h | 16 -- arch/powerpc/include/asm/paca.h |2 +- arch/powerpc/kernel/asm-offsets.c |2 +- arch/powerpc/kernel/dbell.c |2 + arch/powerpc/kernel/entry_64.S | 154 arch/powerpc/kernel/exceptions-64e.S| 224 +++ arch/powerpc/kernel/exceptions-64s.S| 150 ++- arch/powerpc/kernel/head_64.S | 24 ++- arch/powerpc/kernel/idle.c |6 +- arch/powerpc/kernel/idle_book3e.S | 25 +-- arch/powerpc/kernel/idle_power4.S | 24 ++- arch/powerpc/kernel/idle_power7.S | 17 ++- arch/powerpc/kernel/irq.c | 204 +++-- arch/powerpc/kernel/process.c | 26 +++ arch/powerpc/kernel/time.c |8 +- arch/powerpc/platforms/pseries/processor_idle.c | 18 ++- arch/powerpc/xmon/xmon.c|4 +- 19 files changed, 652 insertions(+), 332 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 70354af..3066341 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -232,23 +232,30 @@ label##_hv: \ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common,\ EXC_HV, KVMTEST, vec) -#define __SOFTEN_TEST(h) \ +/* This associate vector numbers with bits in paca-irq_happened */ +#define SOFTEN_VALUE_0x500 PACA_IRQ_EE +#define
[PATCH 07/12] powerpc: Call do_page_fault() with interrupts off
We currently turn interrupts back to their previous state before
calling do_page_fault(). This can be annoying when debugging as
a bad fault will potentially have lost some processor state before
getting into the debugger.
We also end up calling some generic code with interrupts enabled
such as notify_page_fault() with interrupts enabled, which could
be unexpected.
This changes our code to behave more like other architectures,
and make the assembly entry code call into do_page_faults() with
interrupts disabled. They are conditionally re-enabled from
within do_page_fault() in the same spot x86 does it.
While there, add the might_sleep() test in the case of a successful
trylock of the mmap semaphore, again like x86.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/hw_irq.h| 10 +
arch/powerpc/kernel/exceptions-64e.S |5 +--
arch/powerpc/kernel/exceptions-64s.S | 61 ++---
arch/powerpc/kernel/head_32.S|4 +-
arch/powerpc/kernel/head_40x.S |4 +-
arch/powerpc/kernel/head_8xx.S |4 +-
arch/powerpc/kernel/head_booke.h |4 +-
arch/powerpc/kernel/head_fsl_booke.S |2 +-
arch/powerpc/mm/fault.c | 11 ++
9 files changed, 51 insertions(+), 54 deletions(-)
diff --git a/arch/powerpc/include/asm/hw_irq.h
b/arch/powerpc/include/asm/hw_irq.h
index bb712c9..531ba00 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -79,6 +79,11 @@ static inline bool arch_irqs_disabled(void)
get_paca()-hard_enabled = 0; \
} while(0)
+static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
+{
+ return !regs-softe;
+}
+
#else /* CONFIG_PPC64 */
#define SET_MSR_EE(x) mtmsr(x)
@@ -139,6 +144,11 @@ static inline bool arch_irqs_disabled(void)
#define hard_irq_disable() arch_local_irq_disable()
+static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
+{
+ return !(regs-msr MSR_EE);
+}
+
#endif /* CONFIG_PPC64 */
#define ARCH_IRQ_INIT_FLAGSIRQ_NOREQUEST
diff --git a/arch/powerpc/kernel/exceptions-64e.S
b/arch/powerpc/kernel/exceptions-64e.S
index 01095e6..9d437b9 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -313,7 +313,7 @@ interrupt_end_book3e:
NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
mfspr r14,SPRN_DEAR
mfspr r15,SPRN_ESR
- EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
+ EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE_ALL)
b storage_fault_common
/* Instruction Storage Interrupt */
@@ -321,7 +321,7 @@ interrupt_end_book3e:
NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
li r15,0
mr r14,r10
- EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
+ EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE_ALL)
b storage_fault_common
/* External Input Interrupt */
@@ -589,7 +589,6 @@ storage_fault_common:
mr r5,r15
ld r14,PACA_EXGEN+EX_R14(r13)
ld r15,PACA_EXGEN+EX_R15(r13)
- INTS_RESTORE_HARD
bl .do_page_fault
cmpdi r3,0
bne-1f
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index bd30fc2..bd7130c 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -559,6 +559,7 @@ data_access_common:
mfspr r10,SPRN_DSISR
stw r10,PACA_EXGEN+EX_DSISR(r13)
EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
+ DISABLE_INTS
ld r3,PACA_EXGEN+EX_DAR(r13)
lwz r4,PACA_EXGEN+EX_DSISR(r13)
li r5,0x300
@@ -573,6 +574,7 @@ h_data_storage_common:
stw r10,PACA_EXGEN+EX_DSISR(r13)
EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
bl .save_nvgprs
+ DISABLE_INTS
addir3,r1,STACK_FRAME_OVERHEAD
bl .unknown_exception
b .ret_from_except
@@ -581,6 +583,11 @@ h_data_storage_common:
.globl instruction_access_common
instruction_access_common:
EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
+ DISABLE_INTS
+#ifdef CONFIG_TRACE_IRQFLAGS
+ /* Restore r12 clobbered by DISABLE_INTS */
+ ld r12,_MSR(r1)
+#endif
ld r3,_NIP(r1)
andis. r4,r12,0x5820
li r5,0x400
@@ -884,24 +891,6 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
lwz r0,TI_PREEMPT(r11) /* If we're in an NMI */
andis. r0,r0,NMI_MASK@h/* (i.e. an irq when soft-disabled) */
bne 77f /* then don't call hash_page now */
-
- /* We run with interrupts both soft and hard disabled */
- DISABLE_INTS
-
- /*
-* Currently, trace_hardirqs_off() will be called by DISABLE_INTS
-* and will clobber volatile registers when irq tracing is
[PATCH 09/12] powerpc/xmon: Add display of soft hard irq states
Also use local_paca instead of get_paca() to avoid getting into
the smp_processor_id() debugging code from the debugger
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/xmon/xmon.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index cb95eea..63846eb 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1437,7 +1437,8 @@ static void excprint(struct pt_regs *fp)
printf( current = 0x%lx\n, current);
#ifdef CONFIG_PPC64
- printf( paca= 0x%lx\n, get_paca());
+ printf( paca= 0x%lx\t softe: %d\t harde: %d\n,
+ local_paca, local_paca-soft_enabled, local_paca-hard_enabled);
#endif
if (current) {
printf(pid = %ld, comm = %s\n,
@@ -1641,7 +1642,7 @@ static void super_regs(void)
/* Dump out relevant Paca data areas. */
printf(Paca: \n);
- ptrPaca = get_paca();
+ ptrPaca = local_paca;
printf( Local Processor Control Area (LpPaca): \n);
ptrLpPaca = ptrPaca-lppaca_ptr;
@@ -2644,7 +2645,7 @@ static void dump_slb(void)
static void dump_stab(void)
{
int i;
- unsigned long *tmp = (unsigned long *)get_paca()-stab_addr;
+ unsigned long *tmp = (unsigned long *)local_paca-stab_addr;
printf(Segment table contents of cpu %x\n, smp_processor_id());
--
1.7.9
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[PATCH 01/12] powerpc: Remove legacy iSeries bits from assembly files
This removes the various bits of assembly in the kernel entry, exception handling and SLB management code that were specific to running under the legacy iSeries hypervisor which is no longer supported. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h | 15 - arch/powerpc/kernel/entry_64.S | 42 +- arch/powerpc/kernel/exceptions-64s.S | 95 ++--- arch/powerpc/kernel/head_64.S| 44 ++ arch/powerpc/kernel/misc.S |1 - arch/powerpc/kernel/vmlinux.lds.S|5 -- arch/powerpc/mm/slb_low.S| 16 - 7 files changed, 15 insertions(+), 203 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 8057f4f..cc2bcf4 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -272,26 +272,11 @@ label##_hv: \ _MASKABLE_EXCEPTION_PSERIES(vec, label, \ EXC_HV, SOFTEN_TEST_HV) -#ifdef CONFIG_PPC_ISERIES -#define DISABLE_INTS \ - li r11,0; \ - stb r11,PACASOFTIRQEN(r13); \ -BEGIN_FW_FTR_SECTION; \ - stb r11,PACAHARDIRQEN(r13); \ -END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \ - TRACE_DISABLE_INTS; \ -BEGIN_FW_FTR_SECTION; \ - mfmsr r10;\ - ori r10,r10,MSR_EE; \ - mtmsrd r10,1; \ -END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) -#else #define DISABLE_INTS \ li r11,0; \ stb r11,PACASOFTIRQEN(r13); \ stb r11,PACAHARDIRQEN(r13); \ TRACE_DISABLE_INTS -#endif /* CONFIG_PPC_ISERIES */ #define ENABLE_INTS\ ld r12,_MSR(r1); \ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 866462c..0c3764b 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -127,17 +127,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) stb r10,PACASOFTIRQEN(r13) stb r10,PACAHARDIRQEN(r13) std r10,SOFTE(r1) -#ifdef CONFIG_PPC_ISERIES -BEGIN_FW_FTR_SECTION - /* Hack for handling interrupts when soft-enabling on iSeries */ - cmpdi cr1,r0,0x /* syscall 0x */ - andi. r10,r12,MSR_PR /* from kernel */ - crand 4*cr0+eq,4*cr1+eq,4*cr0+eq - bne 2f - b hardware_interrupt_entry -2: -END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) -#endif /* CONFIG_PPC_ISERIES */ /* Hard enable interrupts */ #ifdef CONFIG_PPC_BOOK3E @@ -591,15 +580,10 @@ _GLOBAL(ret_from_except_lite) ld r4,TI_FLAGS(r9) andi. r0,r4,_TIF_USER_WORK_MASK bne do_work -#endif +#endif /* !CONFIG_PREEMPT */ restore: -BEGIN_FW_FTR_SECTION ld r5,SOFTE(r1) -FW_FTR_SECTION_ELSE - b .Liseries_check_pending_irqs -ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES) -2: TRACE_AND_RESTORE_IRQ(r5); /* extract EE bit and use it to restore paca-hard_enabled */ @@ -669,30 +653,6 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) #endif /* CONFIG_PPC_BOOK3E */ -.Liseries_check_pending_irqs: -#ifdef CONFIG_PPC_ISERIES - ld r5,SOFTE(r1) - cmpdi 0,r5,0 - beq 2b - /* Check for pending interrupts (iSeries) */ - ld r3,PACALPPACAPTR(r13) - ld r3,LPPACAANYINT(r3) - cmpdi r3,0 - beq+2b /* skip do_IRQ if no interrupts */ - - li r3,0 - stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */ -#ifdef CONFIG_TRACE_IRQFLAGS - bl .trace_hardirqs_off - mfmsr r10 -#endif - ori r10,r10,MSR_EE - mtmsrd r10 /* hard-enable again */ - addir3,r1,STACK_FRAME_OVERHEAD - bl .do_IRQ - b .ret_from_except_lite /* loop back and handle more */ -#endif - do_work: #ifdef CONFIG_PREEMPT andi. r0,r3,MSR_PR/* Returning to user mode? */ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 15c5a4f..fea8a69 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -19,7 +19,7 @@ * We layout physical memory as follows: * 0x - 0x00ff : Secondary processor spin code * 0x0100 - 0x2fff : pSeries Interrupt prologs - * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs + * 0x3000 - 0x5fff : interrupt
[PATCH 11/12] powerpc: Replace mfmsr instructions with load from PACA kernel_msr field
On 64-bit, the mfmsr instruction can be quite slow, slower than loading a field from the cache-hot PACA, which happens to already contain the value we want in most cases. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h |2 +- arch/powerpc/include/asm/hw_irq.h|4 ++-- arch/powerpc/kernel/entry_64.S | 14 +- arch/powerpc/kernel/exceptions-64s.S |5 ++--- 4 files changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 7f4718c..70354af 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -298,7 +298,7 @@ label##_hv: \ /* Exception addition: Keep interrupt state */ #define ENABLE_INTS\ - mfmsr r11;\ + ld r11,PACAKMSR(r13); \ ld r12,_MSR(r1); \ rlwimi r11,r12,0,MSR_EE; \ mtmsrd r11,1 diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index 531ba00..6c6fa95 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -68,8 +68,8 @@ static inline bool arch_irqs_disabled(void) #define __hard_irq_enable()asm volatile(wrteei 1 : : : memory); #define __hard_irq_disable() asm volatile(wrteei 0 : : : memory); #else -#define __hard_irq_enable()__mtmsrd(mfmsr() | MSR_EE, 1) -#define __hard_irq_disable() __mtmsrd(mfmsr() ~MSR_EE, 1) +#define __hard_irq_enable()__mtmsrd(local_paca-kernel_msr | MSR_EE, 1) +#define __hard_irq_disable() __mtmsrd(local_paca-kernel_msr, 1) #endif #define hard_irq_disable()\ diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index cc030b7..c513beb 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -557,10 +557,8 @@ _GLOBAL(ret_from_except_lite) #ifdef CONFIG_PPC_BOOK3E wrteei 0 #else - mfmsr r10 /* Get current interrupt state */ - rldicl r9,r10,48,1 /* clear MSR_EE */ - rotldi r9,r9,16 - mtmsrd r9,1/* Update machine state */ + ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ + mtmsrd r10,1 /* Update machine state */ #endif /* CONFIG_PPC_BOOK3E */ #ifdef CONFIG_PREEMPT @@ -625,8 +623,8 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) * userspace and we take an exception after restoring r13, * we end up corrupting the userspace r13 value. */ - mfmsr r4 - andcr4,r4,r0/* r0 contains MSR_RI here */ + ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */ + andcr4,r4,r0 /* r0 contains MSR_RI here */ mtmsrd r4,1 /* @@ -686,9 +684,7 @@ do_work: #ifdef CONFIG_PPC_BOOK3E wrteei 0 #else - mfmsr r10 - rldicl r10,r10,48,1 - rotldi r10,r10,16 + ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ mtmsrd r10,1 #endif /* CONFIG_PPC_BOOK3E */ li r0,0 diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index bd7130c..880f360 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -850,9 +850,8 @@ fast_exception_return: REST_GPR(0, r1) REST_8GPRS(2, r1) - mfmsr r10 - rldicl r10,r10,48,1/* clear EE */ - rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ + ld r10,PACAKMSR(r13) + clrrdi r10,r10,2 /* clear RI */ mtmsrd r10,1 mtspr SPRN_SRR1,r12 -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 08/12] powerpc: Add support for page fault retry and fatal signals
Other architectures such as x86 and ARM have been growing
new support for features like retrying page faults after
dropping the mm semaphore to break contention, or being
able to return from a stuck page fault when a SIGKILL is
pending.
This refactors our implementation of do_page_fault() to
move the error handling out of line in a way similar to
x86 and adds support for those two features.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/mm/fault.c | 170 +--
1 files changed, 120 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 7e89006..19f2f94 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -105,6 +105,82 @@ static int store_updates_sp(struct pt_regs *regs)
}
return 0;
}
+/*
+ * do_page_fault error handling helpers
+ */
+
+#define MM_FAULT_RETURN0
+#define MM_FAULT_CONTINUE -1
+#define MM_FAULT_ERR(sig) (sig)
+
+static int out_of_memory(struct pt_regs *regs)
+{
+ /*
+* We ran out of memory, or some other thing happened to us that made
+* us unable to handle the page fault gracefully.
+*/
+ up_read(current-mm-mmap_sem);
+ if (!user_mode(regs))
+ return MM_FAULT_ERR(SIGKILL);
+ pagefault_out_of_memory();
+ return MM_FAULT_RETURN;
+}
+
+static int do_sigbus(struct pt_regs *regs, unsigned long address)
+{
+ siginfo_t info;
+
+ up_read(current-mm-mmap_sem);
+
+ if (user_mode(regs)) {
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = BUS_ADRERR;
+ info.si_addr = (void __user *)address;
+ force_sig_info(SIGBUS, info, current);
+ return MM_FAULT_RETURN;
+ }
+ return MM_FAULT_ERR(SIGBUS);
+}
+
+static int mm_fault_error(struct pt_regs *regs, unsigned long addr, int fault)
+{
+ /*
+* Pagefault was interrupted by SIGKILL. We have no reason to
+* continue the pagefault.
+*/
+ if (fatal_signal_pending(current)) {
+ /*
+* If we have retry set, the mmap semaphore will have
+* alrady been released in __lock_page_or_retry(). Else
+* we release it now.
+*/
+ if (!(fault VM_FAULT_RETRY))
+ up_read(current-mm-mmap_sem);
+ /* Coming from kernel, we need to deal with uaccess fixups */
+ if (user_mode(regs))
+ return MM_FAULT_RETURN;
+ return MM_FAULT_ERR(SIGKILL);
+ }
+
+ /* No fault: be happy */
+ if (!(fault VM_FAULT_ERROR))
+ return MM_FAULT_CONTINUE;
+
+ /* Out of memory */
+ if (fault VM_FAULT_OOM)
+ return out_of_memory(regs);
+
+ /* Bus error. x86 handles HWPOISON here, we'll add this if/when
+* we support the feature in HW
+*/
+ if (fault VM_FAULT_SIGBUS)
+ return do_sigbus(regs, addr);
+
+ /* We don't understand the fault code, this is fatal */
+ BUG();
+ return MM_FAULT_CONTINUE;
+}
/*
* For 600- and 800-family processors, the error_code parameter is DSISR
@@ -124,11 +200,12 @@ int __kprobes do_page_fault(struct pt_regs *regs,
unsigned long address,
{
struct vm_area_struct * vma;
struct mm_struct *mm = current-mm;
- siginfo_t info;
+ unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
int code = SEGV_MAPERR;
- int is_write = 0, ret;
+ int is_write = 0;
int trap = TRAP(regs);
int is_exec = trap == 0x400;
+ int fault;
#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
/*
@@ -145,6 +222,9 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned
long address,
is_write = error_code ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+ if (is_write)
+ flags |= FAULT_FLAG_WRITE;
+
#ifdef CONFIG_PPC_ICSWX
/*
* we need to do this early because this data storage
@@ -152,13 +232,11 @@ int __kprobes do_page_fault(struct pt_regs *regs,
unsigned long address,
* look at it
*/
if (error_code ICSWX_DSI_UCT) {
- int ret;
-
- ret = acop_handle_fault(regs, address, error_code);
- if (ret)
- return ret;
+ int rc = acop_handle_fault(regs, address, error_code);
+ if (rc)
+ return rc;
}
-#endif
+#endif /* CONFIG_PPC_ICSWX */
if (notify_page_fault(regs))
return 0;
@@ -216,6 +294,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned
long address,
if (!user_mode(regs) !search_exception_tables(regs-nip))
goto bad_area_nosemaphore;
+retry:
[PATCH 06/12] powerpc: Disable interrupts in 64-bit kernel FP and vector faults
If we get a floating point, altivec or vsx unavaible interrupt in kernel, we trigger a kernel error. There is no point preserving the interrupt state, in fact, that can even make debugging harder as the processor state might change (we may even preempt) between taking the exception and landing in a debugger. So just make those 3 disable interrupts unconditionally. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/kernel/exceptions-64e.S |8 +++- arch/powerpc/kernel/exceptions-64s.S |6 +++--- arch/powerpc/kernel/traps.c |3 +++ 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S index 429983c..01095e6 100644 --- a/arch/powerpc/kernel/exceptions-64e.S +++ b/arch/powerpc/kernel/exceptions-64e.S @@ -352,11 +352,10 @@ interrupt_end_book3e: START_EXCEPTION(fp_unavailable); NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE) /* we can probably do a shorter exception entry for that one... */ - EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP) + EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_DISABLE_ALL) bne 1f /* if from user, just load it up */ bl .save_nvgprs addir3,r1,STACK_FRAME_OVERHEAD - INTS_RESTORE_HARD bl .kernel_fp_unavailable_exception BUG_OPCODE 1: ld r12,_MSR(r1) @@ -391,10 +390,9 @@ interrupt_end_book3e: /* Auxiliary Processor Unavailable Interrupt */ START_EXCEPTION(ap_unavailable); NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE) - EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP) - addir3,r1,STACK_FRAME_OVERHEAD + EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE_ALL) bl .save_nvgprs - INTS_RESTORE_HARD + addir3,r1,STACK_FRAME_OVERHEAD bl .unknown_exception b .ret_from_except diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 3af80e8..bd30fc2 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -757,8 +757,8 @@ fp_unavailable_common: EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) bne 1f /* if from user, just load it up */ bl .save_nvgprs + DISABLE_INTS addir3,r1,STACK_FRAME_OVERHEAD - ENABLE_INTS bl .kernel_fp_unavailable_exception BUG_OPCODE 1: bl .load_up_fpu @@ -777,8 +777,8 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) #endif bl .save_nvgprs + DISABLE_INTS addir3,r1,STACK_FRAME_OVERHEAD - ENABLE_INTS bl .altivec_unavailable_exception b .ret_from_except @@ -793,8 +793,8 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_VSX) #endif bl .save_nvgprs + DISABLE_INTS addir3,r1,STACK_FRAME_OVERHEAD - ENABLE_INTS bl .vsx_unavailable_exception b .ret_from_except diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 5d40e59..a750409 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -247,6 +247,9 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) addr, regs-nip, regs-link, code); } + if (!arch_irq_disabled_regs(regs)) + local_irq_enable(); + memset(info, 0, sizeof(info)); info.si_signo = signr; info.si_code = code; -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 04/12] powerpc: Improve 64-bit syscall entry/exit
We unconditionally hard enable interrupts. This is unnecessary as syscalls are expected to always be called with interrupts enabled. While at it, we add a WARN_ON if that is not the case and CONFIG_TRACE_IRQFLAGS is enabled (we don't want to add overhead to the fast path when this is not set though). Thus let's remove the enabling (and associated irq tracing) from the syscall entry path. Also on Book3S, replace a few mfmsr instructions with loads of PACAMSR from the PACA, which should be faster schedule better. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/kernel/entry_64.S | 43 +-- 1 files changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 0c3764b..cc030b7 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -115,28 +115,33 @@ BEGIN_FW_FTR_SECTION END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) #endif /* CONFIG_VIRT_CPU_ACCOUNTING CONFIG_PPC_SPLPAR */ -#ifdef CONFIG_TRACE_IRQFLAGS - bl .trace_hardirqs_on - REST_GPR(0,r1) - REST_4GPRS(3,r1) - REST_2GPRS(7,r1) - addir9,r1,STACK_FRAME_OVERHEAD - ld r12,_MSR(r1) -#endif /* CONFIG_TRACE_IRQFLAGS */ - li r10,1 - stb r10,PACASOFTIRQEN(r13) - stb r10,PACAHARDIRQEN(r13) - std r10,SOFTE(r1) + /* +* A syscall should always be called with interrupts enabled +* so we just unconditionally hard-enable here. When some kind +* of irq tracing is used, we additionally check that condition +* is correct +*/ +#if defined(CONFIG_TRACE_IRQFLAGS) defined(CONFIG_BUG) + lbz r10,PACASOFTIRQEN(r13) + xorir10,r10,1 +1: tdnei r10,0 + EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING +#endif - /* Hard enable interrupts */ #ifdef CONFIG_PPC_BOOK3E wrteei 1 #else - mfmsr r11 + ld r11,PACAKMSR(r13) ori r11,r11,MSR_EE mtmsrd r11,1 #endif /* CONFIG_PPC_BOOK3E */ + /* We do need to set SOFTE in the stack frame or the return +* from interrupt will be painful +*/ + li r10,1 + std r10,SOFTE(r1) + #ifdef SHOW_SYSCALLS bl .do_show_syscall REST_GPR(0,r1) @@ -187,16 +192,14 @@ syscall_exit: andi. r10,r8,MSR_RI beq-unrecov_restore #endif - - /* Disable interrupts so current_thread_info()-flags can't change, + /* +* Disable interrupts so current_thread_info()-flags can't change, * and so that we don't get interrupted after loading SRR0/1. */ #ifdef CONFIG_PPC_BOOK3E wrteei 0 #else - mfmsr r10 - rldicl r10,r10,48,1 - rotldi r10,r10,16 + ld r10,PACAKMSR(r13) mtmsrd r10,1 #endif /* CONFIG_PPC_BOOK3E */ @@ -308,7 +311,7 @@ syscall_exit_work: #ifdef CONFIG_PPC_BOOK3E wrteei 1 #else - mfmsr r10 + ld r10,PACAKMSR(r13) ori r10,r10,MSR_EE mtmsrd r10,1 #endif /* CONFIG_PPC_BOOK3E */ -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 00/12] powerpc: Low level spring cleaning
This series goes through various bits and pieces of our exception and interrupts handling, fixin bugs, cleaning up code, adding missing functionality, etc... The last patch of the series is a reworked variant of my lazy irq rework. This needs a good review as it touches pretty nasty bits of code and more testing obviously. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 05/12] powerpc: Improve behaviour of irq tracing on 64-bit exception entry
Some exceptions would unconditionally disable interrupts on entry, which is fine, but calling lockdep every time not only adds more overhead than strictly needed, but also means we get quite a few redudant disable logged, which makes it hard to spot the really bad ones. So instead, split the macro used by the exception code into a normal one and a separate one used when CONFIG_TRACE_IRQFLAGS is enabled, and make the later skip th tracing if interrupts were already disabled. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h | 25 ++--- 1 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index bdc9eeb..7f4718c 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -272,15 +272,34 @@ label##_hv: \ _MASKABLE_EXCEPTION_PSERIES(vec, label, \ EXC_HV, SOFTEN_TEST_HV) +/* + * Our exception common code can be passed various additions + * to specify the behaviour of interrupts, whether to kick the + * runlatch, etc... + */ + +/* Exception addition: Hard disable interrupts */ +#ifdef CONFIG_TRACE_IRQFLAGS #define DISABLE_INTS \ + lbz r10,PACASOFTIRQEN(r13); \ li r11,0; \ - stb r11,PACASOFTIRQEN(r13); \ + cmpwi cr0,r10,0; \ stb r11,PACAHARDIRQEN(r13); \ - TRACE_DISABLE_INTS + beq 44f;\ + stb r11,PACASOFTIRQEN(r13); \ + TRACE_DISABLE_INTS; \ +44: +#else +#define DISABLE_INTS \ + li r11,0; \ + stb r11,PACASOFTIRQEN(r13); \ + stb r11,PACAHARDIRQEN(r13) +#endif /* CONFIG_TRACE_IRQFLAGS */ +/* Exception addition: Keep interrupt state */ #define ENABLE_INTS\ - ld r12,_MSR(r1); \ mfmsr r11;\ + ld r12,_MSR(r1); \ rlwimi r11,r12,0,MSR_EE; \ mtmsrd r11,1 -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 02/12] powerpc: Use the same interrupt prolog for perfmon as other interrupts
The perfmon interrupt is the sole user of a special variant of the interrupt prolog which differs from the one used by external and timer interrupts in that it saves the non-volatile GPRs and doesn't turn the runlatch on. The former is unnecessary and the later is arguably incorrect, so let's clean that up by using the same prolog. While at it we rename that prolog to use the _ASYNC prefix. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- arch/powerpc/include/asm/exception-64s.h | 17 +++-- arch/powerpc/kernel/exceptions-64s.S |6 +++--- 2 files changed, 6 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index cc2bcf4..041b222 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -297,21 +297,10 @@ label##_common: \ /* * Like STD_EXCEPTION_COMMON, but for exceptions that can occur - * in the idle task and therefore need the special idle handling. + * in the idle task and therefore need the special idle handling + * (finish nap and runlatch) */ -#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \ - .align 7; \ - .globl label##_common; \ -label##_common:\ - EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ - FINISH_NAP; \ - DISABLE_INTS; \ - bl .save_nvgprs; \ - addir3,r1,STACK_FRAME_OVERHEAD; \ - bl hdlr; \ - b .ret_from_except - -#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ +#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ .align 7; \ .globl label##_common; \ label##_common:\ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index fea8a69..2240d4e 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -458,15 +458,15 @@ machine_check_common: bl .machine_check_exception b .ret_from_except - STD_EXCEPTION_COMMON_LITE(0x500, hardware_interrupt, do_IRQ) - STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) + STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ) + STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt) STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) - STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception) + STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception) STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) #ifdef CONFIG_ALTIVEC STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) -- 1.7.9 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/srio: Fix the compile errors when building with 64bit
For the file arch/powerpc/sysdev/fsl_rmu.c, there will be some compile errors while using the corenet64_smp_defconfig: I'm sure that replacing 'u32' with 'unsigned long' is really the best thing to do here. It looks to me as though they should be some pointer type. David ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] PPC: Don't sync timebase when inside VM
When running inside a virtual machine, we can not modify timebase, so
let's just not call the functions for it then.
This resolves hangs when booting e500 SMP guests on overcommitted hosts.
Reported-by: Stuart Yoder b08...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/platforms/85xx/smp.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..d4b6c1f 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -249,6 +249,13 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
}
+ /* When running under a hypervisor, we can not modify tb */
+ np = of_find_node_by_path(/hypervisor);
+ if (np) {
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+ }
+
smp_ops = smp_85xx_ops;
#ifdef CONFIG_KEXEC
--
1.6.0.2
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Re: [PATCH] powerpc/srio: Fix the compile errors when building with 64bit
On 12-03-02 02:08 AM, Liu Gang wrote:
For the file arch/powerpc/sysdev/fsl_rmu.c, there will be some compile
errors while using the corenet64_smp_defconfig:
.../fsl_rmu.c:315: error: cast from pointer to integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:330: error: cast to pointer from integer of different size
.../fsl_rmu.c:332: error: cast to pointer from integer of different size
.../fsl_rmu.c:339: error: cast to pointer from integer of different size
.../fsl_rmu.c:340: error: cast to pointer from integer of different size
.../fsl_rmu.c:341: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:659: error: cast from pointer to integer of different size
.../fsl_rmu.c:659: error: format '%8.8x' expects type 'unsigned int',
but argument 5 has type 'size_t'
.../fsl_rmu.c:985: error: cast from pointer to integer of different size
.../fsl_rmu.c:997: error: cast to pointer from integer of different size
Rewrote the corresponding code with the support of 64bit building.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
Hi Liu,
You can't just go adding a Signed-off-by: line for me to a patch that
I've never seen before. Perhaps you meant to add Reported-by: ?
Paul.
--
---
arch/powerpc/sysdev/fsl_rmu.c | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 1548578..468011e 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -311,8 +311,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
/* XXX Need to check/dispatch until queue empty */
if (dsr DOORBELL_DSR_DIQI) {
- u32 dmsg =
- (u32) fsl_dbell-dbell_ring.virt +
+ unsigned long dmsg =
+ (unsigned long) fsl_dbell-dbell_ring.virt +
(in_be32(fsl_dbell-dbell_regs-dqdpar) 0xfff);
struct rio_dbell *dbell;
int found = 0;
@@ -657,7 +657,8 @@ fsl_add_outb_message(struct rio_mport *mport, struct
rio_dev *rdev, int mbox,
int ret = 0;
pr_debug(RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer \
- %8.8x len %8.8x\n, rdev-destid, mbox, (int)buffer, len);
+ %8.8lx len %8.8zx\n, rdev-destid, mbox,
+ (unsigned long)buffer, len);
if ((len 8) || (len RIO_MAX_MSG_SIZE)) {
ret = -EINVAL;
goto out;
@@ -972,7 +973,7 @@ out:
void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
{
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
- u32 phys_buf, virt_buf;
+ unsigned long phys_buf, virt_buf;
void *buf = NULL;
int buf_idx;
@@ -982,7 +983,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int
mbox)
if (phys_buf == in_be32(rmu-msg_regs-ifqepar))
goto out2;
- virt_buf = (u32) rmu-msg_rx_ring.virt + (phys_buf
+ virt_buf = (unsigned long) rmu-msg_rx_ring.virt + (phys_buf
- rmu-msg_rx_ring.phys);
buf_idx = (phys_buf - rmu-msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
buf = rmu-msg_rx_ring.virt_buffer[buf_idx];
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Re: [PATCH] powerpc/srio: Fix the compile errors when building with 64bit
On Mar 2, 2012, at 1:08 AM, Liu Gang wrote:
For the file arch/powerpc/sysdev/fsl_rmu.c, there will be some compile
errors while using the corenet64_smp_defconfig:
.../fsl_rmu.c:315: error: cast from pointer to integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer of different size
.../fsl_rmu.c:330: error: cast to pointer from integer of different size
.../fsl_rmu.c:332: error: cast to pointer from integer of different size
.../fsl_rmu.c:339: error: cast to pointer from integer of different size
.../fsl_rmu.c:340: error: cast to pointer from integer of different size
.../fsl_rmu.c:341: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:348: error: cast to pointer from integer of different size
.../fsl_rmu.c:659: error: cast from pointer to integer of different size
.../fsl_rmu.c:659: error: format '%8.8x' expects type 'unsigned int',
but argument 5 has type 'size_t'
.../fsl_rmu.c:985: error: cast from pointer to integer of different size
.../fsl_rmu.c:997: error: cast to pointer from integer of different size
Rewrote the corresponding code with the support of 64bit building.
Signed-off-by: Liu Gang gang@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
arch/powerpc/sysdev/fsl_rmu.c | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 1548578..468011e 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -311,8 +311,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
/* XXX Need to check/dispatch until queue empty */
if (dsr DOORBELL_DSR_DIQI) {
- u32 dmsg =
- (u32) fsl_dbell-dbell_ring.virt +
+ unsigned long dmsg =
+ (unsigned long) fsl_dbell-dbell_ring.virt +
(in_be32(fsl_dbell-dbell_regs-dqdpar) 0xfff);
struct rio_dbell *dbell;
int found = 0;
@@ -657,7 +657,8 @@ fsl_add_outb_message(struct rio_mport *mport, struct
rio_dev *rdev, int mbox,
int ret = 0;
pr_debug(RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer \
- %8.8x len %8.8x\n, rdev-destid, mbox, (int)buffer, len);
+ %8.8lx len %8.8zx\n, rdev-destid, mbox,
+ (unsigned long)buffer, len);
if ((len 8) || (len RIO_MAX_MSG_SIZE)) {
ret = -EINVAL;
goto out;
For this case it seems as if some cast should be added to DBELL_* macros
@@ -972,7 +973,7 @@ out:
void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
{
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
- u32 phys_buf, virt_buf;
+ unsigned long phys_buf, virt_buf;
Do you really want to change phys_buf to an 'unsigned long'?
Should virt_buf really be void * here?
void *buf = NULL;
int buf_idx;
@@ -982,7 +983,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int
mbox)
if (phys_buf == in_be32(rmu-msg_regs-ifqepar))
goto out2;
- virt_buf = (u32) rmu-msg_rx_ring.virt + (phys_buf
+ virt_buf = (unsigned long) rmu-msg_rx_ring.virt + (phys_buf
- rmu-msg_rx_ring.phys);
buf_idx = (phys_buf - rmu-msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
buf = rmu-msg_rx_ring.virt_buffer[buf_idx];
The memcpy later could remove a cast if you make virt_buf a void *.
--
1.7.0.4
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Re: [PATCH] PPC: Don't sync timebase when inside VM
On Fri, Mar 02, 2012 at 03:12:33PM +0100, Alexander Graf wrote:
When running inside a virtual machine, we can not modify timebase, so
let's just not call the functions for it then.
This resolves hangs when booting e500 SMP guests on overcommitted hosts.
Reported-by: Stuart Yoder b08...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/platforms/85xx/smp.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..d4b6c1f 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -249,6 +249,13 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
}
+ /* When running under a hypervisor, we can not modify tb */
+ np = of_find_node_by_path(/hypervisor);
+ if (np) {
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+ }
+
smp_ops = smp_85xx_ops;
Again, for 85xx we should *never* sync the timebase in the kernel,
hypervisor or no.
-Scott
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Re: [PATCH] PPC: Don't sync timebase when inside VM
On 02.03.2012, at 17:20, Scott Wood wrote:
On Fri, Mar 02, 2012 at 03:12:33PM +0100, Alexander Graf wrote:
When running inside a virtual machine, we can not modify timebase, so
let's just not call the functions for it then.
This resolves hangs when booting e500 SMP guests on overcommitted hosts.
Reported-by: Stuart Yoder b08...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/platforms/85xx/smp.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..d4b6c1f 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -249,6 +249,13 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
}
+/* When running under a hypervisor, we can not modify tb */
+np = of_find_node_by_path(/hypervisor);
+if (np) {
+smp_85xx_ops.give_timebase = NULL;
+smp_85xx_ops.take_timebase = NULL;
+}
+
smp_ops = smp_85xx_ops;
Again, for 85xx we should *never* sync the timebase in the kernel,
hypervisor or no.
The code says if the kexec config option is enabled, do the sync. I'm fairly
sure it's there for a reason.
Git blame points to the following commit:
commit f933a41e419a954ef90605224e02c3ded78f3372
Author: Matthew McClintock m...@freescale.com
Date: Wed Jul 21 16:14:53 2010 -0500
powerpc/85xx: kexec for SMP 85xx BookE systems
Adds support for kexec on 85xx machines for the BookE platform.
Including support for SMP machines
Based off work from Maxim Uvarov muva...@mvista.com
Signed-off-by: Matthew McClintock m...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Alex
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Re: linux-next: boot failure for next-20120227 and later (pci tree related)
On Thu, Mar 1, 2012 at 11:06 PM, Stephen Rothwell s...@canb.auug.org.au wrote: Hi Jesse, Staring with next-20120227, one of my boot tests is failing like this: Hi Stephen, Thanks a lot for the test report and the bisection. I wish I had a machine to test on so I wouldn't have to bother you about it. Any chance you could point me at the complete before/after dmesg logs? There should be information about the PCI host bridge apertures and offsets in the after log. If that's not enough, we might need to collect new before/after logs with something like this (whitespace-mangled): --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -71,7 +71,7 @@ CFLAGS-$(CONFIG_PPC64):= -mminimal-toc -mtraceback=no -mcall-aixdesc CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple KBUILD_CPPFLAGS+= -Iarch/$(ARCH) KBUILD_AFLAGS += -Iarch/$(ARCH) -KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y) +KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y) -DDEBUG CPP= $(CC) -E $(KBUILD_CFLAGS) CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__ Freeing unused kernel memory: 488k freed modprobe used greatest stack depth: 10624 bytes left dracut: dracut-004-32.el6 udev: starting version 147 udevd (1161): /proc/1161/oom_adj is deprecated, please use /proc/1161/oom_score_adj instead. setfont used greatest stack depth: 10528 bytes left dracut: Starting plymouth daemon calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2689 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 9 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2701 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 20 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2713 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2725 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2737 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2749 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2761 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 7 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2773 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 7 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2785 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2797 initcall .wait_scan_init+0x0/0xc4 [scsi_wait_scan] returned 0 after 8 usecs calling .wait_scan_init+0x0/0xc4 [scsi_wait_scan] @ 2809 and eventually our test system decides the machine is dead. This is a PowerPC 970 based blade system (several other PowerPC based systems to not fail). A normal boot only shows .wait_scan_init being called once. (I have initcall_debug=y debug on the command line). I bisected this down to: commit 6c5705fec63d83eeb165fe61e34adc92ecc2ce75 Author: Bjorn Helgaas bhelg...@google.com Date: Thu Feb 23 20:19:03 2012 -0700 powerpc/PCI: get rid of device resource fixups Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. CC: Benjamin Herrenschmidt b...@kernel.crashing.org Signed-off-by: Bjorn Helgaas bhelg...@google.com The only seemingly relevant differences in the boot logs (good to bad) are: pci :03:02.0: supports D1 D2 +PCI: Cannot allocate resource region 0 of PCI bridge 1, will remap +PCI: Cannot allocate resource region 1 of PCI bridge 1, will remap +PCI: Cannot allocate resource region 0 of PCI bridge 6, will remap +PCI: Cannot allocate resource region 1 of PCI bridge 6, will remap +PCI: Cannot allocate resource region 0 of PCI bridge 3, will remap +PCI: Cannot allocate resource region 1 of PCI bridge 3, will remap +PCI: Cannot allocate resource region 0 of device :01:01.0, will remap +PCI: Cannot allocate resource region 2 of device :01:01.0, will remap +PCI: Cannot allocate resource region 6 of device :01:01.0, will remap +PCI: Cannot allocate resource region 0 of device :03:00.0, will remap +PCI: Cannot allocate resource region 0 of device :03:00.1, will remap +PCI: Cannot allocate resource region 0 of device :03:02.0, will remap +PCI: Cannot allocate resource region 1 of device :03:02.0, will remap +PCI: Cannot allocate resource region 2 of device :03:02.0, will remap +PCI: Cannot allocate resource region 6 of device :03:02.0, will remap +PCI: Cannot allocate resource region 0 of device :06:04.0, will remap +PCI: Cannot allocate resource region 2 of device :06:04.0, will remap +PCI: Cannot
Re: [PATCH] PPC: Don't sync timebase when inside VM
On 03/02/2012 10:30 AM, Alexander Graf wrote:
On 02.03.2012, at 17:20, Scott Wood wrote:
On Fri, Mar 02, 2012 at 03:12:33PM +0100, Alexander Graf wrote:
When running inside a virtual machine, we can not modify timebase, so
let's just not call the functions for it then.
This resolves hangs when booting e500 SMP guests on overcommitted hosts.
Reported-by: Stuart Yoder b08...@freescale.com
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/platforms/85xx/smp.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..d4b6c1f 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -249,6 +249,13 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
}
+ /* When running under a hypervisor, we can not modify tb */
+ np = of_find_node_by_path(/hypervisor);
+ if (np) {
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+ }
+
smp_ops = smp_85xx_ops;
Again, for 85xx we should *never* sync the timebase in the kernel,
hypervisor or no.
The code says if the kexec config option is enabled, do the sync. I'm
fairly sure it's there for a reason.
Sigh. I forgot about that. It's because instead of doing kexec the
simple way, we actually physically reset the core. We really shouldn't
do that. And we *really* shouldn't do it just because CONFIG_KEXEC is
defined, regardless of whether we're actually booting from kexec.
-Scott
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Re: [PATCH V3] fsl-sata: add support for interrupt coalsecing feature
On 02/28/2012 09:54 PM, Liu Qiang-B32616 wrote: Hi Jeff, Do you plan to apply it to upstream, or any suggestions? Thanks. This patch has been in libata-dev (and thus linux-next) for about 2 weeks... ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: linux-next: boot failure for next-20120227 and later (pci tree related)
On Fri, 2012-03-02 at 10:10 -0700, Bjorn Helgaas wrote: On Thu, Mar 1, 2012 at 11:06 PM, Stephen Rothwell s...@canb.auug.org.au wrote: Hi Jesse, Staring with next-20120227, one of my boot tests is failing like this: Hi Stephen, Thanks a lot for the test report and the bisection. I wish I had a machine to test on so I wouldn't have to bother you about it. Any chance you could point me at the complete before/after dmesg logs? There should be information about the PCI host bridge apertures and offsets in the after log. If that's not enough, we might need to collect new before/after logs with something like this (whitespace-mangled): Or give me a chance to dig :-) I'll have a look next week. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: linux-next: boot failure for next-20120227 and later (pci tree related)
Hi Bjorn, On Fri, 2 Mar 2012 10:10:02 -0700 Bjorn Helgaas bhelg...@google.com wrote: Thanks a lot for the test report and the bisection. I wish I had a machine to test on so I wouldn't have to bother you about it. That's OK. Any chance you could point me at the complete before/after dmesg logs? There should be information about the PCI host bridge apertures and offsets in the after log. I have put the logs up at http://ozlabs.org/~sfr/console-bad.log and console-good.log. They have been editted to set the initcall return timings to x usecs just for ease of diffing, otherwise verbatim. If that's not enough, we might need to collect new before/after logs with something like this (whitespace-mangled): I'll defer to Ben as to whether that would help as I don't have easy access to the machine until Monday anyway. -- Cheers, Stephen Rothwells...@canb.auug.org.au pgpcqRqvMJClN.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Sampling instruction pointer on PPC
Hello Carl, On 03/01/2012 06:45 PM, Carl E. Love wrote: Victor: The performance counter tools perf and OProfile capture the value of the instruction pointer at the time an interrupt occurs. The file arch/powerpc/oprofile/op_model_power4.c contains the OProfile interrupt handler used for Power 4, 5, 6, and 7. When the performance counters overflow, the instruction pointer (Program Counter) is stored in the SIAR register. The perf and OProfile interrupt handlers store the instruction address in their samples. These tools then use the addresses to create a histogram of where the processor was at the time of the interrupt. I am guessing you are hoping to collect something more like an raw sequence of addresses trying to trace where the processor was in time. That is exactly what I want to do. Basically I want to use IP sampling for detecting and keeping application phase changes. I am not aware of a way to read the value of the instruction pointer directly on the fly. But you could possibly emulate it by setting a program counter count value to 2^31 -1, enable the counter to count cycles, then read the SIAR value. You could do this each time you want to take a sample. It would require a couple reads/writes to registers. Note, the counter generates the interrupt to store the instruction pointer into the SIAR register when the most significant bit of the 32 bit HW count value changes from 0 to 1. You will need to then clear the interrupt, actually I would have to double check but I think the default interrupt handler that is enabled with Perf and OProfile are not running will do that quietly for you. Indeed this seems like it may do the trick. Just one question; from your description I assume that there is no support in the current implementation of perf (e.g., I know perf_event_read_value() is used to read the value of an event, but I cannot find any equivalent function that can write to a counter). I guess that means I need to implement that in the kernel myself, right? Not sure that helps. Carl Love Thank you! Victor On Thu, 2012-03-01 at 18:08 +0100, Victor Jimenez wrote: I am trying to sample instruction pointer along time on a Power7 system. I know that there are accurate mechanisms to do so in Intel processors (e.g., PEBS and Branch Trace Store). Is it possible to do something similar in Power7? Will the samples be accurate? I am worried that significant delays (skids) may appear. Thank you, Victor WARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received. http://www.bsc.es/disclaimer.htm -- To unsubscribe from this list: send the line unsubscribe linux-perf-users in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Victor Jimenez Perez Barcelona Supercomputing Center Centro Nacional de Supercomputacion WWW: http://www.bsc.es Tel: +34-934137167 e-mail: victor.jav...@bsc.es WARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received. http://www.bsc.es/disclaimer.htm___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Which ppc board ?
I'd like to replace my old pmac G4. Are there affordable ppc systems on the market today ? Perhaps some dev board with a p4080 or newer ? -- Giuliano. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
