[PATCH v3 1/4] Talitos: Support for async_tx XOR offload

2012-07-15 Thread Qiang Liu 
Expose Talitos's XOR functionality to be used for RAID parity
calculation via the Async_tx layer.

Cc: Herbert Xu 
Cc: David S. Miller 
Signed-off-by: Dipen Dudhat 
Signed-off-by: Maneesh Gupta 
Signed-off-by: Kim Phillips 
Signed-off-by: Vishnu Suresh 
Signed-off-by: Qiang Liu 
---
 drivers/crypto/Kconfig   |9 +
 drivers/crypto/talitos.c |  410 ++
 drivers/crypto/talitos.h |   53 ++
 3 files changed, 472 insertions(+), 0 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index be6b2ba..f0a7c29 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -222,6 +222,15 @@ config CRYPTO_DEV_TALITOS
  To compile this driver as a module, choose M here: the module
  will be called talitos.

+config CRYPTO_DEV_TALITOS_RAIDXOR
+   bool "Talitos RAID5 XOR Calculation Offload"
+   default y
+   select DMA_ENGINE
+   depends on CRYPTO_DEV_TALITOS
+   help
+ Say 'Y' here to use the Freescale Security Engine (SEC) to
+ offload RAID XOR parity Calculation
+
 config CRYPTO_DEV_IXP4XX
tristate "Driver for IXP4xx crypto hardware acceleration"
depends on ARCH_IXP4XX
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index efff788..1e0c9e6 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -619,6 +619,396 @@ static void talitos_unregister_rng(struct device *dev)
hwrng_unregister(&priv->rng);
 }

+#ifdef CONFIG_CRYPTO_DEV_TALITOS_RAIDXOR
+static void talitos_release_xor(struct device *dev, struct talitos_desc 
*hwdesc,
+   void *context, int error);
+
+static enum dma_status talitos_is_tx_complete(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
+{
+   struct talitos_xor_chan *xor_chan;
+   dma_cookie_t last_used;
+   dma_cookie_t last_complete;
+
+   xor_chan = container_of(chan, struct talitos_xor_chan, common);
+
+   last_used = chan->cookie;
+   last_complete = xor_chan->completed_cookie;
+
+   if (state->last)
+   state->last = last_complete;
+
+   if (state->used)
+   state->used = last_used;
+
+   return dma_async_is_complete(cookie, last_complete, last_used);
+}
+
+static void talitos_process_pending(struct talitos_xor_chan *xor_chan)
+{
+   struct talitos_xor_desc *desc, *_desc;
+   unsigned long flags;
+   int status;
+   struct talitos_private *priv;
+   int ch;
+
+   priv = dev_get_drvdata(xor_chan->dev);
+   ch = atomic_inc_return(&priv->last_chan) &
+ (priv->num_channels - 1);
+   spin_lock_irqsave(&xor_chan->desc_lock, flags);
+
+   list_for_each_entry_safe(desc, _desc, &xor_chan->pending_q, node) {
+   status = talitos_submit(xor_chan->dev, ch, &desc->hwdesc,
+   talitos_release_xor, desc);
+   if (status != -EINPROGRESS)
+   break;
+
+   list_del(&desc->node);
+   list_add_tail(&desc->node, &xor_chan->in_progress_q);
+   }
+
+   spin_unlock_irqrestore(&xor_chan->desc_lock, flags);
+}
+
+static void talitos_xor_run_tx_complete_actions(struct talitos_xor_desc *desc,
+   struct talitos_xor_chan *xor_chan)
+{
+   struct device *dev = xor_chan->dev;
+   dma_addr_t dest, addr;
+   unsigned int src_cnt = desc->unmap_src_cnt;
+   unsigned int len = desc->unmap_len;
+   enum dma_ctrl_flags flags = desc->async_tx.flags;
+   struct dma_async_tx_descriptor *tx = &desc->async_tx;
+
+   /* unmap dma addresses */
+   dest = desc->hwdesc.ptr[6].ptr;
+   if (likely(!(flags & DMA_COMPL_SKIP_DEST_UNMAP)))
+   dma_unmap_page(dev, dest, len, DMA_BIDIRECTIONAL);
+
+   desc->idx = 6 - src_cnt;
+   while(desc->idx < 6) {
+   addr = desc->hwdesc.ptr[desc->idx++].ptr;
+   if (likely(!(flags & DMA_COMPL_SKIP_SRC_UNMAP)))
+   dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
+   }
+
+   /* run dependent operations */
+   dma_run_dependencies(tx);
+}
+
+static void talitos_release_xor(struct device *dev, struct talitos_desc 
*hwdesc,
+   void *context, int error)
+{
+   struct talitos_xor_desc *desc = context;
+   struct talitos_xor_chan *xor_chan;
+   dma_async_tx_callback callback;
+   void *callback_param;
+
+   if (unlikely(error))
+   dev_err(dev, "xor operation: talitos error %d\n", error);
+
+   xor_chan = container_of(desc->async_tx.chan, struct talitos_xor_chan,
+   common);
+   spin_lock_bh(&xor_chan->desc_lock);
+   if (xor_chan->completed_cookie < desc->async_tx.cookie)
+   xor_chan->completed_cookie = desc->async_tx.cookie;
+
+

[PATCH v3 4/4] fsl-dma: use spin_lock_bh to instead of spin_lock_irqsave

2012-07-15 Thread Qiang Liu 
Use spin_lock_bh to instead of spin_lock_irqsave for improving performance.

Cc: Dan Williams 
Cc: Vinod Koul 
Cc: Li Yang 
Signed-off-by: Qiang Liu 
---
 drivers/dma/fsldma.c |   29 -
 1 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 4ee1b8f..e975719 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -616,10 +616,9 @@ static dma_cookie_t fsl_dma_tx_submit(struct 
dma_async_tx_descriptor *tx)
struct fsldma_chan *chan = to_fsl_chan(tx->chan);
struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
struct fsl_desc_sw *child;
-   unsigned long flags;
dma_cookie_t cookie;

-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);

/*
 * assign cookies to all of the software descriptors
@@ -632,7 +631,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct 
dma_async_tx_descriptor *tx)
/* put this transaction onto the tail of the pending queue */
append_ld_queue(chan, desc);

-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);

return cookie;
 }
@@ -741,15 +740,14 @@ static void fsldma_free_desc_list_reverse(struct 
fsldma_chan *chan,
 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
 {
struct fsldma_chan *chan = to_fsl_chan(dchan);
-   unsigned long flags;

chan_dbg(chan, "free all channel resources\n");
-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);
fsldma_cleanup_descriptor(chan);
fsldma_free_desc_list(chan, &chan->ld_pending);
fsldma_free_desc_list(chan, &chan->ld_running);
fsldma_free_desc_list(chan, &chan->ld_completed);
-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);

dma_pool_destroy(chan->desc_pool);
chan->desc_pool = NULL;
@@ -968,7 +966,6 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
 {
struct dma_slave_config *config;
struct fsldma_chan *chan;
-   unsigned long flags;
int size;

if (!dchan)
@@ -978,7 +975,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,

switch (cmd) {
case DMA_TERMINATE_ALL:
-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);

/* Halt the DMA engine */
dma_halt(chan);
@@ -988,7 +985,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
fsldma_free_desc_list(chan, &chan->ld_running);
chan->idle = true;

-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);
return 0;

case DMA_SLAVE_CONFIG:
@@ -1030,11 +1027,10 @@ static int fsl_dma_device_control(struct dma_chan 
*dchan,
 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
 {
struct fsldma_chan *chan = to_fsl_chan(dchan);
-   unsigned long flags;

-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);
fsl_chan_xfer_ld_queue(chan);
-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);
 }

 /**
@@ -1047,7 +1043,6 @@ static enum dma_status fsl_tx_status(struct dma_chan 
*dchan,
 {
struct fsldma_chan *chan = to_fsl_chan(dchan);
enum dma_status ret;
-   unsigned long flags;

ret = dma_cookie_status(dchan, cookie, txstate);
if (ret == DMA_SUCCESS) {
@@ -1055,9 +1050,9 @@ static enum dma_status fsl_tx_status(struct dma_chan 
*dchan,
return ret;
}

-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);
fsldma_cleanup_descriptor(chan);
-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);

return dma_cookie_status(dchan, cookie, txstate);
 }
@@ -1140,7 +1135,7 @@ static void dma_do_tasklet(unsigned long data)

chan_dbg(chan, "tasklet entry\n");

-   spin_lock_irqsave(&chan->desc_lock, flags);
+   spin_lock_bh(&chan->desc_lock);

/* Run all cleanup for this descriptor */
fsldma_cleanup_descriptor(chan);
@@ -1149,7 +1144,7 @@ static void dma_do_tasklet(unsigned long data)
chan->idle = true;

fsl_chan_xfer_ld_queue(chan);
-   spin_unlock_irqrestore(&chan->desc_lock, flags);
+   spin_unlock_bh(&chan->desc_lock);

chan_dbg(chan, "tasklet exit\n");
 }
--
1.7.5.1


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[PATCH v3 3/4] fsl-dma: change release process of dma descriptor for supporting async_tx

2012-07-15 Thread Qiang Liu 
Fix the potential risk when enable config NET_DMA and ASYNC_TX.
Async_tx is lack of support in current release process of dma descriptor,
all descriptors will be released whatever is acked or no-acked by async_tx,
so there is a potential race condition when dma engine is uesd by others
clients (e.g. when enable NET_DMA to offload TCP).

In our case, a race condition which is raised when use both of talitos
and dmaengine to offload xor is because napi scheduler will sync all
pending requests in dma channels, it affects the process of raid operations
due to ack_tx is not checked in fsl dma. The no-acked descriptor is freed
which is submitted just now, as a dependent tx, this freed descriptor trigger
BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit().

Cc: Dan Williams 
Cc: Vinod Koul 
Cc: Li Yang 
Cc: Ira W. Snyder 
Signed-off-by: Qiang Liu 
---
 drivers/dma/fsldma.c |  378 +
 drivers/dma/fsldma.h |1 +
 2 files changed, 225 insertions(+), 154 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 4f2f212..4ee1b8f 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -400,6 +400,217 @@ out_splice:
list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
 }

+/**
+ * fsl_chan_xfer_ld_queue - transfer any pending transactions
+ * @chan : Freescale DMA channel
+ *
+ * HARDWARE STATE: idle
+ * LOCKING: must hold chan->desc_lock
+ */
+static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
+{
+   struct fsl_desc_sw *desc;
+
+   /*
+* If the list of pending descriptors is empty, then we
+* don't need to do any work at all
+*/
+   if (list_empty(&chan->ld_pending)) {
+   chan_dbg(chan, "no pending LDs\n");
+   return;
+   }
+
+   /*
+* The DMA controller is not idle, which means that the interrupt
+* handler will start any queued transactions when it runs after
+* this transaction finishes
+*/
+   if (!chan->idle) {
+   chan_dbg(chan, "DMA controller still busy\n");
+   return;
+   }
+
+   /*
+* If there are some link descriptors which have not been
+* transferred, we need to start the controller
+*/
+
+   /*
+* Move all elements from the queue of pending transactions
+* onto the list of running transactions
+*/
+   chan_dbg(chan, "idle, starting controller\n");
+   desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
+   list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
+
+   /*
+* The 85xx DMA controller doesn't clear the channel start bit
+* automatically at the end of a transfer. Therefore we must clear
+* it in software before starting the transfer.
+*/
+   if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+   u32 mode;
+
+   mode = DMA_IN(chan, &chan->regs->mr, 32);
+   mode &= ~FSL_DMA_MR_CS;
+   DMA_OUT(chan, &chan->regs->mr, mode, 32);
+   }
+
+   /*
+* Program the descriptor's address into the DMA controller,
+* then start the DMA transaction
+*/
+   set_cdar(chan, desc->async_tx.phys);
+   get_cdar(chan);
+
+   dma_start(chan);
+   chan->idle = false;
+}
+
+static int
+fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
+{
+   struct fsl_desc_sw *desc, *_desc;
+
+   /* Run the callback for each descriptor, in order */
+   list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
+
+   if (async_tx_test_ack(&desc->async_tx)) {
+   /* Remove from the list of transactions */
+   list_del(&desc->node);
+#ifdef FSL_DMA_LD_DEBUG
+   chan_dbg(chan, "LD %p free\n", desc);
+#endif
+   dma_pool_free(chan->desc_pool, desc,
+   desc->async_tx.phys);
+   }
+   }
+
+   return 0;
+}
+
+/**
+ * fsldma_run_tx_complete_actions - cleanup and free a single link descriptor
+ * @chan: Freescale DMA channel
+ * @desc: descriptor to cleanup and free
+ * @cookie: Freescale DMA transaction identifier
+ *
+ * This function is used on a descriptor which has been executed by the DMA
+ * controller. It will run any callbacks, submit any dependencies, and then
+ * free the descriptor.
+ */
+static dma_cookie_t fsldma_run_tx_complete_actions(struct fsl_desc_sw *desc,
+   struct fsldma_chan *chan, dma_cookie_t cookie)
+{
+   struct dma_async_tx_descriptor *txd = &desc->async_tx;
+   struct device *dev = chan->common.device->dev;
+   dma_addr_t src = get_desc_src(chan, desc);
+   dma_addr_t dst = get_desc_dst(chan, desc);
+   u32 len = get_desc_cnt(chan, desc);
+
+   BUG_ON(txd->cookie < 0);
+
+   if (txd->cookie > 0) {
+   cookie = txd->cookie

[PATCH v3 2/4] fsl-dma: remove attribute DMA_INTERRUPT of dmaengine

2012-07-15 Thread Qiang Liu 
Delete attribute DMA_INTERRUPT because fsl-dma doesn't support this function,
exception will be thrown if talitos is used to offload xor at the same time.

Cc: Dan Williams 
Cc: Vinod Koul 
Cc: Li Yang 
Signed-off-by: Qiang Liu 
Acked-by: Ira W. Snyder 
---
 drivers/dma/fsldma.c |   31 ---
 1 files changed, 0 insertions(+), 31 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 8f84761..4f2f212 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -543,35 +543,6 @@ static void fsl_dma_free_chan_resources(struct dma_chan 
*dchan)
 }

 static struct dma_async_tx_descriptor *
-fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
-{
-   struct fsldma_chan *chan;
-   struct fsl_desc_sw *new;
-
-   if (!dchan)
-   return NULL;
-
-   chan = to_fsl_chan(dchan);
-
-   new = fsl_dma_alloc_descriptor(chan);
-   if (!new) {
-   chan_err(chan, "%s\n", msg_ld_oom);
-   return NULL;
-   }
-
-   new->async_tx.cookie = -EBUSY;
-   new->async_tx.flags = flags;
-
-   /* Insert the link descriptor to the LD ring */
-   list_add_tail(&new->node, &new->tx_list);
-
-   /* Set End-of-link to the last link descriptor of new list */
-   set_ld_eol(chan, new);
-
-   return &new->async_tx;
-}
-
-static struct dma_async_tx_descriptor *
 fsl_dma_prep_memcpy(struct dma_chan *dchan,
dma_addr_t dma_dst, dma_addr_t dma_src,
size_t len, unsigned long flags)
@@ -1352,12 +1323,10 @@ static int __devinit fsldma_of_probe(struct 
platform_device *op)
fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);

dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
-   dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
dma_cap_set(DMA_SG, fdev->common.cap_mask);
dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
-   fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
fdev->common.device_tx_status = fsl_tx_status;
--
1.7.5.1


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[PATCH v3 0/4] Raid: enable talitos xor offload for improving performance

2012-07-15 Thread Qiang Liu 
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.

Write performance will be improved by 25-30% tested by iozone.
Write performance is improved about 2% after using spin_lock_bh replace
spin_lock_irqsave.
CPU load will be reduced by 8%.

Changes in v3:
- change release process of fsl-dma descriptor for resolve the
potential race condition
- add test result when use spin_lock_bh replace spin_lock_irqsave
- modify the benchmark results according to the latest patch

Changes in v2:
- rebase onto cryptodev tree
- split the patch 3/4 up to 3 independent patches
- remove the patch 4/4, the fix is not for cryptodev tree


Qiang Liu (4):
  Talitos: Support for async_tx XOR offload
  fsl-dma: remove attribute DMA_INTERRUPT of dmaengine
  fsl-dma: change release process of dma descriptor for supporting async_tx
  fsl-dma: use spin_lock_bh to instead of spin_lock_irqsave

 drivers/crypto/Kconfig   |9 +
 drivers/crypto/talitos.c |  410 +++
 drivers/crypto/talitos.h |   53 ++
 drivers/dma/fsldma.c |  436 +-
 drivers/dma/fsldma.h |1 +
 5 files changed, 708 insertions(+), 201 deletions(-)

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[PATCH] powerpc/85xx: workaround for chips with MSI hareware errata to support MSI-X

2012-07-15 Thread Jia Hongtao 
From: Liu Shuo 

The MPIC chip with version 2.0 has a MSI errata (errata PIC1 of mpc8544),
It causes that neither MSI nor MSI-X can work fine. There is a workaround
to allow MSI-X to function properly.

Signed-off-by: Liu Shuo 
Signed-off-by: Li Yang 
---
 arch/powerpc/include/asm/mpic.h |3 ++
 arch/powerpc/sysdev/fsl_msi.c   |   63 +-
 arch/powerpc/sysdev/fsl_msi.h   |3 ++
 3 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c9f698a..a9e4f937 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -110,6 +110,9 @@
 #defineMPIC_VECPRI_SENSE_MASK  0x0040
 #define MPIC_IRQ_DESTINATION   0x00010
 
+#defineMPIC_FSL_BRR1   0x0
+#defineMPIC_FSL_BRR1_VER   0x
+
 #define MPIC_MAX_IRQ_SOURCES   2048
 #define MPIC_MAX_CPUS  32
 #define MPIC_MAX_ISU   32
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 6e097de..f2d340a 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -98,8 +98,23 @@ static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
 
 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
 {
+   struct fsl_msi *msi;
+
if (type == PCI_CAP_ID_MSIX)
pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
+   else if (type == PCI_CAP_ID_MSI) {
+   /*
+* MPIC chip with 2.0 version has erratum PIC1. It
+* causes that neither MSI nor MSI-X can work fine.
+* There is a workaround to allow MSI-X to function
+* properly.
+*/
+   list_for_each_entry(msi, &msi_head, list) {
+   if ((msi->feature & MSI_HW_ERRATA_MASK)
+   == MSI_HW_ERRATA_ENDIAN)
+   return -EINVAL;
+   }
+   }
 
return 0;
 }
@@ -142,7 +157,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int 
hwirq,
msg->address_lo = lower_32_bits(address);
msg->address_hi = upper_32_bits(address);
 
-   msg->data = hwirq;
+   /* See the comment in fsl_msi_check_device() */
+   if ((msi_data->feature & MSI_HW_ERRATA_MASK) == MSI_HW_ERRATA_ENDIAN)
+   msg->data = __swab32(hwirq);
+   else
+   msg->data = hwirq;
 
pr_debug("%s: allocated srs: %d, ibs: %d\n",
__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
@@ -359,13 +378,43 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi 
*msi,
return 0;
 }
 
+/* MPIC chip with 2.0 version has erratum PIC1 */
+static int mpic_has_errata(struct platform_device *dev)
+{
+   struct device_node *mpic_node;
+
+   mpic_node = of_irq_find_parent(dev->dev.of_node);
+   if (mpic_node) {
+   u32 *reg_base, brr1 = 0;
+   /* Get the PIC reg base */
+   reg_base = of_iomap(mpic_node, 0);
+   of_node_put(mpic_node);
+   if (!reg_base) {
+   dev_err(&dev->dev, "ioremap problem failed.\n");
+   return -EIO;
+   }
+
+   /* Get the mpic chip version from block revision register 1 */
+   brr1 = in_be32(reg_base + MPIC_FSL_BRR1);
+   iounmap(reg_base);
+   if ((brr1 & MPIC_FSL_BRR1_VER) == 0x0200)
+   return 1;
+   } else {
+   dev_err(&dev->dev, "MSI can't find his parent mpic node.\n");
+   of_node_put(mpic_node);
+   return -ENODEV;
+   }
+
+   return 0;
+}
+
 static const struct of_device_id fsl_of_msi_ids[];
 static int __devinit fsl_of_msi_probe(struct platform_device *dev)
 {
const struct of_device_id *match;
struct fsl_msi *msi;
struct resource res;
-   int err, i, j, irq_index, count;
+   int err, i, j, irq_index, count, errata;
int rc;
const u32 *p;
struct fsl_msi_feature *features;
@@ -421,6 +470,16 @@ static int __devinit fsl_of_msi_probe(struct 
platform_device *dev)
 
msi->feature = features->fsl_pic_ip;
 
+   if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC) {
+   errata = mpic_has_errata(dev);
+   if (errata > 0) {
+   msi->feature |= MSI_HW_ERRATA_ENDIAN;
+   } else if (errata < 0) {
+   err = errata;
+   goto error_out;
+   }
+   }
+
/*
 * Remember the phandle, so that we can match with any PCI nodes
 * that have an "fsl,msi" property.
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 8225f86..354d546 100644
--- a/arch/powerpc/sysde

[PATCH 2/2 v2] powerpc/fsl: PCI: add quirk_enable_non_msi_intx_interrupt

2012-07-15 Thread Shengzhou Liu 
On current fsl powerpc platforms, the PCIe root port doesn't support
generating MSI/MSI-X and INTx interrupt in RC mode (those interrupts
are supported only in EP mode). So we use the shared error interrupt
by flag PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ for PCIe port driver to
support AER, Hot-plug etc, services.

Signed-off-by: Shengzhou Liu 
---
v2: separated platform-specific part to arch/powerpc/sysdev.

 arch/powerpc/sysdev/fsl_pci.c |2 ++
 arch/powerpc/sysdev/fsl_pci.h |1 +
 2 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288..fb8862f 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -498,6 +498,8 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 
quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
+   quirk_enable_non_msi_intx_interrupt);
 
 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
 struct mpc83xx_pcie_priv {
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..a98c6d8 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -91,6 +91,7 @@ struct ccsr_pci {
 extern int fsl_add_bridge(struct device_node *dev, int is_primary);
 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
 extern int mpc83xx_add_bridge(struct device_node *dev);
+extern void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev);
 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
 
 #endif /* __POWERPC_FSL_PCI_H */
-- 
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[PATCH 1/2 v2] PCI: Add PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ to enable non MSI/INTx interrupt

2012-07-15 Thread Shengzhou Liu 
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt for port service driver to have
AER, Hot-plug, etc, services to work.

Signed-off-by: Shengzhou Liu 
---
v2: separated platform-specific part to arch/powerpc/sysdev.

 drivers/pci/pcie/portdrv_core.c |   10 --
 drivers/pci/quirks.c|9 +
 include/linux/pci.h |5 +
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b3..837ad15 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -212,8 +212,14 @@ static int init_service_irqs(struct pci_dev *dev, int 
*irqs, int mask)
if (!pcie_port_enable_msix(dev, irqs, mask))
return 0;
 
-   /* We're not going to use MSI-X, so try MSI and fall back to INTx */
-   if (!pci_enable_msi(dev) || dev->pin)
+   /*
+* We're not going to use MSI-X, so try MSI and fall back to INTx.
+* Eventually, if neither MSI/MSI-X nor INTx available, try other
+* interrupt. (On some platforms, root port doesn't support generating
+* MSI/MSI-X/INTx in RC mode)
+*/
+   if (!pci_enable_msi(dev) || dev->pin || ((dev->dev_flags &
+   PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ) && dev->irq))
irq = dev->irq;
 
  no_msi:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a75216..2922cb8 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2640,6 +2640,15 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
quirk_msi_intx_disable_bug);
 #endif /* CONFIG_PCI_MSI */
 
+/*
+ * Under some circumstances, root port has neither MSI/MSI-X nor INTx 
generated,
+ * so try other interrupt if supported.
+ */
+void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev)
+{
+   dev->dev_flags |= PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ;
+}
+
 /* Allow manual resource allocation for PCI hotplug bridges
  * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
  * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d8c379d..f051a66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -176,6 +176,11 @@ enum pci_dev_flags {
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
/* Provide indication device is assigned by a Virtual Machine Manager */
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
+   /*
+* Use other interrupt (i.e. system shared interrupt) when MSI/MSI-X
+* and INTx are not supported in RC mode on some platforms.
+*/
+   PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ = (__force pci_dev_flags_t) 8,
 };
 
 enum pci_irq_reroute_variant {
-- 
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Re: [PATCH] powerpc: SMT priority (PPR) save and restore

2012-07-15 Thread Michael Neuling 
Heaven Myneni  wrote:

> powerpc: SMT priority (PPR) save and restore
> 
> On P7 systems, users can define SMT priority levels 2,3 and 4 for
> processes so that some can run higher priority than the other ones.
> In the current kernel, the default priority is set to 4 which prohibits
> processes to use higher priority. Also the kernel boosts the priority to
> 4 during exception without saving the user defined priority values when
> the task enters the kernel. So we will be loosing the process PPR value
> and can not be restored it back when the task exits the kernel.
> 
> This patch sets the default priority to 3 when tasks are created such
> that users can use 4 for higher priority tasks. It also provides to save
> and restore the user defined priorities for all tasks.
> 
> When the task enters in to kernel space, the user defined priority (PPR)
> will be saved in to PACA at the beginning of first level exception
> vector and then copy from PACA to thread_info in second level vector.
> PPR will be restored from thread_info before exits the kernel space.
> 
> P7 temporarily raises the thread priority to higher level during
> exception until the program executes HMT_* calls. But it will not modify
> PPR register. So we saves PPR value whenever some register is available
> to use and then calls HMT_MEDIUM to increase the priority. This feature
> supports on P7 or later processors.
> 
> Signed-off-by: Haren Myneni 

Can you break this patch into a few parts that are easier to review than
one giant patch.  Start by adding the PPR ftr bits, then the extra space
in the paca, then the new macros, then use the new infrastructure.  I'm
sure you can get 5 or so patches which will be much easier to review.

Also this has been white space munged.  See here:
  http://patchwork.ozlabs.org/patch/170993/
All the #defines are broken.

Also, do you know what the impacts of this are on null syscall/page
faults etc on machines which need the PPR switched?  If it's big, we
might want to have this as a CONFIG option for those who don't care and
want the speed bump.

More comments below.

> 
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index 50d82c8..e7b80d6 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -203,6 +203,7 @@ extern const char *powerpc_base_platform;
>  #define CPU_FTR_POPCNTD  
> LONG_ASM_CONST(0x0800)
>  #define CPU_FTR_ICSWX
> LONG_ASM_CONST(0x1000)
>  #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000)
> +#define CPU_FTR_HAS_PPR  
> LONG_ASM_CONST(0x4000)
>  
>  #ifndef __ASSEMBLY__
>  
> @@ -432,7 +433,8 @@ extern const char *powerpc_base_platform;
>   CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
>   CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
>   CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD |
> \
> - CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
> + CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY |
> \
> + CPU_FTR_HAS_PPR)

Add CPU_FTR_HAS_PPR to CPU_FTRS_POSSIBLE as well.


>  #define CPU_FTRS_CELL(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
>   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
>   CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
> diff --git a/arch/powerpc/include/asm/exception-64s.h
> b/arch/powerpc/include/asm/exception-64s.h
> index d58fc4e..1fae8aa 100644
> --- a/arch/powerpc/include/asm/exception-64s.h
> +++ b/arch/powerpc/include/asm/exception-64s.h
> @@ -47,6 +47,7 @@
>  #define EX_R364
>  #define EX_LR72
>  #define EX_CFAR  80
> +#define EX_PPR   88  /* SMT thread status register 
> (priority) */
>  
>  /*
>   * We're short on space and time in the exception prolog, so we can't
> @@ -61,10 +62,46 @@
>  #define EXC_HV   H
>  #define EXC_STD
>  
> +/* 
> + * PPR save/restore macros - Used only on P7 or later processors
> + */
> +#define SAVE_PPR(area, ra, rb)
> \
> +BEGIN_FTR_SECTION_NESTED(940)
> \
> +   ld  ra,area+EX_PPR(r13);/* Read PPR from paca */
> \
> +   clrrdi  rb,r1,THREAD_SHIFT; /* thread_info struct */
> \
> +   std ra,TI_PPR(rb);  /* Save PPR in thread_info */
> \
> +END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
> +
> +#define RESTORE_PPR(ra,rb)
> \
> +BEGIN_FTR_SECTION_NESTED(941)
> \
> +   clrrdi  ra,r1,THREAD_SHIFT;
> \
> +   ld  rb,TI_PPR(ra);  /* Read PPR from thread_info */
> \
> +   mtspr   SPRN_PPR,rb;/* Restore PPR */
> \
> +END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
> +
> +#define RESTORE_PPR_PACA(area,ra)
> \
> +BEGIN_FTR_SECTION_NESTED(942)
> \
> +   ld  ra,area+EX_PPR(r13);
> \
> +   mtspr   SPRN_PPR,ra;
> \
> +END_FTR_S

[PATCH V3] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx

2012-07-15 Thread Jia Hongtao 
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.

Signed-off-by: Zhao Chenhui 
Signed-off-by: Li Yang 
Signed-off-by: Liu Shuo 
Signed-off-by: Jia Hongtao 
---
V3 changed:
1. Rebased the patch.
2. Only build fsl_pci_mcheck_exception on e500

 arch/powerpc/kernel/cpu_setup_fsl_booke.S |2 +-
 arch/powerpc/kernel/traps.c   |3 ++
 arch/powerpc/sysdev/fsl_pci.c |   41 +
 arch/powerpc/sysdev/fsl_pci.h |6 
 4 files changed, 51 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 69fdd23..9c4b768 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -64,7 +64,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl  __e500_icache_setup
bl  __e500_dcache_setup
bl  __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr   r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 1589723..096a1a1 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -555,6 +556,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason & MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+   if (fsl_pci_mcheck_exception(regs))
+   return 1;
}
 
printk("Machine check in kernel mode.\n");
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a7b2a60..3a3e9c8 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -808,6 +809,46 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
 }
 
+#ifdef CONFIG_E500
+static int is_in_pci_mem_space(phys_addr_t addr)
+{
+   struct pci_controller *hose;
+   struct resource *res;
+   int i;
+
+   list_for_each_entry(hose, &hose_list, list_node) {
+   if (!early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP))
+   continue;
+
+   for (i = 0; i < 3; i++) {
+   res = &hose->mem_resources[i];
+   if ((res->flags & IORESOURCE_MEM) &&
+   addr >= res->start && addr <= res->end)
+   return 1;
+   }
+   }
+   return 0;
+}
+
+int fsl_pci_mcheck_exception(struct pt_regs *regs)
+{
+   phys_addr_t addr = 0;
+
+#ifdef CONFIG_PHYS_64BIT
+   addr = mfspr(SPRN_MCARU);
+   addr <<= 32;
+#endif
+   addr += mfspr(SPRN_MCAR);
+
+   if (is_in_pci_mem_space(addr)) {
+   regs->nip += 4;
+   return 1;
+   }
+
+   return 0;
+}
+#endif
+
 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 static const struct of_device_id pci_ids[] = {
{ .compatible = "fsl,mpc8540-pci", },
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd1..efd1907 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -101,5 +101,11 @@ void fsl_pci_init(void);
 static inline void fsl_pci_init(void) {}
 #endif
 
+#ifdef CONFIG_FSL_PCI
+extern int fsl_pci_mcheck_exception(struct pt_regs *);
+#else
+static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
+#endif
+
 #endif /* __POWERPC_FSL_PCI_H */
 #endif /* __KERNEL__ */
-- 
1.7.5.1


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[PATCH V3] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx

2012-07-15 Thread Jia Hongtao 
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.

Signed-off-by: Zhao Chenhui 
Signed-off-by: Li Yang 
Signed-off-by: Liu Shuo 
Signed-off-by: Jia Hongtao 
---
V3 changed: Just rebase the patch.

 arch/powerpc/kernel/cpu_setup_fsl_booke.S |2 +-
 arch/powerpc/kernel/traps.c   |3 ++
 arch/powerpc/sysdev/fsl_pci.c |   39 +
 arch/powerpc/sysdev/fsl_pci.h |6 
 4 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S 
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 69fdd23..9c4b768 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -64,7 +64,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl  __e500_icache_setup
bl  __e500_dcache_setup
bl  __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr   r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 1589723..096a1a1 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -555,6 +556,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason & MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+   if (fsl_pci_mcheck_exception(regs))
+   return 1;
}
 
printk("Machine check in kernel mode.\n");
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a7b2a60..52f3b5d 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -808,6 +809,44 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
 }
 
+static int is_in_pci_mem_space(phys_addr_t addr)
+{
+   struct pci_controller *hose;
+   struct resource *res;
+   int i;
+
+   list_for_each_entry(hose, &hose_list, list_node) {
+   if (!early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP))
+   continue;
+
+   for (i = 0; i < 3; i++) {
+   res = &hose->mem_resources[i];
+   if ((res->flags & IORESOURCE_MEM) &&
+   addr >= res->start && addr <= res->end)
+   return 1;
+   }
+   }
+   return 0;
+}
+
+int fsl_pci_mcheck_exception(struct pt_regs *regs)
+{
+   phys_addr_t addr = 0;
+
+#ifdef CONFIG_PHYS_64BIT
+   addr = mfspr(SPRN_MCARU);
+   addr <<= 32;
+#endif
+   addr += mfspr(SPRN_MCAR);
+
+   if (is_in_pci_mem_space(addr)) {
+   regs->nip += 4;
+   return 1;
+   }
+
+   return 0;
+}
+
 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 static const struct of_device_id pci_ids[] = {
{ .compatible = "fsl,mpc8540-pci", },
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd1..efd1907 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -101,5 +101,11 @@ void fsl_pci_init(void);
 static inline void fsl_pci_init(void) {}
 #endif
 
+#ifdef CONFIG_FSL_PCI
+extern int fsl_pci_mcheck_exception(struct pt_regs *);
+#else
+static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
+#endif
+
 #endif /* __POWERPC_FSL_PCI_H */
 #endif /* __KERNEL__ */
-- 
1.7.5.1


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Re: [RFC PATCH v3 4/13] memory-hotplug : remove /sys/firmware/memmap/X sysfs

2012-07-15 Thread Wen Congyang 
At 07/09/2012 06:26 PM, Yasuaki Ishimatsu Wrote:
> When (hot)adding memory into system, /sys/firmware/memmap/X/{end, start, type}
> sysfs files are created. But there is no code to remove these files. The patch
> implements the function to remove them.
> 
> Note : The code does not free firmware_map_entry since there is no way to free
>memory which is allocated by bootmem.
> 
> CC: David Rientjes 
> CC: Jiang Liu 
> CC: Len Brown 
> CC: Benjamin Herrenschmidt 
> CC: Paul Mackerras 
> CC: Christoph Lameter 
> Cc: Minchan Kim 
> CC: Andrew Morton 
> CC: KOSAKI Motohiro 
> CC: Wen Congyang 
> Signed-off-by: Yasuaki Ishimatsu 
> 
> ---
>  drivers/firmware/memmap.c|   78 
> ++-
>  include/linux/firmware-map.h |6 +++
>  mm/memory_hotplug.c  |6 ++-
>  3 files changed, 88 insertions(+), 2 deletions(-)
> 
> Index: linux-3.5-rc6/mm/memory_hotplug.c
> ===
> --- linux-3.5-rc6.orig/mm/memory_hotplug.c2012-07-09 18:23:13.323844923 
> +0900
> +++ linux-3.5-rc6/mm/memory_hotplug.c 2012-07-09 18:23:19.522767424 +0900
> @@ -661,7 +661,11 @@ EXPORT_SYMBOL_GPL(add_memory);
> 
>  int remove_memory(int nid, u64 start, u64 size)
>  {
> - return -EBUSY;
> + lock_memory_hotplug();
> + /* remove memmap entry */
> + firmware_map_remove(start, start + size - 1, "System RAM");
> + unlock_memory_hotplug();
> + return 0;
> 
>  }
>  EXPORT_SYMBOL_GPL(remove_memory);
> Index: linux-3.5-rc6/include/linux/firmware-map.h
> ===
> --- linux-3.5-rc6.orig/include/linux/firmware-map.h   2012-07-09 
> 18:23:09.532892314 +0900
> +++ linux-3.5-rc6/include/linux/firmware-map.h2012-07-09 
> 18:23:19.523767412 +0900
> @@ -25,6 +25,7 @@
> 
>  int firmware_map_add_early(u64 start, u64 end, const char *type);
>  int firmware_map_add_hotplug(u64 start, u64 end, const char *type);
> +int firmware_map_remove(u64 start, u64 end, const char *type);
> 
>  #else /* CONFIG_FIRMWARE_MEMMAP */
> 
> @@ -38,6 +39,11 @@ static inline int firmware_map_add_hotpl
>   return 0;
>  }
> 
> +static inline int firmware_map_remove(u64 start, u64 end, const char *type)
> +{
> + return 0;
> +}
> +
>  #endif /* CONFIG_FIRMWARE_MEMMAP */
> 
>  #endif /* _LINUX_FIRMWARE_MAP_H */
> Index: linux-3.5-rc6/drivers/firmware/memmap.c
> ===
> --- linux-3.5-rc6.orig/drivers/firmware/memmap.c  2012-07-09 
> 18:23:09.532892314 +0900
> +++ linux-3.5-rc6/drivers/firmware/memmap.c   2012-07-09 18:25:46.371931554 
> +0900
> @@ -21,6 +21,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  /*
>   * Data types 
> --
> @@ -79,7 +80,22 @@ static const struct sysfs_ops memmap_att
>   .show = memmap_attr_show,
>  };
> 
> +#define to_memmap_entry(obj) container_of(obj, struct firmware_map_entry, 
> kobj)
> +
> +static void release_firmware_map_entry(struct kobject *kobj)
> +{
> + struct firmware_map_entry *entry = to_memmap_entry(kobj);
> + struct page *head_page;
> +
> + head_page = virt_to_head_page(entry);
> + if (PageSlab(head_page))
> + kfree(entry);
> +
> + /* There is no way to free memory allocated from bootmem*/
> +}
> +
>  static struct kobj_type memmap_ktype = {
> + .release= release_firmware_map_entry,
>   .sysfs_ops  = &memmap_attr_ops,
>   .default_attrs  = def_attrs,
>  };
> @@ -123,6 +139,16 @@ static int firmware_map_add_entry(u64 st
>   return 0;
>  }
> 
> +/**
> + * firmware_map_remove_entry() - Does the real work to remove a firmware
> + * memmap entry.
> + * @entry: removed entry.
> + **/
> +static inline void firmware_map_remove_entry(struct firmware_map_entry 
> *entry)
> +{
> + list_del(&entry->list);
> +}
> +
>  /*
>   * Add memmap entry on sysfs
>   */
> @@ -144,6 +170,31 @@ static int add_sysfs_fw_map_entry(struct
>   return 0;
>  }
> 
> +/*
> + * Remove memmap entry on sysfs
> + */
> +static inline void remove_sysfs_fw_map_entry(struct firmware_map_entry 
> *entry)
> +{
> + kobject_put(&entry->kobj);
> +}
> +
> +/*
> + * Search memmap entry
> + */
> +
> +struct firmware_map_entry * __meminit
> +find_firmware_map_entry(u64 start, u64 end, const char *type)
> +{
> + struct firmware_map_entry *entry;
> +
> + list_for_each_entry(entry, &map_entries, list)
> + if ((entry->start == start) && (entry->end == end) &&
> + (!strcmp(entry->type, type)))
> + return entry;
> +
> + return NULL;
> +}
> +
>  /**
>   * firmware_map_add_hotplug() - Adds a firmware mapping entry when we do
>   * memory hotplug.
> @@ -196,6 +247,32 @@ int __init firmware_map_add_early(u64 st
>   return firmware_map_add_entry(start, end, type, entry);
>  }
> 
> +/**
> + * firmware_map_remove() - remove

Re: [PATCH] ppc44x/watchdog: Select WATCHDOG_NOWAYOUT option

2012-07-15 Thread Lu.Jiang 

于 2012年07月13日 19:50, Kumar Gala 写道:

On Jul 12, 2012, at 9:44 PM, Jiang Lu wrote:


On PPC44x core, the WRC(Watchdog-timer Reset Control) field of TCR
of timer can not reset by software after set to a non-zero value.
Which means software can not reset the timeout behaviour of watchdog timer.

This patch selects WATCHDOG_NOWAYOUT option for 44x platforms to
indicate the watchdog timer can not be disabled once fired.

Signed-off-by: Jiang Lu 
---
drivers/watchdog/Kconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)

I believe this is not 44x specific, but how Book-E watchdog is architected.


diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3709624..41f3dff 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1084,6 +1084,7 @@ config PIKA_WDT
config BOOKE_WDT
tristate "PowerPC Book-E Watchdog Timer"
depends on BOOKE || 4xx
+   select WATCHDOG_NOWAYOUT if 44x

This should probably be 'select WATCHDOG_NOWAYOUT if BOOKE'


On ppc44x's processor, if we disabled 'WATCHDOG_NOWAYOUT ' option. The 
driver's release routine will try to disable the watchdog , by clearing 
the WIE & WTDP field in TCR.
Since the ppc44x's watch dog can not reset by software, such operation 
only set the timeout value(WDTP) to minimum, and cause the system reboot 
immediately.


I checked ppc 476, 405 & 450's manual, these document said the 
WRC(Watchdog-timer Reset Control) field of TCR of timer
can not reset by software after set to a non-zero value. I think all 
ppc44x core should got same limitation.


While on FSL's platform, we did not met such issue. So I think we should 
select 'WATCHDOG_NOWAYOUT' option for 44x platform.


Regards,
Jiang Lu




---help---
  Watchdog driver for PowerPC Book-E chips, such as the Freescale
  MPC85xx SOCs and the IBM PowerPC 440.
--
1.7.7

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Re: [PATCH 6/6] hrtimer: Update hrtimer base offsets each hrtimer_interrupt

2012-07-15 Thread Rafael J. Wysocki 
On Sunday, July 15, 2012, Andreas Schwab wrote:
> This breaks resume on the iBook G4 (PowerBook6,7).  Apparently during or
> before noirq resume the system is hanging by the same amount of time as
> the system was sleeping.

I'm able to reproduce this problem on Toshiba Portege R500 with similar
symptoms, although that box sometimes hangs hard during resume from system
suspend with the "caps lock" LED blinking.

Reverting the patch fixes the problem 100% of the time.

Thanks,
Rafael
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Re: [PATCH 6/6] hrtimer: Update hrtimer base offsets each hrtimer_interrupt

2012-07-15 Thread Andreas Schwab 
Andreas Schwab  writes:

> This breaks resume on the iBook G4 (PowerBook6,7).  Apparently during or
> before noirq resume the system is hanging by the same amount of time as
> the system was sleeping.

The point where the time is wasted actually appears to be _after_ resume
(the elapsed time for the resume itself isn't affected).

Andreas.

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Re: [PATCH 6/6] hrtimer: Update hrtimer base offsets each hrtimer_interrupt

2012-07-15 Thread Andreas Schwab 
This breaks resume on the iBook G4 (PowerBook6,7).  Apparently during or
before noirq resume the system is hanging by the same amount of time as
the system was sleeping.

Andreas.

-- 
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GPG Key fingerprint = 58CA 54C7 6D53 942B 1756  01D3 44D5 214B 8276 4ED5
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