Re: [PATCHv4 1/2] ppc64: perform proper max_bus_speed detection
On Thu, May 02, 2013 at 12:21:37PM -0300, Kleber Sacilotto de Souza wrote:
> Hi Tony,
>
> It seems Lucas' change is a bit incomplete and is not handling the reference
> counter to
> the device_node correctly. Is the following change what you had in mind?
Ahh Sorry I expected there would be a for_each_parent_of_node macro.
I did a quick grep and it seems that's not very common, so open coding
it should be fine.
>
> dn = pcibios_get_phb_of_node(bus);
> if (!dn)
> return 0;
>
> for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
> pcie_link_speed_stats = (const uint32_t *) of_get_property(pdn,
> "ibm,pcie-link-speed-stats", NULL);
> if (pcie_link_speed_stats)
> break;
> }
>
> of_node_put(pdn);
I think you need the of_node_put() in the body of the loop, otherwise
aren't you leaking refcounts?
Yours Tony
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Re: [PATCH 1/1] powerpc: mpc512x_dma: add support for data transfers between memory and i/o memory
Hello Vinod, Thanks for the review. I will return with improved and tested version 2. Best regards, Alexander ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V7 10/10] powerpc: disable assert_pte_locked
On Mon, Apr 29, 2013 at 01:21:51AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> With THP we set pmd to none, before we do pte_clear. Hence we can't
> walk page table to get the pte lock ptr and verify whether it is locked.
> THP do take pte lock before calling pte_clear. So we don't change the locking
> rules here. It is that we can't use page table walking to check whether
> pte locks are help with THP.
>
> NOTE: This needs to be re-written. Not to be merged upstream.
So, rewrite it..
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/pgtable.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
> index 214130a..d77f94f 100644
> --- a/arch/powerpc/mm/pgtable.c
> +++ b/arch/powerpc/mm/pgtable.c
> @@ -224,6 +224,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma,
> unsigned long address,
> #ifdef CONFIG_DEBUG_VM
> void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
> {
> +#if 0
> pgd_t *pgd;
> pud_t *pud;
> pmd_t *pmd;
> @@ -237,6 +238,7 @@ void assert_pte_locked(struct mm_struct *mm, unsigned
> long addr)
> pmd = pmd_offset(pud, addr);
> BUG_ON(!pmd_present(*pmd));
> assert_spin_locked(pte_lockptr(mm, pmd));
> +#endif
> }
> #endif /* CONFIG_DEBUG_VM */
>
--
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Re: [PATCH -V7 09/10] powerpc: Optimize hugepage invalidate
On Mon, Apr 29, 2013 at 01:21:50AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Hugepage invalidate involves invalidating multiple hpte entries.
> Optimize the operation using H_BULK_REMOVE on lpar platforms.
> On native, reduce the number of tlb flush.
>
> Signed-off-by: Aneesh Kumar K.V
Since this is purely an optimization, have you tried reproducing the
bugs you're chasing with this patch not included?
> ---
> arch/powerpc/include/asm/machdep.h| 3 +
> arch/powerpc/mm/hash_native_64.c | 78 +
> arch/powerpc/mm/pgtable_64.c | 13 +++-
> arch/powerpc/platforms/pseries/lpar.c | 126
> --
> 4 files changed, 210 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/machdep.h
> b/arch/powerpc/include/asm/machdep.h
> index 3f3f691..5d1e7d2 100644
> --- a/arch/powerpc/include/asm/machdep.h
> +++ b/arch/powerpc/include/asm/machdep.h
> @@ -56,6 +56,9 @@ struct machdep_calls {
> void(*hpte_removebolted)(unsigned long ea,
>int psize, int ssize);
> void(*flush_hash_range)(unsigned long number, int local);
> + void(*hugepage_invalidate)(struct mm_struct *mm,
> +unsigned char *hpte_slot_array,
> +unsigned long addr, int psize);
>
> /* special for kexec, to be called in real mode, linear mapping is
>* destroyed as well */
> diff --git a/arch/powerpc/mm/hash_native_64.c
> b/arch/powerpc/mm/hash_native_64.c
> index 6a2aead..8ca178d 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -455,6 +455,83 @@ static void native_hpte_invalidate(unsigned long slot,
> unsigned long vpn,
> local_irq_restore(flags);
> }
>
> +static void native_hugepage_invalidate(struct mm_struct *mm,
> +unsigned char *hpte_slot_array,
> +unsigned long addr, int psize)
> +{
> + int ssize = 0, i;
> + int lock_tlbie;
> + struct hash_pte *hptep;
> + int actual_psize = MMU_PAGE_16M;
> + unsigned int max_hpte_count, valid;
> + unsigned long flags, s_addr = addr;
> + unsigned long hpte_v, want_v, shift;
> + unsigned long hidx, vpn = 0, vsid, hash, slot;
> +
> + shift = mmu_psize_defs[psize].shift;
> + max_hpte_count = HUGE_PAGE_SIZE >> shift;
> +
> + local_irq_save(flags);
> + for (i = 0; i < max_hpte_count; i++) {
> + /*
> + * 8 bits per each hpte entries
> + * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
> + */
> + valid = hpte_slot_array[i] & 0x1;
> + if (!valid)
> + continue;
> + hidx = hpte_slot_array[i] >> 1;
> +
> + /* get the vpn */
> + addr = s_addr + (i * (1ul << shift));
> + if (!is_kernel_addr(addr)) {
> + ssize = user_segment_size(addr);
> + vsid = get_vsid(mm->context.id, addr, ssize);
> + WARN_ON(vsid == 0);
> + } else {
> + vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> + ssize = mmu_kernel_ssize;
> + }
> +
> + vpn = hpt_vpn(addr, vsid, ssize);
> + hash = hpt_hash(vpn, shift, ssize);
> + if (hidx & _PTEIDX_SECONDARY)
> + hash = ~hash;
> +
> + slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
> + slot += hidx & _PTEIDX_GROUP_IX;
> +
> + hptep = htab_address + slot;
> + want_v = hpte_encode_avpn(vpn, psize, ssize);
> + native_lock_hpte(hptep);
> + hpte_v = hptep->v;
> +
> + /* Even if we miss, we need to invalidate the TLB */
> + if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
> + native_unlock_hpte(hptep);
> + else
> + /* Invalidate the hpte. NOTE: this also unlocks it */
> + hptep->v = 0;
> + }
> + /*
> + * Since this is a hugepage, we just need a single tlbie.
> + * use the last vpn.
> + */
> + lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
> + if (lock_tlbie)
> + raw_spin_lock(&native_tlbie_lock);
> +
> + asm volatile("ptesync":::"memory");
> + __tlbie(vpn, psize, actual_psize, ssize);
> + asm volatile("eieio; tlbsync; ptesync":::"memory");
> +
> + if (lock_tlbie)
> + raw_spin_unlock(&native_tlbie_lock);
> +
> + local_irq_restore(flags);
> +}
> +
> +
> static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
> int *psize, int *apsize, int *ssize, unsigned long *vpn)
> {
> @@ -658,4 +735,5 @@ void __init hpte_init_native(v
Re: [PATCH -V7 02/10] powerpc/THP: Implement transparent hugepages for ppc64
On Mon, Apr 29, 2013 at 01:21:43AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" > > We now have pmd entries covering 16MB range and the PMD table double its > original size. > We use the second half of the PMD table to deposit the pgtable (PTE page). > The depoisted PTE page is further used to track the HPTE information. The > information > include [ secondary group | 3 bit hidx | valid ]. We use one byte per each > HPTE entry. > With 16MB hugepage and 64K HPTE we need 256 entries and with 4K HPTE we need > 4096 entries. Both will fit in a 4K PTE page. On hugepage invalidate we need > to walk > the PTE page and invalidate all valid HPTEs. > > This patch implements necessary arch specific functions for THP support and > also > hugepage invalidate logic. These PMD related functions are intentionally kept > similar to their PTE counter-part. > > Signed-off-by: Aneesh Kumar K.V > --- > arch/powerpc/include/asm/page.h | 11 +- > arch/powerpc/include/asm/pgtable-ppc64-64k.h | 3 +- > arch/powerpc/include/asm/pgtable-ppc64.h | 259 +- > arch/powerpc/include/asm/pgtable.h | 5 + > arch/powerpc/include/asm/pte-hash64-64k.h| 17 ++ > arch/powerpc/mm/pgtable_64.c | 318 > +++ > arch/powerpc/platforms/Kconfig.cputype | 1 + > 7 files changed, 611 insertions(+), 3 deletions(-) > > diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h > index 988c812..cbf4be7 100644 > --- a/arch/powerpc/include/asm/page.h > +++ b/arch/powerpc/include/asm/page.h > @@ -37,8 +37,17 @@ > #define PAGE_SIZE(ASM_CONST(1) << PAGE_SHIFT) > > #ifndef __ASSEMBLY__ > -#ifdef CONFIG_HUGETLB_PAGE > +/* > + * With hugetlbfs enabled we allow the HPAGE_SHIFT to run time > + * configurable. But we enable THP only with 16MB hugepage. > + * With only THP configured, we force hugepage size to 16MB. > + * This should ensure that all subarchs that doesn't support > + * THP continue to work fine with HPAGE_SHIFT usage. > + */ > +#if defined(CONFIG_HUGETLB_PAGE) > extern unsigned int HPAGE_SHIFT; > +#elif defined(CONFIG_TRANSPARENT_HUGEPAGE) > +#define HPAGE_SHIFT PMD_SHIFT As I said in comments on the first patch series, this messing around with HPAGE_SHIFT for THP is missing the point. On ppc HPAGE_SHIFT is nothing more than the _default_ hugepage size for explicit hugepages. THP should not be dependent on it in any way. > #else > #define HPAGE_SHIFT PAGE_SHIFT > #endif > diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h > b/arch/powerpc/include/asm/pgtable-ppc64-64k.h > index 45142d6..a56b82f 100644 > --- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h > +++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h > @@ -33,7 +33,8 @@ > #define PGDIR_MASK (~(PGDIR_SIZE-1)) > > /* Bits to mask out from a PMD to get to the PTE page */ > -#define PMD_MASKED_BITS 0x1ff > +/* PMDs point to PTE table fragments which are 4K aligned. */ > +#define PMD_MASKED_BITS 0xfff Hrm. AFAICT this is related to the change in size of PTE tables, and hence the page sharing stuff, so this belongs in the patch which implements that, rather than the THP support itself. > /* Bits to mask out from a PGD/PUD to get to the PMD page */ > #define PUD_MASKED_BITS 0x1ff > > diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h > b/arch/powerpc/include/asm/pgtable-ppc64.h > index ab84332..20133c1 100644 > --- a/arch/powerpc/include/asm/pgtable-ppc64.h > +++ b/arch/powerpc/include/asm/pgtable-ppc64.h > @@ -154,7 +154,7 @@ > #define pmd_present(pmd)(pmd_val(pmd) != 0) > #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) > #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS) > -#define pmd_page(pmd)virt_to_page(pmd_page_vaddr(pmd)) > +extern struct page *pmd_page(pmd_t pmd); > > #define pud_set(pudp, pudval)(pud_val(*(pudp)) = (pudval)) > #define pud_none(pud)(!pud_val(pud)) > @@ -382,4 +382,261 @@ static inline pte_t *find_linux_pte_or_hugepte(pgd_t > *pgdir, unsigned long ea, > > #endif /* __ASSEMBLY__ */ > > +#ifndef _PAGE_SPLITTING > +/* > + * THP pages can't be special. So use the _PAGE_SPECIAL > + */ > +#define _PAGE_SPLITTING _PAGE_SPECIAL > +#endif > + > +#ifndef _PAGE_THP_HUGE > +/* > + * We need to differentiate between explicit huge page and THP huge > + * page, since THP huge page also need to track real subpage details > + * We use the _PAGE_COMBO bits here as dummy for platform that doesn't > + * support THP. > + */ > +#define _PAGE_THP_HUGE 0x1000 So if it's _PAGE_COMBO, use _PAGE_COMBO, instead of the actual number. > +#endif > + > +/* > + * PTE flags to conserve for HPTE identification for THP page. > + */ > +#ifndef _PAGE_THP_HPTEFLAGS > +#define _PAGE_THP_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE) You have this definition both here and in pte-hash64-64k.h. More
Re: [PATCH -V7 06/10] powerpc: Update gup_pmd_range to handle transparent hugepages
On Mon, Apr 29, 2013 at 01:21:47AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" > > Signed-off-by: Aneesh Kumar K.V Reviewed-by: David Gibson -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V7 07/10] powerpc/THP: Add code to handle HPTE faults for large pages
On Mon, Apr 29, 2013 at 01:21:48AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" > > The deposted PTE page in the second half of the PMD table is used to > track the state on hash PTEs. After updating the HPTE, we mark the > coresponding slot in the deposted PTE page valid. > > Signed-off-by: Aneesh Kumar K.V Reviewed-by: David Gibson -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V7 04/10] powerpc: Update find_linux_pte_or_hugepte to handle transparent hugepages
On Mon, Apr 29, 2013 at 01:21:45AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
What's the difference in meaning between pmd_huge() and pmd_large()?
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/hugetlbpage.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
> index 8601f2d..081c001 100644
> --- a/arch/powerpc/mm/hugetlbpage.c
> +++ b/arch/powerpc/mm/hugetlbpage.c
> @@ -954,7 +954,7 @@ pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned
> long ea, unsigned *shift
> pdshift = PMD_SHIFT;
> pm = pmd_offset(pu, ea);
>
> - if (pmd_huge(*pm)) {
> + if (pmd_huge(*pm) || pmd_large(*pm)) {
> ret_pte = (pte_t *) pm;
> goto out;
> } else if (is_hugepd(pm))
--
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Re: [PATCH -V7 08/10] powerpc/THP: Enable THP on PPC64
On Mon, Apr 29, 2013 at 01:21:49AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We enable only if the we support 16MB page size.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/pgtable-ppc64.h | 3 +--
> arch/powerpc/mm/pgtable_64.c | 28
> 2 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
> b/arch/powerpc/include/asm/pgtable-ppc64.h
> index 97fc839..d65534b 100644
> --- a/arch/powerpc/include/asm/pgtable-ppc64.h
> +++ b/arch/powerpc/include/asm/pgtable-ppc64.h
> @@ -426,8 +426,7 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
> return pmd_val(pmd) >> PTE_RPN_SHIFT;
> }
>
> -/* We will enable it in the last patch */
> -#define has_transparent_hugepage() 0
> +extern int has_transparent_hugepage(void);
> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
>
> static inline int pmd_young(pmd_t pmd)
> diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
> index 54216c1..b742d6f 100644
> --- a/arch/powerpc/mm/pgtable_64.c
> +++ b/arch/powerpc/mm/pgtable_64.c
> @@ -754,6 +754,34 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma,
> unsigned long addr,
> return;
> }
>
> +int has_transparent_hugepage(void)
> +{
> + if (!mmu_has_feature(MMU_FTR_16M_PAGE))
> + return 0;
> + /*
> + * We support THP only if HPAGE_SHIFT is 16MB.
> + */
> + if (!HPAGE_SHIFT || (HPAGE_SHIFT != mmu_psize_defs[MMU_PAGE_16M].shift))
> + return 0;
Again, THP should not be dependent on the value of HPAGE_SHIFT. Just
checking that mmu_psize_defsz[MMU_PAGE_16M].shift == 24 should be
sufficient (i.e. that 16M hugepages are supported).
> + /*
> + * We need to make sure that we support 16MB hugepage in a segement
> + * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE
> + * of 64K.
> + */
> + /*
> + * If we have 64K HPTE, we will be using that by default
> + */
> + if (mmu_psize_defs[MMU_PAGE_64K].shift &&
> + (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1))
> + return 0;
> + /*
> + * Ok we only have 4K HPTE
> + */
> + if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1)
> + return 0;
Except you don't actually support THP on 4K base page size yet.
> +
> + return 1;
> +}
> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
>
> pmd_t pmdp_get_and_clear(struct mm_struct *mm,
--
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| _way_ _around_!
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Re: [PATCH -V7 05/10] powerpc: Replace find_linux_pte with find_linux_pte_or_hugepte
On Mon, Apr 29, 2013 at 01:21:46AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Replace find_linux_pte with find_linux_pte_or_hugepte and explicitly
> document why we don't need to handle transparent hugepages at callsites.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/pgtable-ppc64.h | 24
> arch/powerpc/kernel/io-workarounds.c | 10 --
> arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
> arch/powerpc/mm/hash_utils_64.c | 8 +++-
> arch/powerpc/mm/hugetlbpage.c| 8 ++--
> arch/powerpc/mm/tlb_hash64.c | 7 ++-
> arch/powerpc/platforms/pseries/eeh.c | 7 ++-
> 7 files changed, 34 insertions(+), 32 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
> b/arch/powerpc/include/asm/pgtable-ppc64.h
> index f0effab..97fc839 100644
> --- a/arch/powerpc/include/asm/pgtable-ppc64.h
> +++ b/arch/powerpc/include/asm/pgtable-ppc64.h
> @@ -343,30 +343,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep,
> pte_t entry)
>
> void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
> void pgtable_cache_init(void);
> -
> -/*
> - * find_linux_pte returns the address of a linux pte for a given
> - * effective address and directory. If not found, it returns zero.
> - */
> -static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
> -{
> - pgd_t *pg;
> - pud_t *pu;
> - pmd_t *pm;
> - pte_t *pt = NULL;
> -
> - pg = pgdir + pgd_index(ea);
> - if (!pgd_none(*pg)) {
> - pu = pud_offset(pg, ea);
> - if (!pud_none(*pu)) {
> - pm = pmd_offset(pu, ea);
> - if (pmd_present(*pm))
> - pt = pte_offset_kernel(pm, ea);
> - }
> - }
> - return pt;
> -}
> -
> pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
>unsigned *shift);
> #endif /* __ASSEMBLY__ */
> diff --git a/arch/powerpc/kernel/io-workarounds.c
> b/arch/powerpc/kernel/io-workarounds.c
> index 50e90b7..e5263ab 100644
> --- a/arch/powerpc/kernel/io-workarounds.c
> +++ b/arch/powerpc/kernel/io-workarounds.c
> @@ -55,6 +55,7 @@ static struct iowa_bus *iowa_pci_find(unsigned long vaddr,
> unsigned long paddr)
>
> struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
> {
> + unsigned shift;
> struct iowa_bus *bus;
> int token;
>
> @@ -70,11 +71,16 @@ struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
> if (vaddr < PHB_IO_BASE || vaddr >= PHB_IO_END)
> return NULL;
>
> - ptep = find_linux_pte(init_mm.pgd, vaddr);
> + ptep = find_linux_pte_or_hugepte(init_mm.pgd, vaddr, &shift);
> if (ptep == NULL)
> paddr = 0;
> - else
> + else {
> + /*
> + * we don't have hugepages backing iomem
> + */
> + BUG_ON(shift);
> paddr = pte_pfn(*ptep) << PAGE_SHIFT;
> + }
> bus = iowa_pci_find(vaddr, paddr);
>
> if (bus == NULL)
> diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
> b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
> index 19c93ba..8c345df 100644
> --- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
> +++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
> @@ -27,7 +27,7 @@ static void *real_vmalloc_addr(void *x)
> unsigned long addr = (unsigned long) x;
> pte_t *p;
>
> - p = find_linux_pte(swapper_pg_dir, addr);
> + p = find_linux_pte_or_hugepte(swapper_pg_dir, addr, NULL);
> if (!p || !pte_present(*p))
> return NULL;
> /* assume we don't have huge pages in vmalloc space... */
> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
> index d0eb6d4..e942ae9 100644
> --- a/arch/powerpc/mm/hash_utils_64.c
> +++ b/arch/powerpc/mm/hash_utils_64.c
> @@ -1131,6 +1131,7 @@ EXPORT_SYMBOL_GPL(hash_page);
> void hash_preload(struct mm_struct *mm, unsigned long ea,
> unsigned long access, unsigned long trap)
> {
> + int shift;
> unsigned long vsid;
> pgd_t *pgdir;
> pte_t *ptep;
> @@ -1152,10 +1153,15 @@ void hash_preload(struct mm_struct *mm, unsigned long
> ea,
> pgdir = mm->pgd;
> if (pgdir == NULL)
> return;
> - ptep = find_linux_pte(pgdir, ea);
> + /*
> + * THP pages use update_mmu_cache_pmd. We don't do
> + * hash preload there. Hence can ignore THP here
> + */
> + ptep = find_linux_pte_or_hugepte(pgdir, ea, &shift);
> if (!ptep)
> return;
>
> + BUG_ON(shift);
> #ifdef CONFIG_PPC_64K_PAGES
> /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
>* a 64K kernel), then we don't preload, hash_page() will take
> diff --git a/arch/powerpc/mm/hugetlbpage.c b/a
RE: pci overmapping
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, May 02, 2013 11:50 PM
> To: Sethi Varun-B16395
> Cc: Wood Scott-B07421; Yoder Stuart-B08248; ga...@kernel.crashing.org;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: pci overmapping
>
> On 05/02/2013 01:09:53 PM, Sethi Varun-B16395 wrote:
> >
> >
> > > -Original Message-
> > > From: Wood Scott-B07421
> > > Sent: Thursday, May 02, 2013 10:44 PM
> > > To: Yoder Stuart-B08248
> > > Cc: ga...@kernel.crashing.org; Sethi Varun-B16395; linuxppc-
> > > d...@lists.ozlabs.org
> > > Subject: Re: pci overmapping
> > >
> > > On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
> > > > Kumar,
> > > >
> > > > In fsl_pci.c there is a change you made a while back:
> > > > "powerpc/fsl: Setup PCI inbound window based on actual amount of
> > > > memory"
> > > >
> > > > ...and there is this comment in the code:
> > > >
> > > > /* PCIe can overmap inbound & outbound since RX & TX are
> > separated
> > > > */
> > > > if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> > > >
> > > > You are implying that PCIe can overmap and PCI can't. Why is
> > > > that? (I'm assuming that 'overmap' means that inbound window
> > > > can extend beyond the end of ram.)
> > >
> > > Shouldn't the concern be whether we're overlapping outbound, not
> > merely
> > > whether we go beyond the end of RAM?
> > >
> > > And couldn't inbound/outbound overlap be an issue even on PCIe, if
> > > there's a PCI bridge underneath it?
> > I believe that the overlap problem would be avoided in case of 36 bit
> > physical support (outbound window address would be high order 36 bit
> > value), right?
>
> Not necessarily -- it depends on what the bus addresses are, not the host
> addresses.
The fsl_pci code already checks for the overlap condition. The inbound window
range is set to the minimum of memory end address or the start of pci outbound
address. In our case, the guest memory end address (host physical address
derived from the huge tlb page) is less than the pci outbound start address.
But, it could be the other way round as well. In both cases if the inbound
memory can't map the end of RAM address (for the guest), the fsl_pci driver
would enable swiotlb.
For the first case where end of memory is < start of pci outbound address, we
can avoid enabling swiotlb (when end address is not a power of two) by over
committing the inbound address window.
-Varun
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Re: [PATCH -V7 01/10] powerpc/THP: Double the PMD table size for THP
On Mon, Apr 29, 2013 at 01:21:42AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" > > THP code does PTE page allocation along with large page request and deposit > them > for later use. This is to ensure that we won't have any failures when we split > hugepages to regular pages. > > On powerpc we want to use the deposited PTE page for storing hash pte slot and > secondary bit information for the HPTEs. We use the second half > of the pmd table to save the deposted PTE page. > > Signed-off-by: Aneesh Kumar K.V So far so good. Reviewed-by: David Gibson -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
> -Original Message- > From: Wood Scott-B07421 > Sent: Friday, May 03, 2013 1:04 AM > To: Jia Hongtao-B38951 > Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- > B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 > Subject: Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to > fix PCIe erratum on mpc85xx > > On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: > > A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe > > goes down. when the link goes down, Non-posted transactions issued via > > the ATMU requiring completion result in an instruction stall. > > At the same time a machine-check exception is generated to the core to > > allow further processing by the handler. We implements the handler > > which skips the instruction caused the stall. > > > > This patch depends on patch: > > powerpc/85xx: Add platform_device declaration to fsl_pci.h > > > > Signed-off-by: Zhao Chenhui > > Signed-off-by: Li Yang > > Signed-off-by: Liu Shuo > > Signed-off-by: Jia Hongtao > > --- > > V8: > > * Add A variant load instruction emulation. > > ACK > > -Scott Thanks for the review. Hi Kumar, Could you please review these MSI and PCI hang errata patches? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ (This patch) Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v3 1/4] powerpc/mpic: add irq_set_wake support
Hi Kumar, Could you apply these patches? Thanks. > -Original Message- > From: Wang Dongsheng-B40534 > Sent: Tuesday, April 23, 2013 6:10 PM > To: ga...@kernel.crashing.org > Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421 > Subject: RE: [PATCH v3 1/4] powerpc/mpic: add irq_set_wake support > > Hi Kumar, > > Could you apply these patches? > > Thanks. > > [v3,1/4] powerpc/mpic: add irq_set_wake support > http://patchwork.ozlabs.org/patch/234934/ > > [v3,2/4] powerpc/mpic: add global timer support > http://patchwork.ozlabs.org/patch/234935/ > > [v3,3/4] powerpc/mpic: create mpic subsystem object > http://patchwork.ozlabs.org/patch/234936/ > > [v3,4/4] powerpc/fsl: add MPIC timer wakeup support > http://patchwork.ozlabs.org/patch/234937/ > > > > -Original Message- > > From: Wood Scott-B07421 > > Sent: Wednesday, April 17, 2013 7:30 AM > > To: Wang Dongsheng-B40534 > > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; > > ga...@kernel.crashing.org > > Subject: Re: [PATCH v3 1/4] powerpc/mpic: add irq_set_wake support > > > > ACK > > > > -Scott > > > > On 04/16/2013 05:58:52 AM, Wang Dongsheng-B40534 wrote: > > > Hi scott, > > > > > > Could you ACK these patches? > > > > > > [PATCH v3 2/4] powerpc/mpic: add global timer support [PATCH v3 3/4] > > > powerpc/mpic: create mpic subsystem object [PATCH v3 4/4] > > > powerpc/fsl: add MPIC timer wakeup support > > > > > > Thanks. > > > ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/tm: Fix null pointer deference in flush_hash_page
Make sure that current->thread.reg exists before we deference it in
flush_hash_page.
Signed-off-by: Michael Neuling
Reported-by: John J Miller
Cc:
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 3e4c4ed..88ac0ee 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1230,6 +1230,7 @@ void flush_hash_page(unsigned long vpn, real_pte_t pte,
int psize, int ssize,
* unmapping it first, it may see the speculated version.
*/
if (local && cpu_has_feature(CPU_FTR_TM) &&
+ current->thread.regs &&
MSR_TM_ACTIVE(current->thread.regs->msr)) {
tm_enable();
tm_abort(TM_CAUSE_TLBI);
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Re: [PATCH net-next] af_unix: fix a fatal race with bit fields
On Tue, Apr 30, 2013 at 10:04:32PM -0700, Eric Dumazet wrote: > These kind of errors are pretty hard to find, its a pity to spend time > on them. Well, yes. From the first comment in gcc PR52080. "For the following testcase we generate a 8 byte RMW cycle on IA64 which causes locking problems in the linux kernel btrfs filesystem." Did someone fix btrfs, but not check other kernel locks? Having now hit the same problem again, have you checked that other kernel locks don't have adjacent bit fields in the same 64-bit word? And comment the struct to ensure someone doesn't optimize those unsigned chars back to bit fields. -- Alan Modra Australia Development Lab, IBM ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/3] powerpc/perf: Add e6500 PMU driver
e6500 core performance monitors has the following features:
- 6 performance monitor counters
- 512 events supported
- no threshold events
e6500 PMU has more specific events (Data L1 cache misses, Instruction L1
cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads,
etc). Where available, the more specific events have been used which will
produce slightly different results than e500 PMU equivalents.
Based on work done by Priyanka Jain
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h |4 +-
arch/powerpc/perf/Makefile |2 +-
arch/powerpc/perf/e6500-pmu.c | 120
3 files changed, 124 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/perf/e6500-pmu.c
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index c51d52e..0e3ddf5 100644
--- a/arch/powerpc/include/asm/reg_fsl_emb.h
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -34,8 +34,10 @@
#define PMLCA_FCM1 0x1000 /* Freeze when PMM==1 */
#define PMLCA_FCM0 0x0800 /* Freeze when PMM==0 */
#define PMLCA_CE 0x0400 /* Condition Enable */
+#define PMLCA_FGCS10x0002 /* Freeze in guest state */
+#define PMLCA_FGCS00x0001 /* Freeze in hypervisor state */
-#define PMLCA_EVENT_MASK 0x00ff/* Event field */
+#define PMLCA_EVENT_MASK 0x01ff/* Event field */
#define PMLCA_EVENT_SHIFT 16
#define PMRN_PMLCB00x110 /* PM Local Control B0 */
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index af3fac2..06dd8d5 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -8,7 +8,7 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o
power5-pmu.o \
obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
-obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
obj-$(CONFIG_PPC64)+= $(obj64-y)
obj-$(CONFIG_PPC32)+= $(obj32-y)
diff --git a/arch/powerpc/perf/e6500-pmu.c b/arch/powerpc/perf/e6500-pmu.c
new file mode 100644
index 000..cf6eab7
--- /dev/null
+++ b/arch/powerpc/perf/e6500-pmu.c
@@ -0,0 +1,120 @@
+/*
+ * Performance counter support for e6500 family processors.
+ *
+ * Author: Lijun Pan
+ * Based on Priyanka Jain's code
+ * Based on e500-pmu.c
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+
+/*
+ * Map of generic hardware event types to hardware events
+ * Zero if unsupported
+ */
+static int e6500_generic_events[] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = 1,
+ [PERF_COUNT_HW_INSTRUCTIONS] = 2,
+ [PERF_COUNT_HW_CACHE_MISSES] = 221,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 15,
+};
+
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+ [C(L1D)] = {
+ /*RESULT_ACCESS RESULT_MISS */
+ [C(OP_READ)] = {27, 222 },
+ [C(OP_WRITE)] = { 28, 223 },
+ [C(OP_PREFETCH)] = {29, 0 },
+ },
+ [C(L1I)] = {
+ /*RESULT_ACCESS RESULT_MISS */
+ [C(OP_READ)] = {2, 254 },
+ [C(OP_WRITE)] = { -1, -1 },
+ [C(OP_PREFETCH)] = {37, 0 },
+ },
+ /*
+* Assuming LL means L2, it's not a good match for this model.
+* It does not have separate read/write events (but it does have
+* separate instruction/data events).
+*/
+ [C(LL)] = {
+ /*RESULT_ACCESS RESULT_MISS */
+ [C(OP_READ)] = {0, 0 },
+ [C(OP_WRITE)] = { 0, 0 },
+ [C(OP_PREFETCH)] = {0, 0 },
+ },
+ /*
+* There are data/instruction MMU misses, but that's a miss on
+* the chip's internal level-one TLB which is probably not
+* what the user wants. Instead, unified level-two TLB misses
+* are reported here.
+*/
+ [C(DTLB)] = {
+ /*RESULT_ACCESS RESULT_MISS */
+ [C(OP_READ)] = {26, 66 },
+ [C(OP_W
[PATCH 2/3] powerpc/perf: add 2 additional performance monitor counters for e6500 core
There are 6 counters in e6500 core instead of 4 in e500 core.
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h | 12
arch/powerpc/kernel/cputable.c |2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 30 ++
arch/powerpc/perf/core-fsl-emb.c | 24
4 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index 1cf8ab0..c51d52e 100644
--- a/arch/powerpc/include/asm/reg_fsl_emb.h
+++ b/arch/powerpc/include/asm/reg_fsl_emb.h
@@ -19,10 +19,14 @@
#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
#define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
#define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
+#define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
+#define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
#define PMRN_PMLCA00x090 /* PM Local Control A0 */
#define PMRN_PMLCA10x091 /* PM Local Control A1 */
#define PMRN_PMLCA20x092 /* PM Local Control A2 */
#define PMRN_PMLCA30x093 /* PM Local Control A3 */
+#define PMRN_PMLCA40x094 /* PM Local Control A4 */
+#define PMRN_PMLCA50x095 /* PM Local Control A5 */
#define PMLCA_FC 0x8000 /* Freeze Counter */
#define PMLCA_FCS 0x4000 /* Freeze in Supervisor */
@@ -38,6 +42,8 @@
#define PMRN_PMLCB10x111 /* PM Local Control B1 */
#define PMRN_PMLCB20x112 /* PM Local Control B2 */
#define PMRN_PMLCB30x113 /* PM Local Control B3 */
+#define PMRN_PMLCB40x114 /* PM Local Control B4 */
+#define PMRN_PMLCB50x115 /* PM Local Control B5 */
#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
#define PMLCB_THRESHMUL_SHIFT 8
@@ -57,14 +63,20 @@
#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */
#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */
+#define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */
+#define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */
#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
+#define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */
+#define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */
#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
+#define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */
+#define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */
#define PMRN_UPMGC00x180 /* User PM Global Control 0 */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index cc39139..2d4eee2 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2073,7 +2073,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
.dcache_bsize = 64,
- .num_pmcs = 4,
+ .num_pmcs = 6,
.oprofile_cpu_type = "ppc/e6500",
.oprofile_type = PPC_OPROFILE_FSL_EMB,
.cpu_setup = __setup_cpu_e6500,
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c
b/arch/powerpc/oprofile/op_model_fsl_emb.c
index ccc1daa..2a82d3e 100644
--- a/arch/powerpc/oprofile/op_model_fsl_emb.c
+++ b/arch/powerpc/oprofile/op_model_fsl_emb.c
@@ -46,6 +46,12 @@ static inline u32 get_pmlca(int ctr)
case 3:
pmlca = mfpmr(PMRN_PMLCA3);
break;
+ case 4:
+ pmlca = mfpmr(PMRN_PMLCA4);
+ break;
+ case 5:
+ pmlca = mfpmr(PMRN_PMLCA5);
+ break;
default:
panic("Bad ctr number\n");
}
@@ -68,6 +74,12 @@ static inline void set_pmlca(int ctr, u32 pmlca)
case 3:
mtpmr(PMRN_PMLCA3, pmlca);
break;
+ case 4:
+ mtpmr(PMRN_PMLCA4, pmlca);
+ break;
+ case 5:
+ mtpmr(PMRN_PMLCA5, pmlca);
+ break;
default:
panic("Bad ctr number\n");
}
@@ -84,6 +96,10 @@ static inline unsigned int ctr_read(unsigned int i)
r
[PATCH 1/3] powerpc/perf: correct typos in counter enumeration
Signed-off-by: Lijun Pan --- arch/powerpc/include/asm/reg_fsl_emb.h |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h b/arch/powerpc/include/asm/reg_fsl_emb.h index 77bb71c..1cf8ab0 100644 --- a/arch/powerpc/include/asm/reg_fsl_emb.h +++ b/arch/powerpc/include/asm/reg_fsl_emb.h @@ -17,8 +17,8 @@ /* Freescale Book E Performance Monitor APU Registers */ #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ -#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ -#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ +#define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */ +#define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */ #define PMRN_PMLCA00x090 /* PM Local Control A0 */ #define PMRN_PMLCA10x091 /* PM Local Control A1 */ #define PMRN_PMLCA20x092 /* PM Local Control A2 */ @@ -55,8 +55,8 @@ #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ -#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ +#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */ +#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */ #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ -- 1.7.9.7 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH net-next] af_unix: fix a fatal race with bit fields
On Wed, 2013-05-01 at 08:10 -0700, Stephen Hemminger wrote: > > These kind of errors are pretty hard to find, its a pity to spend > time > > on them. > > There is a checkbin target inside arch/powerpc/Makefile > Shouldn't a check be added there to block building kernel with known > bad GCC versions? In this case that makes it all GCC versions except the *very latest* not practical. I suppose we should try to make sure that at least the next batch of enterprise distro get that fix on gcc side. Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: pci overmapping
On 05/02/2013 01:09:53 PM, Sethi Varun-B16395 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, May 02, 2013 10:44 PM
> To: Yoder Stuart-B08248
> Cc: ga...@kernel.crashing.org; Sethi Varun-B16395; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: pci overmapping
>
> On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
> > Kumar,
> >
> > In fsl_pci.c there is a change you made a while back:
> > "powerpc/fsl: Setup PCI inbound window based on actual amount of
> > memory"
> >
> > ...and there is this comment in the code:
> >
> > /* PCIe can overmap inbound & outbound since RX & TX are
separated
> > */
> > if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> >
> > You are implying that PCIe can overmap and PCI can't. Why is
> > that? (I'm assuming that 'overmap' means that inbound window
> > can extend beyond the end of ram.)
>
> Shouldn't the concern be whether we're overlapping outbound, not
merely
> whether we go beyond the end of RAM?
>
> And couldn't inbound/outbound overlap be an issue even on PCIe, if
> there's a PCI bridge underneath it?
I believe that the overlap problem would be avoided in case of 36 bit
physical support (outbound window address would be high order 36 bit
value), right?
Not necessarily -- it depends on what the bus addresses are, not the
host addresses.
-Scott
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RE: pci overmapping
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, May 02, 2013 10:44 PM
> To: Yoder Stuart-B08248
> Cc: ga...@kernel.crashing.org; Sethi Varun-B16395; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: pci overmapping
>
> On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
> > Kumar,
> >
> > In fsl_pci.c there is a change you made a while back:
> > "powerpc/fsl: Setup PCI inbound window based on actual amount of
> > memory"
> >
> > ...and there is this comment in the code:
> >
> > /* PCIe can overmap inbound & outbound since RX & TX are separated
> > */
> > if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> >
> > You are implying that PCIe can overmap and PCI can't. Why is
> > that? (I'm assuming that 'overmap' means that inbound window
> > can extend beyond the end of ram.)
>
> Shouldn't the concern be whether we're overlapping outbound, not merely
> whether we go beyond the end of RAM?
>
> And couldn't inbound/outbound overlap be an issue even on PCIe, if
> there's a PCI bridge underneath it?
I believe that the overlap problem would be avoided in case of 36 bit physical
support (outbound window address would be high order 36 bit value), right?
-Varun
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Re: [PATCH 1/1] powerpc: mpc512x_dma: add support for data transfers between memory and i/o memory
On Wed, May 01, 2013 at 03:28:09PM +0400, Alexander Popov wrote:
> The initial version of this driver supports only memory to memory
> data transfers.
>
> Data transfers between memory and i/o memory require more delicate TCD
> (Transfer Control Descriptor) configuration and DMA channel service requests
> via hardware.
>
> dma_device.device_control callback function is needed to configure
> DMA channel to work with i/o memory.
>
> Signed-off-by: Alexander Popov
> ---
> drivers/dma/mpc512x_dma.c | 230
> ++
> 1 file changed, 192 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
> index 2d95673..8aedff1 100644
> --- a/drivers/dma/mpc512x_dma.c
> +++ b/drivers/dma/mpc512x_dma.c
> @@ -2,6 +2,7 @@
> * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
> * Copyright (C) Semihalf 2009
> * Copyright (C) Ilya Yanok, Emcraft Systems 2010
> + * Copyright (C) Alexander Popov, Promcontroller 2013
> *
> * Written by Piotr Ziecik . Hardware description
> * (defines, structures and comments) was taken from MPC5121 DMA driver
> @@ -28,11 +29,6 @@
> * file called COPYING.
> */
>
> -/*
> - * This is initial version of MPC5121 DMA driver. Only memory to memory
> - * transfers are supported (tested using dmatest module).
> - */
> -
> #include
> #include
> #include
> @@ -183,6 +179,8 @@ struct mpc_dma_desc {
>
> struct mpc_dma_chan {
> struct dma_chan chan;
> + enum dma_transfer_direction dir;
> + enum dma_slave_buswidth slave_reg_width;
> struct list_headfree;
> struct list_headprepared;
> struct list_headqueued;
> @@ -190,6 +188,7 @@ struct mpc_dma_chan {
> struct list_headcompleted;
> struct mpc_dma_tcd *tcd;
> dma_addr_t tcd_paddr;
> + u32 tcd_nunits;
>
> /* Lock for this structure */
> spinlock_t lock;
> @@ -268,7 +267,11 @@ static void mpc_dma_execute(struct mpc_dma_chan *mchan)
>
> if (first != prev)
> mdma->tcd[cid].e_sg = 1;
> - out_8(&mdma->regs->dmassrt, cid);
> +
> + if (first->tcd->biter != 1) /* Request channel service by... */
> + out_8(&mdma->regs->dmaserq, cid); /* hardware */
> + else
> + out_8(&mdma->regs->dmassrt, cid); /* software */
> }
>
> /* Handle interrupt on one half of DMA controller (32 channels) */
> @@ -567,7 +570,42 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t
> cookie,
> return ret;
> }
>
> -/* Prepare descriptor for memory to memory copy */
> +static int mpc_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> + unsigned long arg)
> +{
> + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
> + struct dma_slave_config *cfg = (void *)arg;
> + int ret = 0;
> +
> + if (!chan)
> + return -EINVAL;
> +
> + if (cmd == DMA_SLAVE_CONFIG && cfg) {
> + if (cfg->direction == DMA_DEV_TO_MEM) {
> + if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
> + mchan->slave_reg_width = cfg->src_addr_width;
> + else
> + return -EINVAL;
> + mchan->dir = DMA_DEV_TO_MEM;
> + mchan->tcd_nunits = cfg->src_maxburst;
you need to save the slave addr too.
> + } else if (cfg->direction == DMA_MEM_TO_DEV) {
> + if (cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
> + mchan->slave_reg_width = cfg->dst_addr_width;
> + else
> + return -EINVAL;
> + mchan->dir = DMA_MEM_TO_DEV;
> + mchan->tcd_nunits = cfg->dst_maxburst;
> + } else {
> + mchan->dir = DMA_MEM_TO_MEM;
> + mchan->slave_reg_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
> + mchan->tcd_nunits = 0;
> + }
> + } else
> + return -ENOSYS;
ENXIO?
while at it, consider a different way:
if (cmd != DMA_SLAVE_CONFIG || !cfg)
return -ENXIO;
then you can shift the sholw code one indent left, makes it look a little
better.
> +
> + return ret;
> +}
> +
> static struct dma_async_tx_descriptor *
> mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
> size_t len, unsigned long flags)
> @@ -577,6 +615,7 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t
> dst, dma_addr_t src,
> struct mpc_dma_desc *mdesc = NULL;
> struct mpc_dma_tcd *tcd;
> unsigned long iflags;
> + u32 iter = 0;
>
> /* Get free descriptor */
> spin_lock_i
Re: pci overmapping
On 05/02/2013 12:05:42 PM, Yoder Stuart-B08248 wrote:
Kumar,
In fsl_pci.c there is a change you made a while back:
"powerpc/fsl: Setup PCI inbound window based on actual amount of
memory"
...and there is this comment in the code:
/* PCIe can overmap inbound & outbound since RX & TX are
separated */
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
You are implying that PCIe can overmap and PCI can't. Why is
that? (I'm assuming that 'overmap' means that inbound window
can extend beyond the end of ram.)
Shouldn't the concern be whether we're overlapping outbound, not merely
whether we go beyond the end of RAM?
And couldn't inbound/outbound overlap be an issue even on PCIe, if
there's a PCI bridge underneath it?
-Scott
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pci overmapping
Kumar,
In fsl_pci.c there is a change you made a while back:
"powerpc/fsl: Setup PCI inbound window based on actual amount of memory"
...and there is this comment in the code:
/* PCIe can overmap inbound & outbound since RX & TX are separated */
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
You are implying that PCIe can overmap and PCI can't. Why is
that? (I'm assuming that 'overmap' means that inbound window
can extend beyond the end of ram.)
We are facing an issue for a non-PCI express controller (i.e. without
PCI_CAP_ID_EXP) emulated by QEMU. In our case we need the ATMU
window to extend beyond the end of ram, since the window size has
to be a power of 2.
Thanks,
Stuart
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Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui Signed-off-by: Li Yang Signed-off-by: Liu Shuo Signed-off-by: Jia Hongtao --- V8: * Add A variant load instruction emulation. ACK -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH net-next] af_unix: fix a fatal race with bit fields
On 04/30/2013 10:54:25 PM, Alan Modra wrote: On Tue, Apr 30, 2013 at 07:24:20PM -0700, Eric Dumazet wrote: >li 11,1 >ld 0,0(9) >rldimi 0,11,31,32 >std 0,0(9) >blr >.ident "GCC: (GNU) 4.6.3" > > You can see "ld 0,0(9)" is used : its a 64 bit load. Yup. This is not a powerpc64 specific problem. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52080 Fixed in 4.8.0 and 4.7.3. FWIW (especially if a GCC version check is added), it seems to have been fixed as far back as 4.7.1, not just 4.7.3. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCHv4 1/2] ppc64: perform proper max_bus_speed detection
On 04/25/2013 02:34 PM, Lucas Kannebley Tavares wrote:
> On 04/24/2013 08:48 PM, Tony Breeds wrote:
>>> diff --git a/arch/powerpc/platforms/pseries/pci.c
>>> b/arch/powerpc/platforms/pseries/pci.c
>>> index 0b580f4..7f9c956 100644
>>> --- a/arch/powerpc/platforms/pseries/pci.c
>>> +++ b/arch/powerpc/platforms/pseries/pci.c
>>> @@ -108,3 +108,54 @@ static void fixup_winbond_82c105(struct pci_dev*
>>> dev)
>>> }
>>> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND,
>>> PCI_DEVICE_ID_WINBOND_82C105,
>>>fixup_winbond_82c105);
>>> +
>>> +int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
>>> +{
>>> +struct device_node *dn, *pdn;
>>> +struct pci_bus *bus;
>>> +const uint32_t *pcie_link_speed_stats;
>>> +
>>> +bus = bridge->bus;
>>> +
>>> +dn = pcibios_get_phb_of_node(bus);
>>> +if (!dn)
>>> +return 0;
>>> +
>>> +for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
>>> +pcie_link_speed_stats = (const uint32_t *) of_get_property(dn,
>>> +"ibm,pcie-link-speed-stats", NULL);
>>> +if (pcie_link_speed_stats)
>>> +break;
>>> +}
>>
>> Please use the helpers in include/linux/of.h rather than open coding
>> this.
>>
>> Yours Tony
>
>
> Hi Tony,
>
>
> This is what I can find as an equivalent code:
>
> for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
> pcie_link_speed_stats = (const uint32_t *)
> of_get_property(dn,
> "ibm,pcie-link-speed-stats", NULL);
> if (pcie_link_speed_stats)
> break;
> }
>
> is this your suggestion, or was it another approach that will have the
> same result?
>
> Thanks,
>
Hi Tony,
It seems Lucas' change is a bit incomplete and is not handling the reference
counter to
the device_node correctly. Is the following change what you had in mind?
dn = pcibios_get_phb_of_node(bus);
if (!dn)
return 0;
for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
pcie_link_speed_stats = (const uint32_t *) of_get_property(pdn,
"ibm,pcie-link-speed-stats", NULL);
if (pcie_link_speed_stats)
break;
}
of_node_put(pdn);
Thanks,
--
Kleber Sacilotto de Souza
IBM Linux Technology Center
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[PATCH 2/2] powerpc/512x: DMA via LocalPlus Bus testing driver
This module tests Direct Memory Access to some device on LocalPlus Bus
for Freescale MPC512x. In other words it tests the bundle
of mpc512x_lpbfifo and mpc512x_dma drivers.
This testing driver was multiply used with static RAM (CY62167EV30LL-45ZXI)
which lives on LocalPlus Bus on our board. This testing driver was used
instead of the original static RAM driver and it is an abnormal hack.
That is why I just provide the driver code and don't modify any environment.
Signed-off-by: Alexander Popov
---
drivers/misc/mpc512x_lpbdma_test.c | 310 +
1 file changed, 310 insertions(+)
create mode 100644 drivers/misc/mpc512x_lpbdma_test.c
diff --git a/drivers/misc/mpc512x_lpbdma_test.c
b/drivers/misc/mpc512x_lpbdma_test.c
new file mode 100644
index 000..4fdd052
--- /dev/null
+++ b/drivers/misc/mpc512x_lpbdma_test.c
@@ -0,0 +1,310 @@
+/*
+ * Tests for DMA via LocalPlus Bus for the Freescale MPC512x.
+ *
+ * Copyright (C) Promcontroller, 2013.
+ * Author is Alexander Popov .
+ *
+ * This module tests Direct Memory Access to the devices on LocalPlus Bus.
+ *
+ * This file is released under the GPLv2.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+MODULE_AUTHOR("Alexander Popov ");
+MODULE_LICENSE("GPL");
+
+#define DRV_NAME "mpc512x_lpbdma_test"
+#define ENOUGH 131072
+
+static int repeat = 1;
+
+enum test_iteration_result {
+ NEXT_TEST_PLEASE,
+ TRANSFER_LAUNCHED,
+ ALL_TESTS_DONE,
+};
+
+static struct lpbdma_test_data {
+ struct device *dev;
+ struct resource r_io;
+ void __iomem *bus_vaddr;
+ void *ram_vaddr;
+
+ /* Current data */
+ int current_repeat;
+ int current_test_case;
+ enum mpc512x_lpbfifo_req_dir current_dir;
+ struct mpc512x_lpbfifo_request current_req;
+} tt;
+
+static void lpbdma_prepare_next_iteration(void);
+static void lpbdma_testing(struct work_struct *w);
+static void lpbdma_test_callback(struct mpc512x_lpbfifo_request *req);
+static enum test_iteration_result lpbdma_test_iteration(unsigned int test_case,
+ enum mpc512x_lpbfifo_req_dir dir);
+
+static DECLARE_WORK(lpbdma_work, lpbdma_testing);
+static struct workqueue_struct *wq;
+
+static void lpbdma_prepare_next_iteration(void)
+{
+ tt.current_repeat++;
+
+ if (tt.current_repeat > repeat) {
+ tt.current_repeat = 1;
+ if (tt.current_dir == MPC512X_LPBFIFO_REQ_DIR_READ)
+ tt.current_dir = MPC512X_LPBFIFO_REQ_DIR_WRITE;
+ else {
+ tt.current_dir = MPC512X_LPBFIFO_REQ_DIR_READ;
+ tt.current_test_case += 1;
+ }
+ }
+}
+
+static void lpbdma_testing(struct work_struct *w)
+{
+ lpbdma_prepare_next_iteration();
+ while (lpbdma_test_iteration(tt.current_test_case,
+ tt.current_dir) == NEXT_TEST_PLEASE) {
+ lpbdma_prepare_next_iteration();
+ }
+}
+
+static enum test_iteration_result lpbdma_test_iteration(unsigned int test_case,
+ enum mpc512x_lpbfifo_req_dir dir)
+{
+ struct mpc512x_lpbfifo_request *req = &(tt.current_req);
+ int will_work;
+ unsigned int i;
+ unsigned int bufn;
+ u16 buf;
+
+ /* Prepare request for data transfer */
+ req->cs = 0;
+ req->bus_phys = tt.r_io.start;
+ req->ram_virt = tt.ram_vaddr;
+ req->dir = dir;
+ req->callback = lpbdma_test_callback;
+
+ switch (test_case) {
+ case 0:
+ /* normal LPB_DEV <-> RAM transfer */
+ will_work = 1;
+ req->size = 32768; /* 32 kBytes, for example */
+ req->portsize = LPB_DEV_PORTSIZE_UNDEFINED;
+ break;
+ case 1:
+ /* maximum size transfer */
+ will_work = 1;
+ req->size = 131068; /* 128 kBytes - 4 Bytes */
+ req->portsize = LPB_DEV_PORTSIZE_UNDEFINED;
+ break;
+ case 2:
+ /* maximum transfer size is exceeded */
+ will_work = 0;
+ req->size = 133120; /* 130 kBytes, for example */
+ req->portsize = LPB_DEV_PORTSIZE_UNDEFINED;
+ break;
+ case 3:
+ /* LPB_DEV has own FIFO register
+* It's width is 8 bytes, for example */
+ will_work = 1;
+ req->size = 16384; /* 16 kBytes, for example */
+ req->portsize = LPB_DEV_PORTSIZE_8_BYTES;
+ break;
+ case 4:
+ /* Ditto. But size is not aligned on portsize */
+ will_work = 0;
+ req->size = 16382;
+ req->portsize = LPB_DEV_PORTSIZE_8_BYTES;
+ break;
+ case 5:
+ /* size is not aligned on 4 */
+
[PATCH 1/2] powerpc/512x: add LocalPlus Bus FIFO device driver
This is SCLPC device driver for the Freescale MPC512x.
It is needed for Direct Memory Access to the devices on LocalPlus Bus.
Signed-off-by: Alexander Popov
---
arch/powerpc/boot/dts/mpc5121.dtsi| 8 +-
arch/powerpc/include/asm/mpc5121.h| 32 ++
arch/powerpc/platforms/512x/Kconfig | 6 +
arch/powerpc/platforms/512x/Makefile | 1 +
arch/powerpc/platforms/512x/mpc512x_lpbfifo.c | 493 ++
5 files changed, 539 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/platforms/512x/mpc512x_lpbfifo.c
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi
b/arch/powerpc/boot/dts/mpc5121.dtsi
index 723e292..6c4d551 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -259,7 +259,13 @@
/* LocalPlus controller */
lpc@1 {
compatible = "fsl,mpc5121-lpc";
- reg = <0x1 0x200>;
+ reg = <0x1 0x100>;
+ };
+
+ sclpc@10100 {
+ compatible = "fsl,mpc512x-lpbfifo";
+ reg = <0x10100 0x50>;
+ interrupts = <7 0x8>;
};
pata@10200 {
diff --git a/arch/powerpc/include/asm/mpc5121.h
b/arch/powerpc/include/asm/mpc5121.h
index 885c040..5ed6a8e 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -70,4 +70,36 @@ struct mpc512x_lpc {
int mpc512x_cs_config(unsigned int cs, u32 val);
int __init mpc5121_clk_init(void);
+/*
+ * SCLPC Module (LPB FIFO)
+ */
+enum lpb_dev_portsize {
+ LPB_DEV_PORTSIZE_UNDEFINED = 0,
+ LPB_DEV_PORTSIZE_1_BYTE = 1,
+ LPB_DEV_PORTSIZE_2_BYTES = 2,
+ LPB_DEV_PORTSIZE_4_BYTES = 4,
+ LPB_DEV_PORTSIZE_8_BYTES = 8,
+};
+
+enum mpc512x_lpbfifo_req_dir {
+ MPC512X_LPBFIFO_REQ_DIR_READ,
+ MPC512X_LPBFIFO_REQ_DIR_WRITE,
+};
+
+struct mpc512x_lpbfifo_request {
+ unsigned int cs;
+ phys_addr_t bus_phys; /* physical address of some device on lpb */
+ void *ram_virt; /* virtual address of some region in ram */
+
+ /* Details of transfer */
+ u32 size;
+ enum lpb_dev_portsize portsize;
+ enum mpc512x_lpbfifo_req_dir dir;
+
+ /* Call when the transfer is finished */
+ void (*callback)(struct mpc512x_lpbfifo_request *);
+};
+
+extern int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
+
#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/platforms/512x/Kconfig
b/arch/powerpc/platforms/512x/Kconfig
index 381a592..2e75d3c 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -10,6 +10,12 @@ config PPC_MPC512x
select USB_EHCI_BIG_ENDIAN_MMIO
select USB_EHCI_BIG_ENDIAN_DESC
+config PPC_MPC512x_LPBFIFO
+ tristate "MPC512x LocalPlus bus FIFO driver"
+ depends on PPC_MPC512x && MPC512X_DMA
+ help
+ Enable support for the Freescale MPC512x SCLPC.
+
config MPC5121_ADS
bool "Freescale MPC5121E ADS"
depends on PPC_MPC512x
diff --git a/arch/powerpc/platforms/512x/Makefile
b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4..f2dc44e 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Freescale PowerPC 512x linux kernel.
#
obj-y += clock.o mpc512x_shared.o
+obj-$(CONFIG_PPC_MPC512x_LPBFIFO) += mpc512x_lpbfifo.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC5121_GENERIC) += mpc5121_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/mpc512x_lpbfifo.c
b/arch/powerpc/platforms/512x/mpc512x_lpbfifo.c
new file mode 100644
index 000..7095e70
--- /dev/null
+++ b/arch/powerpc/platforms/512x/mpc512x_lpbfifo.c
@@ -0,0 +1,493 @@
+/*
+ * LocalPlus Bus SCLPC driver for the Freescale MPC512x.
+ *
+ * Copyright (C) Promcontroller, 2013.
+ *
+ * Author is Alexander Popov .
+ *
+ * The driver design is based on mpc52xx_lpbfifo driver
+ * written by Grant Likely .
+ *
+ * This file is released under the GPLv2.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+MODULE_AUTHOR("Alexander Popov ");
+MODULE_DESCRIPTION("MPC512x LocalPlus FIFO device driver");
+MODULE_LICENSE("GPL");
+
+#define DRV_NAME "mpc512x_lpbfifo"
+
+#define LPBFIFO_REG_PACKET_SIZE(0x00)
+#define LPBFIFO_REG_START_ADDRESS (0x04)
+#define LPBFIFO_REG_CONTROL(0x08)
+#define LPBFIFO_REG_ENABLE (0x0C)
+#define LPBFIFO_REG_STATUS (0x14)
+#define LPBFIFO_REG_BYTES_DONE (0x18)
+#define LPBFIFO_REG_EMB_SHARE_COUNTER (0x1C)
+#define LPBFIFO_REG_EMB_PAUSE_CONTROL (0x20)
+#define LPBFIFO_REG_FIFO_DATA (0x40)
+#define LPBFIFO_R
RE: [PATCH 1/2 v15] iommu/fsl: Add additional iommu attributes required by the PAMU driver.
> -Original Message- > From: j...@8bytes.org [mailto:j...@8bytes.org] > Sent: Thursday, May 02, 2013 3:46 PM > To: Sethi Varun-B16395 > Cc: io...@lists.linux-foundation.org; linuxppc-dev@lists.ozlabs.org; > linux-ker...@vger.kernel.org; ga...@kernel.crashing.org; > b...@kernel.crashing.org; Yoder Stuart-B08248; Wood Scott-B07421 > Subject: Re: [PATCH 1/2 v15] iommu/fsl: Add additional iommu attributes > required by the PAMU driver. > > On Tue, Apr 30, 2013 at 05:09:32PM +, Sethi Varun-B16395 wrote: > > Would you take this patchset for 3.10 merge? > > Not this time. The final patch came in very late and is pretty big too. > For code of that size I would like to have a few weeks more testing in > next and probably also a non-Freescale Reviewed-by. [Sethi Varun-B16395] I would request you and Alex Williamson to review the patch and provide a Reviewed-by. -Varun ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -next] kvm/ppc/mpic: fix missing unlock in set_base_addr()
On 02.05.2013, at 07:17, Wei Yongjun wrote: > From: Wei Yongjun > > Add the missing unlock before return from function set_base_addr() > when disables the mapping. > > Introduced by commit 5df554ad5b7522ea62b0ff9d5be35183494efc21 > (kvm/ppc/mpic: in-kernel MPIC emulation) > > Signed-off-by: Wei Yongjun Thanks, applied to kvm-ppc-queue. Alex > --- > arch/powerpc/kvm/mpic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/kvm/mpic.c > index f3148f8..0047a70 100644 > --- a/arch/powerpc/kvm/mpic.c > +++ b/arch/powerpc/kvm/mpic.c > @@ -1475,8 +1475,8 @@ static int set_base_addr(struct openpic *opp, struct > kvm_device_attr *attr) > > map_mmio(opp); > > - mutex_unlock(&opp->kvm->slots_lock); > out: > + mutex_unlock(&opp->kvm->slots_lock); > return 0; > } > > ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2 v15] iommu/fsl: Add additional iommu attributes required by the PAMU driver.
On Tue, Apr 30, 2013 at 05:09:32PM +, Sethi Varun-B16395 wrote: > Would you take this patchset for 3.10 merge? Not this time. The final patch came in very late and is pretty big too. For code of that size I would like to have a few weeks more testing in next and probably also a non-Freescale Reviewed-by. Joerg ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/powernv: defer OPAL exception handler registration
Currently, the OPAL exception vectors are registered before the feature
fixups are processed. This means that the now-firmware-owned vectors
will likely be overwritten by the kernel.
This change moves the exception registration code to an early initcall,
rather than at machine_init time.
Signed-off-by: Jeremy Kerr
---
arch/powerpc/platforms/powernv/opal.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal.c
b/arch/powerpc/platforms/powernv/opal.c
index aaa0dba..ade4463 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -34,7 +34,6 @@ int __init early_init_dt_scan_opal(unsigned long node,
{
const void *basep, *entryp;
unsigned long basesz, entrysz;
- u64 glue;
if (depth != 1 || strcmp(uname, "ibm,opal") != 0)
return 0;
@@ -61,6 +60,16 @@ int __init early_init_dt_scan_opal(unsigned long node,
printk("OPAL V1 detected !\n");
}
+ return 1;
+}
+
+static int __init opal_register_exception_handlers(void)
+{
+ u64 glue;
+
+ if (!(powerpc_firmware_features & FW_FEATURE_OPAL))
+ return -ENODEV;
+
/* Hookup some exception handlers. We use the fwnmi area at 0x7000
* to provide the glue space to OPAL
*/
@@ -74,9 +83,11 @@ int __init early_init_dt_scan_opal(unsigned long node,
glue += 128;
opal_register_exception_handler(OPAL_SOFTPATCH_HANDLER, 0, glue);
- return 1;
+ return 0;
}
+early_initcall(opal_register_exception_handlers);
+
int opal_get_chars(uint32_t vtermno, char *buf, int count)
{
s64 len, rc;
___
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[git pull] Please pull powerpc.git next branch
Hi Linus ! Here's the next pack of powerpc changes ! The main highlights this time around are: - A pile of addition POWER8 bits and nits, such as updated performance counter support (Michael Ellerman), new branch history buffer support (Anshuman Khandual), base support for the new PCI host bridge when not using the hypervisor (Gavin Shan) and other random related bits and fixes from various contributors. - Some rework of our page table format by Aneesh Kumar which fixes a thing or two and paves the way for THP support. THP itself will not make it this time around however. - More Freescale updates, including Altivec support on the new e6500 cores, new PCI controller support, and a pile of new boards support and updates. - The usual batch of trivial cleanups & fixes. Cheers, Ben. The following changes since commit 60d509fa6a9c4653a86ad830e4c4b30360b23f0e: Linux 3.9-rc8 (2013-04-21 14:38:45 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next for you to fetch changes up to 54d5999d98f2ab36ad71b9ef4d82cf5f399205f5: powerpc: Fix build error for book3e (2013-05-02 10:37:37 +1000) Adhemerval Zanella (1): powerpc: Add VDSO version of time Adrian-Leonard Radu (1): powerpc: Use PTR_RET instead of IS_ERR/PTR_ERR Alex Grad (1): powerpc/kgdb: Removed kmalloc returned value cast Alexey Kardashevskiy (1): powerpc: fixing ptrace_get_reg to return an error Anatolij Gustschin (2): powerpc/mpc512x: create SoC devices for more nodes powerpc/512x: add ifm ac14xx board Andy Shevchenko (1): powerpc/pmac/smu: Use %*ph to print small buffers Aneesh Kumar K.V (16): powerpc: Use signed formatting when printing error powerpc: Save DAR and DSISR in pt_regs on MCE powerpc: Don't hard code the size of pte page powerpc: Don't truncate pgd_index wrongly powerpc: New hugepage directory format powerpc: Switch 16GB and 16MB explicit hugepages to a different page table format powerpc: Reduce the PTE_INDEX_SIZE powerpc: Move the pte free routines from common header powerpc: Reduce PTE table memory wastage powerpc: Use encode avpn where we need only avpn values powerpc: Decode the pte-lp-encoding bits correctly. powerpc: Fix hpte_decode to use the correct decoding for page sizes powerpc: print both base and actual page size on hash failure powerpc: Print page size info during boot powerpc: Update tlbie/tlbiel as per ISA doc powerpc: Fix build error for book3e Anshuman Khandual (6): powerpc/perf: Add new BHRB related instructions for POWER8 powerpc/perf: Add basic assembly code to read BHRB entries on POWER8 powerpc/perf: Add new BHRB related generic functions, data and flags powerpc/perf: Define BHRB generic functions, data and flags for POWER8 powerpc/perf: Enable branch stack sampling framework powerpc: Setup BHRB instructions facility in HFSCR for POWER8 Ben Collins (1): powerpc/85xx: sgy-cts1000 - Remove __dev* attributes Benjamin Herrenschmidt (5): Merge remote-tracking branch 'mpe/master' into next Merge remote-tracking branch 'origin/master' into next powerpc/powernv: Fix missing Kconfig dependency for MSIs Merge remote-tracking branch 'agust/next' into next Merge remote-tracking branch 'kumar/next' into next Bharat Bhushan (1): powerpc: Fix interrupt range check on debug exception Brian King (2): pci: Set dev->dev.type in alloc_pci_dev powerpc: Set default VGA device Chen Gang (1): powerpc/pseries/lparcfg: Fix possible overflow are more than 1026 Chen-Hui Zhao (1): powerpc/85xx: fix a bug with the parameter of mpic_reset_core() Gavin Shan (8): powerpc/kernel: Cleanup on rtas_pci.c powerpc/powernv: Use MSI bitmap to manage IRQs powerpc/powernv: Supports PHB3 powerpc/powernv: Add option CONFIG_POWERNV_MSI powerpc/powernv: Patch MSI EOI handler on P8 powerpc/powernv: TCE invalidation for PHB3 powerpc/powernv: Build DMA space for PE on PHB3 powerpc/powernv: Fix invalid IOMMU table Geoff Levand (1): powerpc/ps3: Update ps3_defconfig Ian Munsie (1): powerpc: Add accounting for Doorbell interrupts Jesse Larrew (4): powerpc/pseries: Add PRRN RTAS event handler powerpc/pseries: Update CPU maps when device tree is updated powerpc/pseries: Update NUMA VDSO information when updating CPU maps powerpc/pseries: RE-enable Virtual Processor Home Node updating Jia Hongtao (1): powerpc/85xx: Add platform_device declaration to fsl_pci.h Jiucheng Xu (1): powerpc/85xx: Reserve a partition of NOR flash for QE ucode firmware Kevin Hao (3): powerpc/fsl-pci: don't unmap the PCI SoC controller registers in setup_pci_atmu powerpc/fsl-booke: add the reg
RE: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
> -Original Message- > From: Wood Scott-B07421 > Sent: Tuesday, April 30, 2013 4:30 AM > To: Jia Hongtao-B38951 > Cc: Wood Scott-B07421; Segher Boessenkool; linuxppc-dev@lists.ozlabs.org; > ga...@kernel.crashing.org > Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to > fix PCIe erratum on mpc85xx > > On 04/26/2013 09:26:26 PM, Jia Hongtao-B38951 wrote: > > > -Original Message- > > > From: Wood Scott-B07421 > > > Sent: Friday, April 26, 2013 12:58 AM > > > To: Segher Boessenkool > > > Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; > > > ga...@kernel.crashing.org; Wood Scott-B07421 > > > Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler > > to > > > fix PCIe erratum on mpc85xx > > > > > > On 04/25/2013 10:31:51 AM, Segher Boessenkool wrote: > > > >> * Remove A variant of load instruction emulation > > > > > > > > Why is this? You handle all other simple load insns, there is > > nothing > > > > special about LHA. (I reviewed the V4 email thread, no reason > > for the > > > > chance is given there). > > > > > > The LHA implementation in V5 was incorrect (didn't sign-extend). > > > > > > -Scott > > > > In former email you doubt whether we need A variant or not. > > Any particular reason for that? > > If not should I emulate all the A ARX AU AUX and AX variant? > > I was just noting that the variants you left out from the earlier > revisions (e.g. BRX) were much more likely to be used for I/O than some > of the ones you included (e.g. "A"). Implementing all the normal > load/store instructions would be better, if they're done correctly. > > -Scott All right. I have submitted a new version and please have a review. http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
