RE: [PATCH 4/4 V2] mmc: esdhc: Add broken timeout quirk for p4/p5 board
Thanks. Regards Haijun. -Original Message- From: Wood Scott-B07421 Sent: Saturday, July 20, 2013 1:24 AM To: Zhang Haijun-B42677 Cc: Wood Scott-B07421; linux-...@vger.kernel.org; linuxppc- d...@lists.ozlabs.org; cbouatmai...@gmail.com; c...@laptop.org; Fleming Andy-AFLEMING Subject: Re: [PATCH 4/4 V2] mmc: esdhc: Add broken timeout quirk for p4/p5 board On 07/18/2013 09:19:59 PM, Zhang Haijun-B42677 wrote: Thanks. Regards Haijun. -Original Message- From: Wood Scott-B07421 Sent: Thursday, July 18, 2013 1:14 AM To: Zhang Haijun-B42677 Cc: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; cbouatmai...@gmail.com; c...@laptop.org; Fleming Andy-AFLEMING; Zhang Haijun-B42677; Zhang Haijun-B42677 Subject: Re: [PATCH 4/4 V2] mmc: esdhc: Add broken timeout quirk for p4/p5 board On 07/17/2013 05:11:31 AM, Haijun Zhang wrote: Sometimes command can't be completed within the time give in eSDHC_SYSCTL[DTOCV]. So just give the max value 0x14 to avoid this issue. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for v2: - Rebuild patch of eSDHC host need long time to generate command interrupt drivers/mmc/host/sdhci-of-esdhc.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 570bca8..30bfb5c 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -325,6 +325,12 @@ static void esdhc_of_platform_init(struct sdhci_host *host) if (vvn VENDOR_V_22) host-quirks = ~SDHCI_QUIRK_NO_BUSY_IRQ; + + if ((SVR_SOC_VER(svr) == SVR_B4860) || + (SVR_SOC_VER(svr) == SVR_P5020) || + (SVR_SOC_VER(svr) == SVR_P5040) || + (SVR_SOC_VER(svr) == SVR_P4080)) + host-quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; } Please don't line up the continuation lines of the if-condition with the if-body. [Haijun Wrote:] I'll correct it. Please check variant SoCs as well. If the bug exists on p4080, then it exists on p4040. Likewise with p5040/p5021, and p5020/p5010. Is it present on all revisions of these SoCs? How about p3041, which is usually pretty similar to p5020? p2040/p2041? Is there an erratum number for this problem? [Haijun Wrote:] I only checked this on these boards. These aren't boards; they're chips. Please find out for sure which chips are affected, or else we'll have support issues later when someone is using a chip you didn't test with. And always include the fewer-core variants -- if p4080 is affected, then p4040 is affected, and so on as described above. [Haijun Wrote:] Ok, I'll try to cover all the chips. No errata number yet, Will one be coming? [Haijun Wrote:] I need to confirm with integration team. This may take a long time for so many chips. This quirk only give the host max detecting time value to check card's response. No impact on performance or other functions. Does this affect boot time if a card is not present? [Haijun Wrote:] No impact on boot time. Normally a command can finished within 10*HZ, In extreme cases this time will be extended. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/4 V4] powerpc/85xx: Add support for 85xx cpu type detection
Many Thanks. Regards Haijun. -Original Message- From: Wood Scott-B07421 Sent: Saturday, July 20, 2013 1:21 AM To: Zhang Haijun-B42677 Cc: Zhang Haijun-B42677; linux-...@vger.kernel.org; linuxppc- d...@lists.ozlabs.org; cbouatmai...@gmail.com; c...@laptop.org; Wood Scott- B07421; Fleming Andy-AFLEMING; Zhao Chenhui-B35336 Subject: Re: [PATCH 1/4 V4] powerpc/85xx: Add support for 85xx cpu type detection On 07/18/2013 09:28:20 PM, Zhang Haijun-B42677 wrote: Hi, scott I had update this patch, this is the newest version. If there is no other problem, can you help merge this patch? I hope to make sure the following patch don't need to rebuild due to the change of this patch. It looks OK. I'll pick it up when I do my next batch of patch application (hopefully soon). Go ahead and send the patches that depend on it. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Hi Scott,
The fsl_msi.c build error on MPC83xx platform is fixed by this patch.
Could you please have a review?
Thanks.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Wednesday, July 10, 2013 10:04 AM
To: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Hi Scott,
I made this patch to fix msi compile error on mpc83xx.
Could you please have a review.
Thanks.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, July 02, 2013 9:37 AM
To: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to
`fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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[PATCH v4 0/3] DMA: Freescale: Add support for 8-channel DMA engine
From: Hongbo Zhang hongbo.zh...@freescale.com Hi Vinod, Dan, Scott and Leo, please have a look at these V2 patches. Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set adds support this DMA engine. V3-V4 changes: - introduce new patch [1/3] to revise the legacy dma binding document - and then add new paragraph to describe new dt node binding in [2/3] - rebase to latest kernel v3.11-rc1 V2-V3 changes: - edit Documentation/devicetree/bindings/powerpc/fsl/dma.txt - edit text string in Kconfig and the driver files, using elo series to mention all the current elo* V1-V2 changes: - removed the codes handling the register dgsr1, since it isn't used corrently - renamed the DMA DT compatible to fsl,elo3-dma - renamed the new dts files to elo3-dma-n.dtsi Hongbo Zhang (3): DMA: Freescale: revise device tree binding document DMA: Freescale: Add new 8-channel DMA engine device tree nodes DMA: Freescale: update driver to support 8-channel DMA engine .../devicetree/bindings/powerpc/fsl/dma.txt| 122 +++- arch/powerpc/boot/dts/fsl/b4si-post.dtsi |4 +- arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 81 + arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 81 + arch/powerpc/boot/dts/fsl/t4240si-post.dtsi|4 +- drivers/dma/Kconfig|9 +- drivers/dma/fsldma.c |9 +- drivers/dma/fsldma.h |2 +- 8 files changed, 274 insertions(+), 38 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch add
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
arch/powerpc/boot/dts/fsl/b4si-post.dtsi |4 +-
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 81
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 81
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi|4 +-
5 files changed, 232 insertions(+), 4 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
index 0650171..aa44e3c 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -138,6 +138,72 @@ Example:
};
};
+** Freescale ELO3 DMA Controller
+ This is ELOPLUS controller with 8 channels.
+ Used in Freescale new Txxx and Bxxx series chips, such as:
+ t4240, b4860, t1040
+
+Required properties:
+
+- compatible: should be fsl,elo3-dma
+- reg : registers mapping for DMA general status reg
+- ranges: physical address range of DMA controller channels
+
+- DMA channel nodes:
+- compatible: should be fsl,eloplus-dma-channel
+- reg : registers mapping for channel
+- interrupts: interrupt mapping for DMA channel IRQ
+- interrupt-parent : optional, if needed for interrupt mapping
+
+Example:
+dma@100300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x100300 0x4 0x100600 0x4;
+ ranges = 0x0 0x100100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 28 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 29 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 30 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 31 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 76 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 77 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 78 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 79 2 0 0;
+ };
+};
+
Note on DMA channel compatible properties: The compatible property must say
fsl,elo-dma-channel or fsl,eloplus-dma-channel to be used by the Elo DMA
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 7399154..ea53ea1 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -223,13 +223,13 @@
reg = 0xe2000 0x1000;
};
-/include/ qoriq-dma-0.dtsi
+/include/ elo3-dma-0.dtsi
dma@100300 {
fsl,iommu-parent = pamu0;
fsl,liodn-reg = guts 0x580; /* DMA1LIODNR */
};
-/include/ qoriq-dma-1.dtsi
+/include/ elo3-dma-1.dtsi
dma@101300 {
fsl,iommu-parent = pamu0;
fsl,liodn-reg = guts 0x584; /* DMA2LIODNR */
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
new file mode 100644
index 000..bc8dc29
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
@@ -0,0 +1,81 @@
+/*
+ * QorIQ DMA device tree stub [ controller @ offset 0x10 ]
+ *
+ * Copyright 2011-2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or
[PATCH v4 1/3] DMA: Freescale: revise device tree binding document
From: Hongbo Zhang hongbo.zh...@freescale.com This updates the discription of each type of DMA controller and its channels, it is preparation for adding another new DMA controller binding, also fixes some defects of indent for text alignment at the same time. Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com --- .../devicetree/bindings/powerpc/fsl/dma.txt| 56 +++- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index 2a4b4bc..0650171 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -1,33 +1,33 @@ -* Freescale 83xx DMA Controller +* Freescale DMA Controllers -Freescale PowerPC 83xx have on chip general purpose DMA controllers. +** Freescale ELO DMA Controller + This is a little-endian DMA controller. + Used in Freescale PowerPC 83xx series, such as: + mpc8313, mpc8315, mpc8323, mpc8347, mpc8349, mpc8360, mpc8377, mpc8378, mpc8379. Required properties: - compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma, where CHIP is the processor -(mpc8349, mpc8360, etc.) and the second is -fsl,elo-dma + fsl,CHIP-dma, where CHIP is the processor + and the second is fsl,elo-dma - reg : registers mapping for DMA general status reg -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges: physical address range of DMA controller channels - cell-index: controller index. 0 for controller @ 0x8100 - interrupts: interrupt mapping for DMA IRQ - interrupt-parent : optional, if needed for interrupt mapping - - DMA channel nodes: - compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma-channel, where CHIP is the processor -(mpc8349, mpc8350, etc.) and the second is -fsl,elo-dma-channel. However, see note below. + fsl,CHIP-dma-channel, where CHIP is the processor + and the second is fsl,elo-dma-channel. + However, see note below. - reg : registers mapping for channel - cell-index: dma channel index starts at 0. Optional properties: - interrupts: interrupt mapping for DMA channel IRQ - (on 83xx this is expected to be identical to - the interrupts property of the parent node) + (on 83xx this is expected to be identical to + the interrupts property of the parent node) - interrupt-parent : optional, if needed for interrupt mapping Example: @@ -70,27 +70,31 @@ Example: }; }; -* Freescale 85xx/86xx DMA Controller - -Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. +** Freescale ELOPLUS DMA Controller + This is DMA controller with extended addresses and chaining. + Used in Freescale PowerPC 85xx/86xx and pxxx series chips, such as: + [1] mpc8540, mpc8541, mpc8555, mpc8560, mpc8610, mpc8641, + [2] mpc8536, mpc8544, mpc8548, mpc8568, mpc8569, mpc8572, p1010, p1020, p1021, + p1022, p1023, p2020, p2041, p3041, p4080, p5020, p5040, and also bsc9131. Required properties: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma, where CHIP is the processor -(mpc8540, mpc8540, etc.) and the second is -fsl,eloplus-dma +- compatible: compatible list, contains 2 entries for chips in above + list[1], the first is fsl,CHIP-dma, where CHIP is the + processor and the second is fsl,eloplus-dma. contains + only one fsl,eloplus-dma for chips in above list[2] - reg : registers mapping for DMA general status reg - cell-index: controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 -- ranges : Should be defined as specified in 1) to describe the - DMA controller channels. +- ranges: physical address range of DMA controller channels - DMA channel nodes: -- compatible: compatible list, contains 2 entries, first is -fsl,CHIP-dma-channel, where CHIP is the processor -(mpc8540, mpc8560, etc.) and the second is -fsl,eloplus-dma-channel. However, see note below. +- compatible: compatible list, contains 2 entries for chips in + above
[PATCH v4 3/3] DMA: Freescale: update driver to support 8-channel DMA engine
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
drivers/dma/Kconfig |9 +
drivers/dma/fsldma.c |9 ++---
drivers/dma/fsldma.h |2 +-
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6825957..f3642fc 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -89,14 +89,15 @@ config AT_HDMAC
Support the Atmel AHB DMA controller.
config FSL_DMA
- tristate Freescale Elo and Elo Plus DMA support
+ tristate Freescale ELO series DMA support
depends on FSL_SOC
select DMA_ENGINE
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
---help---
- Enable support for the Freescale Elo and Elo Plus DMA controllers.
- The Elo is the DMA controller on some 82xx and 83xx parts, and the
- Elo Plus is the DMA controller on 85xx and 86xx parts.
+ Enable support for the Freescale ELO series DMA controllers.
+ The ELO is the DMA controller on some mpc82xx and mpc83xx parts, the
+ ELOPLUS is on mpc85xx and mpc86xx and Pxxx parts, and the ELO3 is on
+ some Txxx and Bxxx parts. Look up user manuals for details anyway.
config MPC512X_DMA
tristate Freescale MPC512x built-in DMA engine support
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 49e8fbd..16a9a48 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1261,7 +1261,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
WARN_ON(fdev-feature != chan-feature);
chan-dev = fdev-dev;
- chan-id = ((res.start - 0x100) 0xfff) 7;
+ chan-id = (res.start 0xfff) 0x300 ?
+ ((res.start - 0x100) 0xfff) 7 :
+ ((res.start - 0x200) 0xfff) 7;
if (chan-id = FSL_DMA_MAX_CHANS_PER_DEVICE) {
dev_err(fdev-dev, too many channels for device\n);
err = -EINVAL;
@@ -1434,6 +1436,7 @@ static int fsldma_of_remove(struct platform_device *op)
}
static const struct of_device_id fsldma_of_ids[] = {
+ { .compatible = fsl,elo3-dma, },
{ .compatible = fsl,eloplus-dma, },
{ .compatible = fsl,elo-dma, },
{}
@@ -1455,7 +1458,7 @@ static struct platform_driver fsldma_of_driver = {
static __init int fsldma_init(void)
{
- pr_info(Freescale Elo / Elo Plus DMA driver\n);
+ pr_info(Freescale Elo series DMA driver\n);
return platform_driver_register(fsldma_of_driver);
}
@@ -1467,5 +1470,5 @@ static void __exit fsldma_exit(void)
subsys_initcall(fsldma_init);
module_exit(fsldma_exit);
-MODULE_DESCRIPTION(Freescale Elo / Elo Plus DMA driver);
+MODULE_DESCRIPTION(Freescale Elo series DMA driver);
MODULE_LICENSE(GPL);
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index f5c3879..1ffc244 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -112,7 +112,7 @@ struct fsldma_chan_regs {
};
struct fsldma_chan;
-#define FSL_DMA_MAX_CHANS_PER_DEVICE 4
+#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
struct fsldma_device {
void __iomem *regs; /* DGSR register base */
--
1.7.9.5
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