RE: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
> -Original Message- > From: Wood Scott-B07421 > Sent: Tuesday, September 17, 2013 2:49 AM > To: Kushwaha Prabhakar-B32579 > Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; > ga...@kernel.crashing.org; Aggrwal Poonam-B10812; Jain Priyanka-B32167; > Sethi Varun-B16395 > Subject: Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of > T104x > > On Fri, 2013-09-13 at 02:30 -0500, Kushwaha Prabhakar-B32579 wrote: > > > I also question the need to define separate t1040 compatible values > > > for all of these, if the only difference is whether the onboard > > > switch is enabled or not. > > > > > > > so should I use T104x as compatible field. and in T1040 device tree add > extra node for l2 switch. I am using T1042 as base dts and T1040 includes T1040 + l2switch. so if I use T1042 in compatible. It will give wrong field for someone working on T1040QDS. best solution should be to have a) have T1042 in compatible field. b) T1040 dts override T1042 to t1040 in compatible field. it will give correct picture Regards, Prabhakar ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
I see, thanks. ^_^
于 2013/9/17 3:42, Scott Wood 写道:
On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
On 09/02/2013 06:37 PM, Haijun Zhang wrote:
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
Signed-off-by: Haijun Zhang
---
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
index 5180d9d..0c0efa9 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -130,7 +130,7 @@ usb@22000 {
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
- fsl,sdhci-auto-cmd12;
+ sdhci,auto-cmd12;
interrupts = <41 0x2 0 0>;
};
Hi, scott
Could you help review this patch?
I process patches in periodic batches. There's no need for a reminder
when it's only been two weeks, as long as it's still marked "new" or
"under review" in patchwork (and you should include a patchwork link in
any such reminder e-mail). Especially for a trivial patch such as this,
no comment often means I looked at it and saw no problems and will take
it in the next batch.
Though if you want a comment, don't capitalize "powerpc" in the
subject. :-)
-Scott
--
Thanks & Regards
Haijun.
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Re: [PATCH v2 1/3] powerpc/booke64: add sync after writing PTE
On Mon, 2013-09-16 at 07:38 +1000, Benjamin Herrenschmidt wrote: > On Fri, 2013-09-13 at 22:50 -0500, Scott Wood wrote: > > The ISA says that a sync is needed to order a PTE write with a > > subsequent hardware tablewalk lookup. On e6500, without this sync > > we've been observed to die with a DSI due to a PTE write not being seen > > by a subsequent access, even when everything happens on the same > > CPU. > > This is gross, I didn't realize we had that bogosity in the > architecture... > > Did you measure the performance impact ? I didn't see a noticeable impact on the tests I ran, but those were aimed at measuring TLB miss overhead. I'll need to try it with a benchmark that's more oriented around lots of page table updates. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2][RFC][v3] pci: fsl: rework PCI driver compatible with Layerscape
On Thu, 2013-09-12 at 18:07 +0800, Minghuan Lian wrote:
> The Freescale's Layerscape series processors will use the same PCI
> controller but change cores from PowerPC to ARM. This patch is to
> rework FSL PCI driver to support PowerPC and ARM simultaneously.
> PowerPC uses structure pci_controller to describe PCI controller,
> but arm uses structure hw_pci and pci_sys_data. They also have
> different architecture implementation and initialization flow.
> The architecture-dependent driver will bridge the gap, get the
> settings from the common driver and initialize the corresponding
> structure and call the related interface to register PCI controller.
> The common driver pci-fsl.c removes all the architecture-specific
> code and provides structure fsl_pci to store all the controller
> settings and the common functionalities that include reading/writing
> PCI configuration space, parsing dts node and getting the MEM/IO and
> bus number ranges, setting ATMU and check link status.
>
> Signed-off-by: Minghuan Lian
> ---
> Based on upstream master
> The function has been tested on MPC8315ERDB MPC8572DS P5020DS P3041DS
> and T4240QDS boards
>
> Change log:
> v3:
> 1. use 'fsl_arch' as function name prefix of all the
>architecture-specific hooks.
> 2. Move PCI compatible definitions from arch/powerpc/sysdev/fsl_pci.c
>to driver/pci/host/pci-fsl.c
>
> v2:
> 1. Use 'pci' instead of 'pcie' in new file name and file contents.
> 2. Use iowrite32be()/iowrite32() instead of out_be32/le32()
> 3. Fix ppc_md.dma_set_mask setting
> 4. Synchronizes host->first_busno and pci->first_busno.
> 5. Fix PCI IO space settings
> 6. Some small changes according to Scott's comments.
>
>
> arch/powerpc/Kconfig | 1 +
> arch/powerpc/sysdev/fsl_pci.c | 150 +-
> drivers/edac/mpc85xx_edac.c | 9 -
> drivers/pci/host/Kconfig | 4 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-fsl.c| 656
> +++---
> include/linux/fsl/pci.h | 69 +
> 7 files changed, 648 insertions(+), 242 deletions(-)
The PCI mailing list and maintainer should be included.
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 6b7530f..657d90f 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -691,6 +691,7 @@ config FSL_SOC
>
> config FSL_PCI
> bool
> + select PCI_FSL if FSL_SOC_BOOKE || PPC_86xx
> select PPC_INDIRECT_PCI
> select PCI_QUIRKS
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index a189ff0..4cb12e8 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>
> #define MAX_PHYS_ADDR_BITS 40
> -static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
> +
> +u64 fsl_arch_pci64_dma_offset(void)
> +{
> + return 1ull << MAX_PHYS_ADDR_BITS;
> +}
>
> static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
> {
> @@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64
> dma_mask)
> if ((dev->bus == &pci_bus_type) &&
> dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
> set_dma_ops(dev, &dma_direct_ops);
> - set_dma_offset(dev, pci64_dma_offset);
> + set_dma_offset(dev, fsl_arch_pci64_dma_offset());
> }
Is the intent for fsl_arch_pci64_dma_offset() to eventually do something
that isn't calculable at compile time?
> *dev->dma_mask = dma_mask;
> return 0;
> }
>
> +struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
> +{
> + struct pci_controller *hose = sys;
> + struct fsl_pci *pci = hose->private_data;
If this were just to convert to fsl_pci, that seems like header
material.
> + /* Update the first bus number */
> + if (pci->first_busno != hose->first_busno)
> + pci->first_busno = hose->first_busno;
This isn't part of the interface description in the header...
> +static int mpc83xx_pcie_check_link(struct pci_controller *hose)
> +{
> + u32 val = 0;
> +
> +#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> +#define PCIE_LTSSM_L00x16/* L0 state */
> +
> + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
> + if (val < PCIE_LTSSM_L0)
> + return 1;
> + return 0;
> +}
Aren't PCIE_LTSSM and PCIE_LTSSM_L0 defined in include/linux/fsl/pci.h
at this point?
> @@ -260,14 +259,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
> /* we only need the error registers */
> r.start += 0xe00;
>
> - if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
> - pdata->name)) {
> - printk(KERN_ERR "%s: Error while requesting mem region\n",
> -__func__);
> - res = -EBUSY;
> - g
Re: [linuxppc-release] [Patch v2 1/2] powerpc/t4240emu: Add device tree file for t4240emu
On 09/16/2013 04:38 PM, York Sun wrote: > T4240EMU is an emulator target with minimum peripherals. It is based on > T4240QDS and trimmed down most peripherals due to either not modeled or > lack of board level connections. The main purpose of this minimum dts is > to speed up booting on emulator. > > Signed-off-by: York Sun > --- > Change log: > v2: remote reviewed-by and tested-by lines added by gerrit > resync with t4240qds.dts > Pardon my typo. I meant to type "remove", instead of "remote". York ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [linuxppc-release] [Patch v2] powerpc/corenet64_smp_defconfig: Enable most SPI splash
On 09/16/2013 04:35 PM, York Sun wrote: > Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on > P5040DS. > > Signed-off-by: York Sun > --- > Change log: > v2: remote reviewed-by and tested-by lines added by gerrit > Pardon my typo. I meant to type "remove", instead of "remote". York ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[Patch v2 2/2] powerpc/b4860emu: Add device tree file for b4860emu
B4860EMU is a emualtor target with minimum peripherals. It is based on
B4860QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
resync with b4860qds.dts
arch/powerpc/boot/dts/b4860emu.dts | 219
1 file changed, 219 insertions(+)
create mode 100644 arch/powerpc/boot/dts/b4860emu.dts
diff --git a/arch/powerpc/boot/dts/b4860emu.dts
b/arch/powerpc/boot/dts/b4860emu.dts
new file mode 100644
index 000..0f91230
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -0,0 +1,219 @@
+/*
+ * B4860 emulator Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/include/ "fsl/e6500_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,B4860";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ next-level-cache = <&L2>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ next-level-cache = <&L2>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ next-level-cache = <&L2>;
+ };
+ };
+};
+
+/ {
+ model = "fsl,B4860QDS";
+ compatible = "fsl,B4860EMU", "fsl,B4860QDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x800>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe00 {
+ ranges = <0x 0xf 0xfe00 0x100>;
+ reg = <0xf 0xfe00 0 0x1000>;
+
+ };
+};
+
+&ifc {
+ #address-cells = <2
[Patch v2 1/2] powerpc/t4240emu: Add device tree file for t4240emu
T4240EMU is an emulator target with minimum peripherals. It is based on
T4240QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
resync with t4240qds.dts
arch/powerpc/boot/dts/t4240emu.dts | 270
1 file changed, 270 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t4240emu.dts
diff --git a/arch/powerpc/boot/dts/t4240emu.dts
b/arch/powerpc/boot/dts/t4240emu.dts
new file mode 100644
index 000..44c5a0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -0,0 +1,270 @@
+/*
+ * T4240 emulator Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl/e6500_power_isa.dtsi"
+/ {
+ compatible = "fsl,T4240";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu4: PowerPC,e6500@8 {
+ device_type = "cpu";
+ reg = <8 9>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu5: PowerPC,e6500@10 {
+ device_type = "cpu";
+ reg = <10 11>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu6: PowerPC,e6500@12 {
+ device_type = "cpu";
+ reg = <12 13>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu7: PowerPC,e6500@14 {
+ device_type = "cpu";
+ reg = <14 15>;
+ next-level-cache = <&L2_2>;
+ };
+
+ cpu8: PowerPC,e6500@16 {
+ device_type = "cpu";
+ reg = <16 17>;
+ next-level-cache = <&L2_3>;
+ };
+ cpu9: PowerPC,e6500@18 {
+ device_
[Patch v2] powerpc/corenet64_smp_defconfig: Enable most SPI splash
Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on P5040DS. Signed-off-by: York Sun --- Change log: v2: remote reviewed-by and tested-by lines added by gerrit arch/powerpc/configs/corenet64_smp_defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 6c8b020..1ec6f0c 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -66,6 +66,7 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y CONFIG_FTL=y CONFIG_MTD_CFI=y CONFIG_MTD_GEN_PROBE=y -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
On Mon, Sep 16, 2013 at 11:10:27AM -0500, Kumar Gala wrote: > > On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote: > > > On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote: > >> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote: > > Just a nit, but subject is missing 'e' in 'cornet' :) Will fix. Thanks, Kevin > > - k > pgpO4N3sghgS5.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
On Thu, 2013-09-12 at 18:15 +0100, Mark Rutland wrote: > On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote: > > On 09/02/2013 11:58 PM, Mark Rutland wrote: > > > May some channels be unusable for some reason, or will all eight > > > channels be wired on any given Elo3 DMA? > > Sorry, not get your point clearly, maybe you are clear now because of my > > previous explanations. > > I assume that on any El03 DMA, there won't be a case where you can't > describe the channel at 0x80, for instance. It will always be present > (but it might not be wired up to anything any therefore be useful)? > > This was related to my concerns about the status register description -- > if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get > described in the dt? I guess that would never actually happen because > all 8 channels must always be present in the Elo3 IP block. If a channel is not usable for whatever reason (other than that "used for a different fixed purpose and thus described with a different compatible" thing that was mentioned earlier in these threads), wouldn't it just have status = "disabled" or similar, or be absent? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy in device tree
On Fri, 2013-09-13 at 03:17 +, Zhao Qiang-B45475 wrote: > On Sep 13, 2013, at 12:42 AM, Kumar Gala wrote: > > > -Original Message- > > From: Kumar Gala [mailto:ga...@kernel.crashing.org] > > Sent: Friday, September 13, 2013 12:42 AM > > To: Liu Shengzhou-B36685 > > Cc: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy > > in device tree > > > > > > On Sep 12, 2013, at 1:54 AM, Liu Shengzhou-B36685 wrote: > > > > > > > > > > >> -Original Message- > > >> From: Kumar Gala [mailto:ga...@kernel.crashing.org] > > >> Sent: Wednesday, September 11, 2013 11:13 PM > > >> To: Zhao Qiang-B45475 > > >> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685 > > >> Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of > > >> ethernet-phy in device tree > > >> > > >> > > >> On Sep 10, 2013, at 10:49 PM, Zhao Qiang wrote: > > >> > > >> > > >> NAK. The device tree should represent the HW not what drivers decide > > >> to do with it. > > >> > > >> If different board revs have different interrupt signals than create > > >> dts's to handle the 2 board revs. > > >> > > >> - k > > >> > > > You mean we need to create p1010rdb-pa.dtsi and p1010rdb-pb.dtsi > > replacing current p1010rdb.dtsi just because of the unused phy interrupt? > > > and phy interrupt is not present in those dts of P3/P4/P5 platforms. > > > Actually currently many hardware are not present in dts, such as a lot > > of i2c devices, temperature monitor, etc. > > > > > > -Shengzhou > > > > > > > I'm saying of the board revs are different w/regards to how the PHY > > interrupt is wired, than create two .dts one for each of the board revs. > > > > If the p3/p4/p5 platforms are missing the phy interrupt in the .dts than > > its an error. > > > > Other devices like i2c, temp mon, etc should be added. There is a > > difference between something not existing because people haven't gotten > > around to it / there isn't a binding vs a using the lack of information > > as a configuration mechanism. > > > > - k > > > > > > Kumar, please advice your solution, thanks. He already did -- have separate dts files. This doesn't need to result in massive duplication, because everything but the phy interrupt (and any other differences there may be between revisions) can go into a common dtsi file. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH][v2] powerpc/mpc85xx:Add initial device tree support of T104x
On Sun, 2013-09-15 at 19:31 +0530, Prabhakar Kushwaha wrote:
> The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
> processor cores with high-performance data path acceleration architecture
> and network peripheral interfaces required for networking &
> telecommunications.
>
> T1042 personality is a reduced personality of T1040 without Integrated 8-port
> Gigabit Ethernet switch.
>
> The T1040/T1042 SoC includes the following function and features:
>
> - Four e5500 cores, each with a private 256 KB L2 cache
> - 256 KB shared L3 CoreNet platform cache (CPC)
> - Interconnect CoreNet platform
> - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
>support
> - Data Path Acceleration Architecture (DPAA) incorporating acceleration
> for the following functions:
> - Packet parsing, classification, and distribution
> - Queue management for scheduling, packet sequencing, and congestion
> management
> - Cryptography Acceleration (SEC 5.0)
> - RegEx Pattern Matching Acceleration (PME 2.2)
> - IEEE Std 1588 support
> - Hardware buffer management for buffer allocation and deallocation
> - Ethernet interfaces
> - Integrated 8-port Gigabit Ethernet switch (T1040 only)
> - Four 1 Gbps Ethernet controllers
> - Two RGMII interfaces or one RGMII and one MII interfaces
> - High speed peripheral interfaces
>- Four PCI Express 2.0 controllers running at up to 5 GHz
>- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
>- Upto two QSGMII interface
>- Upto six SGMII interface supporting 1000 Mbps
>- One SGMII interface supporting upto 2500 Mbps
> - Additional peripheral interfaces
>- Two USB 2.0 controllers with integrated PHY
>- SD/eSDHC/eMMC
>- eSPI controller
>- Four I2C controllers
>- Four UARTs
>- Four GPIO controllers
>- Integrated flash controller (IFC)
>- Change this to LCD/ HDMI interface (DIU) with 12 bit dual data rate
>- TDM interface
> - Multicore programmable interrupt controller (PIC)
> - Two 8-channel DMA engines
> - Single source clocking implementation
> - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
>
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Priyanka Jain
> Signed-off-by: Varun Sethi
> Signed-off-by: Prabhakar Kushwaha
> ---
> Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
> Branch next
>
> Changes for v2: Incorporated Scott's comments
> - Update t1040si-post.dtsi
> - update clock device tree node as per
> http://patchwork.ozlabs.org/patch/274134/
> - removed DMA node, It will be added later as per
> http://patchwork.ozlabs.org/patch/271238/
> - Updated display compatible field
>
> arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 41 +++
> arch/powerpc/boot/dts/fsl/t1042si-post.dtsi | 418
> +++
> arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 109 +++
> 3 files changed, 568 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> new file mode 100644
> index 000..ca820f6
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> @@ -0,0 +1,41 @@
> +/*
> + * T1040 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote products
> + * derived from this software without specific prior written
> permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree nodes
On Thu, 2013-09-12 at 21:50 -0500, Tang Yuantian-B29983 wrote: > > -Original Message- > > From: Wood Scott-B07421 > > Sent: 2013年9月12日 星期四 22:44 > > To: Tang Yuantian-B29983 > > Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc- > > d...@lists.ozlabs.org; devicet...@vger.kernel.org; Li Yang-Leo-R58472 > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree > > nodes > > > > On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote: > > > > -Original Message- > > > > From: Wood Scott-B07421 > > > > Sent: 2013年9月12日 星期四 9:10 > > > > To: Tang Yuantian-B29983 > > > > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; > > > > devicet...@vger.kernel.org; Li Yang-Leo-R58472 > > > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device > > > > tree nodes > > > > > > > > This description of "reg" is overly specific (assumes how the parent > > > > node's ranges are set up), incomplete (there's a size as well as the > > > > offset), and does not apply to the clockgen node itself (you > > > > probably shouldn't lump them together like this). > > > > > > > Do you mean I should explain the REG of clockgen and its child node > > respectively? > > > > > > > > +- clocks : shall be the input parent clock phandle for the clock. > > > > > > > > Not required on the clockgen node > > > > > > > Required by child node of clockgen. > > > > My point is that you're lumping several different types of nodes together > > with one binding, when some parts of the binding are not applicable to > > the clockgen node. > > > Not several, just two types of nodes. > One is clockgen node, the other is PLL and mux nodes. clockgen + PLL + mux = 3 = several :-) > The reason they lumped together is that the clockgen node is not only IP block > Node but also a clock provider node I don't understand why that merits lumping them together. Just describe them separately. > At first, I want to add a extra fixed-clock node and move the clock-frequency > of clockgen > Node to it, but it is against the backward compatibility Right. > which I think it is not a big deal, Because nobody hasn't used it yet. The point is it will require updating U-Boot to use it, versus existing U-Boots which already patch up the clock-frequency in the clockgen node. And there's nothing semantically wrong with the way it currently is. > If I add a extra node with the clock-frequency property and don't move the > clock-frequency property of clockgen, that would be redundant because both > clockgen node > and the extra node have the same clock-frequency node. > So, I choose what I did now. I'm not complaining about how you structured the nodes, just how you documented them. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
On Fri, 2013-09-13 at 02:30 -0500, Kushwaha Prabhakar-B32579 wrote:
> > I also question the need to define separate t1040 compatible values for
> > all of these, if the only difference is whether the onboard switch is
> > enabled or not.
> >
>
> so should I use T104x as compatible field. and in T1040 device tree add extra
> node for l2 switch.
No, because we don't know if there will be (e.g) a t1043 that is
different. Just use t1040 as the canonical name.
> > Please update the clock stuff based on
> > http://patchwork.ozlabs.org/patch/274134/
> >
>
> this patch is still under discussion. May I have to wait for the final patch.
> or may I rebase on v4.
You can wait for the final patch, or you can update based on the current
state of the discussion, and be ready to update again if anything
changes.
> > > +/include/ "qoriq-dma-0.dtsi"
> > > + dma@100300 {
> > > + fsl,iommu-parent = <&pamu0>;
> > > + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
> > > + };
> > > +
> > > +/include/ "qoriq-dma-1.dtsi"
> > > + dma@101300 {
> > > + fsl,iommu-parent = <&pamu0>;
> > > + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
> > > + };
> >
> > These are elo3:
> > http://patchwork.ozlabs.org/patch/271238/
>
> This patch is still under discussion.
> I am not sure, I should wait for final patch or change code as per v9
> version.
I think that patch is pretty well settled at this point. Just make it a
prerequisite for this patch.
-Scott
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Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
On Thu, 2013-09-12 at 21:53 -0500, Wang Dongsheng-B40534 wrote: > > > -Original Message- > > From: Wood Scott-B07421 > > Sent: Friday, September 13, 2013 2:07 AM > > To: Wang Dongsheng-B40534 > > Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc- > > d...@lists.ozlabs.org > > Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and > > altivec idle > > > > On Wed, 2013-09-11 at 22:48 -0500, Wang Dongsheng-B40534 wrote: > > > > > > > -Original Message- > > > > From: Wood Scott-B07421 > > > > Sent: Thursday, September 12, 2013 7:04 AM > > > > To: Wang Dongsheng-B40534 > > > > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org > > > > Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state > > > > and altivec idle > > > > > > > > On Wed, 2013-09-11 at 13:56 +0800, Dongsheng Wang wrote: > > > > > From: Wang Dongsheng > > > > > > > > > > Add a sys interface to enable/diable pw20 state or altivec idle, > > > > > and control the wait entry time. > > > > > > > > > > Enable/Disable interface: > > > > > 0, disable. 1, enable. > > > > > /sys/devices/system/cpu/cpuX/pw20_state > > > > > /sys/devices/system/cpu/cpuX/altivec_idle > > > > > > > > > > Set wait entry bit interface: > > > > > bit value range 0~63, 0 bit is Mintime, 63 bit is Maxtime. > > > > > /sys/devices/system/cpu/cpuX/pw20_wait_entry_bit > > > > > /sys/devices/system/cpu/cpuX/altivec_idle_wait_entry_bit > > > > > > > > I'm no fan of the way powerpc does bit numbering, but don't flip it > > > > around here -- you'll just cause confusion. > > > > > > > OK. 0 bit is maxtime, 63 bit is mintime. > > > > > > > Better yet, this interface should take real time units rather than a > > > > timebase bit. > > > > > > > I think the real time is not suitable, because timebase bit does not > > > correspond with real time. > > > > It's a bit sloppy due to how the hardware works, but you could convert it > > like you did in earlier patches. Semantically it should probably be the > > minimum time to wait before entering the low power state. > > > But there has a problem, we can't convert bit to the real time when user read > this sysfs. > Like: > echo 1000(us) > /sys/*/pw20_wait_entry_bit, after convert we get bit is 49. > cat /sys/*/pw20_wait_entry_bit, after convert the time is 1598(us). > > The read out of the time is not real time. Unless we define a variable to > save the real time. It's not the end of the world if the value is different when read back. It just gets rounded up when you write it. > > > > Also, you disable the power saving mode if the maximum interval is > > > > selected, > > > It's not disable the pw20 state or altivec idle, just max-delay entry > > time. > > > > No, the code checks for zero to set or clear the enabling bit (e.g. > > PW20_WAIT). > > > There has pw20_state/altivec_idle sys interface to control "enable/disable", > There is only to control wait bit. Did you mean remove > "pw20_state/altivec_idle" > sys interface, and reuse "pw20_wait_entry_bit/altivec_idle*" sys interface? > When echo zero into "pw20_wait_entry_bit" we just to disable pw20 state, I > think that is reasonable. :) Sorry, I misread the patch and didn't realize these were separate interfaces. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote: > Le 12/09/2013 20:44, Scott Wood a écrit : > > On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote: > >> This is a reorganisation of the setup of the TLB at kernel startup, in > >> order > >> to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of > >> MPC866 > >> and MPC885 reference manuals. > >> > >> Signed-off-by: Christophe Leroy > >> > >> diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S > >> linux-3.11/arch/powerpc/kernel/head_8xx.S > >> --- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 > >> 22:46:10.0 +0200 > >> +++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 > >> 11:28:54.0 +0200 > >> @@ -785,27 +785,24 @@ > >>* these mappings is mapped by page tables. > >>*/ > >> initial_mmu: > >> - tlbia /* Invalidate all TLB entries */ > >> -/* Always pin the first 8 MB ITLB to prevent ITLB > >> - misses while mucking around with SRR0/SRR1 in asm > >> -*/ > >> - lis r8, MI_RSV4I@h > >> - ori r8, r8, 0x1c00 > >> - > >> + lis r8, MI_RESETVAL@h > >>mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ > >> > >> -#ifdef CONFIG_PIN_TLB > >> - lis r10, (MD_RSV4I | MD_RESETVAL)@h > >> - ori r10, r10, 0x1c00 > >> - mr r8, r10 > >> -#else > >>lis r10, MD_RESETVAL@h > >> -#endif > >> #ifndef CONFIG_8xx_COPYBACK > >>orisr10, r10, MD_WTDEF@h > >> #endif > >>mtspr SPRN_MD_CTR, r10/* Set data TLB control */ > >> > >> + tlbia /* Invalidate all TLB entries */ > > Is this change to make sure we invalidate everything even if the > > bootloader set RSV4I? > Most probably. It is step 2 of the process defined in MPC866 and MPC885 > Reference Manuals: > > §8.10.3 Loading Locked TLB Entries: > The process of loading a single reserved entry in the TLB is as follows: To minimize code churn we should just fix actual problems, rather than shuffle things around to conform to a suggested sequence. After all, we're not just trying to load a single entry. > >> + ori r8, r8, 0x1c00 > >> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ > >> +#ifdef CONFIG_PIN_TLB > >> + ori r10, r10, 0x1c00 > >> + mtspr SPRN_MD_CTR, r10/* Set data TLB control */ > >> +#endif > > Still 0x1c00? > Yes, I kept the same entries in order to limit modifications: > * 28 = First 8Mbytes page > * 29 = IMMR > * 30 = Second 8Mbytes page > * 31 = Third 8Mbytes page If you actually want to program them in increasing order then it looks like you're still missing a write to CTR between the last two 8M entries -- thus you'll overwrite the IMMR with the last 8M entry. That was the same problem that v1 fixed -- did that change get lost accidentally? The hardware wants to decrement; why fight it? > >>/* Now map the lower 8 Meg into the TLBs. For this quick hack, > >> * we can load the instruction and data TLB registers with the > >> * same values. > >> @@ -825,6 +822,12 @@ > >>mtspr SPRN_MI_AP, r8 > >>mtspr SPRN_MD_AP, r8 > >> > >> + /* Always pin the first 8 MB ITLB to prevent ITLB > >> + * misses while mucking around with SRR0/SRR1 in asm > >> + */ > >> + lis r8, (MI_RSV4I | MI_RESETVAL)@h > >> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ > > Entry 0 is not pinnable. > Here we are not trying to pin entry 0. Sorry, misread the patch. > We are at step 8, we are setting > MI_RSV4I. At the same time, we set MD_CTR to 0 which is off the pinned > range, to be sure that we won't overwrite one of the pinned entries. > > The main difference compared to the previous implementation is that > before, we were setting the RSV4I bit before loading the TLB entries. > Now, as defined in the Reference Manuals, we are doing it at the end. Have you seen any evidence that it matters? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] powerpc/fsl-booke: Add initial T104x_QDS board support
On Fri, 2013-09-13 at 02:35 -0500, Kushwaha Prabhakar-B32579 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, September 12, 2013 5:11 AM
> > To: Kushwaha Prabhakar-B32579
> > Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Jain
> > Priyanka-B32167; Aggrwal Poonam-B10812
> > Subject: Re: [PATCH 1/2] powerpc/fsl-booke: Add initial T104x_QDS board
> > support
> >
> > On Wed, 2013-09-11 at 12:28 +0530, Prabhakar Kushwaha wrote:
> > > + aliases {
> > > + /* TODO */
> > > + };
> >
> > TODO? Did you mean this patch as an RFC?
> >
>
>
> actually, this patch is not adding in dpaa related node(fman,bman etc).
> I am keeping place holder for alias of Ethernet nodes.
If you don't have any board-level aliases yet, then just don't include
the aliases node in this file.
> > Also, whitespace.
> >
>
> does whitespace is not captured in checkpatch?
Not in dts files.
> > Maybe some of this stuff could be put in a common dtsi between t1040 and
> > t1042?
> >
> > Ideally for t1042 you'd just take the entire t1040 tree as an include,
> > and add the switch
> >
>
> means, I just create T1042qds.dts and for T1040.dts include t1042dts + switch
Is it t1040 that has the switch or t1042?
-Scott
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Re: [PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
> On 09/02/2013 06:37 PM, Haijun Zhang wrote:
> > We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
> > to distinguish if the sdhc host has quirk
> > SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
> >
> > Signed-off-by: Haijun Zhang
> > ---
> > arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > index 5180d9d..0c0efa9 100644
> > --- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > @@ -130,7 +130,7 @@ usb@22000 {
> >
> > /include/ "pq3-esdhc-0.dtsi"
> > sdhc@2e000 {
> > - fsl,sdhci-auto-cmd12;
> > + sdhci,auto-cmd12;
> > interrupts = <41 0x2 0 0>;
> > };
> >
> >
>
>
> Hi, scott
>
> Could you help review this patch?
I process patches in periodic batches. There's no need for a reminder
when it's only been two weeks, as long as it's still marked "new" or
"under review" in patchwork (and you should include a patchwork link in
any such reminder e-mail). Especially for a trivial patch such as this,
no comment often means I looked at it and saw no problems and will take
it in the next batch.
Though if you want a comment, don't capitalize "powerpc" in the
subject. :-)
-Scott
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Re: [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote: > On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote: >> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote: Just a nit, but subject is missing 'e' in 'cornet' :) - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH v4 11/12] powerpc/powernv: Remove machine check handling in OPAL.
From: Mahesh Salgaonkar Now that we are ready to handle machine check directly in linux, do not register with firmware to handle machine check exception. Signed-off-by: Mahesh Salgaonkar --- arch/powerpc/platforms/powernv/opal.c |8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c index f789514..0170d19 100644 --- a/arch/powerpc/platforms/powernv/opal.c +++ b/arch/powerpc/platforms/powernv/opal.c @@ -83,14 +83,10 @@ static int __init opal_register_exception_handlers(void) if (!(powerpc_firmware_features & FW_FEATURE_OPAL)) return -ENODEV; - /* Hookup some exception handlers. We use the fwnmi area at 0x7000 -* to provide the glue space to OPAL + /* Hookup some exception handlers except machine check. We use the +* fwnmi area at 0x7000 to provide the glue space to OPAL */ glue = 0x7000; - opal_register_exception_handler(OPAL_MACHINE_CHECK_HANDLER, - __pa(opal_mc_secondary_handler[0]), - glue); - glue += 128; opal_register_exception_handler(OPAL_HYPERVISOR_MAINTENANCE_HANDLER, 0, glue); glue += 128; ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH v4 12/12] powerpc/powernv: Machine check exception handling.
From: Mahesh Salgaonkar
Add basic error handling in machine check exception handler.
- If MSR_RI isn't set, we can not recover.
- Check if disposition set to OpalMCE_DISPOSITION_RECOVERED.
- Check if address at fault is inside kernel address space, if not then send
SIGBUS to process if we hit exception when in userspace.
- If address at fault is not provided then and if we get a synchronous machine
check while in userspace then kill the task.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/include/asm/mce.h|1 +
arch/powerpc/kernel/mce.c | 27 +
arch/powerpc/platforms/powernv/opal.c | 43 -
3 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 3276b40..a2b8c7b 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -193,5 +193,6 @@ extern void release_mce_event(void);
extern void machine_check_queue_event(void);
extern void machine_check_process_queued_event(void);
extern void machine_check_print_event_info(struct machine_check_event *evt);
+extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index 1cca4b6..3100509 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -316,3 +316,30 @@ void machine_check_print_event_info(struct
machine_check_event *evt)
break;
}
}
+
+uint64_t get_mce_fault_addr(struct machine_check_event *evt)
+{
+ switch (evt->error_type) {
+ case MCE_ERROR_TYPE_UE:
+ if (evt->u.ue_error.effective_address_provided)
+ return evt->u.ue_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_SLB:
+ if (evt->u.slb_error.effective_address_provided)
+ return evt->u.slb_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_ERAT:
+ if (evt->u.erat_error.effective_address_provided)
+ return evt->u.erat_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_TLB:
+ if (evt->u.tlb_error.effective_address_provided)
+ return evt->u.tlb_error.effective_address;
+ break;
+ default:
+ case MCE_ERROR_TYPE_UNKNOWN:
+ break;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(get_mce_fault_addr);
diff --git a/arch/powerpc/platforms/powernv/opal.c
b/arch/powerpc/platforms/powernv/opal.c
index 0170d19..2070970 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -240,6 +241,44 @@ int opal_put_chars(uint32_t vtermno, const char *data, int
total_len)
return written;
}
+static int opal_recover_mce(struct pt_regs *regs,
+ struct machine_check_event *evt)
+{
+ int recovered = 0;
+ uint64_t ea = get_mce_fault_addr(evt);
+
+ if (!(regs->msr & MSR_RI)) {
+ /* If MSR_RI isn't set, we cannot recover */
+ recovered = 0;
+ } else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
+ /* Platform corrected itself */
+ recovered = 1;
+ } else if (ea && !is_kernel_addr(ea)) {
+ /*
+* Faulting address is not in kernel text. We should be fine.
+* We need to find which process uses this address.
+* For now, kill the task if we have received exception when
+* in userspace.
+*
+* TODO: Queue up this address for hwpoisioning later.
+*/
+ if (user_mode(regs) && !is_global_init(current)) {
+ _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+ recovered = 1;
+ } else
+ recovered = 0;
+ } else if (user_mode(regs) && !is_global_init(current) &&
+ evt->severity == MCE_SEV_ERROR_SYNC) {
+ /*
+* If we have received a synchronous error when in userspace
+* kill the task.
+*/
+ _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+ recovered = 1;
+ }
+ return recovered;
+}
+
int opal_machine_check(struct pt_regs *regs)
{
struct machine_check_event evt;
@@ -255,7 +294,9 @@ int opal_machine_check(struct pt_regs *regs)
}
machine_check_print_event_info(&evt);
- return evt.severity == MCE_SEV_FATAL ? 0 : 1;
+ if (opal_recover_mce(regs, &evt))
+ return 1;
+ return 0;
}
static irqreturn_t opal_interrupt(int irq, void *data)
___
[RFC PATCH v4 10/12] powerpc/book3s: Queue up and process delayed MCE events.
From: Mahesh Salgaonkar
When machine check real mode handler can not continue into host kernel
in V mode, it returns from the interrupt and we loose MCE event which
never gets logged. In such a situation queue up the MCE event so that
we can log it later when we get back into host kernel with r1 pointing to
kernel stack e.g. during syscall exit.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/include/asm/mce.h|3 +
arch/powerpc/kernel/entry_64.S|5 +
arch/powerpc/kernel/exceptions-64s.S |7 +-
arch/powerpc/kernel/mce.c | 154 +
arch/powerpc/platforms/powernv/opal.c | 97 -
5 files changed, 168 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 87cad2a..3276b40 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -190,5 +190,8 @@ extern void save_mce_event(struct pt_regs *regs, long
handled,
struct mce_error_info *mce_err, uint64_t addr);
extern int get_mce_event(struct machine_check_event *mce, bool release);
extern void release_mce_event(void);
+extern void machine_check_queue_event(void);
+extern void machine_check_process_queued_event(void);
+extern void machine_check_print_event_info(struct machine_check_event *evt);
#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 2bd0b88..71bcd41 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -183,6 +183,11 @@ syscall_exit:
bl .do_show_syscall_exit
ld r3,RESULT(r1)
#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+BEGIN_FTR_SECTION
+ bl .machine_check_process_queued_event
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+#endif
CURRENT_THREAD_INFO(r12, r1)
ld r8,_MSR(r1)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 0a92ba4..ce57cec 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -824,7 +824,8 @@ BEGIN_FTR_SECTION
/* Supervisor state loss */
li r0,1
stb r0,PACA_NAPSTATELOST(r13)
-3: MACHINE_CHECK_HANDLER_WINDUP
+3: bl .machine_check_queue_event
+ MACHINE_CHECK_HANDLER_WINDUP
GET_PACA(r13)
ld r1,PACAR1(r13)
b .power7_enter_nap_mode
@@ -864,8 +865,10 @@ BEGIN_FTR_SECTION
2:
/*
* Return from MC interrupt.
-* TODO: Queue up the MCE event so that we can log it later.
+* Queue up the MCE event so that we can log it later, while
+* returning from kernel or opal call.
*/
+ bl .machine_check_queue_event
MACHINE_CHECK_HANDLER_WINDUP
rfid
9:
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index aeecdf1..1cca4b6 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -31,6 +31,10 @@
static DEFINE_PER_CPU(int, mce_nest_count);
static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event);
+/* Queue for delayed MCE events. */
+static DEFINE_PER_CPU(int, mce_queue_count);
+static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event_queue);
+
static void mce_set_error_info(struct machine_check_event *mce,
struct mce_error_info *mce_err)
{
@@ -162,3 +166,153 @@ void release_mce_event(void)
{
get_mce_event(NULL, true);
}
+
+/*
+ * Queue up the MCE event which then can be handled later.
+ */
+void machine_check_queue_event(void)
+{
+ int index;
+ struct machine_check_event evt;
+
+ if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
+ return;
+
+ index = __get_cpu_var(mce_queue_count)++;
+ /* If queue is full, just return for now. */
+ if (index >= MAX_MC_EVT) {
+ __get_cpu_var(mce_queue_count)--;
+ return;
+ }
+ __get_cpu_var(mce_event_queue[index]) = evt;
+}
+
+/*
+ * process pending MCE event from the mce event queue. This function will be
+ * called during syscall exit.
+ */
+void machine_check_process_queued_event(void)
+{
+ int index;
+
+ preempt_disable();
+ /*
+* For now just print it to console.
+* TODO: log this error event to FSP or nvram.
+*/
+ while (__get_cpu_var(mce_queue_count) > 0) {
+ index = __get_cpu_var(mce_queue_count) - 1;
+ machine_check_print_event_info(
+ &__get_cpu_var(mce_event_queue[index]));
+ __get_cpu_var(mce_queue_count)--;
+ }
+ preempt_enable();
+}
+
+void machine_check_print_event_info(struct machine_check_event *evt)
+{
+ const char *level, *sevstr, *subtype;
+ static const char *mc_ue_types[] = {
+ "Indeterminate",
+ "Instruction fetch",
+ "Page table wal
[RFC PATCH v4 09/12] powerpc/book3s: Decode and save machine check event.
From: Mahesh Salgaonkar
Now that we handle machine check in linux, the MCE decoding should also
take place in linux host. This info is crucial to log before we go down
in case we can not handle the machine check errors. This patch decodes
and populates a machine check event which contain high level meaning full
MCE information.
We do this in real mode C code with ME bit on. The MCE information is still
available on emergency stack (in pt_regs structure format). Even if we take
another exception at this point the MCE early handler will allocate a new
stack frame on top of current one. So when we return back here we still have
our MCE information safe on current stack.
We use per cpu buffer to save high level MCE information. Each per cpu buffer
is an array of machine check event structure indexed by per cpu counter
mce_nest_count. The mce_nest_count is incremented every time we enter
machine check early handler in real mode to get the current free slot
(index = mce_nest_count - 1). The mce_nest_count is decremented once the
MCE info is consumed by virtual mode machine exception handler.
This patch provides save_mce_event(), get_mce_event() and release_mce_event()
generic routines that can be used by machine check handlers to populate and
retrieve the event. The routine release_mce_event() will free the event slot so
that it can be reused. Caller can invoke get_mce_event() with a release flag
either to release the event slot immediately OR keep it so that it can be
fetched again. The event slot can be also released anytime by invoking
release_mce_event().
This patch also updates kvm code to invoke get_mce_event to retrieve generic
mce event rather than paca->opal_mce_evt.
The KVM code always calls get_mce_event() with release flags set to false so
that event is available for linus host machine
If machine check occurs while we are in guest, KVM tries to handle the error.
If KVM is able to handle MC error successfully, it enters the guest and
delivers the machine check to guest. If KVM is not able to handle MC error, it
exists the guest and passes the control to linux host machine check handler
which then logs MC event and decides how to handle it in linux host. In failure
case, KVM needs to make sure that the MC event is available for linux host to
consume. Hence KVM always calls get_mce_event() with release flags set to false
and later it invokes release_mce_event() only if it succeeds to handle error.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/include/asm/mce.h| 124 +
arch/powerpc/kernel/Makefile |2
arch/powerpc/kernel/mce.c | 164 +
arch/powerpc/kernel/mce_power.c | 116 ++-
arch/powerpc/kvm/book3s_hv_ras.c | 32 --
arch/powerpc/platforms/powernv/opal.c | 35 +++
6 files changed, 434 insertions(+), 39 deletions(-)
create mode 100644 arch/powerpc/kernel/mce.c
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index e3ffa82..87cad2a 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -66,5 +66,129 @@
#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
P8_DSISR_MC_ERAT_MULTIHIT_SEC)
+enum MCE_Version {
+ MCE_V1 = 1,
+};
+
+enum MCE_Severity {
+ MCE_SEV_NO_ERROR = 0,
+ MCE_SEV_WARNING = 1,
+ MCE_SEV_ERROR_SYNC = 2,
+ MCE_SEV_FATAL = 3,
+};
+
+enum MCE_Disposition {
+ MCE_DISPOSITION_RECOVERED = 0,
+ MCE_DISPOSITION_NOT_RECOVERED = 1,
+};
+
+enum MCE_Initiator {
+ MCE_INITIATOR_UNKNOWN = 0,
+ MCE_INITIATOR_CPU = 1,
+};
+
+enum MCE_ErrorType {
+ MCE_ERROR_TYPE_UNKNOWN = 0,
+ MCE_ERROR_TYPE_UE = 1,
+ MCE_ERROR_TYPE_SLB = 2,
+ MCE_ERROR_TYPE_ERAT = 3,
+ MCE_ERROR_TYPE_TLB = 4,
+};
+
+enum MCE_UeErrorType {
+ MCE_UE_ERROR_INDETERMINATE = 0,
+ MCE_UE_ERROR_IFETCH = 1,
+ MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
+ MCE_UE_ERROR_LOAD_STORE = 3,
+ MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
+};
+
+enum MCE_SlbErrorType {
+ MCE_SLB_ERROR_INDETERMINATE = 0,
+ MCE_SLB_ERROR_PARITY = 1,
+ MCE_SLB_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_EratErrorType {
+ MCE_ERAT_ERROR_INDETERMINATE = 0,
+ MCE_ERAT_ERROR_PARITY = 1,
+ MCE_ERAT_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_TlbErrorType {
+ MCE_TLB_ERROR_INDETERMINATE = 0,
+ MCE_TLB_ERROR_PARITY = 1,
+ MCE_TLB_ERROR_MULTIHIT = 2,
+};
+
+struct machine_check_event {
+ enum MCE_Versionversion:8; /* 0x00 */
+ uint8_t in_use; /* 0x01 */
+ enum MCE_Severity severity:8; /* 0x02 */
+ enum MCE_Initiator initiator:8;/* 0x03 */
+ enum MCE_ErrorType error_type:8; /* 0x04 */
+ enum MCE_Dispositiondisposition:8; /* 0x05 */
+ uint8_t reserved_1[2
[RFC PATCH v4 08/12] powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8.
From: Mahesh Salgaonkar
This patch handles the memory errors on power8. If we get a machine check
exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to
recover.
Signed-off-by: Mahesh Salgaonkar
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/mce.h |3 +++
arch/powerpc/kernel/cputable.c |4
arch/powerpc/kernel/mce_power.c | 34 ++
3 files changed, 41 insertions(+)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 8157d4e..e3ffa82 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -64,4 +64,7 @@
P7_DSISR_MC_SLB_MULTIHIT | \
P7_DSISR_MC_SLB_MULTIHIT_PARITY)
+#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
+P8_DSISR_MC_ERAT_MULTIHIT_SEC)
+
#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index c28cc2c..0195358 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -74,6 +74,7 @@ extern void __restore_cpu_a2(void);
extern void __flush_tlb_power7(unsigned long inval_selector);
extern void __flush_tlb_power8(unsigned long inval_selector);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
#endif /* CONFIG_PPC64 */
#if defined(CONFIG_E500)
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -462,6 +463,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_power8,
.cpu_restore= __restore_cpu_power8,
.flush_tlb = __flush_tlb_power8,
+ .machine_check_early= __machine_check_early_realmode_p8,
.platform = "power8",
},
{ /* Power7 */
@@ -521,6 +523,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_power8,
.cpu_restore= __restore_cpu_power8,
.flush_tlb = __flush_tlb_power8,
+ .machine_check_early= __machine_check_early_realmode_p8,
.platform = "power8",
},
{ /* Power8 */
@@ -540,6 +543,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_power8,
.cpu_restore= __restore_cpu_power8,
.flush_tlb = __flush_tlb_power8,
+ .machine_check_early= __machine_check_early_realmode_p8,
.platform = "power8",
},
{ /* Cell Broadband Engine */
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 6905473..60a217f 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -148,3 +148,37 @@ long __machine_check_early_realmode_p7(struct pt_regs
*regs)
/* TODO: Decode machine check reason. */
return handled;
}
+
+static long mce_handle_ierror_p8(uint64_t srr1)
+{
+ long handled = 0;
+
+ handled = mce_handle_common_ierror(srr1);
+
+ if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
+ flush_and_reload_slb();
+ handled = 1;
+ }
+ return handled;
+}
+
+static long mce_handle_derror_p8(uint64_t dsisr)
+{
+ return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
+}
+
+long __machine_check_early_realmode_p8(struct pt_regs *regs)
+{
+ uint64_t srr1;
+ long handled = 1;
+
+ srr1 = regs->msr;
+
+ if (P7_SRR1_MC_LOADSTORE(srr1))
+ handled = mce_handle_derror_p8(regs->dsisr);
+ else
+ handled = mce_handle_ierror_p8(srr1);
+
+ /* TODO: Decode machine check reason. */
+ return handled;
+}
___
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[RFC PATCH v4 07/12] powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7.
From: Mahesh Salgaonkar If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning on MMU. Otherwise we would run into nested machine checks. If we get a machine check when we are in guest, then just flush the SLBs and continue. This patch handles errors for power7. The next patch will handle errors for power8 Signed-off-by: Mahesh Salgaonkar Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/bitops.h |5 + arch/powerpc/include/asm/mce.h| 67 + arch/powerpc/kernel/Makefile |1 arch/powerpc/kernel/cputable.c|4 + arch/powerpc/kernel/mce_power.c | 150 + 5 files changed, 227 insertions(+) create mode 100644 arch/powerpc/include/asm/mce.h create mode 100644 arch/powerpc/kernel/mce_power.c diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 910194e..a5e9a7d 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -46,6 +46,11 @@ #include #include +/* PPC bit number conversion */ +#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) +#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) +#define PPC_BITMASK(bs, be)((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + /* * clear_bit doesn't imply a memory barrier */ diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h new file mode 100644 index 000..8157d4e --- /dev/null +++ b/arch/powerpc/include/asm/mce.h @@ -0,0 +1,67 @@ +/* + * Machine check exception header file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright 2013 IBM Corporation + * Author: Mahesh Salgaonkar + */ + +#ifndef __ASM_PPC64_MCE_H__ +#define __ASM_PPC64_MCE_H__ + +#include + +/* + * Machine Check bits on power7 and power8 + */ +#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */ + +/* SRR1 bits for machine check (On Power7 and Power8) */ +#define P7_SRR1_MC_IFETCH(srr1)((srr1) & PPC_BITMASK(43, 45)) /* P8 too */ + +#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */ +#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */ +#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */ +#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45)) +#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */ +#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD(0x6 << PPC_BITLSHIFT(45)) /* P8 too */ +#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45)) + +/* SRR1 bits for machine check (On Power8) */ +#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT(0x4 << PPC_BITLSHIFT(45)) + +/* DSISR bits for machine check (On Power7 and Power8) */ +#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */ +#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */ +#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */ +#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */ +#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */ +#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */ +#define P7_DSISR_MC_SLB_MULTIHIT_PARITY(PPC_BIT(57)) /* P8 too */ + +/* + * DSISR bits for machine check (Power8) in addition to above. + * Secondary DERAT Multihit + */ +#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54)) + +/* SLB error bits */ +#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \ +P7_DSISR_MC_SLB_PARITY_MFSLB | \ +P7_DSISR_MC_SLB_MULTIHIT | \ +P7_DSISR_MC_SLB_MULTIHIT_PARITY) + +#endif /* __ASM_PPC64_MCE_H__ */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index a8619bf..a1aba53 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o +obj-$(CONFIG_PPC_BOOK3S_64)+=
[RFC PATCH v4 06/12] powerpc/book3s: Add flush_tlb operation in cpu_spec.
From: Mahesh Salgaonkar
This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this patch introduce flush_tlb for p7 and p8.
Signed-off-by: Mahesh Salgaonkar
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/cputable.h |5
arch/powerpc/kernel/cpu_setup_power.S | 38 +++--
arch/powerpc/kernel/cputable.c|8 +++
arch/powerpc/kvm/book3s_hv_ras.c | 18 +++-
4 files changed, 44 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index d8c098e..d76e47b 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -97,6 +97,11 @@ struct cpu_spec {
*/
long(*machine_check_early)(struct pt_regs *regs);
+ /*
+* Processor specific routine to flush tlbs.
+*/
+ void(*flush_tlb)(unsigned long inval_selector);
+
};
extern struct cpu_spec *cur_cpu_spec;
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index 18b5b9c..37d1bb0 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -29,7 +29,7 @@ _GLOBAL(__setup_cpu_power7)
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
bl __init_LPCR
- bl __init_TLB
+ bl __init_tlb_power7
mtlrr11
blr
@@ -42,7 +42,7 @@ _GLOBAL(__restore_cpu_power7)
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
bl __init_LPCR
- bl __init_TLB
+ bl __init_tlb_power7
mtlrr11
blr
@@ -59,7 +59,7 @@ _GLOBAL(__setup_cpu_power8)
orisr3, r3, LPCR_AIL_3@h
bl __init_LPCR
bl __init_HFSCR
- bl __init_TLB
+ bl __init_tlb_power8
bl __init_PMU_HV
mtlrr11
blr
@@ -78,7 +78,7 @@ _GLOBAL(__restore_cpu_power8)
orisr3, r3, LPCR_AIL_3@h
bl __init_LPCR
bl __init_HFSCR
- bl __init_TLB
+ bl __init_tlb_power8
bl __init_PMU_HV
mtlrr11
blr
@@ -134,15 +134,31 @@ __init_HFSCR:
mtspr SPRN_HFSCR,r3
blr
-__init_TLB:
- /*
-* Clear the TLB using the "IS 3" form of tlbiel instruction
-* (invalidate by congruence class). P7 has 128 CCs, P8 has 512
-* so we just always do 512
-*/
+/*
+ * Clear the TLB using the specified IS form of tlbiel instruction
+ * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
+ *
+ * r3 = IS field
+ */
+__init_tlb_power7:
+ li r3,0xc00/* IS field = 0b11 */
+_GLOBAL(__flush_tlb_power7)
+ li r6,128
+ mtctr r6
+ mr r7,r3 /* IS field */
+ ptesync
+2: tlbiel r7
+ addir7,r7,0x1000
+ bdnz2b
+ ptesync
+1: blr
+
+__init_tlb_power8:
+ li r3,0xc00/* IS field = 0b11 */
+_GLOBAL(__flush_tlb_power8)
li r6,512
mtctr r6
- li r7,0xc00/* IS field = 0b11 */
+ mr r7,r3 /* IS field */
ptesync
2: tlbiel r7
addir7,r7,0x1000
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 22973a7..cdbe115 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -71,6 +71,8 @@ extern void __restore_cpu_power7(void);
extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power8(void);
extern void __restore_cpu_a2(void);
+extern void __flush_tlb_power7(unsigned long inval_selector);
+extern void __flush_tlb_power8(unsigned long inval_selector);
#endif /* CONFIG_PPC64 */
#if defined(CONFIG_E500)
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -440,6 +442,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
.cpu_setup = __setup_cpu_power7,
.cpu_restore= __restore_cpu_power7,
+ .flush_tlb = __flush_tlb_power7,
.platform = "power7",
},
{ /* 2.07-compliant processor, i.e. Power8 "architected" mode */
@@ -456,6 +459,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
.cpu_setup = __setup_cpu_power8,
.cpu_restore= __restore_cpu_power8,
+ .flush_tlb = __flush_tlb_power8,
.platform = "power8",
},
{ /* Power7 */
[RFC PATCH v4 05/12] powerpc/book3s: Introduce a early machine check hook in cpu_spec.
From: Mahesh Salgaonkar
This patch adds the early machine check function pointer in cputable for
CPU specific early machine check handling. The early machine handle routine
will be called in real mode to handle SLB and TLB errors. We can not reuse
the existing machine_check hook because it is always invoked in kernel
virtual mode and we would already be in trouble if we get SLB or TLB errors.
This patch just sets up a mechanism to invoke CPU specific handler. The
subsequent patches will populate the function pointer.
Signed-off-by: Mahesh Salgaonkar
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/cputable.h |7 +++
arch/powerpc/kernel/traps.c |7 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 6f3887d..d8c098e 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -90,6 +90,13 @@ struct cpu_spec {
* if the error is fatal, 1 if it was fully recovered and 0 to
* pass up (not CPU originated) */
int (*machine_check)(struct pt_regs *regs);
+
+ /*
+* Processor specific early machine check handler which is
+* called in real mode to handle SLB and TLB errors.
+*/
+ long(*machine_check_early)(struct pt_regs *regs);
+
};
extern struct cpu_spec *cur_cpu_spec;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index e8d6bf1..8b0a946 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -292,8 +292,11 @@ void system_reset_exception(struct pt_regs *regs)
*/
long machine_check_early(struct pt_regs *regs)
{
- /* TODO: handle/decode machine check reason */
- return 0;
+ long handled = 0;
+
+ if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
+ handled = cur_cpu_spec->machine_check_early(regs);
+ return handled;
}
#endif
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[RFC PATCH v4 04/12] powerpc/book3s: Return from interrupt if coming from evil context.
From: Mahesh Salgaonkar We can get machine checks from any context. We need to make sure that we handle all of them correctly. If we are coming from hypervisor user-space, we can continue in host kernel in virtual mode to deliver the MC event. If we got woken up from power-saving mode then we may come in with one of the following state: a. No state loss b. Supervisor state loss c. Hypervisor state loss For (a) and (b), we go back to nap again. State (c) is fatal, keep spinning. For all other context which we not sure of queue up the MCE event and return from the interrupt. Signed-off-by: Mahesh Salgaonkar --- arch/powerpc/kernel/exceptions-64s.S | 82 ++ arch/powerpc/kernel/idle_power7.S|1 2 files changed, 83 insertions(+) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 87a70d2..0a92ba4 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -155,6 +155,24 @@ machine_check_pSeries_1: */ HMT_MEDIUM_PPR_DISCARD SET_SCRATCH0(r13) /* save r13 */ +#ifdef CONFIG_PPC_P7_NAP +BEGIN_FTR_SECTION + /* Running native on arch 2.06 or later, check if we are +* waking up from nap. We only handle no state loss and +* supervisor state loss. We do -not- handle hypervisor +* state loss at this time. +*/ + mfspr r13,SPRN_SRR1 + rlwinm. r13,r13,47-31,30,31 + beq 9f + + /* waking up from powersave (nap) state */ + cmpwi cr1,r13,2 + /* Total loss of HV state is fatal. let's just stay stuck here */ + bgt cr1,. +9: +END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) +#endif /* CONFIG_PPC_P7_NAP */ EXCEPTION_PROLOG_0(PACA_EXMC) BEGIN_FTR_SECTION b machine_check_pSeries_early @@ -787,6 +805,70 @@ BEGIN_FTR_SECTION bl .save_nvgprs addir3,r1,STACK_FRAME_OVERHEAD bl .machine_check_early + ld r12,_MSR(r1) +#ifdef CONFIG_PPC_P7_NAP + /* +* Check if thread was in power saving mode. We come here when any +* of the following is true: +* a. thread wasn't in power saving mode +* b. thread was in power saving mode with no state loss or +*supervisor state loss +* +* Go back to nap again if (b) is true. +*/ + rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ + beq 4f /* No, it wasn;t */ + /* Thread was in power saving mode. Go back to nap again. */ + cmpwi r11,2 + bne 3f + /* Supervisor state loss */ + li r0,1 + stb r0,PACA_NAPSTATELOST(r13) +3: MACHINE_CHECK_HANDLER_WINDUP + GET_PACA(r13) + ld r1,PACAR1(r13) + b .power7_enter_nap_mode +4: +#endif + /* +* Check if we are coming from hypervisor userspace. If yes then we +* continue in host kernel in V mode to deliver the MC event. +*/ + rldicl. r11,r12,4,63/* See if MC hit while in HV mode. */ + beq 5f + andi. r11,r12,MSR_PR /* See if coming from user. */ + bne 9f /* continue in V mode if we are. */ + +5: +#ifdef CONFIG_KVM_BOOK3S_64_HV + /* +* We are coming from kernel context. Check if we are coming from +* guest. if yes, then we can continue. We will fall through +* do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. +*/ + lbz r11,HSTATE_IN_GUEST(r13) + cmpwi r11,0 /* Check if coming from guest */ + bne 9f /* continue if we are. */ +#endif + /* +* At this point we are not sure about what context we come from. +* Queue up the MCE event and return from the interrupt. +* But before that, check if this is an un-recoverable exception. +* If yes, then stay on emergency stack and panic. +*/ + andi. r11,r12,MSR_RI + bne 2f +1: addir3,r1,STACK_FRAME_OVERHEAD + bl .unrecoverable_exception + b 1b +2: + /* +* Return from MC interrupt. +* TODO: Queue up the MCE event so that we can log it later. +*/ + MACHINE_CHECK_HANDLER_WINDUP + rfid +9: /* Deliver the machine check to host kernel in V mode. */ MACHINE_CHECK_HANDLER_WINDUP b machine_check_pSeries diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S index e11863f..c4b384d 100644 --- a/arch/powerpc/kernel/idle_power7.S +++ b/arch/powerpc/kernel/idle_power7.S @@ -84,6 +84,7 @@ _GLOBAL(power7_nap) std r9,_MSR(r1) std r1,PACAR1(r13) +_GLOBAL(power7_enter_nap_mode) #ifdef CONFIG_KVM_BOOK3S_64_HV /* Tell KVM we're napping */ li r4,KVM_HWTHREAD_IN_NA
[RFC PATCH v4 02/12] powerpc/book3s: Introduce exclusive emergency stack for machine check exception.
From: Mahesh Salgaonkar
This patch introduces exclusive emergency stack for machine check exception.
We use emergency stack to handle machine check exception so that we can save
MCE information (srr1, srr0, dar and dsisr) before turning on ME bit and be
ready for re-entrancy. This helps us to prevent clobbering of MCE information
in case of nested machine checks.
The reason for using emergency stack over normal kernel stack is that the
machine check might occur in the middle of setting up a stack frame which may
result into improper use of kernel stack.
Signed-off-by: Mahesh Salgaonkar
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/paca.h |9 +
arch/powerpc/kernel/setup_64.c | 10 +-
arch/powerpc/xmon/xmon.c|4
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 77c91e7..b4ca4e9 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -147,6 +147,15 @@ struct paca_struct {
*/
struct opal_machine_check_event *opal_mc_evt;
#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+ /* Exclusive emergency stack pointer for machine check exception. */
+ void *mc_emergency_sp;
+ /*
+* Flag to check whether we are in machine check early handler
+* and already using emergency stack.
+*/
+ u16 in_mce;
+#endif
/* Stuff for accurate time accounting */
u64 user_time; /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 389fb807..6f96af0 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -529,7 +529,8 @@ static void __init exc_lvl_early_init(void)
/*
* Stack space used when we detect a bad kernel stack pointer, and
- * early in SMP boots before relocation is enabled.
+ * early in SMP boots before relocation is enabled. Exclusive emergency
+ * stack for machine checks.
*/
static void __init emergency_stack_init(void)
{
@@ -552,6 +553,13 @@ static void __init emergency_stack_init(void)
sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
sp += THREAD_SIZE;
paca[i].emergency_sp = __va(sp);
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ /* emergency stack for machine check exception handling. */
+ sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
+ sp += THREAD_SIZE;
+ paca[i].mc_emergency_sp = __va(sp);
+#endif
}
}
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 96bf5bd..5f17adb 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2044,6 +2044,10 @@ static void dump_one_paca(int cpu)
DUMP(p, stab_addr, "lx");
#endif
DUMP(p, emergency_sp, "p");
+#ifdef CONFIG_PPC_BOOK3S_64
+ DUMP(p, mc_emergency_sp, "p");
+ DUMP(p, in_mce, "x");
+#endif
DUMP(p, data_offset, "lx");
DUMP(p, hw_cpu_id, "x");
DUMP(p, cpu_start, "x");
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[RFC PATCH v4 03/12] powerpc/book3s: handle machine check in Linux host.
From: Mahesh Salgaonkar Move machine check entry point into Linux. So far we were dependent on firmware to decode MCE error details and handover the high level info to OS. This patch introduces early machine check routine that saves the MCE information (srr1, srr0, dar and dsisr) to the emergency stack. We allocate stack frame on emergency stack and set the r1 accordingly. This allows us to be prepared to take another exception without loosing context. One thing to note here that, if we get another machine check while ME bit is off then we risk a checkstop. Hence we restrict ourselves to save only MCE information and register saved on PACA_EXMC save are before we turn the ME bit on. We use paca->in_mce flag to differentiate between first entry and nested machine check entry which helps proper use of emergency stack. We increment paca->in_mce every time we enter in early machine check handler and decrement it while leaving. When we enter machine check early handler first time (paca->in_mce == 0), we are sure nobody is using MC emergency stack and allocate a stack frame at the start of the emergency stack. During subsequent entry (paca->in_mce > 0), we know that r1 points inside emergency stack and we allocate separate stack frame accordingly. This prevents us from clobbering MCE information during nested machine checks. The early machine check handler changes are placed under CPU_FTR_HVMODE section. This makes sure that the early machine check handler will get executed only in hypervisor kernel. This is the code flow: Machine Check Interrupt | V 0x200 vector ME=0, IR=0, DR=0 | V +---+ |machine_check_pSeries_early: | ME=0, IR=0, DR=0 | Alloc frame on emergency stack | | Save srr1, srr0, dar and dsisr on stack | +---+ | (ME=1, IR=0, DR=0, RFID) | V machine_check_handle_earlyME=1, IR=0, DR=0 | V +---+ | machine_check_early (r3=pt_regs)| ME=1, IR=0, DR=0 | Things to do: (in next patches) | | Flush SLB for SLB errors| | Flush TLB for TLB errors| | Decode and save MCE info| +---+ | (Fall through existing exception handler routine.) | V machine_check_pSerie ME=1, IR=0, DR=0 | (ME=1, IR=1, DR=1, RFID) | V machine_check_common ME=1, IR=1, DR=1 . . . Signed-off-by: Mahesh Salgaonkar --- arch/powerpc/kernel/asm-offsets.c|4 + arch/powerpc/kernel/exceptions-64s.S | 111 ++ arch/powerpc/kernel/traps.c | 12 3 files changed, 127 insertions(+) diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 8207459..e0e8ebb 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -238,6 +238,10 @@ int main(void) DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx)); #endif /* CONFIG_PPC_STD_MMU_64 */ DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); +#ifdef CONFIG_PPC_BOOK3S_64 + DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp)); + DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce)); +#endif DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state)); DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime)); diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 902ca3c..87a70d2 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -156,7 +156,11 @@ machine_check_pSeries_1: HMT_MEDIUM_PPR_DISCARD SET_SCRATCH0(r13) /* save r13 */ EXCEPTION_PROLOG_0(PACA_EXMC) +BEGIN_FTR_SECTION + b machine_check_pSeries_early +FTR_SECTION_ELSE b machine_check_pSeries_0 +ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) . = 0x300 .globl data_access_pSeries @@ -404,6 +408,64 @@ denorm_exception_hv: .align 7 /* moved from 0x200 */ +machine_check_pSer
[RFC PATCH v4 00/12] Machine check handling in linux host.
Hi, Please find the patch set that performs the machine check handling inside linux host. The design is to be able to handle re-entrancy so that we do not clobber the machine check information during nested machine check interrupt. The patch 2 introduces separate emergency stack in paca structure exclusively for machine check exception handling. Patch 3 implements the logic to save the raw MCE info onto the emergency stack and prepares to take another exception. Patch 5 and 6 adds CPU-side hooks for early machine check handler and TLB flush. The patch 7 and 8 is responsible to detect SLB/TLB errors and flush them off in the real mode. The patch 9 implements the logic to decode and save high level MCE information to per cpu buffer without clobbering. Patch 10 implements mechanism to queue up MCE event in cases where early handler can not deliver the event to host kernel right away. The patch 12 adds the basic error handling to the high level C code with MMU on. I have tested SLB multihit, MC coming from opal context on powernv. Please review and let me know your comments. Changes in v4: - Split the prolog common macro in 3 parts in patch 1. - Save the regs from EXMC save area to stack before turning on ME bit. - Set/Clear MSR_RI bit at right places. - Handle a situation where machine check comes in when thread was in power saving mode. - Queue up the MCE event and return from the interrupt if MC is hit during context which we are not sure of. Go to kernel in V mode only if we are coming from hypervisor userspace (HV=1, PR=1). Changes in v3: - Rebased to v3.11-rc7 - Handle MCE coming from opal context, secondary thread nap and return from interrupt. Queue up the MCE event in this scenario and log it later during syscall exit path. Changes in v2: - Moved early machine check handling code under CPU_FTR_HVMODE section. This makes sure that the early machine check handler will get executed only in hypervisor kernel. - Add dedicated emergency stack for machine check so that we don't end up disturbing others who use same emergency stack. - Fixed the machine check early handle where it used to assume that r1 always contains the valid stack pointer. - Fixed an issue where per-cpu mce_nest_count variable underflows when kvm fails to handle MC error and exit the guest. - Fixed the code to restore r13 while before exiting early handler. Thanks, -Mahesh. --- Mahesh Salgaonkar (12): powerpc/book3s: Split the common exception prolog logic into two section. powerpc/book3s: Introduce exclusive emergency stack for machine check exception. powerpc/book3s: handle machine check in Linux host. powerpc/book3s: Return from interrupt if coming from evil context. powerpc/book3s: Introduce a early machine check hook in cpu_spec. powerpc/book3s: Add flush_tlb operation in cpu_spec. powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7. powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8. powerpc/book3s: Decode and save machine check event. powerpc/book3s: Queue up and process delayed MCE events. powerpc/powernv: Remove machine check handling in OPAL. powerpc/powernv: Machine check exception handling. arch/powerpc/include/asm/bitops.h|5 arch/powerpc/include/asm/cputable.h | 12 + arch/powerpc/include/asm/exception-64s.h | 21 +- arch/powerpc/include/asm/mce.h | 198 + arch/powerpc/include/asm/paca.h |9 + arch/powerpc/kernel/Makefile |1 arch/powerpc/kernel/asm-offsets.c|4 arch/powerpc/kernel/cpu_setup_power.S| 38 ++- arch/powerpc/kernel/cputable.c | 16 + arch/powerpc/kernel/entry_64.S |5 arch/powerpc/kernel/exceptions-64s.S | 196 + arch/powerpc/kernel/idle_power7.S|1 arch/powerpc/kernel/mce.c| 345 ++ arch/powerpc/kernel/mce_power.c | 284 + arch/powerpc/kernel/setup_64.c | 10 + arch/powerpc/kernel/traps.c | 15 + arch/powerpc/kvm/book3s_hv_ras.c | 50 ++-- arch/powerpc/platforms/powernv/opal.c| 161 -- arch/powerpc/xmon/xmon.c |4 19 files changed, 1220 insertions(+), 155 deletions(-) create mode 100644 arch/powerpc/include/asm/mce.h create mode 100644 arch/powerpc/kernel/mce.c create mode 100644 arch/powerpc/kernel/mce_power.c -- -Mahesh ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH v4 01/12] powerpc/book3s: Split the common exception prolog logic into two section.
From: Mahesh Salgaonkar This patch splits the common exception prolog logic into three parts to facilitate reuse of existing code in the next patch. This patch also re-arranges few instructions in such a way that the second part now deals with saving register values from paca save area to stack frame, and the third part deals with saving current register values to stack frame. The second and third part will be reused in the machine check exception routine in the subsequent patch. Please note that this patch does not introduce or change existing code logic. Instead it is just a code movement and instruction re-ordering. Patch Acked-by Paul. But made some minor modification (explained above) to address Paul's comment in the later patch(3). Signed-off-by: Mahesh Salgaonkar Acked-by: Paul Mackerras --- arch/powerpc/include/asm/exception-64s.h | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 07ca627..94ab2d2 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -281,9 +281,12 @@ do_kvm_##n: \ beq 4f; /* if from kernel mode */ \ ACCOUNT_CPU_USER_ENTRY(r9, r10); \ SAVE_PPR(area, r9, r10); \ -4: std r2,GPR2(r1);/* save r2 in stackframe*/ \ - SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ - SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe*/ \ +4: EXCEPTION_PROLOG_COMMON_2(area)\ + EXCEPTION_PROLOG_COMMON_3(n) \ + ACCOUNT_STOLEN_TIME + +/* Save original regs values from save area to stack frame. */ +#define EXCEPTION_PROLOG_COMMON_2(area) \ ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ ld r10,area+EX_R10(r13); \ std r9,GPR9(r1); \ @@ -298,9 +301,14 @@ do_kvm_##n: \ ld r10,area+EX_CFAR(r13); \ std r10,ORIG_GPR3(r1); \ END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);\ - GET_LR(r9,area);/* Get LR, later save to stack */ \ + GET_LR(r9,area);/* Save LR to stack */ \ + std r9,_LINK(r1); + +#define EXCEPTION_PROLOG_COMMON_3(n) \ + std r2,GPR2(r1);/* save r2 in stackframe*/ \ + SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ + SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe*/ \ ld r2,PACATOC(r13);/* get kernel TOC into r2 */ \ - std r9,_LINK(r1); \ mfctr r10;/* save CTR in stackframe */ \ std r10,_CTR(r1); \ lbz r10,PACASOFTIRQEN(r13);\ @@ -312,8 +320,7 @@ do_kvm_##n: \ li r10,0; \ ld r11,exception_marker@toc(r2); \ std r10,RESULT(r1); /* clear regs->result */ \ - std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ - ACCOUNT_STOLEN_TIME + std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ /* * Exception vectors. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 7/8][v4] power: implement is_instr_load_store().
On 9/13/2013 7:49 PM, Sukadev Bhattiprolu wrote:
Implement is_instr_load_store() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions.
This function will be used in a follow-on patch to save memory hierarchy
information of the load/store.
+/*
+ * Values of bits 21:30 of Fixed-point and Floating-point Load and Store
+ * instructions.
+ *
+ * Reference: PowerISA_V2.06B_Public.pdf, Sections 3.3.2 through 3.3.6 and
+ * 4.6.2 through 4.6.4.
+ */
+#definex_lbzx 87
+#definex_lbzux 119
+#definex_lhzx 279
+
+static unsigned int x_form_load_store[] = {
+ x_lbzx, x_lbzux,x_lhzx, x_lhzux,x_lhax,
+ x_lhaux,x_lwzx, x_lwzux,x_lwax, x_lwaux,
+ x_ldx, x_ldux, x_stbx, x_stbux,x_sthx,
+ x_sthux,x_stwx, x_stwux,x_stdx, x_stdux,
+ x_lhbrx,x_lwbrx,x_sthbrx, x_stwbrx, x_ldbrx,
+ x_stdbrx, x_lswi, x_lswx, x_stswi,x_stswx,
+ x_lfsx, x_lfsux,x_lfdx, x_lfdux,x_lfiwax,
+ x_lfiwzx, x_stfsx,x_stfsux, x_stfdx,x_stfdux,
+ x_stfiwax, x_lfdpx,x_stfdpx
+};
+
+
Can you explain why this function only covers fixed point and floating
point instructions? I.e., why did you skip Altivec and VSX?
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Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
On 09/13/2013 04:53 PM, Kumar Gala wrote:
> On Sep 13, 2013, at 4:14 AM, Valentin Longchamp wrote:
>> On 09/11/2013 08:58 AM, Prabhakar Kushwaha wrote:
>>> +
>>> +&pci0 {
>>> + compatible = "fsl,t1042-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
>>> + device_type = "pci";
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + bus-range = <0x0 0xff>;
>>> + interrupts = <20 2 0 0>;
>>> + fsl,iommu-parent = <&pamu0>;
>>> + pcie@0 {
>>> + reg = <0 0 0 0 0>;
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + device_type = "pci";
>>> + interrupts = <20 2 0 0>;
>>> + interrupt-map-mask = <0xf800 0 0 7>;
>>> + interrupt-map = <
>>> + /* IDSEL 0x0 */
>>> + 0 0 1 &mpic 40 1 0 0
>>> + 0 0 2 &mpic 1 1 0 0
>>> + 0 0 3 &mpic 2 1 0 0
>>> + 0 0 4 &mpic 3 1 0 0
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&pci1 {
>>> + compatible = "fsl,t1042-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
>>> + device_type = "pci";
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + bus-range = <0 0xff>;
>>> + interrupts = <21 2 0 0>;
>>> + fsl,iommu-parent = <&pamu0>;
>>> + pcie@0 {
>>> + reg = <0 0 0 0 0>;
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + device_type = "pci";
>>> + interrupts = <21 2 0 0>;
>>> + interrupt-map-mask = <0xf800 0 0 7>;
>>> + interrupt-map = <
>>> + /* IDSEL 0x0 */
>>> + 0 0 1 &mpic 41 1 0 0
>>> + 0 0 2 &mpic 5 1 0 0
>>> + 0 0 3 &mpic 6 1 0 0
>>> + 0 0 4 &mpic 7 1 0 0
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&pci2 {
>>> + compatible = "fsl,t1042-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
>>> + device_type = "pci";
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + bus-range = <0x0 0xff>;
>>> + interrupts = <22 2 0 0>;
>>> + fsl,iommu-parent = <&pamu0>;
>>> + pcie@0 {
>>> + reg = <0 0 0 0 0>;
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + device_type = "pci";
>>> + interrupts = <22 2 0 0>;
>>> + interrupt-map-mask = <0xf800 0 0 7>;
>>> + interrupt-map = <
>>> + /* IDSEL 0x0 */
>>> + 0 0 1 &mpic 42 1 0 0
>>> + 0 0 2 &mpic 9 1 0 0
>>> + 0 0 3 &mpic 10 1 0 0
>>> + 0 0 4 &mpic 11 1 0 0
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&pci3 {
>>> + compatible = "fsl,t1042-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
>>> + device_type = "pci";
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + bus-range = <0x0 0xff>;
>>> + interrupts = <23 2 0 0>;
>>> + fsl,iommu-parent = <&pamu0>;
>>> + pcie@0 {
>>> + reg = <0 0 0 0 0>;
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + device_type = "pci";
>>> + interrupts = <23 2 0 0>;
>>> + interrupt-map-mask = <0xf800 0 0 7>;
>>> + interrupt-map = <
>>> + /* IDSEL 0x0 */
>>> + 0 0 1 &mpic 43 1 0 0
>>> + 0 0 2 &mpic 0 1 0 0
>>> + 0 0 3 &mpic 4 1 0 0
>>> + 0 0 4 &mpic 8 1 0 0
>>> + >;
>>> + };
>>> +};
>>> +
>>
>> The above 4 nodes have the consequence that it will then be mandatory that a
>> board support .dts file that would like to inlcude the SOC-NAMEsi-post.dtsi
>> defines the pci0, pci1, pci2, pci3 aliases.
>>
>> Now it is possible that a board does not implement pci1 for instance. So its
>> .dts file would ideally not define a node for it, and thus not define the
>> respective alias. However, this triggers this dtc compile error (which is
>> correct):
>>
>>> [chlongv1@chber1-10533x linux-km]$ make kmp204x.dtb
>>> DTC arch/powerpc/boot/kmp204x.dtb
>>> Error: arch/powerpc/boot/dts/fsl/p2041si-post.dtsi:98.2-3 label or path,
>>> 'pci1', not found
>>> FATAL ERROR: Syntax error parsing input tree
>>> make[1]: *** [arch/powerpc/boot/kmp204x.dtb] Error 1
>>> make: *** [kmp204x.dtb] Error 2
>>
>> The solution I have found is to define a "dummy" disabled node so that I can
>> define the alias, but I am not really happy about this:
>>
>>> pci1: pcie@ffe201000 {
>>> status = "disabled";
>>> };
>>
>> I am here missing something obvious or shouldn't it be possible that such
>> .dtsi
>> files allow not to define unused/unnecessary nodes ?
>
> Isn't this correct, that you are disabling the PCIe1 interface
Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface
On Mon, Sep 09, 2013 at 05:20:44PM +0200, Alexander Gordeev wrote: > On Fri, Sep 06, 2013 at 05:32:05PM -0600, Bjorn Helgaas wrote: > > I propose that you rework it that way, and at least find out what > > (if anything) would break if we do that. Or maybe we just give up > > some optimization; it would be nice to quantify that, too. > > Hi Bjorn, > > The series is what it seems a direction to take. > > Looks like we need PPC folks to agree on the quota check update > for pSeries (yes, they do bail out with a positive return value > from arch_msi_check_device()): Hi Ben, An initiative to simplify MSI/MSI-X allocation interface is brewing. It seems pSeries quota thing is an obstacle. If it could be given up (patch 2/9). Thanks! -- Regards, Alexander Gordeev agord...@redhat.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
On 09/13/2013 01:15 AM, Mark Rutland wrote: On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote: On 09/02/2013 11:58 PM, Mark Rutland wrote: Hi, On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zh...@freescale.com wrote: From: Hongbo Zhang Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds the device tree nodes for them. Signed-off-by: Hongbo Zhang --- .../devicetree/bindings/powerpc/fsl/dma.txt| 67 arch/powerpc/boot/dts/fsl/b4si-post.dtsi |4 +- arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi | 82 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi | 82 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi|4 +- 5 files changed, 235 insertions(+), 4 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt index ddf17af..332ac77 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt @@ -126,6 +126,73 @@ Example: }; }; +** Freescale Elo3 DMA Controller + This is EloPlus controller with 8 channels, used in Freescale Txxx and Bxxx I was under the impression EloPlus was the previous revision. Should that say Elo3, or is Elo3 considered to be an EloPlus implementation? In this patch 1/3 I revise the doc to make it clear we have Elo and EloPlus, and I'm adding another new Elo3. Yes the only difference between Elo3 and EloPlus is channel numbers(8 channels vs 4 channels), so we can call "Elo3 is an 8-channel EloPlus" Ok. + series chips, such as t1040, t4240, b4860. + +Required properties: + +- compatible: must include "fsl,elo3-dma" +- reg : The example has two reg entries. What both are should be specified. From what you described last time, it sounds like each is a status register for four channels. Presumably the first covers the channels at 0x0,0x80,0x100,0x180, and the second covers the channels at 0x300,0x380,0x400,0x480? If the registers have specific names in a datasheet, it would be worth mentioning them. Yes, each is a status register for four channels, you got it -- this means my statement works. Is it necessary to specify all the register names? I can describe my two registers, but in other cases the reg entryies can cover tens even hundreds of registers, just a summary is OK I think. I think there should at least be a description of which channels each reg entry corresponds to. I see this hasn't been done so far for the older Elo DMAs, but they only had 4 channels max, and one status reg. OK, I will update the reg description to make it more clear. If the specification of the DMA controller allows for more channels, it may be worth describing that case now. This DMA controller doesn't allows for more channels. (Even if it does, it should be another new controller) Ok. +- ranges: describes the mapping between the address space of the + DMA channels and the address space of the DMA controller This looks odd as a required property, and I'm slightly confused. Is this used to map the reg values of the DMA channels, or is it used when mapping the DMA address space (for which dma-ranges exists in ePAPR and other bindings). It is used to map the reg values of DMA channels. Ok, I guess that makes sense. + +- DMA channel nodes: +- compatible: must include "fsl,eloplus-dma-channel" +- reg : What does this represent? What are valid values? In the example below it looks like these are offsets of control registers within the dma controller. Yes, they are offsets of control registers within dma controller, but the contents in these registers are for dma channels. Physically we have dma controller registers and dma channel registers, they are in one continuous physical address space, we divide all these registers into two controller/channel parts, according to contents in these registers, common status registers for all channels are called dma controller registers, otherwise channel specific registers are called dma channel registers. I see, so this reg represents a channels channel specific registers (which are distinct from the shared status registers). I was confused initially as to what address space they were in, but that makes sense with your description of ranges above. If the reg property may have any value, how do they get mapped to bits in the status register(s)? In fact, each channel has its own status register(and also other registers), the dma controller status register is just aggregation of all channel status register. (that seems duplicated somehow, maybe this is due to hardware compatibility with legacy one, and the de
Re: [PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
On 09/02/2013 06:37 PM, Haijun Zhang wrote:
We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
Signed-off-by: Haijun Zhang
---
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
index 5180d9d..0c0efa9 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -130,7 +130,7 @@ usb@22000 {
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
- fsl,sdhci-auto-cmd12;
+ sdhci,auto-cmd12;
interrupts = <41 0x2 0 0>;
};
Hi, scott
Could you help review this patch?
--
Thanks & Regards
Haijun
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