Re: [PATCH v2 2/2] flexcan: add err interrupt for p1010rdb
On 06/20/2014 04:01 AM, Zhao Qiang wrote: add err interrupt for p1010rdb into dts. Signed-off-by: Zhao Qiang b45...@freescale.com --- Changes for v2: - add binding documentation update Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 7 +-- arch/powerpc/boot/dts/fsl/p1010si-post.dtsi | 6 -- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 56d6cc3..81929e5 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -10,7 +10,9 @@ Required properties: - fsl,p1010-flexcan - reg : Offset and length of the register set for this device -- interrupts : Interrupt tuple for this device +- interrupts : Interrupt tuple for this device. + The first interrupt is for FlexCAN(Message Buffer and Wake Up) + The second is for error(Shared with IFC, PEX1 and some other device) The second interrupt is optional, at least on ARM we don't need it, please reflect this in the documentation update. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions| Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917- | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de | signature.asc Description: OpenPGP digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 5/7] mmc: sdhci: host: add new f_sdh30
On Friday 20 June 2014 17:35:26 Vincent Yang wrote: +Required properties: +- compatible: fujitsu,f_sdh30 + +Optional properties: +- gpios: Specify gpios for controlling signal level +- clocks: Specify clocks used by SDHCI controller +- clock-names: Specify the clock-names to be used If you want to use clock-names, you have to specify the exact names of the clock input signals used by your device, and the order in which they are listed. For both the clocks and the gpios, you have to specify how many signals there are, and ideally describe what they are used for. In case of a gpio controlling the signal level, it may be better to model this as a gpio-regulator device, depending on how exactly it is used. When posting a DT binding document, please always add devicet...@vger.kernel.org to Cc. Arnd ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH 0/7] mmc: sdhci: adding support for a new Fujitsu sdhci IP
Hi, We are adding support for a new Fujitsu sdhci IP. These patches are against v3.16-rc1 mainline since nothing in mmc-next at this moment. These patches are tested on 3.16-rc1 integration tree. We welcome any comment and advice about how to make any improvements or better align them with upstream. Thanks a lot! Best regards, Vincent Yang Vincent Yang (7): mmc: sdhci: add quirk for broken 3.0V support mmc: sdhci: add quirk for voltage switch callback mmc: sdhci: add quirk for tuning work around mmc: sdhci: add quirk for single block transactions mmc: sdhci: host: add new f_sdh30 mmc: core: hold SD Clock before CMD11 during Signal Voltage Switch Procedure mmc: core: add manual resume capability .../devicetree/bindings/mmc/sdhci-fujitsu.txt | 25 ++ drivers/mmc/core/core.c| 8 +- drivers/mmc/core/sd.c | 4 + drivers/mmc/host/Kconfig | 7 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci.c | 18 +- drivers/mmc/host/sdhci.h | 1 + drivers/mmc/host/sdhci_f_sdh30.c | 429 + drivers/mmc/host/sdhci_f_sdh30.h | 40 ++ include/linux/mmc/host.h | 14 + include/linux/mmc/sdhci.h | 8 + 11 files changed, 550 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt create mode 100644 drivers/mmc/host/sdhci_f_sdh30.c create mode 100644 drivers/mmc/host/sdhci_f_sdh30.h -- 1.9.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH 1/7] mmc: sdhci: add quirk for broken 3.0V support
This patch defines a quirk for platforms unable
to enable 3.0V support.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 47055f3..523075f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3069,6 +3069,9 @@ int sdhci_add_host(struct sdhci_host *host)
}
#endif /* CONFIG_REGULATOR */
+ if (host-quirks2 SDHCI_QUIRK2_NO_3_0_V)
+ caps[0] = ~SDHCI_CAN_VDD_300;
+
/*
* According to SD Host Controller spec v3.00, if the Host System
* can afford more than 150mA, Host Driver should set XPC to 1. Also
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 08abe99..cac0958 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_HS200 (16)
/* Controller does not support DDR50 */
#define SDHCI_QUIRK2_BROKEN_DDR50 (17)
+/* The system physically doesn't support 3.0v, even if the host does */
+#define SDHCI_QUIRK2_NO_3_0_V (18)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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[RFC PATCH 2/7] mmc: sdhci: add quirk for voltage switch callback
This patch defines a quirk to do a callback when
switching voltages so do controller-specific
actions.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
drivers/mmc/host/sdhci.c | 5 +
drivers/mmc/host/sdhci.h | 1 +
include/linux/mmc/sdhci.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 523075f..98d996f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1763,6 +1763,11 @@ static int sdhci_do_start_signal_voltage_switch(struct
sdhci_host *host,
ctrl |= SDHCI_CTRL_VDD_180;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ /* Some controller need to do more when switching */
+ if ((host-quirks2 SDHCI_QUIRK2_VOLTAGE_SWITCH)
+ host-ops-voltage_switch)
+ host-ops-voltage_switch(host);
+
/* Wait for 5ms */
usleep_range(5000, 5500);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 4a5cd5e..63c7a46 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -292,6 +292,7 @@ struct sdhci_ops {
void(*adma_workaround)(struct sdhci_host *host, u32 intmask);
void(*platform_init)(struct sdhci_host *host);
void(*card_event)(struct sdhci_host *host);
+ void(*voltage_switch)(struct sdhci_host *host);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index cac0958..13ab139 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_DDR50 (17)
/* The system physically doesn't support 3.0v, even if the host does */
#define SDHCI_QUIRK2_NO_3_0_V (18)
+/* Do a callback when switching voltages so do controller-specific actions */
+#define SDHCI_QUIRK2_VOLTAGE_SWITCH(19)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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[RFC PATCH 3/7] mmc: sdhci: add quirk for tuning work around
This patch defines a quirk for tuning work
around for some sdhci host controller. It sets
both SDHCI_CTRL_EXEC_TUNING and SDHCI_CTRL_TUNED_CLK
for tuning.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
drivers/mmc/host/sdhci.c | 2 ++
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 98d996f..fe69cc5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1867,6 +1867,8 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32
opcode)
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ if (host-quirks2 SDHCI_QUIRK2_TUNING_WORK_AROUND)
+ ctrl |= SDHCI_CTRL_TUNED_CLK;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
/*
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 13ab139..5690a1f 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -102,6 +102,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_NO_3_0_V (18)
/* Do a callback when switching voltages so do controller-specific actions */
#define SDHCI_QUIRK2_VOLTAGE_SWITCH(19)
+/* forced tuned clock */
+#define SDHCI_QUIRK2_TUNING_WORK_AROUND(110)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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[RFC PATCH 4/7] mmc: sdhci: add quirk for single block transactions
This patch defines a quirk to disable the block count
for single block transactions.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
drivers/mmc/host/sdhci.c | 8 +---
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fe69cc5..21a29ae 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -876,7 +876,7 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
static void sdhci_set_transfer_mode(struct sdhci_host *host,
struct mmc_command *cmd)
{
- u16 mode;
+ u16 mode = 0;
struct mmc_data *data = cmd-data;
if (data == NULL) {
@@ -889,9 +889,11 @@ static void sdhci_set_transfer_mode(struct sdhci_host
*host,
WARN_ON(!host-data);
- mode = SDHCI_TRNS_BLK_CNT_EN;
+ if (!(host-quirks2 SDHCI_QUIRK2_SUPPORT_SINGLE))
+ mode = SDHCI_TRNS_BLK_CNT_EN;
+
if (mmc_op_multi(cmd-opcode) || data-blocks 1) {
- mode |= SDHCI_TRNS_MULTI;
+ mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
/*
* If we are sending CMD23, CMD12 never gets sent
* on successful completion (so no Auto-CMD12).
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 5690a1f..ac645b9 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -104,6 +104,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_VOLTAGE_SWITCH(19)
/* forced tuned clock */
#define SDHCI_QUIRK2_TUNING_WORK_AROUND(110)
+/* disable the block count for single block transactions */
+#define SDHCI_QUIRK2_SUPPORT_SINGLE(111)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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[RFC PATCH 5/7] mmc: sdhci: host: add new f_sdh30
This patch adds new host controller driver for
Fujitsu SDHCI controller f_sdh30.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
.../devicetree/bindings/mmc/sdhci-fujitsu.txt | 25 ++
drivers/mmc/host/Kconfig | 7 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci_f_sdh30.c | 340 +
drivers/mmc/host/sdhci_f_sdh30.h | 40 +++
5 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt
create mode 100644 drivers/mmc/host/sdhci_f_sdh30.c
create mode 100644 drivers/mmc/host/sdhci_f_sdh30.h
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt
b/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt
new file mode 100644
index 000..b6704cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-fujitsu.txt
@@ -0,0 +1,25 @@
+* Fujitsu SDHCI controller
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the sdhci_f_sdh30 driver.
+
+Required properties:
+- compatible: fujitsu,f_sdh30
+
+Optional properties:
+- gpios: Specify gpios for controlling signal level
+- clocks: Specify clocks used by SDHCI controller
+- clock-names: Specify the clock-names to be used
+
+Example:
+
+ sdhci1: sdio@3660 {
+ compatible = fujitsu,f_sdh30;
+ reg = 0 0x3660 0x1000;
+ interrupts = 0 172 0x4,
+0 173 0x4;
+ gpios = gpio0 7 0;
+ clocks = clk_hdmi_2_0, clk_hdmi_3_0;
+ clock-names = sd_sd4clk, sd_bclk;
+ };
+
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 7fee224..a1f3207 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -281,6 +281,13 @@ config MMC_SDHCI_BCM2835
This selects the BCM2835 SD/MMC controller. If you have a BCM2835
platform with SD or MMC devices, say Y or M here.
+config MMC_SDHCI_F_SDH30
+ tristate SDHCI support for Fujitsu Semiconductor F_SDH30
+ depends on MMC_SDHCI (ARCH_MB8AC0300 || ARCH_MB86S70)
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
If unsure, say N.
config MMC_MOXART
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 7f81ddf..a4c89e5 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C)+= sdhci-s3c.o
obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30)+= sdhci_f_sdh30.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c
new file mode 100644
index 000..d916c47
--- /dev/null
+++ b/drivers/mmc/host/sdhci_f_sdh30.c
@@ -0,0 +1,340 @@
+/*
+ * linux/drivers/mmc/host/sdhci_f_sdh30.c
+ *
+ * Copyright (C) 2013 - 2014 Fujitsu Semiconductor, Ltd
+ * Vincent Yang vincent.y...@tw.fujitsu.com
+ * Copyright (C) 2014 Linaro Ltd Andy Green andy.gr...@linaro.org
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include linux/err.h
+#include linux/delay.h
+#include linux/module.h
+#include linux/mmc/sd.h
+#include linux/mmc/host.h
+#include linux/mmc/card.h
+#include linux/gpio.h
+#include linux/of_gpio.h
+#include linux/of_address.h
+#include linux/platform_device.h
+#include linux/pm.h
+#include linux/pm_runtime.h
+#include linux/suspend.h
+
+#include sdhci.h
+#include sdhci-pltfm.h
+#include sdhci_f_sdh30.h
+#include ../core/core.h
+
+#define DRIVER_NAME f_sdh30
+
+
+struct f_sdhost_priv {
+ struct clk *clk_sd4;
+ struct clk *clk_b;
+ int gpio_select_1v8;
+ u32 vendor_hs200;
+ struct device *dev;
+};
+
+void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
+{
+ struct f_sdhost_priv *priv = sdhci_priv(host);
+ u32 ctrl = 0;
+
+ usleep_range(2500, 3000);
+ ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
+ ctrl |= F_SDH30_CRES_O_DN;
+ sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
+ ctrl |= F_SDH30_MSEL_O_1_8;
+ sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
+
+ if (gpio_is_valid(priv-gpio_select_1v8)) {
+ dev_info(priv-dev, %s: setting gpio\n, __func__);
+ gpio_direction_output(priv-gpio_select_1v8, 0);
+ }
+
+ ctrl = ~F_SDH30_CRES_O_DN;
+
[RFC PATCH 6/7] mmc: core: hold SD Clock before CMD11 during Signal Voltage Switch Procedure
This patch is to fix an issue found on mb86s7x platforms. [symptom] There are some UHS-1 SD memory cards sometimes cannot be detected correctly, e.g., Transcend 600x SDXC 64GB UHS-1 memory card. During Signal Voltage Switch Procedure, failure to switch is indicated by the card holding DAT[3:0] low. [analysis] According to SD Host Controller Simplified Specification Version 3.00 chapter 3.6.1, the Signal Voltage Switch Procedure should be: (1) Check S18A; (2) Issue CMD11; (3) Check CMD 11 response; (4) Stop providing SD clock; (5) Check DAT[3:0] should be b; (6) Set 1.8V Signal Enable; (7) Wait 5ms; (8) Check 1.8V Signal Enable; (9) Provide SD Clock; (10) Wait 1ms; (11) Check DAT[3:0] should be b; (12) error handling With CONFIG_MMC_CLKGATE=y, sometimes there is one more gating/un-gating SD clock between (2) and (3). In this case, some UHS-1 SD cards will hold DAT[3:0] b at (11) and thus fails Signal Voltage Switch Procedure. [solution] By mmc_host_clk_hold() before CMD11, the additional gating/un-gating SD clock between (2) and (3) can be prevented and thus no failure at (11). It has been verified with many UHS-1 SD cards on mb86s7x platforms and works correctly. Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com --- drivers/mmc/core/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 7dc0c85..764af63 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1428,6 +1428,8 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr) pr_warning(%s: cannot verify signal voltage switch\n, mmc_hostname(host)); + mmc_host_clk_hold(host); + cmd.opcode = SD_SWITCH_VOLTAGE; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; @@ -1438,8 +1440,6 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr) if (!mmc_host_is_spi(host) (cmd.resp[0] R1_ERROR)) return -EIO; - - mmc_host_clk_hold(host); /* * The card should drive cmd and dat[0:3] low immediately * after the response of cmd11, but wait 1 ms to be sure -- 1.9.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH 7/7] mmc: core: add manual resume capability
This patch adds manual resume for some embedded platforms with rootfs
stored in SD card. It references CONFIG_MMC_BLOCK_DEFERRED_RESUME in
kernel 3.10. It lets host controller driver to manually handle resume
by itself.
[symptom]
This issue is found on mb86s7x platforms with rootfs stored in SD card.
It failed to resume form STR suspend mode because SD card cannot be ready
in time. It take longer time (e.g., 600ms) to be ready for access.
The error log looks like below:
root@localhost:~# echo mem /sys/power/state
[ 30.441974] SUSPEND
SCB Firmware : Category 01 Version 02.03 Rev. 00_
Config : (no configuration)
root@localhost:~# [ 30.702976] Buffer I/O error on device mmcblk1p2, logical
block 31349
[ 30.709678] Buffer I/O error on device mmcblk1p2, logical block 168073
[ 30.716220] Buffer I/O error on device mmcblk1p2, logical block 168074
[ 30.722759] Buffer I/O error on device mmcblk1p2, logical block 168075
[ 30.729456] Buffer I/O error on device mmcblk1p2, logical block 31349
[ 30.735916] Buffer I/O error on device mmcblk1p2, logical block 31350
[ 30.742370] Buffer I/O error on device mmcblk1p2, logical block 31351
[ 30.749025] Buffer I/O error on device mmcblk1p2, logical block 168075
[ 30.755657] Buffer I/O error on device mmcblk1p2, logical block 31351
[ 30.763130] Aborting journal on device mmcblk1p2-8.
[ 30.768060] JBD2: Error -5 detected when updating journal superblock for
mmcblk1p2-8.
[ 30.776085] EXT4-fs error (device mmcblk1p2): ext4_journal_check_start:56:
Detected aborted journal
[ 30.785259] EXT4-fs (mmcblk1p2): Remounting filesystem read-only
[ 31.370716] EXT4-fs error (device mmcblk1p2): ext4_find_entry:1309: inode
#2490369: comm udevd: reading directory lblock 0
[ 31.382485] EXT4-fs error (device mmcblk1p2): ext4_find_entry:1309: inode
#1048577: comm udevd: reading directory lblock 0
[analysis]
In system resume path, mmc_sd_resume() is failed with error code -123
because at that time SD card is still not ready on mb86s7x platforms.
[solution]
In order to not blocking system resume path, this patch just sets a flag
MMC_BUSRESUME_MANUAL_RESUME when this error happened, and then host controller
driver can understand it by this flag. Then host controller driver have to
resume SD card manually and asynchronously.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
---
drivers/mmc/core/core.c | 4 ++
drivers/mmc/core/sd.c| 4 ++
drivers/mmc/host/sdhci_f_sdh30.c | 89
include/linux/mmc/host.h | 14 +++
4 files changed, 111 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 764af63..51fce49 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -2648,6 +2648,10 @@ int mmc_pm_notify(struct notifier_block *notify_block,
case PM_POST_RESTORE:
spin_lock_irqsave(host-lock, flags);
+ if (mmc_bus_manual_resume(host)) {
+ spin_unlock_irqrestore(host-lock, flags);
+ break;
+ }
host-rescan_disable = 0;
spin_unlock_irqrestore(host-lock, flags);
_mmc_detect_change(host, 0, false);
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 0c44510..859390d 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -1133,6 +1133,10 @@ static int mmc_sd_resume(struct mmc_host *host)
if (!(host-caps MMC_CAP_RUNTIME_RESUME)) {
err = _mmc_sd_resume(host);
+ if ((host-caps2 MMC_CAP2_MANUAL_RESUME) err)
+ mmc_set_bus_resume_policy(host, 1);
+ else
+ mmc_set_bus_resume_policy(host, 0);
pm_runtime_set_active(host-card-dev);
pm_runtime_mark_last_busy(host-card-dev);
}
diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c
index d916c47..2ed6cac 100644
--- a/drivers/mmc/host/sdhci_f_sdh30.c
+++ b/drivers/mmc/host/sdhci_f_sdh30.c
@@ -30,6 +30,12 @@
#include ../core/core.h
#define DRIVER_NAME f_sdh30
+#define RESUME_WAIT_COUNT 100
+#define RESUME_WAIT_TIME 50
+#define RESUME_WAIT_JIFFIESmsecs_to_jiffies(RESUME_DETECT_TIME)
+#define RESUME_DETECT_COUNT16
+#define RESUME_DETECT_TIME 50
+#define RESUME_DETECT_JIFFIES msecs_to_jiffies(RESUME_DETECT_TIME)
struct f_sdhost_priv {
@@ -38,8 +44,59 @@ struct f_sdhost_priv {
int gpio_select_1v8;
u32 vendor_hs200;
struct device *dev;
+ unsigned int quirks;/* Deviations from spec. */
+
+/* retry to detect mmc device when resume */
+#define F_SDH30_QUIRK_RESUME_DETECT_RETRY (10)
+
+ struct workqueue_struct *resume_detect_wq;
+ struct delayed_work resume_detect_work;
+ unsigned intresume_detect_count;
+ unsigned intresume_wait_count;
};
+static void
Re: [RFC PATCH 5/7] mmc: sdhci: host: add new f_sdh30
Hi Arnd, Thanks a lot for your review. I will update it in next version. Best regards, Vincent Yang 2014-06-20 18:00 GMT+08:00 Arnd Bergmann a...@arndb.de: On Friday 20 June 2014 17:35:26 Vincent Yang wrote: +Required properties: +- compatible: fujitsu,f_sdh30 + +Optional properties: +- gpios: Specify gpios for controlling signal level +- clocks: Specify clocks used by SDHCI controller +- clock-names: Specify the clock-names to be used If you want to use clock-names, you have to specify the exact names of the clock input signals used by your device, and the order in which they are listed. For both the clocks and the gpios, you have to specify how many signals there are, and ideally describe what they are used for. In case of a gpio controlling the signal level, it may be better to model this as a gpio-regulator device, depending on how exactly it is used. When posting a DT binding document, please always add devicet...@vger.kernel.org to Cc. Arnd ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] vfio: Fix endianness handling for emulated BARs
On 06/20/2014 01:21 PM, Alex Williamson wrote: On Thu, 2014-06-19 at 13:48 +1000, Alexey Kardashevskiy wrote: On 06/19/2014 11:50 AM, Alexey Kardashevskiy wrote: On 06/19/2014 10:50 AM, Alexey Kardashevskiy wrote: On 06/19/2014 04:35 AM, Alex Williamson wrote: On Wed, 2014-06-18 at 21:36 +1000, Alexey Kardashevskiy wrote: VFIO exposes BARs to user space as a byte stream so userspace can read it using pread()/pwrite(). Since this is a byte stream, VFIO should not do byte swapping and simply return values as it gets them from PCI device. Instead, the existing code assumes that byte stream in read/write is little-endian and it fixes endianness for values which it passes to ioreadXX/iowriteXX helpers. This works for little-endian as PCI is little endian and le32_to_cpu/... are stubs. vfio read32: val = cpu_to_le32(ioread32(io + off)); Where the typical x86 case, ioread32 is: #define ioread32(addr) readl(addr) and readl is: __le32_to_cpu(__raw_readl(addr)); So we do canceling byte swaps, which are both nops on x86, and end up returning device endian, which we assume is little endian. vfio write32 is similar: iowrite32(le32_to_cpu(val), io + off); The implicit cpu_to_le32 of iowrite32() and our explicit swap cancel out, so input data is device endian, which is assumed little. This also works for big endian but rather by an accident: it reads 4 bytes from the stream (@val is big endian), converts to CPU format (which should be big endian) as it was little endian (@val becomes actually little endian) and calls iowrite32() which does not do swapping on big endian system. Really? In arch/powerpc/kernel/iomap.c iowrite32() is just a wrapper around writel(), which seems to use the generic implementation, which does include a cpu_to_le32. Ouch, wrong comment. iowrite32() does swapping. My bad. I also see other big endian archs like parisc doing cpu_to_le32 on iowrite32, so I don't think this statement is true. I imagine it's probably working for you because the swap cancel. This removes byte swapping and makes use ioread32be/iowrite32be (and 16bit versions) on big-endian systems. The be helpers take native endian values and do swapping at the moment of writing to a PCI register using one of store byte-reversed instructions. So now you want iowrite32() on little endian and iowrite32be() on big endian, the former does a cpu_to_le32 (which is a nop on little endian) and the latter does a cpu_to_be32 (which is a nop on big endian)... should we just be using __raw_writel() on both? We can do that too. The beauty of iowrite32be on ppc64 is that it does not swap and write separately, it is implemented via the Store Word Byte-Reverse Indexed X-form single instruction. And some archs (do not know which ones) may add memory barriers in their implementations of ioread/iowrite. __raw_writel is too raw :) There doesn't actually seem to be any change in behavior here, it just eliminates back-to-back byte swaps, which are a nop on x86, but not power, right? Exactly. No dependency for QEMU. How about that: === VFIO exposes BARs to user space as a byte stream so userspace can read it using pread()/pwrite(). Since this is a byte stream, VFIO should not do byte swapping and simply return values as it gets them from PCI device. Instead, the existing code assumes that byte stream in read/write is little-endian and it fixes endianness for values which it passes to ioreadXX/iowriteXX helpers in native format. The IO helpers do swapping again. Since both byte swaps are nops on little-endian host, this works. This also works for big endian but rather by an accident: it reads 4 bytes from the stream (@val is big endian), converts to CPU format (which should be big endian) as it was little endian (and @val becomes actually little endian) and calls iowrite32() which does swapping on big endian system again. So byte swap gets cancelled, __raw_writel() receives a native value and then *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; just does the right thing. I am wrong here, sorry. This is what happens when you watch soccer between 2am and 4am :) This removes byte swaps and makes use of ioread32be/iowrite32be (and 16bit versions) which do explicit byte swapping at the moment of write to a PCI register. PPC64 uses a special Store Word Byte-Reverse Indexed X-form instruction which does swap and store. No swapping is done here if we use ioread32be as it calls in_be32 and that animal does lwz which is simple load from memory. So @val (16/32 bit variable on stack) will have different values on LE and BE but since we do not handle it the host and just memcpy it to the buffer, nothing breaks here. So it should be like this: === VFIO exposes BARs to user space as a byte stream so userspace can read it using pread()/pwrite(). Since this is a byte stream, VFIO should not do byte swapping and simply return
Re: [PATCH v2 2/2] flexcan: add err interrupt for p1010rdb
On Fri, 2014-06-20 at 10:52 +0200, Marc Kleine-Budde wrote: On 06/20/2014 04:01 AM, Zhao Qiang wrote: add err interrupt for p1010rdb into dts. Signed-off-by: Zhao Qiang b45...@freescale.com --- Changes for v2: - add binding documentation update Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 7 +-- arch/powerpc/boot/dts/fsl/p1010si-post.dtsi | 6 -- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 56d6cc3..81929e5 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -10,7 +10,9 @@ Required properties: - fsl,p1010-flexcan - reg : Offset and length of the register set for this device -- interrupts : Interrupt tuple for this device +- interrupts : Interrupt tuple for this device. + The first interrupt is for FlexCAN(Message Buffer and Wake Up) + The second is for error(Shared with IFC, PEX1 and some other device) The second interrupt is optional, at least on ARM we don't need it, please reflect this in the documentation update. The binding also shouldn't specify that the interrupt is shared, much less with specific things. It's not relevant, and may not be universally true. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2 1/2] flexcan: add err_irq handler for flexcan
On Fri, 2014-06-20 at 10:01 +0800, Zhao Qiang wrote:
when flexcan is not physically linked, command 'cantest' will
trigger an err_irq, add err_irq handler for it.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- use a space instead of tab
- use flexcan_poll_state instead of print
drivers/net/can/flexcan.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index f425ec2..7432ba4 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -208,6 +208,7 @@ struct flexcan_priv {
void __iomem *base;
u32 reg_esr;
u32 reg_ctrl_default;
+ unsigned int err_irq;
Why unsigned?
+static irqreturn_t flexcan_err_irq(int irq, void *dev_id)
+{
+ struct net_device *dev = dev_id;
+ struct flexcan_priv *priv = netdev_priv(dev);
+ struct flexcan_regs __iomem *regs = priv-base;
+ u32 reg_ctrl, reg_esr;
+
+ reg_esr = flexcan_read(regs-esr);
+ reg_ctrl = flexcan_read(regs-ctrl);
+ if (reg_esr FLEXCAN_ESR_TX_WRN) {
+ flexcan_write(reg_esr ~FLEXCAN_ESR_TX_WRN, regs-esr);
+ flexcan_write(reg_ctrl ~FLEXCAN_CTRL_ERR_MSK, regs-ctrl);
+ flexcan_poll_state(dev, reg_esr);
+ }
+ return IRQ_HANDLED;
+}
You should only return IRQ_HANDLED if there was something to handle.
@@ -944,6 +962,12 @@ static int flexcan_open(struct net_device *dev)
if (err)
goto out_close;
+ if (priv-err_irq)
+ err = request_irq(priv-err_irq, flexcan_err_irq, IRQF_SHARED,
+ dev-name, dev);
+ if (err)
+ goto out_close;
Is this really a fatal error? And why do you check err outside the if
(priv-err_irq) block? What if some previous code left err non-zero
(either now or after some future code change)?
@@ -1126,6 +1150,10 @@ static int flexcan_probe(struct platform_device *pdev)
if (irq = 0)
return -ENODEV;
+ err_irq = platform_get_irq(pdev, 1);
+ if (err_irq = 0)
+ err_irq = 0;
+
Why is this = 0 check needed?
-Scott
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Re: [RFC PATCH 1/7] mmc: sdhci: add quirk for broken 3.0V support
On Fri, Jun 20, 2014 at 05:35:22PM +0800, Vincent Yang wrote:
This patch defines a quirk for platforms unable
to enable 3.0V support.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
I don't think you need this patch. Instead, you can exclude 3V using the
voltage-ranges = in the device tree.
Thanks,
Anton
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 47055f3..523075f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3069,6 +3069,9 @@ int sdhci_add_host(struct sdhci_host *host)
}
#endif /* CONFIG_REGULATOR */
+ if (host-quirks2 SDHCI_QUIRK2_NO_3_0_V)
+ caps[0] = ~SDHCI_CAN_VDD_300;
+
/*
* According to SD Host Controller spec v3.00, if the Host System
* can afford more than 150mA, Host Driver should set XPC to 1. Also
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 08abe99..cac0958 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_HS200(16)
/* Controller does not support DDR50 */
#define SDHCI_QUIRK2_BROKEN_DDR50(17)
+/* The system physically doesn't support 3.0v, even if the host does */
+#define SDHCI_QUIRK2_NO_3_0_V(18)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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Re: [PATCH] vfio: Fix endianness handling for emulated BARs
On Thu, 2014-06-19 at 21:21 -0600, Alex Williamson wrote:
Working on big endian being an accident may be a matter of perspective
:-)
The comment remains that this patch doesn't actually fix anything except
the overhead on big endian systems doing redundant byte swapping and
maybe the philosophy that vfio regions are little endian.
Yes, that works by accident because technically VFIO is a transport and
thus shouldn't perform any endian swapping of any sort, which remains
the responsibility of the end driver which is the only one to know
whether a given BAR location is a a register or some streaming data
and in the former case whether it's LE or BE (some PCI devices are BE
even ! :-)
But yes, in the end, it works with the dual cancelling swaps and the
overhead of those swaps is probably drowned in the noise of the syscall
overhead.
I'm still not a fan of iowrite vs iowritebe, there must be something we
can use that doesn't have an implicit swap.
Sadly there isn't ... In the old day we didn't even have the be
variant and readl/writel style accessors still don't have them either
for all archs.
There is __raw_readl/writel but here the semantics are much more than
just don't swap, they also don't have memory barriers (which means
they are essentially useless to most drivers unless those are platform
specific drivers which know exactly what they are doing, or in the rare
cases such as accessing a framebuffer which we know never have side
effects).
Calling it iowrite*_native is also an abuse of the namespace.
Next thing we know some common code
will legitimately use that name.
I might make sense to those definitions into a common header. There have
been a handful of cases in the past that wanted that sort of native
byte order MMIOs iirc (though don't ask me for examples, I can't really
remember).
If we do need to define an alias
(which I'd like to avoid) it should be something like vfio_iowrite32.
Thanks,
Cheers,
Ben.
Alex
===
any better?
Suggested-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
drivers/vfio/pci/vfio_pci_rdwr.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c
b/drivers/vfio/pci/vfio_pci_rdwr.c
index 210db24..f363b5a 100644
--- a/drivers/vfio/pci/vfio_pci_rdwr.c
+++ b/drivers/vfio/pci/vfio_pci_rdwr.c
@@ -21,6 +21,18 @@
#include vfio_pci_private.h
+#ifdef __BIG_ENDIAN__
+#define ioread16_native ioread16be
+#define ioread32_native ioread32be
+#define iowrite16_native iowrite16be
+#define iowrite32_native iowrite32be
+#else
+#define ioread16_native ioread16
+#define ioread32_native ioread32
+#define iowrite16_native iowrite16
+#define iowrite32_native iowrite32
+#endif
+
/*
* Read or write from an __iomem region (MMIO or I/O port) with an
excluded
* range which is inaccessible. The excluded range drops writes and
fills
@@ -50,9 +62,9 @@ static ssize_t do_io_rw(void __iomem *io, char
__user *buf,
if (copy_from_user(val, buf, 4))
return -EFAULT;
- iowrite32(le32_to_cpu(val), io + off);
+ iowrite32_native(val, io + off);
} else {
- val = cpu_to_le32(ioread32(io + off));
+ val = ioread32_native(io + off);
if (copy_to_user(buf, val, 4))
return -EFAULT;
@@ -66,9 +78,9 @@ static ssize_t do_io_rw(void __iomem *io, char
__user *buf,
if (copy_from_user(val, buf, 2))
return -EFAULT;
- iowrite16(le16_to_cpu(val), io + off);
+ iowrite16_native(val, io + off);
} else {
- val = cpu_to_le16(ioread16(io + off));
+ val = ioread16_native(io + off);
if (copy_to_user(buf, val, 2))
return -EFAULT;
--
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Re: [PATCH] vfio: Fix endianness handling for emulated BARs
On Sat, 2014-06-21 at 00:14 +1000, Alexey Kardashevskiy wrote: We can still use __raw_writelco, would that be ok? No unless you understand precisely what kind of memory barriers each platform require for these. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] arm64, ia64, ppc, s390, sh, tile, um, x86, mm: Remove default gate area
The core mm code will provide a default gate area based on
FIXADDR_USER_START and FIXADDR_USER_END if
!defined(__HAVE_ARCH_GATE_AREA) defined(AT_SYSINFO_EHDR).
This default is only useful for ia64. arm64, ppc, s390, sh, tile,
64-bit UML, and x86_32 have their own code just to disable it. arm,
32-bit UML, and x86_64 have gate areas, but they have their own
implementations.
This gets rid of the default and moves the code into ia64.
This should save some code on architectures without a gate area: it's
now possible to inline the gate_area functions in the default case.
Signed-off-by: Andy Lutomirski l...@amacapital.net
---
arch/arm64/include/asm/page.h | 3 ---
arch/arm64/kernel/vdso.c | 19 ---
arch/ia64/include/asm/page.h | 2 ++
arch/ia64/mm/init.c| 26 ++
arch/powerpc/include/asm/page.h| 3 ---
arch/powerpc/kernel/vdso.c | 16
arch/s390/include/asm/page.h | 2 --
arch/s390/kernel/vdso.c| 15 ---
arch/sh/include/asm/page.h | 5 -
arch/sh/kernel/vsyscall/vsyscall.c | 15 ---
arch/tile/include/asm/page.h | 6 --
arch/tile/kernel/vdso.c| 15 ---
arch/um/include/asm/page.h | 5 +
arch/x86/include/asm/page.h| 1 -
arch/x86/include/asm/page_64.h | 2 ++
arch/x86/um/asm/elf.h | 1 -
arch/x86/um/mem_64.c | 15 ---
arch/x86/vdso/vdso32-setup.c | 19 +--
include/linux/mm.h | 17 -
mm/memory.c| 38 --
mm/nommu.c | 5 -
21 files changed, 48 insertions(+), 182 deletions(-)
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 46bf666..992710f 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -28,9 +28,6 @@
#define PAGE_SIZE (_AC(1,UL) PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
-/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
-#define __HAVE_ARCH_GATE_AREA 1
-
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARM64_64K_PAGES
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
index 50384fe..f630626 100644
--- a/arch/arm64/kernel/vdso.c
+++ b/arch/arm64/kernel/vdso.c
@@ -187,25 +187,6 @@ const char *arch_vma_name(struct vm_area_struct *vma)
}
/*
- * We define AT_SYSINFO_EHDR, so we need these function stubs to keep
- * Linux happy.
- */
-int in_gate_area_no_mm(unsigned long addr)
-{
- return 0;
-}
-
-int in_gate_area(struct mm_struct *mm, unsigned long addr)
-{
- return 0;
-}
-
-struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
-{
- return NULL;
-}
-
-/*
* Update the vDSO data page to keep in sync with kernel timekeeping.
*/
void update_vsyscall(struct timekeeper *tk)
diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h
index f1e1b2e..1f1bf14 100644
--- a/arch/ia64/include/asm/page.h
+++ b/arch/ia64/include/asm/page.h
@@ -231,4 +231,6 @@ get_order (unsigned long size)
#define PERCPU_ADDR(-PERCPU_PAGE_SIZE)
#define LOAD_OFFSET(KERNEL_START - KERNEL_TR_PAGE_SIZE)
+#define __HAVE_ARCH_GATE_AREA 1
+
#endif /* _ASM_IA64_PAGE_H */
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index 25c3502..35efaa3 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -278,6 +278,32 @@ setup_gate (void)
ia64_patch_gate();
}
+static struct vm_area_struct gate_vma;
+
+static int __init gate_vma_init(void)
+{
+ gate_vma.vm_mm = NULL;
+ gate_vma.vm_start = FIXADDR_USER_START;
+ gate_vma.vm_end = FIXADDR_USER_END;
+ gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
+ gate_vma.vm_page_prot = __P101;
+
+ return 0;
+}
+__initcall(gate_vma_init);
+
+struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
+{
+ return gate_vma;
+}
+
+int in_gate_area_no_mm(unsigned long addr)
+{
+ if ((addr = FIXADDR_USER_START) (addr FIXADDR_USER_END))
+ return 1;
+ return 0;
+}
+
void ia64_mmu_init(void *my_cpu_data)
{
unsigned long pta, impl_va_bits;
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 32e4e21..26fe1ae 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -48,9 +48,6 @@ extern unsigned int HPAGE_SHIFT;
#define HUGE_MAX_HSTATE(MMU_PAGE_COUNT-1)
#endif
-/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
-#define __HAVE_ARCH_GATE_AREA 1
-
/*
* Subtle: (1 PAGE_SHIFT) is an int, not an unsigned long. So if we
* assign PAGE_MASK to a larger type it gets extended the way we want
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index ce74c33..f174351 100644
---
[PATCH 1/2] pcmcia: Remove m8xx_pcmcia driver
This driver doesn't build, and apparently has not built since
arch/ppc was removed in 2008 (when mk_int_int_mask was removed
from asm/irq.h, among other build errors).
A few weeks ago I asked whether anyone was actively maintaining
this code, and got no positive response:
http://patchwork.ozlabs.org/patch/352082/
So, let's remove it.
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Vitaly Bordug v...@kernel.crashing.org
Cc: linux-pcm...@lists.infradead.org
Cc: Paul Bolle pebo...@tiscali.nl
---
arch/powerpc/include/asm/mpc8xx.h|2 -
arch/powerpc/platforms/8xx/m8xx_setup.c |2 -
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 61 --
drivers/pcmcia/Kconfig | 10 -
drivers/pcmcia/Makefile |1 -
drivers/pcmcia/m8xx_pcmcia.c | 1168 --
6 files changed, 1244 deletions(-)
delete mode 100644 drivers/pcmcia/m8xx_pcmcia.c
diff --git a/arch/powerpc/include/asm/mpc8xx.h
b/arch/powerpc/include/asm/mpc8xx.h
index 98f3c4f..8ab22e8 100644
--- a/arch/powerpc/include/asm/mpc8xx.h
+++ b/arch/powerpc/include/asm/mpc8xx.h
@@ -7,6 +7,4 @@
#ifndef __CONFIG_8xx_DEFS
#define __CONFIG_8xx_DEFS
-extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
-
#endif /* __CONFIG_8xx_DEFS */
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c
b/arch/powerpc/platforms/8xx/m8xx_setup.c
index 587a282..623bb43 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -28,8 +28,6 @@
#include mpc8xx.h
-struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
-
extern int cpm_pic_init(void);
extern int cpm_get_irq(void);
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index c126258..3d5e4e1 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -46,61 +46,6 @@
static u32 __iomem *bcsr, *bcsr5;
-#ifdef CONFIG_PCMCIA_M8XX
-static void pcmcia_hw_setup(int slot, int enable)
-{
- if (enable)
- clrbits32(bcsr[1], BCSR1_PCCEN);
- else
- setbits32(bcsr[1], BCSR1_PCCEN);
-}
-
-static int pcmcia_set_voltage(int slot, int vcc, int vpp)
-{
- u32 reg = 0;
-
- switch (vcc) {
- case 0:
- break;
- case 33:
- reg |= BCSR1_PCCVCC0;
- break;
- case 50:
- reg |= BCSR1_PCCVCC1;
- break;
- default:
- return 1;
- }
-
- switch (vpp) {
- case 0:
- break;
- case 33:
- case 50:
- if (vcc == vpp)
- reg |= BCSR1_PCCVPP1;
- else
- return 1;
- break;
- case 120:
- if ((vcc == 33) || (vcc == 50))
- reg |= BCSR1_PCCVPP0;
- else
- return 1;
- default:
- return 1;
- }
-
- /* first, turn off all power */
- clrbits32(bcsr[1], 0x0061);
-
- /* enable new powersettings */
- setbits32(bcsr[1], reg);
-
- return 0;
-}
-#endif
-
struct cpm_pin {
int port, pin, flags;
};
@@ -245,12 +190,6 @@ static void __init mpc885ads_setup_arch(void)
of_detach_node(np);
of_node_put(np);
}
-
-#ifdef CONFIG_PCMCIA_M8XX
- /* Set up board specific hook-ups.*/
- m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
- m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
-#endif
}
static int __init mpc885ads_probe(void)
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 0c657d6..087d7d7 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -144,16 +144,6 @@ config TCIC
Bridge is the name used for the hardware inside your computer that
PCMCIA cards are plugged into. If unsure, say N.
-config PCMCIA_M8XX
- tristate MPC8xx PCMCIA support
- depends on PCCARD PPC 8xx
- select PCCARD_IODYN if PCMCIA != n
- help
- Say Y here to include support for PowerPC 8xx series PCMCIA
- controller.
-
- This driver is also available as a module called m8xx_pcmcia.
-
config PCMCIA_ALCHEMY_DEVBOARD
tristate Alchemy Db/Pb1xxx PCMCIA socket services
depends on MIPS_ALCHEMY PCMCIA
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 7745b51..e62c26b 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_PD6729) += pd6729.o
obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_I82092) += i82092.o
obj-$(CONFIG_TCIC) += tcic.o
-obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
obj-$(CONFIG_PCMCIA_SOC_COMMON)+= soc_common.o
obj-$(CONFIG_PCMCIA_SA11XX_BASE) +=
[PATCH 2/2] powerpc/8xx: Remove empty asm/mpc8xx.h
m8xx_pcmcia_ops was the only thing in this file (other than a comment that describes a usage that doesn't match the file's contents); now that m8xx_pcmcia_ops is gone, remove the empty file. Signed-off-by: Scott Wood scottw...@freescale.com Cc: Pantelis Antoniou pantelis.anton...@gmail.com Cc: Vitaly Bordug v...@kernel.crashing.org Cc: net...@vger.kernel.org --- arch/powerpc/include/asm/fs_pd.h | 1 - arch/powerpc/include/asm/mpc8xx.h| 10 -- arch/powerpc/platforms/8xx/m8xx_setup.c | 1 - arch/powerpc/platforms/8xx/mpc885ads_setup.c | 1 - arch/powerpc/platforms/8xx/tqm8xx_setup.c| 1 - arch/powerpc/sysdev/micropatch.c | 1 - drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 1 - drivers/net/ethernet/freescale/fs_enet/mac-scc.c | 1 - 8 files changed, 17 deletions(-) delete mode 100644 arch/powerpc/include/asm/mpc8xx.h diff --git a/arch/powerpc/include/asm/fs_pd.h b/arch/powerpc/include/asm/fs_pd.h index 9361cd5..f79d6c7 100644 --- a/arch/powerpc/include/asm/fs_pd.h +++ b/arch/powerpc/include/asm/fs_pd.h @@ -28,7 +28,6 @@ #ifdef CONFIG_8xx #include asm/8xx_immap.h -#include asm/mpc8xx.h extern immap_t __iomem *mpc8xx_immr; diff --git a/arch/powerpc/include/asm/mpc8xx.h b/arch/powerpc/include/asm/mpc8xx.h deleted file mode 100644 index 8ab22e8..000 --- a/arch/powerpc/include/asm/mpc8xx.h +++ /dev/null @@ -1,10 +0,0 @@ -/* This is the single file included by all MPC8xx build options. - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8xx configuration, they all include - * this one and the configuration switching is done here. - */ -#ifndef __CONFIG_8xx_DEFS -#define __CONFIG_8xx_DEFS - -#endif /* __CONFIG_8xx_DEFS */ diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index 623bb43..d303774 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -18,7 +18,6 @@ #include linux/fsl_devices.h #include asm/io.h -#include asm/mpc8xx.h #include asm/8xx_immap.h #include asm/prom.h #include asm/fs_pd.h diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c index 3d5e4e1..5921dcb 100644 --- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c +++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c @@ -35,7 +35,6 @@ #include asm/page.h #include asm/processor.h #include asm/time.h -#include asm/mpc8xx.h #include asm/8xx_immap.h #include asm/cpm1.h #include asm/fs_pd.h diff --git a/arch/powerpc/platforms/8xx/tqm8xx_setup.c b/arch/powerpc/platforms/8xx/tqm8xx_setup.c index 251aba8..dda6078 100644 --- a/arch/powerpc/platforms/8xx/tqm8xx_setup.c +++ b/arch/powerpc/platforms/8xx/tqm8xx_setup.c @@ -37,7 +37,6 @@ #include asm/page.h #include asm/processor.h #include asm/time.h -#include asm/mpc8xx.h #include asm/8xx_immap.h #include asm/cpm1.h #include asm/fs_pd.h diff --git a/arch/powerpc/sysdev/micropatch.c b/arch/powerpc/sysdev/micropatch.c index c0bb76e..6727dc5 100644 --- a/arch/powerpc/sysdev/micropatch.c +++ b/arch/powerpc/sysdev/micropatch.c @@ -13,7 +13,6 @@ #include linux/mm.h #include linux/interrupt.h #include asm/irq.h -#include asm/mpc8xx.h #include asm/page.h #include asm/pgtable.h #include asm/8xx_immap.h diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c index fc54134..1eedfba 100644 --- a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c +++ b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c @@ -41,7 +41,6 @@ #ifdef CONFIG_8xx #include asm/8xx_immap.h #include asm/pgtable.h -#include asm/mpc8xx.h #include asm/cpm1.h #endif diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-scc.c b/drivers/net/ethernet/freescale/fs_enet/mac-scc.c index b4bf02f..90b3b19 100644 --- a/drivers/net/ethernet/freescale/fs_enet/mac-scc.c +++ b/drivers/net/ethernet/freescale/fs_enet/mac-scc.c @@ -40,7 +40,6 @@ #ifdef CONFIG_8xx #include asm/8xx_immap.h #include asm/pgtable.h -#include asm/mpc8xx.h #include asm/cpm1.h #endif -- 1.9.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/8xx: Remove empty asm/mpc8xx.h
From: Scott Wood scottw...@freescale.com Date: Fri, 20 Jun 2014 20:02:07 -0500 m8xx_pcmcia_ops was the only thing in this file (other than a comment that describes a usage that doesn't match the file's contents); now that m8xx_pcmcia_ops is gone, remove the empty file. Signed-off-by: Scott Wood scottw...@freescale.com For networking bits: Acked-by: David S. Miller da...@davemloft.net ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 1/7] mmc: sdhci: add quirk for broken 3.0V support
Hi Anton,
Thanks a lot for your review.
I will update it in next version.
Best regards,
Vincent Yang
2014-06-21 4:26 GMT+08:00 Anton Vorontsov an...@enomsg.org:
On Fri, Jun 20, 2014 at 05:35:22PM +0800, Vincent Yang wrote:
This patch defines a quirk for platforms unable
to enable 3.0V support.
It is a preparation and will be used by Fujitsu
SDHCI controller f_sdh30 driver.
Signed-off-by: Vincent Yang vincent.y...@tw.fujitsu.com
I don't think you need this patch. Instead, you can exclude 3V using the
voltage-ranges = in the device tree.
Thanks,
Anton
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 47055f3..523075f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3069,6 +3069,9 @@ int sdhci_add_host(struct sdhci_host *host)
}
#endif /* CONFIG_REGULATOR */
+ if (host-quirks2 SDHCI_QUIRK2_NO_3_0_V)
+ caps[0] = ~SDHCI_CAN_VDD_300;
+
/*
* According to SD Host Controller spec v3.00, if the Host System
* can afford more than 150mA, Host Driver should set XPC to 1. Also
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 08abe99..cac0958 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_HS200(16)
/* Controller does not support DDR50 */
#define SDHCI_QUIRK2_BROKEN_DDR50(17)
+/* The system physically doesn't support 3.0v, even if the host does */
+#define SDHCI_QUIRK2_NO_3_0_V(18)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.0
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[PATCH] trivial: drivers/macintosh/smu.c: Fix closing brace followed by if
A closing brace followed by if is almost certainly a mistake. Maybe
else if was meant, but in this case it doesn't really matter.
Signed-off-by: Rasmus Villemoes li...@rasmusvillemoes.dk
---
drivers/macintosh/smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c
index 23b4a3b..4eab93a 100644
--- a/drivers/macintosh/smu.c
+++ b/drivers/macintosh/smu.c
@@ -1257,7 +1257,8 @@ static unsigned int smu_fpoll(struct file *file,
poll_table *wait)
if (pp-busy pp-cmd.status != 1)
mask |= POLLIN;
spin_unlock_irqrestore(pp-lock, flags);
- } if (pp-mode == smu_file_events) {
+ }
+ if (pp-mode == smu_file_events) {
/* Not yet implemented */
}
return mask;
--
1.9.2
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