Re: [PATCH v6 35/37] cxlflash: Fix to avoid corrupting port selection mask

[Manoj Kumar]

Acked-by: Manoj Kumar 

On 10/21/2015 3:16 PM, Matthew R. Ochs wrote:

The port selection mask of a LUN can be corrupted when the manage LUN
ioctl (DK_CXLFLASH_MANAGE_LUN) is issued more than once for any device.


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Re: [PATCH v6 37/37] cxlflash: Fix to avoid bypassing context cleanup

[Manoj Kumar]

Acked-by: Manoj Kumar 

On 10/21/2015 3:16 PM, Matthew R. Ochs wrote:

Contexts may be skipped over for cleanup in situations where contention
for the adapter's table-list mutex is experienced in the presence of a
signal during the execution of the release handler.


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Re: [PATCH V4 00/31] powerpc/mm: Update page table format for book3s 64

[Denis Kirjanov]

On 10/17/15, Aneesh Kumar K.V  wrote:
> Hi All,
>
> This patch series attempt to update book3s 64 linux page table format to
> make it more flexible. Our current pte format is very restrictive and we
> overload multiple pte bits. This is due to the non-availability of free bits
> in pte_t. We use pte_t to track the validity of 4K subpages. This patch
> series free up pte_t of 11 bits by moving 4K subpage tracking to the
> lower half of PTE page. The pte format is updated such that we have a
> better method for identifying a pte entry at pmd level. This will also
> enable
> us to implement hugetlb migration(not yet done in this series).

Hi, what tree does this apply to?

>
> Before making the changes to the pte format, I am splitting the
> pte header definition such that we now have the below layout for headers
>
> book3s
>32
>  hash.h pgtable.h
>64
>  hash.h  pgtable.h hash-4k.h hash-64k.h
> booke
>   32
>  pgtable.h pte-40x.h pte-44x.h pte-8xx.h pte-fsl-booke.h
>   64
> pgtable-4k.h  pgtable-64k.h  pgtable.h
>
> I have done the header split such that booke headers and modified to the
> minimum so as to avoid
> causing breakage in booke.
>
> The patch series can also be found at
> https://github.com/kvaneesh/linux.git book3s-pte-format
> https://github.com/kvaneesh/linux/commits/book3s-pte-format
>
>
> Performance numbers with and without patch series.
>
> Path length __hash_page_4k
> with patch: 196
> without patch: 142
>
> Path length __hash_page_64k
> with patch: 219
> without patch: 154
>
> But even if we have a path lengh increase of around 50 instructions. We
> don't see
> the impact when running workload. I tried the kernelbuild test.
>
> With THP enabled (which is default) we see an improvement. I haven't fully
> looked at
> the reason. This could be due to reduced contention of ptl lock.
> __hash_thp_page is
> already a C code.
>
> make -j64 vmlinux modules
> With fix:
> -
> real1m35.509s
> user56m8.565s
> sys 4m34.973s
>
> real1m32.174s
> user57m2.336s
> sys 4m39.142s
>
> Without fix:
> ---
> real1m37.703s
> user58m50.783s
> sys 7m52.440s
>
> real1m37.890s
> user57m55.445s
> sys 7m50.501s
>
> THP disabled:
>
> make -j64 vmlinux modules
> With fix:
> -
> real1m37.197s
> user58m28.672s
> sys 7m58.188s
>
> real1m44.638s
> user58m37.551s
> sys 7m53.960s
>
> Without fix:
> 
> real1m41.224s
> user58m46.944s
> sys 7m49.714s
>
> real1m42.585s
> user59m14.019s
> sys 7m52.714s
>
>
> Changes from V3:
> * Add missing #define pgprot_*
> * Add Acked-by
>
> Changes from V2:
> * rebase to -next for powerpc tree
>
> Changes from V1:
> 1) Build fix with STRICT_MM_TYPES enabled
> 2) pte_mkwrite fix for nohash
> 3) rebase to latest linus tree.
>
>
> Aneesh Kumar K.V (31):
>   powerpc/mm: move pte headers to book3s directory
>   powerpc/mm: move pte headers to book3s directory (part 2)
>   powerpc/mm: make a separate copy for book3s
>   powerpc/mm: make a separate copy for book3s (part 2)
>   powerpc/mm: Move hash specific pte width and other defines to book3s
>   powerpc/mm: Delete booke bits from book3s
>   powerpc/mm: Don't have generic headers introduce functions touching
> pte bits
>   powerpc/mm: Drop pte-common.h from BOOK3S 64
>   powerpc/mm: Don't use pte_val as lvalue
>   powerpc/mm: Don't use pmd_val,pud_val and pgd_val as lvalue
>   powerpc/mm: Move hash64 PTE bits from book3s/64/pgtable.h to hash.h
>   powerpc/mm: Move PTE bits from generic functions to hash64 functions.
>   powerpc/booke: Move nohash headers (part 1)
>   powerpc/booke: Move nohash headers (part 2)
>   powerpc/booke: Move nohash headers (part 3)
>   powerpc/booke: Move nohash headers (part 4)
>   powerpc/booke: Move nohash headers (part 5)
>   powerpc/mm: Increase the pte frag size.
>   powerpc/mm: Convert 4k hash insert to C
>   powerpc/mm: update __real_pte to take address as argument
>   powerpc/mm: make pte page hash index slot 8 bits
>   powerpc/mm: Don't track subpage valid bit in pte_t
>   powerpc/mm: Increase the width of #define
>   powerpc/mm: Convert __hash_page_64K to C
>   powerpc/mm: Convert 4k insert from asm to C
>   powerpc/mm: Remove the dependency on pte bit position in asm code
>   powerpc/mm: Add helper for converting pte bit to hpte bits
>   powerpc/mm: Move WIMG update to helper.
>   powerpc/mm: Move hugetlb related headers
>   powerpc/mm: Move THP headers around
>   powerpc/mm: Add a _PAGE_PTE bit
>
>  .../include/asm/{pte-hash32.h => book3s/32/hash.h} |6 +-
>  .../asm/{pgtable-ppc32.h => book3s/32/pgtable.h}   |  286 --
>  .../{pgtable-ppc64-4k.h => book3s/64/hash-4k.h}|   58 +-
>  arch/powerpc/include/asm/book3s/64/hash-64k.h  |  296 ++
>  arch/powerpc/include/asm/book3s/64/hash.h  |  530 +++
>  arch/powerpc/include/asm/book3s/64/pgtable.h   |  266 ++
>  

Re: Time to remove platforms/cell?

[Geoff Levand]

Hi,

On Fri, 2015-10-09 at 23:13 +0200, Marc Dietrich wrote:
> Am Freitag, 9. Oktober 2015, 10:45:42 schrieb Geoff Levand:
> > With the 4.2-rc4 kernel, kexec seems to work when CONFIG_SPU_FS=n. 
> >  I
> > have not tried with petitboot release white-09.09.01-15.56 yet though.
> 
> I guess you mean 4.3-rc4. Still no luck with CONFIG_SPU_FS=n. No output even 
> with direct calling kexec. Can you put a working kernel/initrd to some place 
> so I can try this?

I did some more work on this, but still did not find out what the problem
is.  Kexec from 4.3 -> 4.3 works, but with the white-09.09.01-15.56
petitboot (2.6.30.9) -> 4.3 gets a kernel panic:

 -> early_setup(), dt_ptr: 0x7fff000
Kernel panic - not syncing: BUG: Failed verifying flat device tree, bad version?

I'll look at it some more as I find time.

-Geoff
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Re: [PATCH v6 36/37] cxlflash: Fix to avoid lock instrumentation rejection

[Manoj Kumar]

Acked-by: Manoj Kumar 

On 10/21/2015 3:16 PM, Matthew R. Ochs wrote:

When running with lock instrumentation (e.g. lockdep), some of the
instrumentation can become disabled at probe time for a cxlflash
adapter. This is due to a missing lock registration for the tmf_slock.

The fix is to call spin_lock_init() for the tmf_slock during probe.


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Re: [RFC PATCH 0/8] clk: qoriq: Move chip-specific knowledge into driver

[Michael Turquette]

Quoting Scott Wood (2015-10-09 16:57:44)
> On Thu, 2015-10-01 at 19:26 -0500, Scott Wood wrote:
> > [Resending to updated e-mail address]
> > 
> > On Tue, 2015-08-11 at 11:25 -0700, Michael Turquette wrote:
> > > Hi Scott,
> > > 
> > > Quoting Scott Wood (2015-06-18 19:49:10)
> > > > The existing device tree bindings are error-prone and inflexible. 
> > > > Correct the mistake by moving the knowledge into the driver, which
> > > > has more flexibility in describing the quirks of each chip.  This leaves
> > > > the device tree to its proper role of identifying a programming 
> > > > interface
> > > > rather than describing its individual registers.
> > > 
> > > Sorry for not responding to this one sooner. Fell through the cracks.
> > > 
> > > All of the changes to drives/clk/clk-qoriq.c look great to me. I assume
> > > you need to keep all of these patches together and want to the take
> > > through the freescale tree? If so feel free to add,
> > > 
> > > Acked-by: Michael Turquette 
> > 
> > Is the ack still valid for the v3 patchset?

Yes. Looks Stephen beat me to it though.

Regards,
Mike

> 
> ping
> 
> -Scott
> 
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Re: [PATCH tip/locking/core v4 1/6] powerpc: atomic: Make *xchg and *cmpxchg a full barrier

[Boqun Feng]

On Wed, Oct 21, 2015 at 09:48:25PM +0200, Peter Zijlstra wrote:
> On Wed, Oct 21, 2015 at 12:35:23PM -0700, Paul E. McKenney wrote:
> > > > > > I ask this because I recall Peter once bought up a discussion:
> > > > > > 
> > > > > > https://lkml.org/lkml/2015/8/26/596
> 
> > > So a full barrier on one side of these operations is enough, I think.
> > > IOW, there is no need to strengthen these operations.
> > 
> > Do we need to also worry about other futex use cases?
> 
> Worry, always!
> 
> But yes, there is one more specific usecase, which is that of a
> condition variable.
> 
> When we go sleep on a futex, we might want to assume visibility of the
> stores done by the thread that woke us by the time we wake up.
> 

But the thing is futex atomics in PPC are already RELEASE(pc)+ACQUIRE
and imply a full barrier, is an RELEASE(sc) semantics really needed
here?

Further more, is this condition variable visibility guaranteed by other
part of futex? Because in futex_wake_op:

futex_wake_op()
  ...
  double_unlock_hb(hb1, hb2);  <- RELEASE(pc) barrier here.
  wake_up_q(_q);

and in futex_wait():

futex_wait()
  ...
  futex_wait_queue_me(hb, , to); <- schedule() here
  ...
  unqueue_me()
drop_futex_key_refs(>key);
iput()/mmdrop(); <- a full barrier
  

The RELEASE(pc) barrier pairs with the full barrier, therefore the
userspace wakee can observe the condition variable modification.

> 
> 
> And.. aside from the thoughts I outlined in the email referenced above,
> there is always the chance people accidentally rely on the strong
> ordering on their x86 CPU and find things come apart when ran on their
> ARM/MIPS/etc..
> 
> There are a fair number of people who use the raw futex call and we have
> 0 visibility into many of them. The assumed and accidental ordering
> guarantees will forever remain a mystery.
> 

Understood. That's truely a potential problem. Considering not all the
architectures imply a full barrier at user<->kernel boundries, maybe we
can use one bit in the opcode of the futex system call to indicate
whether userspace treats futex as fully ordered. Like:

#define FUTEX_ORDER_SEQ_CST  0
#define FUTEX_ORDER_RELAXED  64 (bit 7 and bit 8 are already used)

Therefore all existing code will run with a strong ordering version of
futex(of course, we need to check and modify kernel code first to
guarantee that), and if userspace code uses FUTEX_ORDER_RELAXED, it must
not rely on futex() for the strong ordering, and should add memory
barriers itself if necessary.

Regards,
Boqun


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Re: [PATCH V7 0/6] Redesign SR-IOV on PowerNV

[Gavin Shan]

On Thu, Oct 22, 2015 at 09:22:13AM +0800, Wei Yang wrote:
>In original design, it tries to group VFs to enable more number of VFs in the
>system, when VF BAR is bigger than 64MB. This design has a flaw in which one
>error on a VF will interfere other VFs in the same group.
>
>This patch series change this design by using M64 BAR in Single PE mode to
>cover only one VF BAR. By doing so, it gives absolute isolation between VFs.
>

This series looks good to me, no obvious problems found. By the way, The
VF EEH patchset has been there for some time, could you respin it on top
of this series and resend that after retesting?

In case Michael need the ack as mentioned last time in IRC:

Acked-by: Gavin Shan 

>v7:
>   * clear res->flags when truncating the IOV BAR
>v6:
>   * add the minimum size check when M64 BAR is in Single PE mode
>   * truncate IOV BAR when powernv can't handle it
>v5:
>   * rebase on top of v4.2, with commit 68230242cdb "net/mlx4_core: Add port
> attribute when tracking counters" reverted
>   * add some reason in change log of Patch 1
>   * make the pnv_pci_iov_resource_alignment() more easy to read
>   * initialize pe_num_map[] just after it is allocated
>   * test ssh from guest to host via VF passed and then shutdown the guest
>   * no code change
>v4:
>   * rebase the code on top of v4.2-rc7
>   * switch back to use the dynamic version of pe_num_map and m64_map
>   * split the memory allocation and PE assignment of pe_num_map to make it
> more easy to read
>   * check pe_num_map value before free PE.
>   * add the rename reason for pe_num_map and m64_map in change log
>v3:
>   * return -ENOSPC when a VF has non-64bit prefetchable BAR
>   * rename offset to pe_num_map and define it staticly
>   * change commit log based on comments
>   * define m64_map staticly
>v2:
>   * clean up iov bar alignment calculation
>   * change m64s to m64_bars
>   * add a field to represent M64 Single PE mode will be used
>   * change m64_wins to m64_map
>   * calculate the gate instead of hard coded
>   * dynamically allocate m64_map
>   * dynamically allocate PE#
>   * add a case to calculate iov bar alignment when M64 Single PE is used
>   * when M64 Single PE is used, compare num_vfs with M64 BAR available number 
> in system at first
>
>
>Wei Yang (6):
>  powerpc/powernv: don't enable SRIOV when VF BAR has non
>64bit-prefetchable BAR
>  powerpc/powernv: simplify the calculation of iov resource alignment
>  powerpc/powernv: use one M64 BAR in Single PE mode for one VF BAR
>  powerpc/powernv: replace the hard coded boundary with gate
>  powerpc/powernv: boundary the total VF BAR size instead of the
>individual one
>  powerpc/powernv: allocate sparse PE# when using M64 BAR in Single PE
>mode
>
> arch/powerpc/include/asm/pci-bridge.h |   7 +-
> arch/powerpc/platforms/powernv/pci-ioda.c | 347 --
> 2 files changed, 192 insertions(+), 162 deletions(-)
>
>-- 
>2.5.0
>

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Re: [PATCH v6 22/22] of/platform: Defer probes of registered devices

[Scott Wood]

On Thu, 2015-10-22 at 15:04 +0200, Tomeu Vizoso wrote:
> On 22 October 2015 at 00:51, Scott Wood  wrote:
> > On Wed, 2015-10-21 at 08:44 -0500, Rob Herring wrote:
> > > On Wed, Oct 21, 2015 at 12:54 AM, Scott Wood 
> > > wrote:
> > > > On Mon, 2015-09-21 at 16:03 +0200, Tomeu Vizoso wrote:
> > > > > Instead of trying to match and probe platform and AMBA devices right
> > > > > after each is registered, delay their probes until 
> > > > > device_initcall_sync.
> > > > > 
> > > > > This means that devices will start probing once all built-in drivers
> > > > > have registered, and after all platform and AMBA devices from the DT
> > > > > have been registered already.
> > > > > 
> > > > > This allows us to prevent deferred probes by probing dependencies on
> > > > > demand.
> > > > > 
> > > > > Signed-off-by: Tomeu Vizoso 
> > > > > ---
> > > > > 
> > > > > Changes in v4:
> > > > > - Also defer probes of AMBA devices registered from the DT as they 
> > > > > can
> > > > >   also request resources.
> > > > > 
> > > > >  drivers/of/platform.c | 11 ---
> > > > >  1 file changed, 8 insertions(+), 3 deletions(-)
> > > > 
> > > > This breaks arch/powerpc/sysdev/fsl_pci.c.  The PCI bus is an OF 
> > > > platform
> > > > device, and it must be probed before pcibios_init() which is a
> > > > subsys_initcall(), or else the PCI bus never gets scanned.
> > > 
> > > Thanks for the report. This is probably getting dropped, but it could
> > > be disabled for PPC.
> > 
> > I don't think that adding another arbitrary arch difference would be the
> > right solution.
> 
> I think Rob meant temporarily disable it while things get fixed. At
> least, 

So, what is the permanent fix for the swiotlb issue (or more generally, the 
inability to have a late_initcall that runs after non-module, non-hotplug 
platform devices have been probed)?

> I don't see any reason why PPC wouldn't benefit from this
> series.

It's not clear to me what the benefit of this is at all, much less for PPC.   
What is the fundamental problem with deferred probes?  In the cover letter 
you say this change saves 2.3 seconds, but where is that time being consumed? 
 Are the drivers taking too long in their probe function trying to initialize 
and then deferring, rather than checking for dependencies up front?  Or are 
there really so many devices and such a pessimal ordering that most of the 
time is spent iterating through and reordering the list, with each defer 
happening quickly?

Even if something different does need to be done at this level, forcing all 
OF platform devices to be probed at the late_initcall level seems quite 
intrusive.  You limited it to OF because people complained that other things 
will break.  Things still broke.  Surely there's a better way to address the 
problem.  Can't the delay be requested by drivers that might otherwise need 
to defer (which could be done incrementally, focusing on the worst 
performance problems), rather than enabling it for everything?

-Scott


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[PATCH] ASoC: fsl: Use #ifdef instead of #if for CONFIG_PM_SLEEP

[Nicolin Chen]

Change them to #ifdef as CONFIG_PM_SLEEP might not be defined at all.

Reported-by: kbuild test robot 
Signed-off-by: Nicolin Chen 
---
 sound/soc/fsl/fsl_esai.c | 2 +-
 sound/soc/fsl/fsl_sai.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index aab675a..59f234e 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -900,7 +900,7 @@ static const struct of_device_id fsl_esai_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
 
-#if CONFIG_PM_SLEEP
+#ifdef CONFIG_PM_SLEEP
 static int fsl_esai_suspend(struct device *dev)
 {
struct fsl_esai *esai = dev_get_drvdata(dev);
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index f652f2e..15173e9 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -807,7 +807,7 @@ static const struct of_device_id fsl_sai_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
 
-#if CONFIG_PM_SLEEP
+#ifdef CONFIG_PM_SLEEP
 static int fsl_sai_suspend(struct device *dev)
 {
struct fsl_sai *sai = dev_get_drvdata(dev);
-- 
1.9.1

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Re: [PATCH] powerpc: Introduce the use of the managed version of kzalloc

[Anatolij Gustschin]

On Tue, 27 May 2014 01:51:31 +0530
Himangi Saraogi  wrote:
...
> 
> Signed-off-by: Himangi Saraogi 
> Acked-by: Julia Lawall 
> ---
> Not compile tested
>  arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)

applied to mpc5xxx/next.

Thanks,

Anatolij
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Re: [PATCH] powerpc: mpc512x: drop bogus and unused psc register bit definitions

[Anatolij Gustschin]

On Tue, 21 Jul 2015 09:21:13 +0200
Uwe Kleine-König  wrote:

> These were introduced in commit 25ae3a0739c6 ("[POWERPC] mpc512x: Add
> MPC512x PSC support to MPC52xx psc driver") and never used. Moreover
> according to the datasheet[1] MEMERROR is bit 25 (0x40) and ORERR is
> bit 27 (0x10).
> 
> [1] MPC5125RM Rev. 2; 11/2009
> 
> Signed-off-by: Uwe Kleine-König 
> ---
>  arch/powerpc/include/asm/mpc52xx_psc.h | 2 --
>  1 file changed, 2 deletions(-)

applied to mpc5xxx/next.

Thanks,

Anatolij
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Re: [PATCH v6 36/37] cxlflash: Fix to avoid lock instrumentation rejection

[Andrew Donnellan]

On 22/10/15 07:16, Matthew R. Ochs wrote:

When running with lock instrumentation (e.g. lockdep), some of the
instrumentation can become disabled at probe time for a cxlflash
adapter. This is due to a missing lock registration for the tmf_slock.

The fix is to call spin_lock_init() for the tmf_slock during probe.

Signed-off-by: Matthew R. Ochs 


Reviewed-by: Andrew Donnellan 

--
Andrew Donnellan  Software Engineer, OzLabs
andrew.donnel...@au1.ibm.com  Australia Development Lab, Canberra
+61 2 6201 8874 (work)IBM Australia Limited

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Re: [PATCH 9/9] powerpc: optimise csum_partial() call when len is constant

[Scott Wood]

On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> csum_partial is often called for small fixed length packets
> for which it is suboptimal to use the generic csum_partial()
> function.
> 
> For instance, in my configuration, I got:
> * One place calling it with constant len 4
> * Seven places calling it with constant len 8
> * Three places calling it with constant len 14
> * One place calling it with constant len 20
> * One place calling it with constant len 24
> * One place calling it with constant len 32
> 
> This patch renames csum_partial() to __csum_partial() and
> implements csum_partial() as a wrapper inline function which
> * uses csum_add() for small 16bits multiple constant length
> * uses ip_fast_csum() for other 32bits multiple constant
> * uses __csum_partial() in all other cases
> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/include/asm/checksum.h | 80 ++
> ---
>  arch/powerpc/lib/checksum_32.S  |  4 +-
>  arch/powerpc/lib/checksum_64.S  |  4 +-
>  arch/powerpc/lib/ppc_ksyms.c|  2 +-
>  4 files changed, 62 insertions(+), 28 deletions(-)

Benchmarks?

-Scott

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[GIT PULL] Please pull powerpc/linux.git powerpc-4.3-5 tag

[Michael Ellerman]

Hi Linus,

Please pull some more powerpc fixes for 4.3:

The following changes since commit abb39bc792aa8e9143e78a39ec13d7de1391f4b4:

  selftests/powerpc: Fix build failure of load_unaligned_zeropad test 
(2015-10-13 15:08:37 +1100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git 
tags/powerpc-4.3-5

for you to fetch changes up to 8832317f662c06f5c06e638f57bfe89a71c9b266:

  powerpc/rtas: Validate rtas.entry before calling enter_rtas() (2015-10-22 
11:03:25 +1100)


powerpc fixes for 4.3 #4

 - Revert "Use the POWER8 Micro Partition Prefetch Engine in KVM HV on POWER8" 
from Paul
 - Handle irq_happened flag correctly in off-line loop from Paul
 - Validate rtas.entry before calling enter_rtas() from Vasant


Paul Mackerras (2):
  powerpc: Revert "Use the POWER8 Micro Partition Prefetch Engine in KVM HV 
on POWER8"
  powerpc/powernv: Handle irq_happened flag correctly in off-line loop

Vasant Hegde (1):
  powerpc/rtas: Validate rtas.entry before calling enter_rtas()

 arch/powerpc/include/asm/cache.h  |  7 -
 arch/powerpc/include/asm/kvm_host.h   |  2 --
 arch/powerpc/include/asm/ppc-opcode.h | 17 ---
 arch/powerpc/include/asm/reg.h|  1 -
 arch/powerpc/kernel/rtas.c|  3 ++
 arch/powerpc/kvm/book3s_hv.c  | 55 +--
 arch/powerpc/platforms/powernv/smp.c  | 29 ++
 7 files changed, 28 insertions(+), 86 deletions(-)


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Re: [PATCH v6 16/37] cxlflash: Fix async interrupt bypass logic

[Andrew Donnellan]

On 22/10/15 07:13, Matthew R. Ochs wrote:

A bug was introduced earlier in the development cycle when cleaning
up logic statements. Instead of skipping bits that are not set, set
bits are skipped, causing async interrupts to not be handled correctly.

To fix, simply add back in the proper evaluation for an unset bit.

Signed-off-by: Matthew R. Ochs 
Signed-off-by: Manoj N. Kumar 
Reviewed-by: Brian King 


Reviewed-by: Andrew Donnellan 

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andrew.donnel...@au1.ibm.com  Australia Development Lab, Canberra
+61 2 6201 8874 (work)IBM Australia Limited

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Re: [PATCH v6 35/37] cxlflash: Fix to avoid corrupting port selection mask

[Andrew Donnellan]

On 22/10/15 07:16, Matthew R. Ochs wrote:

The port selection mask of a LUN can be corrupted when the manage LUN
ioctl (DK_CXLFLASH_MANAGE_LUN) is issued more than once for any device.


> ...


Signed-off-by: Matthew R. Ochs 


Reviewed-by: Andrew Donnellan 

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Re: Time to remove platforms/cell?

[Michael Ellerman]

On Thu, 2015-10-22 at 12:15 -0700, Geoff Levand wrote:

> Hi,
> 
> On Fri, 2015-10-09 at 23:13 +0200, Marc Dietrich wrote:

> > Am Freitag, 9. Oktober 2015, 10:45:42 schrieb Geoff Levand:

> > > With the 4.2-rc4 kernel, kexec seems to work when CONFIG_SPU_FS=n. 
> > >  I
> > > have not tried with petitboot release white-09.09.01-15.56 yet though.
> > 
> > I guess you mean 4.3-rc4. Still no luck with CONFIG_SPU_FS=n. No output 
> > even 
> > with direct calling kexec. Can you put a working kernel/initrd to some 
> > place 
> > so I can try this?
> 
> I did some more work on this, but still did not find out what the problem
> is.  Kexec from 4.3 -> 4.3 works, but with the white-09.09.01-15.56
> petitboot (2.6.30.9) -> 4.3 gets a kernel panic:
> 
>  -> early_setup(), dt_ptr: 0x7fff000
> Kernel panic - not syncing: BUG: Failed verifying flat device tree, bad 
> version?
> 
> I'll look at it some more as I find time.

That says that the device tree firmware gave you (ie. from kexec), is using an
old version of the device tree format.

I can't remember off the top of my head which version you need, but basically
newer kernels require a newer device tree format. So your kexec might be too
old?

cheers

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Re: [PATCH v12 5/6] QE: use subsys_initcall to init qe

[Scott Wood]

On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> diff --git a/arch/powerpc/sysdev/qe_lib/qe.c > 
> b/arch/powerpc/sysdev/qe_lib/qe.c
> index c2518cd..3f9f596 100644
> --- a/arch/powerpc/sysdev/qe_lib/qe.c
> +++ b/arch/powerpc/sysdev/qe_lib/qe.c
> @@ -671,6 +671,21 @@ unsigned int qe_get_num_of_snums(void)
>  }
>  EXPORT_SYMBOL(qe_get_num_of_snums);
>  
> +static int __init qe_init(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,qe");
> + if (!np) {
> + pr_err("%s: Could not find Quicc Engine node\n", __func__);
> + return -ENODEV;
> + }
> + qe_reset();
> + of_node_put(np);
> + return 0;
> +}
> +subsys_initcall(qe_init);

Do not print an error, just because QE is not present.

-Scott

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Re: [PATCH v12 3/6] CPM/QE: use genalloc to manage CPM/QE muram

[Scott Wood]

On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> Use genalloc to manage CPM/QE muram instead of rheap.
> 
> Signed-off-by: Zhao Qiang 
> ---
> Changes for v9:
>   - splitted from patch 3/5, modify cpm muram management functions.
> Changes for v10:
>   - modify cpm muram first, then move to qe_common
>   - modify commit.
> Changes for v11:
>   - factor out the common alloc code
>   - modify min_alloc_order to zero for cpm_muram_alloc_fixed.
> Changes for v12:
>   - Nil 
> 
>  arch/powerpc/include/asm/cpm.h   |   1 +
>  arch/powerpc/platforms/Kconfig   |   2 +-
>  arch/powerpc/sysdev/cpm_common.c | 129 +++-
> ---
>  3 files changed, 93 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
> index 4398a6c..0e1ac3f 100644
> --- a/arch/powerpc/include/asm/cpm.h
> +++ b/arch/powerpc/include/asm/cpm.h
> @@ -161,6 +161,7 @@ int cpm_muram_init(void);
>  unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
>  int cpm_muram_free(unsigned long offset);
>  unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long 
> size);
> +unsigned long cpm_muram_alloc_common(unsigned long size, void *data);
>  void __iomem *cpm_muram_addr(unsigned long offset);
>  unsigned long cpm_muram_offset(void __iomem *addr);
>  dma_addr_t cpm_muram_dma(void __iomem *addr);
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
> index b7f9c40..01626be7 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -275,7 +275,7 @@ config TAU_AVERAGE
>  config QUICC_ENGINE
>   bool "Freescale QUICC Engine (QE) Support"
>   depends on FSL_SOC && PPC32
> - select PPC_LIB_RHEAP
> + select GENERIC_ALLOCATOR
>   select CRC32
>   help
> The QUICC Engine (QE) is a new generation of communications
> diff --git a/arch/powerpc/sysdev/cpm_common.c 
> b/arch/powerpc/sysdev/cpm_common.c
> index 4f78695..ff47072 100644
> --- a/arch/powerpc/sysdev/cpm_common.c
> +++ b/arch/powerpc/sysdev/cpm_common.c
> @@ -17,6 +17,7 @@
>   * published by the Free Software Foundation.
>   */
>  
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -27,7 +28,6 @@
>  
>  #include 
>  #include 
> -#include 
>  #include 
>  
>  #include 
> @@ -65,14 +65,22 @@ void __init udbg_init_cpm(void)
>  }
>  #endif
>  
> +static struct gen_pool *muram_pool;
>  static spinlock_t cpm_muram_lock;
> -static rh_block_t cpm_boot_muram_rh_block[16];
> -static rh_info_t cpm_muram_info;
>  static u8 __iomem *muram_vbase;
>  static phys_addr_t muram_pbase;
>  
> -/* Max address size we deal with */
> +struct muram_block {
> + struct list_head head;
> + unsigned long start;
> + int size;
> +};
> +
> +static LIST_HEAD(muram_block_list);
> +
> +/* max address size we deal with */
>  #define OF_MAX_ADDR_CELLS4
> +#define GENPOOL_OFFSET   (4096 * 8)
>  
>  int cpm_muram_init(void)
>  {
> @@ -87,50 +95,52 @@ int cpm_muram_init(void)
>   return 0;
>  
>   spin_lock_init(_muram_lock);
> - /* initialize the info header */
> - rh_init(_muram_info, 1,
> - sizeof(cpm_boot_muram_rh_block) /
> - sizeof(cpm_boot_muram_rh_block[0]),
> - cpm_boot_muram_rh_block);
> -
>   np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
>   if (!np) {
>   /* try legacy bindings */
>   np = of_find_node_by_name(NULL, "data-only");
>   if (!np) {
> - printk(KERN_ERR "Cannot find CPM muram data node");
> + pr_err("Cannot find CPM muram data node");
>   ret = -ENODEV;
> - goto out;
> + goto out_muram;
>   }
>   }
>  
> + muram_pool = gen_pool_create(0, -1);
>   muram_pbase = of_translate_address(np, zero);
>   if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
> - printk(KERN_ERR "Cannot translate zero through CPM muram node");
> + pr_err("Cannot translate zero through CPM muram node");
>   ret = -ENODEV;
> - goto out;
> + goto out_pool;
>   }
>  
>   while (of_address_to_resource(np, i++, ) == 0) {
>   if (r.end > max)
>   max = r.end;
> + ret = gen_pool_add(muram_pool, r.start - muram_pbase +
> +GENPOOL_OFFSET, resource_size(), -1);
> + if (ret) {
> + pr_err("QE: couldn't add muram to pool!\n");
> + goto out_pool;
> + }
>  

Whitespace

> - rh_attach_region(_muram_info, r.start - muram_pbase,
> -  resource_size());
>   }
>  
>   muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
>   if (!muram_vbase) {
> - 

Re: [PATCH v12 4/6] QE/CPM: move muram management functions to qe_common

[Scott Wood]

On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> QE and CPM have the same muram, they use the same management
> functions. Now QE support both ARM and PowerPC, it is necessary
> to move QE to "driver/soc", so move the muram management functions
> from cpm_common to qe_common for preparing to move QE code to "driver/soc"
> 
> Signed-off-by: Zhao Qiang 
> ---
> Changes for v2:
>   - no changes
> Changes for v3:
>   - no changes
> Changes for v4:
>   - no changes
> Changes for v5:
>   - no changes
> Changes for v6:
>   - using genalloc instead rheap to manage QE MURAM
>   - remove qe_reset from platform file, using 
>   - subsys_initcall to call qe_init function.
> Changes for v7:
>   - move this patch from 3/3 to 2/3
>   - convert cpm with genalloc
>   - check for gen_pool allocation failure
> Changes for v8:
>   - rebase
>   - move BD_SC_* macro instead of copy
> Changes for v9:
>   - doesn't modify CPM, add a new patch to modify.
>   - rebase
> Changes for v10:
>   - rebase
> Changes for v11:
>   - remove renaming
>   - delete removing qe_reset and delete adding qe_init.
> Changes for v12:
>   - SPI_FSL_CPM depends on QE-MURAM, select QUICC_ENGINE for it. 

Why is the SPI change part of this patch?  Why is it even part of this 
patchset, rather than an independent patch sent to the SPI list and 
maintainer?  If it's tied to other changes you're making, explain that.  As 
is, there is zero mention of the SPI change in the part of the e-mail that 
will become the git changelog.

> 
>  arch/powerpc/include/asm/cpm.h |  44 -
>  arch/powerpc/include/asm/qe.h  |  16 ++
>  arch/powerpc/sysdev/cpm_common.c   | 210 +-
> ---
>  arch/powerpc/sysdev/qe_lib/Makefile|   2 +-
>  .../sysdev/{cpm_common.c => qe_lib/qe_common.c}| 188 +-
>  drivers/spi/Kconfig|   1 +
>  6 files changed, 28 insertions(+), 433 deletions(-)
>  copy arch/powerpc/sysdev/{cpm_common.c => qe_lib/qe_common.c} (54%)
> 
> diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
> index 0e1ac3f..05a1c15 100644
> --- a/arch/powerpc/include/asm/cpm.h
> +++ b/arch/powerpc/include/asm/cpm.h
> @@ -155,50 +155,6 @@ typedef struct cpm_buf_desc {
>   */
>  #define BD_I2C_START (0x0400)
>  
> -int cpm_muram_init(void);
> -
> -#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
> -unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
> -int cpm_muram_free(unsigned long offset);
> -unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long 
> size);
> -unsigned long cpm_muram_alloc_common(unsigned long size, void *data);
> -void __iomem *cpm_muram_addr(unsigned long offset);
> -unsigned long cpm_muram_offset(void __iomem *addr);
> -dma_addr_t cpm_muram_dma(void __iomem *addr);
> -#else
> -static inline unsigned long cpm_muram_alloc(unsigned long size,
> - unsigned long align)
> -{
> - return -ENOSYS;
> -}
> -
> -static inline int cpm_muram_free(unsigned long offset)
> -{
> - return -ENOSYS;
> -}
> -
> -static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
> -   unsigned long size)
> -{
> - return -ENOSYS;
> -}
> -
> -static inline void __iomem *cpm_muram_addr(unsigned long offset)
> -{
> - return NULL;
> -}
> -
> -static inline unsigned long cpm_muram_offset(void __iomem *addr)
> -{
> - return -ENOSYS;
> -}
> -
> -static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
> -{
> - return 0;
> -}
> -#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
> -
>  #ifdef CONFIG_CPM
>  int cpm_command(u32 command, u8 opcode);
>  #else
> diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
> index 32b9bfa..c2dd8e6 100644
> --- a/arch/powerpc/include/asm/qe.h
> +++ b/arch/powerpc/include/asm/qe.h
> @@ -16,11 +16,15 @@
>  #define _ASM_POWERPC_QE_H
>  #ifdef __KERNEL__
>  
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
>  
>  #define QE_NUM_OF_SNUM   256 /* There are 256 serial number in QE */
>  #define QE_NUM_OF_BRGS   16
> @@ -92,6 +96,18 @@ extern void qe_reset(void);
>  static inline void qe_reset(void) {}
>  #endif
>  
> +int cpm_muram_init(void);
> +
> +#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
> +unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
> +int cpm_muram_free(unsigned long offset);
> +unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long 
> size);
> +unsigned long cpm_muram_alloc_common(unsigned long size, void *data);
> +void __iomem *cpm_muram_addr(unsigned long offset);
> +unsigned long cpm_muram_offset(void __iomem *addr);
> +dma_addr_t cpm_muram_dma(void 

Re: [PATCH 6/9] powerpc32: optimise a few instructions in csum_partial()

[Scott Wood]

On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> r5 does contain the value to be updated, so lets use r5 all way long
> for that. It makes the code more readable.
> 
> To avoid confusion, it is better to use adde instead of addc
> 
> The first addition is useless. Its only purpose is to clear carry.
> As r4 is a signed int that is always positive, this can be done by
> using srawi instead of srwi
> 
> Let's also remove the comment about bdnz having no overhead as it
> is not correct on all powerpc, at least on MPC8xx
> 
> In the last part, in our situation, the remaining quantity of bytes
> to be proceeded is between 0 and 3. Therefore, we can base that part
> on the value of bit 31 and bit 30 of r4 instead of anding r4 with 3
> then proceding on comparisons and substractions.
> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/lib/checksum_32.S | 37 +
>  1 file changed, 17 insertions(+), 20 deletions(-)

Do you have benchmarks for these optimizations?

-Scott

> 
> diff --git a/arch/powerpc/lib/checksum_32.S b/arch/powerpc/lib/checksum_32.S
> index 3472372..9c12602 100644
> --- a/arch/powerpc/lib/checksum_32.S
> +++ b/arch/powerpc/lib/checksum_32.S
> @@ -27,35 +27,32 @@
>   * csum_partial(buff, len, sum)
>   */
>  _GLOBAL(csum_partial)
> - addic   r0,r5,0
>   subir3,r3,4
> - srwi.   r6,r4,2
> + srawi.  r6,r4,2 /* Divide len by 4 and also clear carry */
>   beq 3f  /* if we're doing < 4 bytes */
> - andi.   r5,r3,2 /* Align buffer to longword boundary */
> + andi.   r0,r3,2 /* Align buffer to longword boundary */
>   beq+1f
> - lhz r5,4(r3)/* do 2 bytes to get aligned */
> - addir3,r3,2
> + lhz r0,4(r3)/* do 2 bytes to get aligned */
>   subir4,r4,2
> - addcr0,r0,r5
> + addir3,r3,2
>   srwi.   r6,r4,2 /* # words to do */
> + adder5,r5,r0
>   beq 3f
>  1:   mtctr   r6
> -2:   lwzur5,4(r3)/* the bdnz has zero overhead, so it should */
> - adder0,r0,r5/* be unnecessary to unroll this loop */
> +2:   lwzur0,4(r3)
> + adder5,r5,r0
>   bdnz2b
> - andi.   r4,r4,3
> -3:   cmpwi   0,r4,2
> - blt+4f
> - lhz r5,4(r3)
> +3:   andi.   r0,r4,2
> + beq+4f
> + lhz r0,4(r3)
>   addir3,r3,2
> - subir4,r4,2
> - adder0,r0,r5
> -4:   cmpwi   0,r4,1
> - bne+5f
> - lbz r5,4(r3)
> - slwir5,r5,8 /* Upper byte of word */
> - adder0,r0,r5
> -5:   addze   r3,r0   /* add in final carry */
> + adder5,r5,r0
> +4:   andi.   r0,r4,1
> + beq+5f
> + lbz r0,4(r3)
> + slwir0,r0,8 /* Upper byte of word */
> + adder5,r5,r0
> +5:   addze   r3,r5   /* add in final carry */
>   blr
>  
>  /*
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[PATCH] clk: qoriq: Fix wrong data in p2041_cmux_grp2

[Scott Wood]

Signed-off-by: Scott Wood 
---
This is on top of http://patchwork.ozlabs.org/patch/519801/
and I'll apply them together.

 drivers/clk/clk-qoriq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 8f9c93b..07985a5 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -128,8 +128,8 @@ static const struct clockgen_muxinfo p2041_cmux_grp1 = {
 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
{
[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
-   [4] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
-   [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+   [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+   [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
}
 };
 
-- 
2.1.4

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Re: [PATCH v12 6/6] QE: Move QE from arch/powerpc to drivers/soc

[Scott Wood]

On Wed, Oct 14, 2015 at 03:16:08PM +0800, Zhao Qiang wrote:
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
> index 01626be7..c9541a5 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -272,25 +272,6 @@ config TAU_AVERAGE
>  
> If in doubt, say N here.
>  
> -config QUICC_ENGINE
> - bool "Freescale QUICC Engine (QE) Support"
> - depends on FSL_SOC && PPC32
> - select GENERIC_ALLOCATOR
> - select CRC32
> - help
> -   The QUICC Engine (QE) is a new generation of communications
> -   coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
> -   Selecting this option means that you wish to build a kernel
> -   for a machine with a QE coprocessor.
> -
> -config QE_GPIO
> - bool "QE GPIO support"
> - depends on QUICC_ENGINE
> - select ARCH_REQUIRE_GPIOLIB
> - help
> -   Say Y here if you're going to use hardware that connects to the
> -   QE GPIOs.

Why was QE_GPIO moved as part of this patch?


> diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/drivers/soc/fsl/qe/Kconfig
> similarity index 50%
> copy from arch/powerpc/sysdev/qe_lib/Kconfig
> copy to drivers/soc/fsl/qe/Kconfig
> index 3c25199..283fe0d 100644
> --- a/arch/powerpc/sysdev/qe_lib/Kconfig
> +++ b/drivers/soc/fsl/qe/Kconfig
> @@ -2,6 +2,17 @@
>  # QE Communication options
>  #
>  
> +config QUICC_ENGINE
> + bool "Freescale QUICC Engine (QE) Support"
> + depends on FSL_SOC && PPC32
> + select GENERIC_ALLOCATOR
> + select CRC32
> + help
> +   The QUICC Engine (QE) is a new generation of communications
> +   coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
> +   Selecting this option means that you wish to build a kernel
> +   for a machine with a QE coprocessor.
> +
>  config UCC_SLOW
>   bool
>   default y if SERIAL_QE
> @@ -19,9 +30,3 @@ config UCC_FAST
>  config UCC
>   bool
>   default y if UCC_FAST || UCC_SLOW
> -
> -config QE_USB
> - bool
> - default y if USB_FSL_QE
> - help
> -   QE USB Controller support

Why did some config symbols get moved and others not?

> diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
> new file mode 100644
> index 000..51c9dce
> --- /dev/null
> +++ b/drivers/soc/fsl/qe/Makefile
> @@ -0,0 +1,9 @@
> +#
> +#Makefile for the Linux fsl parts of QE
> +#

"fsl parts of QE"?  Are there non-fsl parts of QE?

-Scott
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Re: [PATCH 3/9] powerpc32: checksum_wrappers_64 becomes checksum_wrappers

[Scott Wood]

On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> The powerpc64 checksum wrapper functions adds csum_and_copy_to_user()
> which otherwise is implemented in include/net/checksum.h by using
> csum_partial() then copy_to_user()
> 
> Those two wrapper fonctions are also applicable to powerpc32 as it is
> based on the use of csum_partial_copy_generic() which also
> exists on powerpc32
> 
> This patch renames arch/powerpc/lib/checksum_wrappers_64.c to
> arch/powerpc/lib/checksum_wrappers.c and
> makes it non-conditional to CONFIG_WORD_SIZE
> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/include/asm/checksum.h  | 9 --
> ---
>  arch/powerpc/lib/Makefile| 3 +--
>  arch/powerpc/lib/{checksum_wrappers_64.c => checksum_wrappers.c} | 0
>  3 files changed, 1 insertion(+), 11 deletions(-)
>  rename arch/powerpc/lib/{checksum_wrappers_64.c => checksum_wrappers.c} 
> (100%)

I wonder why it was 64-bit specific in the first place.

CCing Anton Blanchard.  

-Scott

> 
> diff --git a/arch/powerpc/include/asm/checksum.h 
> b/arch/powerpc/include/asm/checksum.h
> index d2ca07b..afa6722 100644
> --- a/arch/powerpc/include/asm/checksum.h
> +++ b/arch/powerpc/include/asm/checksum.h
> @@ -47,21 +47,12 @@ extern __wsum csum_partial_copy_generic(const void 
> *src, void *dst,
> int len, __wsum sum,
> int *src_err, int *dst_err);
>  
> -#ifdef __powerpc64__
>  #define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
>  extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
> int len, __wsum sum, int *err_ptr);
>  #define HAVE_CSUM_COPY_USER
>  extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
>   int len, __wsum sum, int *err_ptr);
> -#else
> -/*
> - * the same as csum_partial, but copies from src to dst while it
> - * checksums.
> - */
> -#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
> -csum_partial_copy_generic((__force const void *)(src), (dst), 
> (len), (sum), (errp), NULL)
> -#endif
>  
>  #define csum_partial_copy_nocheck(src, dst, len, sum)   \
>  csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> index a47e142..e46b068 100644
> --- a/arch/powerpc/lib/Makefile
> +++ b/arch/powerpc/lib/Makefile
> @@ -22,8 +22,7 @@ obj64-$(CONFIG_SMP) += locks.o
>  obj64-$(CONFIG_ALTIVEC)  += vmx-helper.o
>  
>  ifeq ($(CONFIG_GENERIC_CSUM),)
> -obj-y+= checksum_$(CONFIG_WORD_SIZE).o
> -obj-$(CONFIG_PPC64)  += checksum_wrappers_64.o
> +obj-y+= checksum_$(CONFIG_WORD_SIZE).o 
> checksum_wrappers.o
>  endif
>  
>  obj-$(CONFIG_PPC_EMULATE_SSTEP)  += sstep.o ldstfp.o
> diff --git a/arch/powerpc/lib/checksum_wrappers_64.c 
> b/arch/powerpc/lib/checksum_wrappers.c
> similarity index 100%
> rename from arch/powerpc/lib/checksum_wrappers_64.c
> rename to arch/powerpc/lib/checksum_wrappers.c
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Re: [PATCH 8/9] powerpc: simplify csum_add(a, b) in case a or b is constant 0

[Scott Wood]

On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> Simplify csum_add(a, b) in case a or b is constant 0
> 
> Signed-off-by: Christophe Leroy 
> ---
>  arch/powerpc/include/asm/checksum.h | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/checksum.h 
> b/arch/powerpc/include/asm/checksum.h
> index 56deea8..f8a9704 100644
> --- a/arch/powerpc/include/asm/checksum.h
> +++ b/arch/powerpc/include/asm/checksum.h
> @@ -119,7 +119,13 @@ static inline __wsum csum_add(__wsum csum, __wsum 
> addend)
>  {
>  #ifdef __powerpc64__
>   u64 res = (__force u64)csum;
> +#endif
> + if (__builtin_constant_p(csum) && csum == 0)
> + return addend;
> + if (__builtin_constant_p(addend) && addend == 0)
> + return csum;
>  
> +#ifdef __powerpc64__
>   res += (__force u64)addend;
>   return (__force __wsum)((u32)res + (res >> 32));
>  #else

How often does this happen?

-Scott

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[PATCH v3 05/18] powerpc/85xx: Load all early TLB entries at once

[Scott Wood]

Use an AS=1 trampoline TLB entry to allow all normal TLB1 entries to
be loaded at once.  This avoids the need to keep the translation that
code is executing from in the same TLB entry in the final TLB
configuration as during early boot, which in turn is helpful for
relocatable kernels (e.g. kdump) where the kernel is not running from
what would be the first TLB entry.

On e6500, we limit map_mem_in_cams() to the primary hwthread of a
core (the boot cpu is always considered primary, as a kdump kernel
can be entered on any cpu).  Each TLB only needs to be set up once,
and when we do, we don't want another thread to be running when we
create a temporary trampoline TLB1 entry.

Signed-off-by: Scott Wood 
---
v3: Drop rename of settlbcam to preptlbcam, as the settlbcam wrapper
was unused.

 arch/powerpc/kernel/setup_64.c   |  8 +
 arch/powerpc/mm/fsl_booke_mmu.c  |  4 +--
 arch/powerpc/mm/mmu_decl.h   |  1 +
 arch/powerpc/mm/tlb_nohash.c | 19 +++-
 arch/powerpc/mm/tlb_nohash_low.S | 63 
 5 files changed, 92 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index bdcbb71..505ec2c 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -108,6 +108,14 @@ static void setup_tlb_core_data(void)
for_each_possible_cpu(cpu) {
int first = cpu_first_thread_sibling(cpu);
 
+   /*
+* If we boot via kdump on a non-primary thread,
+* make sure we point at the thread that actually
+* set up this TLB.
+*/
+   if (cpu_first_thread_sibling(boot_cpuid) == first)
+   first = boot_cpuid;
+
paca[cpu].tcd_ptr = [first].tcd;
 
/*
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 354ba3c..bb1f88c 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -141,8 +141,6 @@ static void settlbcam(int index, unsigned long virt, 
phys_addr_t phys,
tlbcam_addrs[index].start = virt;
tlbcam_addrs[index].limit = virt + size - 1;
tlbcam_addrs[index].phys = phys;
-
-   loadcam_entry(index);
 }
 
 unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
@@ -188,6 +186,8 @@ static unsigned long map_mem_in_cams_addr(phys_addr_t phys, 
unsigned long virt,
virt += cam_sz;
phys += cam_sz;
}
+
+   loadcam_multi(0, i, max_cam_idx);
tlbcam_index = i;
 
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 085b66b..27c3a2d 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -152,6 +152,7 @@ extern int switch_to_as1(void);
 extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
 #endif
 extern void loadcam_entry(unsigned int index);
+extern void loadcam_multi(int first_idx, int num, int tmp_idx);
 
 struct tlbcam {
u32 MAS0;
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 723a099..a7381fb 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -42,6 +42,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -628,10 +629,26 @@ static void early_init_this_mmu(void)
 #ifdef CONFIG_PPC_FSL_BOOK3E
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
unsigned int num_cams;
+   int __maybe_unused cpu = smp_processor_id();
+   bool map = true;
 
/* use a quarter of the TLBCAM for bolted linear map */
num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
-   linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
+
+   /*
+* Only do the mapping once per core, or else the
+* transient mapping would cause problems.
+*/
+#ifdef CONFIG_SMP
+   if (cpu != boot_cpuid &&
+   (cpu != cpu_first_thread_sibling(cpu) ||
+cpu == cpu_first_thread_sibling(boot_cpuid)))
+   map = false;
+#endif
+
+   if (map)
+   linear_map_top = map_mem_in_cams(linear_map_top,
+num_cams);
}
 #endif
 
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 43ff3c7..68c4775 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -400,6 +400,7 @@ _GLOBAL(set_context)
  * extern void loadcam_entry(unsigned int index)
  *
  * Load TLBCAM[index] entry in to the L2 CAM MMU
+ * Must preserve r7, r8, r9, and r10
  */
 _GLOBAL(loadcam_entry)
mflrr5
@@ -423,4 +424,66 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
tlbwe
isync
blr
+
+/*
+ * Load multiple TLB 

Re: [v2] powerpc/e6500: hw tablewalk: make sure we invalidate and write to the same tlb entry

[Kevin Hao]

On Fri, Oct 16, 2015 at 07:01:55PM -0500, Scott Wood wrote:
> On Tue, Aug 18, 2015 at 03:55:56PM +0800, Kevin Hao wrote:
> > diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
> > index e4185581c5a7..3a5b89dfb5a1 100644
> > --- a/arch/powerpc/mm/tlb_low_64e.S
> > +++ b/arch/powerpc/mm/tlb_low_64e.S
> > @@ -68,11 +68,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> > ld  r14,PACAPGD(r13)
> > std r15,EX_TLB_R15(r12)
> > std r10,EX_TLB_CR(r12)
> > +#ifdef CONFIG_PPC_FSL_BOOK3E
> > +BEGIN_FTR_SECTION
> > +   std r7,EX_TLB_R7(r12)
> > +END_FTR_SECTION_IFSET(CPU_FTR_SMT)
> > +#endif
> > TLB_MISS_PROLOG_STATS
> >  .endm
> >  
> >  .macro tlb_epilog_bolted
> > ld  r14,EX_TLB_CR(r12)
> > +#ifdef CONFIG_PPC_FSL_BOOK3E
> > +BEGIN_FTR_SECTION
> > +   ld  r7,EX_TLB_R7(r12)
> > +END_FTR_SECTION_IFSET(CPU_FTR_SMT)
> > +#endif
> 
> r7 is used outside the CPU_FTR_SMT section of the e6500 TLB handler.

Sorry for the delay response just back from vacation. I will move the load
of TCD_ESEL_NEXT out of CPU_FTR_SMT wrap.

Thanks,
Kevin


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Re: [PATCH v6 22/22] of/platform: Defer probes of registered devices

[Tomeu Vizoso]

On 22 October 2015 at 00:51, Scott Wood  wrote:
> On Wed, 2015-10-21 at 08:44 -0500, Rob Herring wrote:
>> On Wed, Oct 21, 2015 at 12:54 AM, Scott Wood 
>> wrote:
>> > On Mon, 2015-09-21 at 16:03 +0200, Tomeu Vizoso wrote:
>> > > Instead of trying to match and probe platform and AMBA devices right
>> > > after each is registered, delay their probes until device_initcall_sync.
>> > >
>> > > This means that devices will start probing once all built-in drivers
>> > > have registered, and after all platform and AMBA devices from the DT
>> > > have been registered already.
>> > >
>> > > This allows us to prevent deferred probes by probing dependencies on
>> > > demand.
>> > >
>> > > Signed-off-by: Tomeu Vizoso 
>> > > ---
>> > >
>> > > Changes in v4:
>> > > - Also defer probes of AMBA devices registered from the DT as they can
>> > >   also request resources.
>> > >
>> > >  drivers/of/platform.c | 11 ---
>> > >  1 file changed, 8 insertions(+), 3 deletions(-)
>> >
>> > This breaks arch/powerpc/sysdev/fsl_pci.c.  The PCI bus is an OF platform
>> > device, and it must be probed before pcibios_init() which is a
>> > subsys_initcall(), or else the PCI bus never gets scanned.
>>
>> Thanks for the report. This is probably getting dropped, but it could
>> be disabled for PPC.
>
> I don't think that adding another arbitrary arch difference would be the
> right solution.

I think Rob meant temporarily disable it while things get fixed. At
least, I don't see any reason why PPC wouldn't benefit from this
series.

Regards,

Tomeu

>> Any plans to fix this and make PCI hosts hotplugable? For the scanning
>> part, generally the host controller drivers are responsible for
>> scanning their bus now.
>
> Scanning from the host controller driver seems like a reasonable goal, though
>
> it'd take a bit of digging to extract whatever other things fsl_pci may
> depend on from the common PPC PCI code, in particular the various things that
>
> pcibios_resource_survey() does after all PCI buses have been scanned.
>
> There's also check_swiotlb_enabled(), another subsys_initcall, which frees
> the swiotlb memory if ppc_swiotlb_enable hasn't been set.  The PCI host
> controller probe sets ppc_swiotlb_enable if it wasn't able to create an
> inbound mapping for all RAM.  Even if we were to change that to a later
> initcall, there's nothing later than late_initcall that we could use.
>
> -Scott
>
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Re: [PATCH v4 2/2] powerpc/512x: add a device tree binding for LocalPlus Bus FIFO

[Anatolij Gustschin]

On Mon, 12 Oct 2015 00:08:02 +0300
Alexander Popov  wrote:

> Add a device tree binding for Freescale MPC512x LocalPlus Bus FIFO and
> introduce the document describing that binding.
> 
> Signed-off-by: Alexander Popov 
> ---
>  .../bindings/powerpc/fsl/mpc512x_lpbfifo.txt| 21 
> +
>  arch/powerpc/boot/dts/mpc5121.dtsi  | 11 +--
>  arch/powerpc/boot/dts/mpc5125twr.dts| 11 ++-
>  3 files changed, 40 insertions(+), 3 deletions(-)
>  create mode 100644 
> Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt

applied to mpc5xxx/next.

Thanks,

Anatolij
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[PATCH v3] powerpc/e6500: hw tablewalk: make sure we invalidate and write to the same tlb entry

[Kevin Hao]

In order to workaround Erratum A-008139, we have to invalidate the
tlb entry with tlbilx before overwriting. Due to the performance
consideration, we don't add any memory barrier when acquire/release
the tcd lock. This means the two load instructions for esel_next do
have the possibility to return different value. This is definitely
not acceptable due to the Erratum A-008139. We have two options to
fix this issue:
  a) Add memory barrier when acquire/release tcd lock to order the
 load/store to esel_next.
  b) Just make sure to invalidate and write to the same tlb entry and
 tolerate the race that we may get the wrong value and overwrite
 the tlb entry just updated by the other thread.

We observe better performance using option b. So reserve an additional
register to save the value of the esel_next.

Signed-off-by: Kevin Hao 
---
v3: Move the load of TCD_ESEL_NEXT out of CPU_FTR_SMT since it is also used for
non-SMT codes. Boot test for both SMT and non-SMT mode.

v2: Use an additional register for saving the value of esel_next instead of 
lwsync.

 arch/powerpc/include/asm/exception-64e.h | 11 ++-
 arch/powerpc/mm/tlb_low_64e.S| 25 +
 2 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64e.h 
b/arch/powerpc/include/asm/exception-64e.h
index a8b52b61043f..d53575becbed 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -69,13 +69,14 @@
 #define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
 #define EX_TLB_SRR0(10 * 8)
 #define EX_TLB_SRR1(11 * 8)
+#define EX_TLB_R7  (12 * 8)
 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
-#define EX_TLB_R8  (12 * 8)
-#define EX_TLB_R9  (13 * 8)
-#define EX_TLB_LR  (14 * 8)
-#define EX_TLB_SIZE(15 * 8)
+#define EX_TLB_R8  (13 * 8)
+#define EX_TLB_R9  (14 * 8)
+#define EX_TLB_LR  (15 * 8)
+#define EX_TLB_SIZE(16 * 8)
 #else
-#define EX_TLB_SIZE(12 * 8)
+#define EX_TLB_SIZE(13 * 8)
 #endif
 
 #defineSTART_EXCEPTION(label)  
\
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index e4185581c5a7..29d6987c37ba 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -68,11 +68,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
ld  r14,PACAPGD(r13)
std r15,EX_TLB_R15(r12)
std r10,EX_TLB_CR(r12)
+#ifdef CONFIG_PPC_FSL_BOOK3E
+   std r7,EX_TLB_R7(r12)
+#endif
TLB_MISS_PROLOG_STATS
 .endm
 
 .macro tlb_epilog_bolted
ld  r14,EX_TLB_CR(r12)
+#ifdef CONFIG_PPC_FSL_BOOK3E
+   ld  r7,EX_TLB_R7(r12)
+#endif
ld  r10,EX_TLB_R10(r12)
ld  r11,EX_TLB_R11(r12)
ld  r13,EX_TLB_R13(r12)
@@ -297,6 +303,7 @@ itlb_miss_fault_bolted:
  * r13 = PACA
  * r11 = tlb_per_core ptr
  * r10 = crap (free to use)
+ * r7  = esel_next
  */
 tlb_miss_common_e6500:
crmove  cr2*4+2,cr0*4+2 /* cr2.eq != 0 if kernel address */
@@ -325,7 +332,11 @@ BEGIN_FTR_SECTION  /* CPU_FTR_SMT */
bne 10b
b   1b
.previous
+END_FTR_SECTION_IFSET(CPU_FTR_SMT)
+
+   lbz r7,TCD_ESEL_NEXT(r11)
 
+BEGIN_FTR_SECTION  /* CPU_FTR_SMT */
/*
 * Erratum A-008139 says that we can't use tlbwe to change
 * an indirect entry in any way (including replacing or
@@ -334,8 +345,7 @@ BEGIN_FTR_SECTION   /* CPU_FTR_SMT */
 * with tlbilx before overwriting.
 */
 
-   lbz r15,TCD_ESEL_NEXT(r11)
-   rlwinm  r10,r15,16,0xff
+   rlwinm  r10,r7,16,0xff
orisr10,r10,MAS0_TLBSEL(1)@h
mtspr   SPRN_MAS0,r10
isync
@@ -429,15 +439,14 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_SMT)
mtspr   SPRN_MAS2,r15
 
 tlb_miss_huge_done_e6500:
-   lbz r15,TCD_ESEL_NEXT(r11)
lbz r16,TCD_ESEL_MAX(r11)
lbz r14,TCD_ESEL_FIRST(r11)
-   rlwimi  r10,r15,16,0x00ff   /* insert esel_next into MAS0 */
-   addir15,r15,1   /* increment esel_next */
+   rlwimi  r10,r7,16,0x00ff/* insert esel_next into MAS0 */
+   addir7,r7,1 /* increment esel_next */
mtspr   SPRN_MAS0,r10
-   cmpwr15,r16
-   iseleq  r15,r14,r15 /* if next == last use first */
-   stb r15,TCD_ESEL_NEXT(r11)
+   cmpwr7,r16
+   iseleq  r7,r14,r7   /* if next == last use first */
+   stb r7,TCD_ESEL_NEXT(r11)
 
tlbwe
 
-- 
2.4.3

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Re: [PATCH v4 1/2] powerpc/512x: add LocalPlus Bus FIFO device driver

[Anatolij Gustschin]

On Mon, 12 Oct 2015 00:08:01 +0300
Alexander Popov  wrote:

> This driver for Freescale MPC512x LocalPlus Bus FIFO (called SCLPC
> in the Reference Manual) allows Direct Memory Access transfers
> between RAM and peripheral devices on LocalPlus Bus.
> 
> Signed-off-by: Alexander Popov 
> ---
>  arch/powerpc/configs/mpc512x_defconfig|   1 +
>  arch/powerpc/include/asm/mpc5121.h|  59 +++
>  arch/powerpc/platforms/512x/Kconfig   |   6 +
>  arch/powerpc/platforms/512x/Makefile  |   1 +
>  arch/powerpc/platforms/512x/mpc512x_lpbfifo.c | 539 
> ++
>  5 files changed, 606 insertions(+)
>  create mode 100644 arch/powerpc/platforms/512x/mpc512x_lpbfifo.c

extended with MODULE_DEVICE_TABLE() for of_device_id struct and
applied to mpc5xxx/next.

Thanks,

Anatolij
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Re: [RESEND PATCH 1/2] powerpc: platforms: mpc52xx_lpbfifo: Fix module autoload for OF platform driver

[Anatolij Gustschin]

On Tue, 20 Oct 2015 16:04:12 +0100
Luis de Bethencourt  wrote:

> From: Luis de Bethencourt 
> 
> This platform driver has a OF device ID table but the OF module
> alias information is not created so module autoloading won't work.
> 
> Signed-off-by: Luis de Bethencourt 
> ---
>  arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c | 1 +
>  1 file changed, 1 insertion(+)

applied to mpc5xxx/next.

Thanks,

Anatolij
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