[PATCH] cxl: static-ify variables to fix sparse warnings

[Andrew Donnellan]

Make a couple more variables static. Found by sparse.

Signed-off-by: Andrew Donnellan 
---
 drivers/misc/cxl/flash.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/cxl/flash.c b/drivers/misc/cxl/flash.c
index 68dd0b7..c63d61e 100644
--- a/drivers/misc/cxl/flash.c
+++ b/drivers/misc/cxl/flash.c
@@ -24,8 +24,8 @@ struct ai_header {
 };
 
 static struct semaphore sem;
-unsigned long *buffer[CXL_AI_MAX_ENTRIES];
-struct sg_list *le;
+static unsigned long *buffer[CXL_AI_MAX_ENTRIES];
+static struct sg_list *le;
 static u64 continue_token;
 static unsigned int transfer;
 
-- 
Andrew Donnellan  OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com  IBM Australia Limited

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Re: [1/3] powerpc: scan_features() updates incorrect bits

[Michael Ellerman]

On Sat, 2016-04-16 at 00:27 +1000, Michael Ellerman wrote:
> On Fri, 2016-15-04 at 02:06:13 UTC, Unknown sender due to SPF wrote:
> > The real LE feature entry in the ibm_pa_feature struct has the
> > wrong number of elements. Instead of checking for byte 5, bit 0,
> > we check for byte 0, bit 0, and we also incorrectly update cpu user
> > feature bit 5.
> 
> Finally the user feature, we're setting 5, ie. 0x4 | 0x1, which is:
> 
> #define PPC_FEATURE_PPC_LE0x0001
> 
> And nothing else, 0x4 is free.

Bt, we should reserve 0x4 for the foreseeable future. Because it is
erroneously set on older kernels.

cheers

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linux-next: manual merge of the livepatching tree with the powerpc tree

[Stephen Rothwell]

Hi Jiri,

Today's linux-next merge of the livepatching tree got a conflict in:

  arch/powerpc/kernel/process.c

between commit:

  7f92bc569455 ("powerpc: sparse: Include headers for __weak symbols")

from the powerpc tree and commit:

  5d31a96e6c01 ("powerpc/livepatch: Add livepatch stack to struct thread_info")

from the livepatching tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/powerpc/kernel/process.c
index 4695088e7dd2,a290ee374aa0..
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@@ -56,7 -55,8 +56,9 @@@
  #include 
  #endif
  #include 
 +#include 
+ #include 
+ 
  #include 
  #include 
  
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Re: [1/3] powerpc: scan_features() updates incorrect bits

[Michael Ellerman]

On Fri, 2016-15-04 at 02:06:13 UTC, Unknown sender due to SPF wrote:
> The real LE feature entry in the ibm_pa_feature struct has the
> wrong number of elements. Instead of checking for byte 5, bit 0,
> we check for byte 0, bit 0, and we also incorrectly update cpu user
> feature bit 5.
> 
> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
> index 7030b03..9a3a7c6 100644
> --- a/arch/powerpc/kernel/prom.c
> +++ b/arch/powerpc/kernel/prom.c
> @@ -158,7 +158,7 @@ static struct ibm_pa_feature {
>   {CPU_FTR_NOEXECUTE, 0, 0,   0, 6, 0},
>   {CPU_FTR_NODSISRALIGN, 0, 0,1, 1, 1},
>   {0, MMU_FTR_CI_LARGE_PAGE, 0,   1, 2, 0},
> - {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
> + {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 0, 5, 0, 0},

This should be:

> + {CPU_FTR_REAL_LE, 0, PPC_FEATURE_TRUE_LE, 5, 0, 0},

Because the struct layout is:

static struct ibm_pa_feature {
unsigned long   cpu_features;   /* CPU_FTR_xxx bit */
unsigned long   mmu_features;   /* MMU_FTR_xxx bit */
unsigned intcpu_user_ftrs;  /* PPC_FEATURE_xxx bit */
unsigned intcpu_user_ftrs2; /* PPC_FEATURE2_xxx bit */
unsigned char   pabyte; /* byte number in ibm,pa-features */
unsigned char   pabit;  /* bit number (big-endian) */
unsigned char   invert; /* if 1, pa bit set => clear feature */
}


I'll fix it up locally.

cheers
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Re: [v4, 2/3] ppc64/book3s: make some room for common interrupt vector code

[Hari Bathini]

On 04/15/2016 06:29 PM, Michael Ellerman wrote:

On Fri, 2016-04-15 at 21:06 +1000, Michael Ellerman wrote:

Hi Hari,

Thanks for persisting with this.

On Thu, 2016-07-04 at 21:58:50 UTC, Hari Bathini wrote:

With the previous patch, we choke out whatever little space is left
below 0x7000 (FWNMI hard block) while there is a hole of ~1400 bytes
below __end_interrupts marker when CONFIG_CBE_RAS is disabled.
Considering CONFIG_CBE_RAS is not enabled by default for BOOK3S, this
is not a desirable scenario especially when we have to worry about
each additional instruction that goes below 0x7000.

Memory region from 0x1800 to 0x4000 is dedicated for common interrupt
vector code. Also, we never hit an interrupt below 0x300 when IR=DR=1
implying memory region between 0x4000 to 0x4300 can also be used for
common interrupt vector code. So, we can effectively use memory region
between 0x1800 to 0x4300 for common interrupt vector code.

On Power9 the system-call-vectored instruction will use the region at 0x3000, so
moving code into that space is not a good long term plan.

I'll take your v2 and put it in next next week.

I'll add this fixes line, which I think is correct:

Fixes: c1fb6816fb1b ("powerpc: Add relocation on exception vector handlers")


Yeah. Thanks!


cheers

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Re: [PATCH kernel v3 9/9] powerpc/powernv/npu: Enable NVLink pass through

[Alistair Popple]

Hi David,

On Fri, 15 Apr 2016 14:40:20 David Gibson wrote:
> On Tue, Apr 12, 2016 at 06:37:50PM +1000, Alexey Kardashevskiy wrote:
> > IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
> > also has a couple of fast speed links (NVLink). The interface to links
> > is exposed as an emulated PCI bridge which is included into the same
> > IOMMU group as the corresponding GPU.
> > 
> > In the kernel, NPUs get a separate PHB of the PNV_PHB_NPU type and a PE.
> > 
> > In order to make these links work when GPU is passed to the guest,
> > these bridges need to be passed as well; otherwise performance will
> > degrade.
> > 
> > This implements and exports API to manage NPU state in regard to VFIO;
> > it replicates iommu_table_group_ops.
> > 
> > This defines a new pnv_pci_ioda2_npu_ops which is assigned to
> > the IODA2 bridge if there are NPUs for a GPU on the bridge.
> > The new callbacks call the default IODA2 callbacks plus new NPU API.
> > This adds a gpe_table_group_to_npe() helper to find NPU PE for the IODA2
> > table_group, it is not expected to fail as the helper is only called
> > from the pnv_pci_ioda2_npu_ops.
> > 
> > This adds a pnv_pci_npu_setup_iommu() helper which adds NPUs to
> > the GPU group if any found. The helper uses helpers to look for
> > the "ibm,gpu" property in the device tree which is a phandle of
> > the corresponding GPU.
> > 
> > This adds an additional loop over PEs in pnv_ioda_setup_dma() as the main
> > loop skips NPU PEs as they do not have 32bit DMA segments.
> > 
> > Signed-off-by: Alexey Kardashevskiy 
> > ---
> > Changes:
> > v3:
> > * moved NPU-to-GPU IOMMU grouping later after all PHBs are discovered
> > * removed hack to make iommu_add_device() work, iommu_group_add_device()
> > is used instead
> > * cleanup in gpe_table_group_to_npe_cb()
> > 
> > v2:
> > * reimplemented to support NPU + GPU in the same group
> > * merged "powerpc/powernv/npu: Add NPU devices to IOMMU group" and
> > "powerpc/powernv/npu: Enable passing through via VFIO" into this patch
> > ---
> >  arch/powerpc/platforms/powernv/npu-dma.c  | 126 
> > ++
> >  arch/powerpc/platforms/powernv/pci-ioda.c | 105 +
> >  arch/powerpc/platforms/powernv/pci.h  |   6 ++
> >  3 files changed, 237 insertions(+)
> > 
> > diff --git a/arch/powerpc/platforms/powernv/npu-dma.c 
> > b/arch/powerpc/platforms/powernv/npu-dma.c
> > index 8e70221..7cb9f6a 100644
> > --- a/arch/powerpc/platforms/powernv/npu-dma.c
> > +++ b/arch/powerpc/platforms/powernv/npu-dma.c
> > @@ -12,6 +12,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #include 
> >  #include 
> > @@ -262,3 +263,128 @@ void pnv_npu_try_dma_set_bypass(struct pci_dev 
> > *gpdev, bool bypass)
> > }
> > }
> >  }
> > +
> > +long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> > +   struct iommu_table *tbl)
> > +{
> > +   struct pnv_phb *phb = npe->phb;
> > +   int64_t rc;
> > +   const unsigned long size = tbl->it_indirect_levels ?
> > +   tbl->it_level_size : tbl->it_size;
> > +   const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
> > +   const __u64 win_size = tbl->it_size << tbl->it_page_shift;
> > +
> > +   pe_info(npe, "Setting up window#%d %llx..%llx pg=%lx\n", num,
> > +   start_addr, start_addr + win_size - 1,
> > +   IOMMU_PAGE_SIZE(tbl));
> > +
> > +   /* Ignore @num as there is just one window per NPU */
> > +   rc = opal_pci_map_pe_dma_window(phb->opal_id,
> > +   npe->pe_number,
> > +   npe->pe_number,
> > +   tbl->it_indirect_levels + 1,
> > +   __pa(tbl->it_base),
> > +   size << 3,
> > +   IOMMU_PAGE_SIZE(tbl));
> > +   if (rc) {
> > +   pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
> > +   return rc;
> > +   }
> > +
> > +   pnv_pci_link_table_and_group(phb->hose->node, num,
> > +   tbl, >table_group);
> > +   pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
> > +
> > +   return rc;
> > +}
> > +
> > +long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
> > +{
> > +   struct pnv_phb *phb = npe->phb;
> > +   long ret;
> > +
> > +   pe_info(npe, "Removing DMA window #%d\n", num);
> > +
> > +   /* Ignore @num as there is just one window per NPU */
> > +   ret = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
> > +   npe->pe_number,
> > +   0/* levels */, 0/* table address */,
> > +   0/* table size */, 0/* page size */);
> > +   if (ret)
> > +   pe_warn(npe, "Unmapping failed, ret = %ld\n", ret);
> > +   else
> > +   pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
> > +
> > +   pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
> > +   >table_group);
> > +
> > +   return ret;
> > +}
> > +
> > +/* Switch 

Sam460ex pciex1 sound card issue

[Julian Margetson]

Hi

I am having problem with pciex1 sound card on my Sam460ex.
The card is an ice1724 based model.
I have reported the the issue to the alsa-dev mailing list.
So far no one has any ideas so I am exploring the possibility of the 
issue being caused by something going

wrong on the initialization of the motherboard.

The sound card is recognized but only works on about 1 in 5 boots .
By contrast a CMI8738 pciex1 sound card  works perfectly as do USB cm108 
based external cards .


In looking at the dmesg output from a boot where the ice1724 card is 
working the only difference that i can see is

 the start at [ 0.15]

[ 0.15] clocksource: timebase: mask: 0x max_cycles: 
0x10a60dda894, max_idle_ns: 440795207041 ns


for the non working boots is

[ 0.14] clocksource: timebase: mask: 0x max_cycles: 
0x10a60dda894, max_idle_ns: 440795207041 ns


Attached the two dmesg logs.

Regards
Julian








[0.00] Using Canyonlands machine description
[0.00] Initializing cgroup subsys cpu
[0.00] Linux version 4.4.7-sam460ex-jm (root@julian-VirtualBox) (gcc 
version 5.3.1 20160330 (Ubuntu 5.3.1-13ubuntu3) ) #7 PREEMPT Sun Apr 17 
10:38:34 AST 2016
[0.00] Found legacy serial port 0 for /plb/opb/serial@ef600300
[0.00]   mem=4ef600300, taddr=4ef600300, irq=0, clk=11059200, speed=0
[0.00] Found legacy serial port 1 for /plb/opb/serial@ef600400
[0.00]   mem=4ef600400, taddr=4ef600400, irq=0, clk=11059200, speed=0
[0.00] Top of RAM: 0x8000, Total RAM: 0x8000
[0.00] Memory hole size: 0MB
[0.00] Zone ranges:
[0.00]   DMA  [mem 0x-0x2fff]
[0.00]   Normal   empty
[0.00]   HighMem  [mem 0x3000-0x7fff]
[0.00] Movable zone start for each node
[0.00] Early memory node ranges
[0.00]   node   0: [mem 0x-0x7fff]
[0.00] Initmem setup node 0 [mem 0x-0x7fff]
[0.00] On node 0 totalpages: 524288
[0.00] free_area_init_node: node 0, pgdat c0b570cc, node_mem_map 
eefed000
[0.00]   DMA zone: 1536 pages used for memmap
[0.00]   DMA zone: 0 pages reserved
[0.00]   DMA zone: 196608 pages, LIFO batch:31
[0.00]   HighMem zone: 327680 pages, LIFO batch:31
[0.00] MMU: Allocated 1088 bytes of context maps for 255 contexts
[0.00] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[0.00] pcpu-alloc: [0] 0 
[0.00] Built 1 zonelists in Zone order, mobility grouping on.  Total 
pages: 522752
[0.00] Kernel command line: root=/dev/sda6 console=ttyS0,115200 
console=tty0
[0.00] PID hash table entries: 4096 (order: 2, 16384 bytes)
[0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[0.00] Sorting __ex_table...
[0.00] Memory: 2001796K/2097152K available (7308K kernel code, 316K 
rwdata, 3784K rodata, 236K init, 372K bss, 95356K reserved, 0K cma-reserved, 
1310720K highmem)
[0.00] Kernel virtual memory layout:
[0.00]   * 0xfffcf000..0xf000  : fixmap
[0.00]   * 0xffc0..0xffe0  : highmem PTEs
[0.00]   * 0xffa0..0xffc0  : consistent mem
[0.00]   * 0xffa0..0xffa0  : early ioremap
[0.00]   * 0xf100..0xffa0  : vmalloc & ioremap
[0.00] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[0.00] Preemptible hierarchical RCU implementation.
[0.00]  Build-time adjustment of leaf fanout to 32.
[0.00] NR_IRQS:512 nr_irqs:512 16
[0.00] UIC0 (32 IRQ sources) at DCR 0xc0
[0.00] UIC1 (32 IRQ sources) at DCR 0xd0
[0.00] UIC2 (32 IRQ sources) at DCR 0xe0
[0.00] UIC3 (32 IRQ sources) at DCR 0xf0
[0.00] time_init: decrementer frequency = 1155.10 MHz
[0.00] time_init: processor frequency   = 1155.10 MHz
[0.15] clocksource: timebase: mask: 0x max_cycles: 
0x10a60dda894, max_idle_ns: 440795207041 ns
[0.23] clocksource: timebase mult[dda520] shift[24] registered
[0.32] clockevent: decrementer mult[93d70a53] shift[31] cpu[0]
[0.000137] Console: colour dummy device 80x25
[0.000515] console [tty0] enabled
[0.000548] pid_max: default: 32768 minimum: 301
[0.000653] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[0.000677] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[0.003216] devtmpfs: initialized
[0.005878] clocksource: jiffies: mask: 0x max_cycles: 0x, 
max_idle_ns: 1911260446275000 ns
[0.006487] xor: measuring software checksum speed
[0.016595]8regs :   896.000 MB/sec
[0.026428]8regs_prefetch:   708.000 MB/sec
[0.036471]32regs:  1232.000 MB/sec
[0.046543]

Re: [PATCH V2 23/68] powerpc/mm: Make page table size a variable

[Aneesh Kumar K.V]

Balbir Singh  writes:

>> index 2f818cbd8aa6..dcb9d6e94a0c 100644
>> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
>> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
>> @@ -5,48 +5,20 @@
>>   * for each page table entry.  The PMD and PGD level use a 32b record for
>>   * each entry by assuming that each entry is page aligned.
>>   */
>> -#define PTE_INDEX_SIZE  9
>> -#define PMD_INDEX_SIZE  7
>> -#define PUD_INDEX_SIZE  9
>> -#define PGD_INDEX_SIZE  9
>> +#define H_PTE_INDEX_SIZE  9
>> +#define H_PMD_INDEX_SIZE  7
>> +#define H_PUD_INDEX_SIZE  9
>> +#define H_PGD_INDEX_SIZE  9
>>  
>
> Any comments on where these numbers came from?
>
> From these numbers for 4K pages we have
>
> Each PMD is 2M
> Each PUD is 256M
> Each PGD is 128G

I am not sure I understand. We are updating linux page table details for
hash config here. This patch doesn't make any functionality change, it
just make sure few #defines are marked as a variable.


-aneesh

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Re: [PATCH V2 18/68] powerpc/mm: Move hash and no hash code to separate files

[Aneesh Kumar K.V]

Balbir Singh  writes:
>> +
...

>> +/*
>> + * map_kernel_page currently only called by __ioremap
>> + * map_kernel_page adds an entry to the ioremap page table
>> + * and adds an entry to the HPT, possibly bolting it
>> + */
>> +int map_kernel_page(unsigned long ea, unsigned long pa, unsigned long flags)
>> +{
>> +pgd_t *pgdp;
>> +pud_t *pudp;
>> +pmd_t *pmdp;
>> +pte_t *ptep;
>> +
>> +if (slab_is_available()) {
>> +pgdp = pgd_offset_k(ea);
>> +pudp = pud_alloc(_mm, pgdp, ea);
>> +if (!pudp)
>> +return -ENOMEM;
>> +pmdp = pmd_alloc(_mm, pudp, ea);
>> +if (!pmdp)
>> +return -ENOMEM;
>> +ptep = pte_alloc_kernel(pmdp, ea);
>> +if (!ptep)
>> +return -ENOMEM;
>> +set_pte_at(_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
>> +  __pgprot(flags)));
>> +} else {
>> +/*
>> + * If the mm subsystem is not fully up, we cannot create a
>> + * linux page table entry for this mapping.  Simply bolt an
>> + * entry in the hardware page table.
>> + *
>> + */
>> +if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, flags,
>> +  mmu_io_psize, mmu_kernel_ssize)) {
>> +printk(KERN_ERR "Failed to do bolted mapping IO "
>> +   "memory at %016lx !\n", pa);
>> +return -ENOMEM;
>
> What happens when we do unmap this? I know this code has been around for a 
> while
> so its not new

you mean iounmap ? it do call vunmap, which look for a linux page table
entry. If it is a bolt_mapping entry as above, we will not have a linux
page table entry and that unmap will not relaly remove the mapping. 

>
>> +}
>> +}
>> +
>> +smp_wmb();
>> +return 0;
>> +}

-aneesh

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Re: [PATCH V2 17/68] powerpc/mm/hash: Add support for POWER9 hash

[Aneesh Kumar K.V]

Balbir Singh  writes:

> On 09/04/16 16:13, Aneesh Kumar K.V wrote:
>> PowerISA 3.0 adds a parition table indexed by LPID. Parition table allow
>> us to specify the MMU model that will be used for guest and host
>> translation.
>> 
>> This patch add support with SLB based hash model (UPRT = 0). What is
>> required with this model is to support the new hash page table entry
>> format and also setup Partition table such we use hash table for
>> address translation.
>> 
>> We don't have segment table support yet.
>> 
>> Inorder to make sure we don't load KVM module on Power9 (since we
>> don't have kvm support yet) this patch also disable kvm on Power9
>> 
>> Signed-off-by: Aneesh Kumar K.V 
>> ---
>>  arch/powerpc/include/asm/book3s/64/mmu-hash.h | 13 +++--
>>  arch/powerpc/kvm/book3s_hv.c  |  6 
>>  arch/powerpc/kvm/book3s_pr.c  |  6 +++-
>>  arch/powerpc/mm/hash_native_64.c  | 11 ++-
>>  arch/powerpc/mm/hash_utils_64.c   | 42 
>> +--
>>  arch/powerpc/mm/pgtable_64.c  |  7 +
>>  arch/powerpc/platforms/ps3/htab.c |  2 +-
>>  arch/powerpc/platforms/pseries/lpar.c |  2 +-
>>  8 files changed, 81 insertions(+), 8 deletions(-)
>> 
>> diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h 
>> b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
>> index ce73736b42db..843b5d839904 100644
>> --- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h
>> +++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
>> @@ -78,6 +78,10 @@
>>  #define HPTE_V_SECONDARYASM_CONST(0x0002)
>>  #define HPTE_V_VALIDASM_CONST(0x0001)
>>  
>> +/*
>> + * ISA 3.0 have a different HPTE format.
>> + */
>> +#define HPTE_R_3_0_SSIZE_SHIFT  58
>>  #define HPTE_R_PP0  ASM_CONST(0x8000)
>>  #define HPTE_R_TS   ASM_CONST(0x4000)
>>  #define HPTE_R_KEY_HI   ASM_CONST(0x3000)
>> @@ -224,7 +228,8 @@ static inline unsigned long hpte_encode_avpn(unsigned 
>> long vpn, int psize,
>>   */
>>  v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
>>  v <<= HPTE_V_AVPN_SHIFT;
>> -v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
>> +if (!cpu_has_feature(CPU_FTR_ARCH_300))
>> +v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
>>  return v;
>>  }
>>  
>> @@ -248,8 +253,12 @@ static inline unsigned long hpte_encode_v(unsigned long 
>> vpn, int base_psize,
>>   * aligned for the requested page size
>>   */
>>  static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
>> -  int actual_psize)
>> +  int actual_psize, int ssize)
>>  {
>> +
>> +if (cpu_has_feature(CPU_FTR_ARCH_300))
>> +pa |= ((unsigned long) ssize) << HPTE_R_3_0_SSIZE_SHIFT;
>> +
>
> Looks good, I was wondering if we can compute 
> cpu_has_feature(CPU_FTR_ARCH_300) once for the instance
> and use it, but I am just nit-picking. I've never tried using 
> ASM_MMU_FTR_IF(), I don't know
> if you've explored it. Not very important for this patchset though


There were multiple efforts w.r.t. to this. I tried to fix only
radix_enabled() using code patching. But we also had Kevin doing

http://mid.gmane.org/1440072876-8321-1-git-send-email-haoke...@gmail.com


>
>>  /* A 4K page needs no special encoding */
>>  if (actual_psize == MMU_PAGE_4K)
>>  return pa & HPTE_R_RPN;
>> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
>> index baeddb06811d..c07600efcef6 100644
>> --- a/arch/powerpc/kvm/book3s_hv.c
>> +++ b/arch/powerpc/kvm/book3s_hv.c
>> @@ -3083,6 +3083,12 @@ static int kvmppc_core_check_processor_compat_hv(void)
>>  if (!cpu_has_feature(CPU_FTR_HVMODE) ||
>>  !cpu_has_feature(CPU_FTR_ARCH_206))
>>  return -EIO;
>> +/*
>> + * Disable KVM for Power9, untill the required bits merged.
>> + */
>> +if (cpu_has_feature(CPU_FTR_ARCH_300))
>> +return -EIO;
>> +
>>  return 0;
>>  }
>>  
>> diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
>> index 95bceca8f40e..ffbaf40b7f31 100644
>> --- a/arch/powerpc/kvm/book3s_pr.c
>> +++ b/arch/powerpc/kvm/book3s_pr.c
>> @@ -1683,7 +1683,11 @@ static void kvmppc_core_destroy_vm_pr(struct kvm *kvm)
>>  
>>  static int kvmppc_core_check_processor_compat_pr(void)
>>  {
>> -/* we are always compatible */
>> +/*
>> + * Disable KVM for Power9 untill the required bits merged.
>> + */
>> +if (cpu_has_feature(CPU_FTR_ARCH_300))
>> +return -EIO;
>>  return 0;
>>  }
>>  
>> diff --git a/arch/powerpc/mm/hash_native_64.c 
>> b/arch/powerpc/mm/hash_native_64.c
>> index 8eaac81347fd..d873f6507f72 100644
>> --- a/arch/powerpc/mm/hash_native_64.c
>> +++ b/arch/powerpc/mm/hash_native_64.c
>> 

Re: [PATCH V3 00/29] bitops: add parity functions

[Dmitry Torokhov]

On Thu, Apr 14, 2016 at 10:36:41AM +0800, zengzhao...@163.com wrote:
>  drivers/input/joystick/grip_mp.c |  16 +--
>  drivers/input/joystick/sidewinder.c  |  24 +
>  drivers/input/mouse/elantech.c   |  10 +-
>  drivers/input/mouse/elantech.h   |   1 -
>  drivers/input/serio/ams_delta_serio.c|   8 +-
>  drivers/input/serio/pcips2.c |   2 +-
>  drivers/input/serio/saps2.c  |   2 +-

For input bits:

Acked-by: Dmitry Torokhov 

Thanks.

-- 
Dmitry
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[added to the 3.18 stable tree] sched: Fix crash in sched_init_numa()

[Sasha Levin]

From: Raghavendra K T 

This patch has been added to the 3.18 stable tree. If you have any
objections, please let us know.

===

[ Upstream commit 9c03ee147193645be4c186d3688232fa438c57c7 ]

The following PowerPC commit:

  c118baf80256 ("arch/powerpc/mm/numa.c: do not allocate bootmem memory for non 
existing nodes")

avoids allocating bootmem memory for non existent nodes.

But when DEBUG_PER_CPU_MAPS=y is enabled, my powerNV system failed to boot
because in sched_init_numa(), cpumask_or() operation was done on
unallocated nodes.

Fix that by making cpumask_or() operation only on existing nodes.

[ Tested with and w/o DEBUG_PER_CPU_MAPS=y on x86 and PowerPC. ]

Reported-by: Jan Stancek 
Tested-by: Jan Stancek 
Signed-off-by: Raghavendra K T 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Link: 
http://lkml.kernel.org/r/1452884483-11676-1-git-send-email-raghavendra...@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Sasha Levin 
---
 kernel/sched/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index d650e1e..4317f01 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -6416,7 +6416,7 @@ static void sched_init_numa(void)
 
sched_domains_numa_masks[i][j] = mask;
 
-   for (k = 0; k < nr_node_ids; k++) {
+   for_each_node(k) {
if (node_distance(j, k) > 
sched_domains_numa_distance[i])
continue;
 
-- 
2.5.0

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[added to the 4.1 stable tree] sched: Fix crash in sched_init_numa()

[Sasha Levin]

From: Raghavendra K T 

This patch has been added to the 4.1 stable tree. If you have any
objections, please let us know.

===

[ Upstream commit 9c03ee147193645be4c186d3688232fa438c57c7 ]

The following PowerPC commit:

  c118baf80256 ("arch/powerpc/mm/numa.c: do not allocate bootmem memory for non 
existing nodes")

avoids allocating bootmem memory for non existent nodes.

But when DEBUG_PER_CPU_MAPS=y is enabled, my powerNV system failed to boot
because in sched_init_numa(), cpumask_or() operation was done on
unallocated nodes.

Fix that by making cpumask_or() operation only on existing nodes.

[ Tested with and w/o DEBUG_PER_CPU_MAPS=y on x86 and PowerPC. ]

Reported-by: Jan Stancek 
Tested-by: Jan Stancek 
Signed-off-by: Raghavendra K T 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Link: 
http://lkml.kernel.org/r/1452884483-11676-1-git-send-email-raghavendra...@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Sasha Levin 
---
 kernel/sched/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 4d870eb..3b0f4c0 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -6480,7 +6480,7 @@ static void sched_init_numa(void)
 
sched_domains_numa_masks[i][j] = mask;
 
-   for (k = 0; k < nr_node_ids; k++) {
+   for_each_node(k) {
if (node_distance(j, k) > 
sched_domains_numa_distance[i])
continue;
 
-- 
2.5.0

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