Re: [PATCH v3 devicetree 0/2] Add Seville Ethernet switch to T1040RDB
On Thu, Oct 01, 2020 at 01:10:05PM -0700, David Miller wrote: > From: Vladimir Oltean > Date: Thu, 1 Oct 2020 16:20:11 +0300 > > > Seville is a DSA switch that is embedded inside the T1040 SoC, and > > supported by the mscc_seville DSA driver inside drivers/net/dsa/ocelot. > > > > This series adds this switch to the SoC's dtsi files and to the T1040RDB > > board file. > > I am assuming the devicetree folks will pick this series up. > > Thanks. > I can also resend via net-next if that's easier (the last commit on arch/powerpc/boot/dts/fsl/t104*, as per today's linux-next, has been in 2018, so there is no conflict). I need to resend anyway, due to an epic failure where I got the port numbering wrong...
Re: [PATCH] ASoC: fsl_spdif: Fix unnecessary check in fsl_spdif_probe()
On Wed, 26 Aug 2020 23:09:18 +0800, Tang Bin wrote: > The function fsl_spdif_probe() is only called with an openfirmware > platform device. Therefore there is no need to check that the passed > in device is NULL. Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl_spdif: Fix unnecessary check in fsl_spdif_probe() commit: 601fd3a7d849cf8a5dbd3628b3c29af9e5377961 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: [PATCH -next] ASoC: fsl: imx-mc13783: use devm_snd_soc_register_card()
On Tue, 29 Sep 2020 19:29:30 +0800, Qinglang Miao wrote: > Using devm_snd_soc_register_card() can make the code > shorter and cleaner. Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl: imx-mc13783: use devm_snd_soc_register_card() commit: bc772a46125f344ffabd7596c5b6b8c6ef703ea0 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: [PATCH 05/14] fs: don't allow kernel reads and writes without iter ops
On Thu, Oct 01, 2020 at 03:38:52PM -0700, Eric Biggers wrote:
> mutex_lock(>pipe_mutex);
> while (bytes) {
> - wr = __kernel_write(file, data, bytes, NULL);
> + wr = __kernel_write(file, data, bytes, >f_pos);
Better
loff_t dummy = 0;
...
wr = __kernel_write(file, data, bytes, );
Re: [PATCH 05/14] fs: don't allow kernel reads and writes without iter ops
Christoph, Al, and Linus:
On Thu, Sep 03, 2020 at 04:22:33PM +0200, Christoph Hellwig wrote:
> @@ -510,28 +524,31 @@ static ssize_t new_sync_write(struct file *filp, const
> char __user *buf, size_t
> /* caller is responsible for file_start_write/file_end_write */
> ssize_t __kernel_write(struct file *file, const void *buf, size_t count,
> loff_t *pos)
> {
> - mm_segment_t old_fs;
> - const char __user *p;
> + struct kvec iov = {
> + .iov_base = (void *)buf,
> + .iov_len= min_t(size_t, count, MAX_RW_COUNT),
> + };
> + struct kiocb kiocb;
> + struct iov_iter iter;
> ssize_t ret;
>
> if (WARN_ON_ONCE(!(file->f_mode & FMODE_WRITE)))
> return -EBADF;
> if (!(file->f_mode & FMODE_CAN_WRITE))
> return -EINVAL;
> + /*
> + * Also fail if ->write_iter and ->write are both wired up as that
> + * implies very convoluted semantics.
> + */
> + if (unlikely(!file->f_op->write_iter || file->f_op->write))
> + return warn_unsupported(file, "write");
>
> - old_fs = get_fs();
> - set_fs(KERNEL_DS);
> - p = (__force const char __user *)buf;
> - if (count > MAX_RW_COUNT)
> - count = MAX_RW_COUNT;
> - if (file->f_op->write)
> - ret = file->f_op->write(file, p, count, pos);
> - else if (file->f_op->write_iter)
> - ret = new_sync_write(file, p, count, pos);
> - else
> - ret = -EINVAL;
> - set_fs(old_fs);
> + init_sync_kiocb(, file);
> + kiocb.ki_pos = *pos;
> + iov_iter_kvec(, WRITE, , 1, iov.iov_len);
> + ret = file->f_op->write_iter(, );
next-20201001 crashes on boot for me because there is a bad interaction between
this commit in vfs/for-next:
commit 4d03e3cc59828c82ee89ea6e27a2f3cdf95aaadf
Author: Christoph Hellwig
Date: Thu Sep 3 16:22:33 2020 +0200
fs: don't allow kernel reads and writes without iter ops
... and Linus's mainline commit:
commit 90fb702791bf99b959006972e8ee7bb4609f441b
Author: Linus Torvalds
Date: Tue Sep 29 17:18:34 2020 -0700
autofs: use __kernel_write() for the autofs pipe writing
Linus's commit made autofs start passing pos=NULL to __kernel_write().
But, Christoph's commit made __kernel_write() no longer accept a NULL pos.
The following fixes it:
diff --git a/fs/autofs/waitq.c b/fs/autofs/waitq.c
index 5ced859dac53..b04c528b19d3 100644
--- a/fs/autofs/waitq.c
+++ b/fs/autofs/waitq.c
@@ -53,7 +53,7 @@ static int autofs_write(struct autofs_sb_info *sbi,
mutex_lock(>pipe_mutex);
while (bytes) {
- wr = __kernel_write(file, data, bytes, NULL);
+ wr = __kernel_write(file, data, bytes, >f_pos);
if (wr <= 0)
break;
data += wr;
I'm not sure what was intended, though.
Full stack trace below.
BUG: kernel NULL pointer dereference, address:
#PF: supervisor read access in kernel mode
#PF: error_code(0x) - not-present page
PGD 0 P4D 0
Oops: [#1] PREEMPT SMP NOPTI
CPU: 12 PID: 383 Comm: systemd-binfmt Tainted: GT
5.9.0-rc7-next-20201001 #2
Hardware name: Gigabyte Technology Co., Ltd. X399 AORUS Gaming 7/X399 AORUS
Gaming 7, BIOS F2 08/31/2017
RIP: 0010:init_sync_kiocb include/linux/fs.h:2050 [inline]
RIP: 0010:__kernel_write+0x16c/0x2b0 fs/read_write.c:546
Code: 24 4a b9 01 00 00 00 0f 45 c7 be 01 00 00 00 48 8d 7c 24 10 48 c7 44 24
40 00 00 00 00 48 c7 44 24 58 00 00 00 00 89 44 24 4c <48> 8b 03 48 c7 44 24 60
00 00 00 00 48 89 44 24 50 4c 89 64 24 38
RSP: 0018:a2fc0102f8b0 EFLAGS: 00010246
RAX: 0002 RBX: RCX: 0001
RDX: a2fc0102f8b0 RSI: 0001 RDI: a2fc0102f8c0
RBP: 8ad2927e2940 R08: 0130 R09: 8ad29a201800
R10: 000f R11: 8ad292547510 R12: 8ad2927e2940
R13: a2fc0102f8e8 R14: 8ad29a951768 R15: 0130
FS: 7f11023b9000() GS:8ad29ed0() knlGS:
CS: 0010 DS: ES: CR0: 80050033
CR2: CR3: 000857b62000 CR4: 003506e0
Call Trace:
autofs_write fs/autofs/waitq.c:56 [inline]
autofs_notify_daemon.constprop.0+0x115/0x260 fs/autofs/waitq.c:163
autofs_wait+0x5b1/0x750 fs/autofs/waitq.c:465
autofs_mount_wait+0x2d/0x60 fs/autofs/root.c:250
autofs_d_automount+0xc4/0x1a0 fs/autofs/root.c:379
follow_automount fs/namei.c:1198 [inline]
__traverse_mounts+0x8d/0x230 fs/namei.c:1243
traverse_mounts fs/namei.c:1272 [inline]
handle_mounts fs/namei.c:1381 [inline]
step_into+0x44e/0x730 fs/namei.c:1691
walk_component+0x7e/0x1b0 fs/namei.c:1867
link_p
Re: [PATCH 1/6] powerpc/time: Rename mftbl() to mftb()
On Thu, Oct 01, 2020 at 12:42:39PM +, Christophe Leroy wrote: > On PPC64, we have mftb(). > On PPC32, we have mftbl() and an #define mftb() mftbl(). > > mftb() and mftbl() are equivalent, their purpose is to read the > content of SPRN_TRBL, as returned by 'mftb' simplified instruction. > > binutils seems to define 'mftbl' instruction as an equivalent > of 'mftb'. > > However in both 32 bits and 64 bits documentation, only 'mftb' is > defined, and when performing a disassembly with objdump, the displayed > instruction is 'mftb' > > No need to have two ways to do the same thing with different > names, rename mftbl() to have only mftb(). There are mttbl and mttbu insns (and no mttb insn); they write a 32-bit half for the time base. There is an mftb, and an mftbu. mftbu reads the upper half, while mftb reads the *whole* register. SPR 269 is the TBU register, while SPR 268 is called both TB and TBL. Yes, it is confusing :-) The "mftb" name is much clearer than "mftbl" (on 64-bit), because it reads the whole 64-bit register. On 32-bit mftbl is clearer (but not defined in the architecture, not officially an insn or even an extended mnemonic). Segher
Re: [RFC PATCH next-20200930] treewide: Convert macro and uses of __section(foo) to __section("foo")
On Thu, 2020-10-01 at 14:39 -0500, Segher Boessenkool wrch/ote: > Hi! > > On Thu, Oct 01, 2020 at 12:15:39PM +0200, Miguel Ojeda wrote: > > > So it looks like the best option is to exclude these > > > 2 files from conversion. > > > > Agreed. Nevertheless, is there any reason arch/powerpc/* should not be > > compiling cleanly with compiler.h? (CC'ing the rest of the PowerPC > > reviewers and ML). > > You need to #include compiler_types.h to get this #define? Actually no, you need to add #include to both files and then it builds properly. Ideally though nothing should include this file directly. > (The twice-defined thing is a warning, not an error. It should be fixed > of course, but it is less important; although it may be pointing to a > deeper problem.) > > > Segher
Re: [PATCH v3 devicetree 0/2] Add Seville Ethernet switch to T1040RDB
From: Vladimir Oltean Date: Thu, 1 Oct 2020 16:20:11 +0300 > Seville is a DSA switch that is embedded inside the T1040 SoC, and > supported by the mscc_seville DSA driver inside drivers/net/dsa/ocelot. > > This series adds this switch to the SoC's dtsi files and to the T1040RDB > board file. I am assuming the devicetree folks will pick this series up. Thanks.
Re: [RFC PATCH next-20200930] treewide: Convert macro and uses of __section(foo) to __section("foo")
Hi! On Thu, Oct 01, 2020 at 12:15:39PM +0200, Miguel Ojeda wrote: > > So it looks like the best option is to exclude these > > 2 files from conversion. > > Agreed. Nevertheless, is there any reason arch/powerpc/* should not be > compiling cleanly with compiler.h? (CC'ing the rest of the PowerPC > reviewers and ML). You need to #include compiler_types.h to get this #define? (The twice-defined thing is a warning, not an error. It should be fixed of course, but it is less important; although it may be pointing to a deeper problem.) Segher
Re: [RFC PATCH next-20200930] treewide: Convert macro and uses of __section(foo) to __section("foo")
On Thu, 2020-10-01 at 12:15 +0200, Miguel Ojeda wrote: > Hi Joe, Buenas Miguel. > On Thu, Oct 1, 2020 at 12:56 AM Joe Perches wrote: > > So I installed the powerpc cross compiler, and > > nope, that doesn't work, it makes a mess. > > Thanks a lot for reviving the script and sending the treewide cleanup! No charge... I think the end result is cleaner and more obvious. > > So it looks like the best option is to exclude these > > 2 files from conversion. > > Agreed. Nevertheless, is there any reason arch/powerpc/* should not be > compiling cleanly with compiler.h? (CC'ing the rest of the PowerPC > reviewers and ML). That's not a can of worms I care to open. Perhaps the powerpc folk can do some fishing.
[PATCH v3 2/2] lkdtm/powerpc: Add SLB multihit test
To check machine check handling, add support to inject slb
multihit errors.
Reviewed-by: Michal Suchánek
Co-developed-by: Mahesh Salgaonkar
Signed-off-by: Mahesh Salgaonkar
Signed-off-by: Ganesh Goudar
---
drivers/misc/lkdtm/Makefile | 1 +
drivers/misc/lkdtm/core.c | 3 +
drivers/misc/lkdtm/lkdtm.h | 3 +
drivers/misc/lkdtm/powerpc.c| 156
tools/testing/selftests/lkdtm/tests.txt | 1 +
5 files changed, 164 insertions(+)
create mode 100644 drivers/misc/lkdtm/powerpc.c
diff --git a/drivers/misc/lkdtm/Makefile b/drivers/misc/lkdtm/Makefile
index c70b3822013f..f37ecfb0a707 100644
--- a/drivers/misc/lkdtm/Makefile
+++ b/drivers/misc/lkdtm/Makefile
@@ -10,6 +10,7 @@ lkdtm-$(CONFIG_LKDTM) += rodata_objcopy.o
lkdtm-$(CONFIG_LKDTM) += usercopy.o
lkdtm-$(CONFIG_LKDTM) += stackleak.o
lkdtm-$(CONFIG_LKDTM) += cfi.o
+lkdtm-$(CONFIG_PPC64) += powerpc.o
KASAN_SANITIZE_stackleak.o := n
KCOV_INSTRUMENT_rodata.o := n
diff --git a/drivers/misc/lkdtm/core.c b/drivers/misc/lkdtm/core.c
index a5e344df9166..8d5db42baa90 100644
--- a/drivers/misc/lkdtm/core.c
+++ b/drivers/misc/lkdtm/core.c
@@ -178,6 +178,9 @@ static const struct crashtype crashtypes[] = {
#ifdef CONFIG_X86_32
CRASHTYPE(DOUBLE_FAULT),
#endif
+#ifdef CONFIG_PPC64
+ CRASHTYPE(PPC_SLB_MULTIHIT),
+#endif
};
diff --git a/drivers/misc/lkdtm/lkdtm.h b/drivers/misc/lkdtm/lkdtm.h
index 8878538b2c13..b305bd511ee5 100644
--- a/drivers/misc/lkdtm/lkdtm.h
+++ b/drivers/misc/lkdtm/lkdtm.h
@@ -104,4 +104,7 @@ void lkdtm_STACKLEAK_ERASING(void);
/* cfi.c */
void lkdtm_CFI_FORWARD_PROTO(void);
+/* powerpc.c */
+void lkdtm_PPC_SLB_MULTIHIT(void);
+
#endif
diff --git a/drivers/misc/lkdtm/powerpc.c b/drivers/misc/lkdtm/powerpc.c
new file mode 100644
index ..033111f7d929
--- /dev/null
+++ b/drivers/misc/lkdtm/powerpc.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include "lkdtm.h"
+
+/* Gets index for new slb entry */
+static inline unsigned long get_slb_index(void)
+{
+ unsigned long index;
+
+ index = get_paca()->stab_rr;
+
+ /*
+* simple round-robin replacement of slb starting at SLB_NUM_BOLTED.
+*/
+ if (index < (mmu_slb_size - 1))
+ index++;
+ else
+ index = SLB_NUM_BOLTED;
+ get_paca()->stab_rr = index;
+ return index;
+}
+
+#define slb_esid_mask(ssize) \
+ (((ssize) == MMU_SEGSIZE_256M) ? ESID_MASK : ESID_MASK_1T)
+
+/* Form the operand for slbmte */
+static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
+unsigned long slot)
+{
+ return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot;
+}
+
+#define slb_vsid_shift(ssize) \
+ ((ssize) == MMU_SEGSIZE_256M ? SLB_VSID_SHIFT : SLB_VSID_SHIFT_1T)
+
+/* Form the operand for slbmte */
+static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
+unsigned long flags)
+{
+ return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
+ ((unsigned long)ssize << SLB_VSID_SSIZE_SHIFT);
+}
+
+/* Inserts new slb entry */
+static void insert_slb_entry(char *p, int ssize)
+{
+ unsigned long flags, entry;
+
+ flags = SLB_VSID_KERNEL | mmu_psize_defs[MMU_PAGE_64K].sllp;
+ preempt_disable();
+
+ entry = get_slb_index();
+ asm volatile("slbmte %0,%1" :
+ : "r" (mk_vsid_data((unsigned long)p, ssize, flags)),
+ "r" (mk_esid_data((unsigned long)p, ssize, entry))
+ : "memory");
+
+ entry = get_slb_index();
+ asm volatile("slbmte %0,%1" :
+ : "r" (mk_vsid_data((unsigned long)p, ssize, flags)),
+ "r" (mk_esid_data((unsigned long)p, ssize, entry))
+ : "memory");
+ preempt_enable();
+ /*
+* This triggers exception, If handled correctly we must recover
+* from this error.
+*/
+ p[0] = '!';
+}
+
+/* Inject slb multihit on vmalloc-ed address i.e 0xD00... */
+static void inject_vmalloc_slb_multihit(void)
+{
+ char *p;
+
+ p = vmalloc(2048);
+ if (!p)
+ return;
+
+ insert_slb_entry(p, MMU_SEGSIZE_1T);
+ vfree(p);
+}
+
+/* Inject slb multihit on kmalloc-ed address i.e 0xC00... */
+static void inject_kmalloc_slb_multihit(void)
+{
+ char *p;
+
+ p = kmalloc(2048, GFP_KERNEL);
+ if (!p)
+ return;
+
+ insert_slb_entry(p, MMU_SEGSIZE_1T);
+ kfree(p);
+}
+
+/*
+ * Few initial SLB entries are bolted. Add a test to inject
+ * multihit in bolted entry 0.
+ */
+static void insert_dup_slb_entry_0(void)
+{
+ unsigned long test_address = 0xC000;
+ volatile unsigned long *test_ptr;
+
[PATCH v3 1/2] powerpc/mce: remove nmi_enter/exit from real mode handler
Use of nmi_enter/exit in real mode handler causes the kernel to panic
and reboot on injecting slb mutihit on pseries machine running in hash
mmu mode, As these calls try to accesses memory outside RMO region in
real mode handler where translation is disabled.
Add check to not to use these calls on pseries machine running in hash
mmu mode.
Fixes: 116ac378bb3f ("powerpc/64s: machine check interrupt update NMI
accounting")
Signed-off-by: Ganesh Goudar
---
arch/powerpc/kernel/mce.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index ada59f6c4298..3bf39dd5dd43 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -591,12 +591,14 @@ EXPORT_SYMBOL_GPL(machine_check_print_event_info);
long notrace machine_check_early(struct pt_regs *regs)
{
long handled = 0;
- bool nested = in_nmi();
+ bool is_pseries_hpt_guest;
u8 ftrace_enabled = this_cpu_get_ftrace_enabled();
this_cpu_set_ftrace_enabled(0);
-
- if (!nested)
+ is_pseries_hpt_guest = machine_is(pseries) &&
+ mmu_has_feature(MMU_FTR_HPTE_TABLE);
+ /* Do not use nmi_enter/exit for pseries hpte guest */
+ if (!is_pseries_hpt_guest)
nmi_enter();
hv_nmi_check_nonrecoverable(regs);
@@ -607,7 +609,7 @@ long notrace machine_check_early(struct pt_regs *regs)
if (ppc_md.machine_check_early)
handled = ppc_md.machine_check_early(regs);
- if (!nested)
+ if (!is_pseries_hpt_guest)
nmi_exit();
this_cpu_set_ftrace_enabled(ftrace_enabled);
--
2.26.2
[PATCH v3 0/2] powerpc/mce: Fix mce handler and add selftest
This patch series fixes mce handling for pseries, Adds LKDTM test for SLB multihit recovery and enables selftest for the same, basically to test MCE handling on pseries/powernv machines running in hash mmu mode. v3: * Merging selftest changes with patch 2/2, Instead of having separate patch. * Minor improvements like adding enough comments, Makefile changes, including header file and adding some prints. v2: * Remove in_nmi check before calling nmi_enter/exit, as nesting is supported. * Fix build errors and remove unused variables. * Integrate error injection code into LKDTM. * Add support to inject multihit in paca. Ganesh Goudar (2): powerpc/mce: remove nmi_enter/exit from real mode handler lkdtm/powerpc: Add SLB multihit test arch/powerpc/kernel/mce.c | 10 +- drivers/misc/lkdtm/Makefile | 1 + drivers/misc/lkdtm/core.c | 3 + drivers/misc/lkdtm/lkdtm.h | 3 + drivers/misc/lkdtm/powerpc.c| 156 tools/testing/selftests/lkdtm/tests.txt | 1 + 6 files changed, 170 insertions(+), 4 deletions(-) create mode 100644 drivers/misc/lkdtm/powerpc.c -- 2.26.2
[PATCH] powerpc: Send SIGBUS from machine_check
Embedded PPC CPU should send SIGBUS to user space when applicable.
Signed-off-by: Joakim Tjernlund
---
arch/powerpc/kernel/traps.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 0381242920d9..12715d24141c 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -621,6 +621,11 @@ int machine_check_e500mc(struct pt_regs *regs)
reason & MCSR_MEA ? "Effective" : "Physical", addr);
}
+ if ((user_mode(regs))) {
+ _exception(SIGBUS, regs, reason, regs->nip);
+ recoverable = 1;
+ }
+
silent_out:
mtspr(SPRN_MCSR, mcsr);
return mfspr(SPRN_MCSR) == 0 && recoverable;
@@ -665,6 +670,10 @@ int machine_check_e500(struct pt_regs *regs)
if (reason & MCSR_BUS_RPERR)
printk("Bus - Read Parity Error\n");
+ if ((user_mode(regs))) {
+ _exception(SIGBUS, regs, reason, regs->nip);
+ return 1;
+ }
return 0;
}
@@ -695,6 +704,10 @@ int machine_check_e200(struct pt_regs *regs)
if (reason & MCSR_BUS_WRERR)
printk("Bus - Write Bus Error on buffered store or cache line
push\n");
+ if ((user_mode(regs))) {
+ _exception(SIGBUS, regs, reason, regs->nip);
+ return 1;
+ }
return 0;
}
#elif defined(CONFIG_PPC32)
@@ -731,6 +744,10 @@ int machine_check_generic(struct pt_regs *regs)
default:
printk("Unknown values in msr\n");
}
+ if ((user_mode(regs))) {
+ _exception(SIGBUS, regs, reason, regs->nip);
+ return 1;
+ }
return 0;
}
#endif /* everything else */
--
2.26.2
[PATCH] powerpc/32s: Setup the early hash table at all time.
At the time being, an early hash table is set up when
CONFIG_KASAN is selected.
There is nothing wrong with setting such an early hash table
all the time, even if it is not used. This is a statically
allocated 256 kB table which lies in the init data section.
This makes the code simpler and may in the future allow to
setup early IO mappings with fixmap instead of hard coding BATs.
Put create_hpte() and flush_hash_pages() in the .ref.text section
in order to avoid warning for the reference to early_hash[]. This
reference is removed by MMU_init_hw_patch() before init memory is
freed.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 13 +
arch/powerpc/mm/book3s32/hash_low.S | 9 +++--
arch/powerpc/mm/book3s32/mmu.c| 14 +-
arch/powerpc/mm/kasan/kasan_init_32.c | 19 ---
4 files changed, 17 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 2bd0aa3a4cc7..b5458113e0b0 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -166,9 +166,9 @@ __after_mmu_off:
bl initial_bats
bl load_segment_registers
-#ifdef CONFIG_KASAN
+BEGIN_MMU_FTR_SECTION
bl early_hash_table
-#endif
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
#if defined(CONFIG_BOOTX_TEXT)
bl setup_disp_bat
#endif
@@ -953,7 +953,6 @@ _ENTRY(__restore_cpu_setup)
* Load stuff into the MMU. Intended to be called with
* IR=0 and DR=0.
*/
-#ifdef CONFIG_KASAN
early_hash_table:
sync/* Force all PTE updates to finish */
isync
@@ -964,8 +963,10 @@ early_hash_table:
lis r6, early_hash - PAGE_OFFSET@h
ori r6, r6, 3 /* 256kB table */
mtspr SPRN_SDR1, r6
+ lis r6, early_hash@h
+ lis r3, Hash@ha
+ stw r6, Hash@l(r3)
blr
-#endif
load_up_mmu:
sync/* Force all PTE updates to finish */
@@ -1055,11 +1056,7 @@ start_here:
bl machine_init
bl __save_cpu_setup
bl MMU_init
-#ifdef CONFIG_KASAN
-BEGIN_MMU_FTR_SECTION
bl MMU_init_hw_patch
-END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
-#endif
/*
* Go back to running unmapped so we can load up new values
diff --git a/arch/powerpc/mm/book3s32/hash_low.S
b/arch/powerpc/mm/book3s32/hash_low.S
index 1690d369688b..8fc594ff7286 100644
--- a/arch/powerpc/mm/book3s32/hash_low.S
+++ b/arch/powerpc/mm/book3s32/hash_low.S
@@ -15,6 +15,7 @@
*/
#include
+#include
#include
#include
#include
@@ -287,9 +288,9 @@ _ASM_NOKPROBE_SYMBOL(add_hash_page)
*
* For speed, 4 of the instructions get patched once the size and
* physical address of the hash table are known. These definitions
- * of Hash_base and Hash_bits below are just an example.
+ * of Hash_base and Hash_bits below are for the early hash table.
*/
-Hash_base = 0xc018
+Hash_base = early_hash
Hash_bits = 12 /* e.g. 256kB hash table */
Hash_msk = (((1 << Hash_bits) - 1) * 64)
@@ -310,6 +311,7 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64)
#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
#define HASH_RIGHT 31-LG_PTEG_SIZE
+__REF
_GLOBAL(create_hpte)
/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
rlwinm r8,r5,32-9,30,30/* _PAGE_RW -> PP msb */
@@ -476,6 +478,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
sync/* make sure pte updates get to memory */
blr
+ .previous
_ASM_NOKPROBE_SYMBOL(create_hpte)
.section .bss
@@ -496,6 +499,7 @@ htab_hash_searches:
*
* We assume that there is a hash table in use (Hash != 0).
*/
+__REF
_GLOBAL(flush_hash_pages)
/*
* We disable interrupts here, even on UP, because we want
@@ -632,6 +636,7 @@ _GLOBAL(flush_hash_pages)
SYNC_601
isync
blr
+ .previous
EXPORT_SYMBOL(flush_hash_pages)
_ASM_NOKPROBE_SYMBOL(flush_hash_pages)
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index d426eaf76bb0..3cf1177738ea 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -31,6 +31,8 @@
#include
+u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};
+
struct hash_pte *Hash;
static unsigned long Hash_size, Hash_mask;
unsigned long _SDR1;
@@ -425,15 +427,6 @@ void __init MMU_init_hw(void)
hash_mb2 = hash_mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
if (lg_n_hpteg > 16)
hash_mb2 = 16 - LG_HPTEG_SIZE;
-
- /*
-* When KASAN is selected, there is already an early temporary hash
-* table and the switch to the final hash table is done later.
-*/
- if (IS_ENABLED(CONFIG_KASAN))
- return;
-
- MMU_init_hw_patch();
}
void __init MMU_init_hw_patch(void)
@@ -441,6 +434,9 @@ void __init
Re: [PATCH v3 devicetree 1/2] powerpc: dts: t1040: add bindings for Seville Ethernet switch
On Thu, Oct 01, 2020 at 04:20:12PM +0300, Vladimir Oltean wrote: > Add the description of the embedded L2 switch inside the SoC dtsi file > for NXP T1040. > > Signed-off-by: Vladimir Oltean > Reviewed-by: Maxim Kochetkov Reviewed-by: Andrew Lunn Andrew
Re: [PATCH v3 devicetree 2/2] powerpc: dts: t1040rdb: add ports for Seville Ethernet switch
On Thu, Oct 01, 2020 at 04:20:13PM +0300, Vladimir Oltean wrote: > Define the network interface names for the switch ports and hook them up > to the 2 QSGMII PHYs that are onboard. > > A conscious decision was taken to go along with the numbers that are > written on the front panel of the board and not with the hardware > numbers of the switch chip ports. The 2 numbering schemes are > shifted by 8. > > Signed-off-by: Vladimir Oltean > Reviewed-by: Maxim Kochetkov Reviewed-by: Andrew Lunn Andrew
[PATCH v3 devicetree 2/2] powerpc: dts: t1040rdb: add ports for Seville Ethernet switch
Define the network interface names for the switch ports and hook them up
to the 2 QSGMII PHYs that are onboard.
A conscious decision was taken to go along with the numbers that are
written on the front panel of the board and not with the hardware
numbers of the switch chip ports. The 2 numbering schemes are
shifted by 8.
Signed-off-by: Vladimir Oltean
Reviewed-by: Maxim Kochetkov
---
Changes in v3:
Renamed interfaces from swpN to ETHN, as per Andrew Lunn's suggestion.
Changes in v2:
Use the existing way of accessing the mdio bus and not labels.
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 107 +
1 file changed, 107 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index 65ff34c49025..e4067f3d2980 100644
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -64,6 +64,40 @@ mdio@fc000 {
phy_sgmii_2: ethernet-phy@3 {
reg = <0x03>;
};
+
+ /* VSC8514 QSGMII PHY */
+ phy_qsgmii_0: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ phy_qsgmii_1: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ phy_qsgmii_2: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ phy_qsgmii_3: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+
+ /* VSC8514 QSGMII PHY */
+ phy_qsgmii_4: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ phy_qsgmii_5: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ phy_qsgmii_6: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ phy_qsgmii_7: ethernet-phy@b {
+ reg = <0xb>;
+ };
};
};
};
@@ -76,3 +110,76 @@ cpld@3,0 {
};
#include "t1040si-post.dtsi"
+
+_switch {
+ status = "okay";
+};
+
+_port0 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_0>;
+ phy-mode = "qsgmii";
+ label = "ETH4";
+ status = "okay";
+};
+
+_port1 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_1>;
+ phy-mode = "qsgmii";
+ label = "ETH5";
+ status = "okay";
+};
+
+_port2 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_2>;
+ phy-mode = "qsgmii";
+ label = "ETH6";
+ status = "okay";
+};
+
+_port3 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_3>;
+ phy-mode = "qsgmii";
+ label = "ETH7";
+ status = "okay";
+};
+
+_port4 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_4>;
+ phy-mode = "qsgmii";
+ label = "ETH8";
+ status = "okay";
+};
+
+_port5 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_5>;
+ phy-mode = "qsgmii";
+ label = "ETH9";
+ status = "okay";
+};
+
+_port6 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_6>;
+ phy-mode = "qsgmii";
+ label = "ETH10";
+ status = "okay";
+};
+
+_port7 {
+ managed = "in-band-status";
+ phy-handle = <_qsgmii_7>;
+ phy-mode = "qsgmii";
+ label = "ETH11";
+ status = "okay";
+};
+
+_port8 {
+ ethernet = <>;
+ status = "okay";
+};
--
2.25.1
[PATCH v3 devicetree 1/2] powerpc: dts: t1040: add bindings for Seville Ethernet switch
Add the description of the embedded L2 switch inside the SoC dtsi file
for NXP T1040.
Signed-off-by: Vladimir Oltean
Reviewed-by: Maxim Kochetkov
---
Changes in v3:
Added definition for frame extraction interrupt, even if the driver
doesn't use it at the moment.
Changes in v2:
Make switch node disabled by default.
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 78 +
1 file changed, 78 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 315d0557eefc..f58eb820eb5e 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -628,6 +628,84 @@ mdio@fd000 {
status = "disabled";
};
};
+
+ seville_switch: ethernet-switch@80 {
+ compatible = "mscc,vsc9953-switch";
+ reg = <0x80 0x29>;
+ interrupts = <26 2 0 0>;
+ interrupt-names = "xtr";
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ seville_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ seville_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ seville_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ seville_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ seville_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+
+ seville_port5: port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+
+ seville_port6: port@6 {
+ reg = <6>;
+ status = "disabled";
+ };
+
+ seville_port7: port@7 {
+ reg = <7>;
+ status = "disabled";
+ };
+
+ seville_port8: port@8 {
+ reg = <8>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ seville_port9: port@9 {
+ reg = <9>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+ };
+ };
};
{
--
2.25.1
[PATCH v3 devicetree 0/2] Add Seville Ethernet switch to T1040RDB
Seville is a DSA switch that is embedded inside the T1040 SoC, and supported by the mscc_seville DSA driver inside drivers/net/dsa/ocelot. This series adds this switch to the SoC's dtsi files and to the T1040RDB board file. Vladimir Oltean (2): powerpc: dts: t1040: add bindings for Seville Ethernet switch powerpc: dts: t1040rdb: add ports for Seville Ethernet switch arch/powerpc/boot/dts/fsl/t1040rdb.dts | 107 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 78 ++ 2 files changed, 185 insertions(+) -- 2.25.1
[PATCH 6/6] powerpc/time: Make get_tb() common to PPC32 and PPC64
mftbu() is always defined now, so the #ifdef can be removed
and replaced by an IS_ENABLED(CONFIG_PPC64) inside the
PPC32 version of get_tb().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/time.h | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 01b054b9766f..418edaba8bd0 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -74,16 +74,13 @@ static inline u64 get_vtb(void)
return 0;
}
-#ifdef CONFIG_PPC64
-static inline u64 get_tb(void)
-{
- return mftb();
-}
-#else /* CONFIG_PPC64 */
static inline u64 get_tb(void)
{
unsigned int tbhi, tblo, tbhi2;
+ if (IS_ENABLED(CONFIG_PPC64))
+ return mftb();
+
do {
tbhi = mftbu();
tblo = mftb();
@@ -92,7 +89,6 @@ static inline u64 get_tb(void)
return ((u64)tbhi << 32) | tblo;
}
-#endif /* !CONFIG_PPC64 */
static inline u64 get_tb_or_rtc(void)
{
--
2.25.0
[PATCH 5/6] powerpc/time: Make get_tbl() common to PPC32 and PPC64
On PPC64, get_tbl() is defined as an alias of get_tb() which return
the result of mftb(). That exactly the same as what the PPC32 version
does. We don't need two versions.
Remove the PPC64 definition of get_tbl() and use the PPC32 version
for both.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/time.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index c4ea81c966b0..01b054b9766f 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -41,18 +41,11 @@ struct div_result {
/* Accessor functions for the timebase (RTC on 601) registers. */
#define __USE_RTC()(IS_ENABLED(CONFIG_PPC_BOOK3S_601))
-#ifdef CONFIG_PPC64
-
/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
-#define get_tblget_tb
-
-#else
-
static inline unsigned long get_tbl(void)
{
return mftb();
}
-#endif /* !CONFIG_PPC64 */
static inline unsigned int get_rtcl(void)
{
--
2.25.0
[PATCH 3/6] powerpc/time: Avoid using get_tbl() and get_tbu() internally
get_tbl() is confusing as it returns the content of TBL register
on PPC32 but the concatenation of TBL and TBU on PPC64.
Use mftb() instead.
Do the same with get_tbu() for consistency allthough it's name
is less confusing.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/delay.h | 2 +-
arch/powerpc/include/asm/time.h | 8
arch/powerpc/kernel/time.c | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/asm/delay.h
index 66963f7d3e64..51bb8c1476c7 100644
--- a/arch/powerpc/include/asm/delay.h
+++ b/arch/powerpc/include/asm/delay.h
@@ -54,7 +54,7 @@ extern void udelay(unsigned long usecs);
({
\
typeof(condition) __ret; \
unsigned long __loops = tb_ticks_per_usec * timeout; \
- unsigned long __start = get_tbl(); \
+ unsigned long __start = mftb(); \
\
if (delay) { \
while (!(__ret = (condition)) && \
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index b0fb8456305f..3ef0f4b3299e 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -97,9 +97,9 @@ static inline u64 get_tb(void)
unsigned int tbhi, tblo, tbhi2;
do {
- tbhi = get_tbu();
- tblo = get_tbl();
- tbhi2 = get_tbu();
+ tbhi = mftbu();
+ tblo = mftb();
+ tbhi2 = mftbu();
} while (tbhi != tbhi2);
return ((u64)tbhi << 32) | tblo;
@@ -153,7 +153,7 @@ static inline unsigned long tb_ticks_since(unsigned long
tstamp)
int delta = get_rtcl() - (unsigned int) tstamp;
return delta < 0 ? delta + 10 : delta;
}
- return get_tbl() - tstamp;
+ return mftb() - tstamp;
}
#define mulhwu(x,y) \
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index f85539ebb513..a9cbd5a61585 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -467,8 +467,8 @@ void __delay(unsigned long loops)
*/
spin_cpu_relax();
} else {
- start = get_tbl();
- while (get_tbl() - start < loops)
+ start = mftb();
+ while (mftb() - start < loops)
spin_cpu_relax();
}
spin_end();
--
2.25.0
[PATCH 1/6] powerpc/time: Rename mftbl() to mftb()
On PPC64, we have mftb().
On PPC32, we have mftbl() and an #define mftb() mftbl().
mftb() and mftbl() are equivalent, their purpose is to read the
content of SPRN_TRBL, as returned by 'mftb' simplified instruction.
binutils seems to define 'mftbl' instruction as an equivalent
of 'mftb'.
However in both 32 bits and 64 bits documentation, only 'mftb' is
defined, and when performing a disassembly with objdump, the displayed
instruction is 'mftb'
No need to have two ways to do the same thing with different
names, rename mftbl() to have only mftb().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 5 ++---
arch/powerpc/include/asm/time.h | 2 +-
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 788058af1d44..c66dcdb47c44 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1439,19 +1439,18 @@ static inline void msr_check_and_clear(unsigned long
bits)
#else /* __powerpc64__ */
#if defined(CONFIG_PPC_8xx)
-#define mftbl()({unsigned long rval; \
+#define mftb() ({unsigned long rval; \
asm volatile("mftbl %0" : "=r" (rval)); rval;})
#define mftbu()({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
#else
-#define mftbl()({unsigned long rval; \
+#define mftb() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRL)); rval;})
#define mftbu()({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;})
#endif
-#define mftb() mftbl()
#endif /* !__powerpc64__ */
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index a80abf64c8a5..b0fb8456305f 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -50,7 +50,7 @@ struct div_result {
static inline unsigned long get_tbl(void)
{
- return mftbl();
+ return mftb();
}
static inline unsigned int get_tbu(void)
--
2.25.0
[PATCH 4/6] powerpc/time: Remove get_tbu()
get_tbu() is redundant with mftbu() and is not used anymore.
Remove it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/time.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 3ef0f4b3299e..c4ea81c966b0 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -52,11 +52,6 @@ static inline unsigned long get_tbl(void)
{
return mftb();
}
-
-static inline unsigned int get_tbu(void)
-{
- return mftbu();
-}
#endif /* !CONFIG_PPC64 */
static inline unsigned int get_rtcl(void)
--
2.25.0
[PATCH 2/6] powerpc/time: Make mftb() common to PPC32 and PPC64
No need to have two versions that are identical.
CONFIG_PPC_CELL is only selected by PPC64 targets.
CONFIG_E500 is the only PPC64 target selecting CONFIG_FSL_BOOK3E.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c66dcdb47c44..f877a576b338 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1419,8 +1419,7 @@ static inline void msr_check_and_clear(unsigned long bits)
__msr_check_and_clear(bits);
}
-#ifdef __powerpc64__
-#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
+#if defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)
#define mftb() ({unsigned long rval; \
asm volatile( \
"90:mfspr %0, %2;\n"\
@@ -1430,28 +1429,23 @@ static inline void msr_check_and_clear(unsigned long
bits)
: "=r" (rval) \
: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
rval;})
+#elif defined(CONFIG_PPC_8xx)
+#define mftb() ({unsigned long rval; \
+ asm volatile("mftbl %0" : "=r" (rval)); rval;})
#else
#define mftb() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : \
"=r" (rval) : "i" (SPRN_TBRL)); rval;})
#endif /* !CONFIG_PPC_CELL */
-#else /* __powerpc64__ */
-
#if defined(CONFIG_PPC_8xx)
-#define mftb() ({unsigned long rval; \
- asm volatile("mftbl %0" : "=r" (rval)); rval;})
#define mftbu()({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
#else
-#define mftb() ({unsigned long rval; \
- asm volatile("mfspr %0, %1" : "=r" (rval) : \
- "i" (SPRN_TBRL)); rval;})
#define mftbu()({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;})
#endif
-#endif /* !__powerpc64__ */
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
--
2.25.0
[PATCH] powerpc/time: Remove ifdef in get_dec() and set_dec()
Move SPRN_PIT definition in reg.h.
This allows to remove ifdef in get_dec() and set_dec() and
makes them more readable.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/include/asm/reg_booke.h | 1 -
arch/powerpc/include/asm/time.h | 23 ++-
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index d25c357a873c..788058af1d44 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -521,6 +521,8 @@
#define SPRN_TSCR 0x399 /* Thread Switch Control Register */
#define SPRN_DEC 0x016 /* Decrement Register */
+#define SPRN_PIT 0x3DB /* Programmable Interval Timer
(40x/BOOKE) */
+
#define SPRN_DER 0x095 /* Debug Enable Register */
#define DER_RSTE 0x4000 /* Reset Interrupt */
#define DER_CHSTPE 0x2000 /* Check Stop */
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index ff30f1076162..29a948e0c0f2 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -174,7 +174,6 @@
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_MMUCFG0x3F7 /* MMU Configuration Register */
-#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
#define SPRN_L2CSR10x3FA /* L2 Data Cache Control and Status Register 1
*/
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 6c663a382a75..a80abf64c8a5 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -126,11 +126,10 @@ static inline void set_tb(unsigned int upper, unsigned
int lower)
*/
static inline u64 get_dec(void)
{
-#if defined(CONFIG_40x)
- return (mfspr(SPRN_PIT));
-#else
- return (mfspr(SPRN_DEC));
-#endif
+ if (IS_ENABLED(CONFIG_40x))
+ return mfspr(SPRN_PIT);
+
+ return mfspr(SPRN_DEC);
}
/*
@@ -140,14 +139,12 @@ static inline u64 get_dec(void)
*/
static inline void set_dec(u64 val)
{
-#if defined(CONFIG_40x)
- mtspr(SPRN_PIT, (u32) val);
-#else
-#ifndef CONFIG_BOOKE
- --val;
-#endif
- mtspr(SPRN_DEC, val);
-#endif /* not 40x */
+ if (IS_ENABLED(CONFIG_40x))
+ mtspr(SPRN_PIT, (u32)val);
+ else if (IS_ENABLED(CONFIG_BOOKE))
+ mtspr(SPRN_DEC, val);
+ else
+ mtspr(SPRN_DEC, val - 1);
}
static inline unsigned long tb_ticks_since(unsigned long tstamp)
--
2.25.0
[PATCH] powerpc/time: Remove ifdef in get_vtb()
SPRN_VTB and CPU_FTR_ARCH_207S are always defined,
no need of an ifdef.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/time.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index cb326720a8a1..6c663a382a75 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -80,10 +80,9 @@ static inline u64 get_rtc(void)
static inline u64 get_vtb(void)
{
-#ifdef CONFIG_PPC_BOOK3S_64
if (cpu_has_feature(CPU_FTR_ARCH_207S))
return mfspr(SPRN_VTB);
-#endif
+
return 0;
}
--
2.25.0
Re: [RFC PATCH next-20200930] treewide: Convert macro and uses of __section(foo) to __section("foo")
Hi Joe, On Thu, Oct 1, 2020 at 12:56 AM Joe Perches wrote: > > So I installed the powerpc cross compiler, and > nope, that doesn't work, it makes a mess. Thanks a lot for reviving the script and sending the treewide cleanup! > So it looks like the best option is to exclude these > 2 files from conversion. Agreed. Nevertheless, is there any reason arch/powerpc/* should not be compiling cleanly with compiler.h? (CC'ing the rest of the PowerPC reviewers and ML). Cheers, Miguel
