Re: [PATCH] mm: remove kern_addr_valid() completely
On Tue, Oct 18, 2022 at 3:21 PM Kefeng Wang wrote:
>
> Most architectures(except arm64/x86/sparc) simply return 1 for
> kern_addr_valid(), which is only used in read_kcore(), and it
> calls copy_from_kernel_nofault() which could check whether the
> address is a valid kernel address, so no need kern_addr_valid(),
> let's remove unneeded kern_addr_valid() completely.
>
> Signed-off-by: Kefeng Wang
> ---
> arch/alpha/include/asm/pgtable.h | 2 -
> arch/arc/include/asm/pgtable-bits-arcv2.h | 2 -
> arch/arm/include/asm/pgtable-nommu.h | 2 -
> arch/arm/include/asm/pgtable.h| 4 --
> arch/arm64/include/asm/pgtable.h | 2 -
> arch/arm64/mm/mmu.c | 47 ---
> arch/arm64/mm/pageattr.c | 3 +-
> arch/csky/include/asm/pgtable.h | 3 --
> arch/hexagon/include/asm/page.h | 7
> arch/ia64/include/asm/pgtable.h | 16
> arch/loongarch/include/asm/pgtable.h | 2 -
> arch/m68k/include/asm/pgtable_mm.h| 2 -
> arch/m68k/include/asm/pgtable_no.h| 1 -
> arch/microblaze/include/asm/pgtable.h | 3 --
> arch/mips/include/asm/pgtable.h | 2 -
> arch/nios2/include/asm/pgtable.h | 2 -
> arch/openrisc/include/asm/pgtable.h | 2 -
> arch/parisc/include/asm/pgtable.h | 15
> arch/powerpc/include/asm/pgtable.h| 7
> arch/riscv/include/asm/pgtable.h | 2 -
> arch/s390/include/asm/pgtable.h | 2 -
> arch/sh/include/asm/pgtable.h | 2 -
> arch/sparc/include/asm/pgtable_32.h | 6 ---
> arch/sparc/mm/init_32.c | 3 +-
> arch/sparc/mm/init_64.c | 1 -
> arch/um/include/asm/pgtable.h | 2 -
> arch/x86/include/asm/pgtable_32.h | 9 -
> arch/x86/include/asm/pgtable_64.h | 1 -
> arch/x86/mm/init_64.c | 41
> arch/xtensa/include/asm/pgtable.h | 2 -
> fs/proc/kcore.c | 26 +
> 31 files changed, 11 insertions(+), 210 deletions(-)
>
> diff --git a/arch/alpha/include/asm/pgtable.h
> b/arch/alpha/include/asm/pgtable.h
> index 3ea9661c09ff..9e45f6735d5d 100644
> --- a/arch/alpha/include/asm/pgtable.h
> +++ b/arch/alpha/include/asm/pgtable.h
> @@ -313,8 +313,6 @@ extern inline pte_t mk_swap_pte(unsigned long type,
> unsigned long offset)
> #define __pte_to_swp_entry(pte)((swp_entry_t) { pte_val(pte) })
> #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
>
> -#define kern_addr_valid(addr) (1)
> -
> #define pte_ERROR(e) \
> printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
> #define pmd_ERROR(e) \
> diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h
> b/arch/arc/include/asm/pgtable-bits-arcv2.h
> index b23be557403e..515e82db519f 100644
> --- a/arch/arc/include/asm/pgtable-bits-arcv2.h
> +++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
> @@ -120,8 +120,6 @@ void update_mmu_cache(struct vm_area_struct *vma,
> unsigned long address,
> #define __pte_to_swp_entry(pte)((swp_entry_t) { pte_val(pte)
> })
> #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
>
> -#define kern_addr_valid(addr) (1)
> -
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> #include
> #endif
> diff --git a/arch/arm/include/asm/pgtable-nommu.h
> b/arch/arm/include/asm/pgtable-nommu.h
> index d16aba48fa0a..25d8c7bb07e0 100644
> --- a/arch/arm/include/asm/pgtable-nommu.h
> +++ b/arch/arm/include/asm/pgtable-nommu.h
> @@ -21,8 +21,6 @@
> #define pgd_none(pgd) (0)
> #define pgd_bad(pgd) (0)
> #define pgd_clear(pgdp)
> -#define kern_addr_valid(addr) (1)
> -/* FIXME */
> /*
> * PMD_SHIFT determines the size of the area a second-level page table can
> map
> * PGDIR_SHIFT determines what a third-level page table entry can map
> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
> index 78a532068fec..00954ab1a039 100644
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -298,10 +298,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t
> newprot)
> */
> #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
> __SWP_TYPE_BITS)
>
> -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
> -/* FIXME: this is not correct */
> -#define kern_addr_valid(addr) (1)
> -
> /*
> * We provide our own arch_get_unmapped_area to cope with VIPT caches.
> */
> diff --git a/arch/arm64/include/asm/pgtable.h
> b/arch/arm64/include/asm/pgtable.h
> index 71a1af42f0e8..4873c1d6e7d0 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -1021,8 +1021,6 @@ static inline pmd_t pmdp_establish(struct
> vm_area_struct *vma,
> */
> #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
> __SWP_TYPE_BITS)
>
> -extern int
[powerpc:fixes-test] BUILD SUCCESS dc398a084d459f065658855454e09f2778f8c5cc
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes-test branch HEAD: dc398a084d459f065658855454e09f2778f8c5cc powerpc/64s/interrupt: Perf NMI should not take normal exit path elapsed time: 799m configs tested: 56 configs skipped: 118 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: powerpc allnoconfig powerpc allmodconfig i386 randconfig-a012 i386 randconfig-a014 i386 randconfig-a016 i386 allyesconfig i386defconfig mips allyesconfig x86_64 rhel-8.3-func x86_64rhel-8.3-kselftests xtensa audio_kc705_defconfig arc tb10x_defconfig openrisc simple_smp_defconfig arm64allyesconfig arm defconfig arm allyesconfig powerpc stx_gp3_defconfig powerpc currituck_defconfig powerpc mpc834x_mds_defconfig arc randconfig-r043-20221018 s390 randconfig-r044-20221018 riscvrandconfig-r042-20221018 x86_64randconfig-a011 x86_64randconfig-a013 x86_64randconfig-a015 x86_64 rhel-8.3-kvm x86_64 rhel-8.3-syz x86_64 rhel-8.3-kunit x86_64 defconfig x86_64 allyesconfig x86_64 rhel-8.3 i386 randconfig-c001 s390defconfig s390 allmodconfig arc defconfig alpha defconfig s390 allyesconfig m68k allyesconfig m68k allmodconfig arc allyesconfig alphaallyesconfig um x86_64_defconfig um i386_defconfig clang tested configs: x86_64randconfig-c007 mips randconfig-c004-20221018 i386 randconfig-c001 s390 randconfig-c005-20221018 arm randconfig-c002-20221018 riscvrandconfig-c006-20221018 powerpc randconfig-c003-20221018 i386 randconfig-a002 i386 randconfig-a006 i386 randconfig-a004 x86_64randconfig-a005 x86_64randconfig-a003 x86_64randconfig-a001 x86_64randconfig-k001 -- 0-DAY CI Kernel Test Service https://01.org/lkp
[powerpc:fixes] BUILD SUCCESS 2147783d6bf0b7ca14c72a25527dc5135bd17f65
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes branch HEAD: 2147783d6bf0b7ca14c72a25527dc5135bd17f65 powerpc/pseries: Use lparcfg to reconfig VAS windows for DLPAR CPU elapsed time: 721m configs tested: 90 configs skipped: 109 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: powerpc allnoconfig powerpc allmodconfig um x86_64_defconfig um i386_defconfig x86_64 rhel-8.3-kvm x86_64 rhel-8.3-syz x86_64 rhel-8.3-kunit x86_64randconfig-a011 x86_64randconfig-a013 x86_64randconfig-a015 s390defconfig s390 allmodconfig arc defconfig alpha defconfig s390 allyesconfig mips allyesconfig sh allmodconfig sh sh7724_generic_defconfig ia64 tiger_defconfig microblaze mmu_defconfig powerpc ppc6xx_defconfig xtensa audio_kc705_defconfig arc tb10x_defconfig openrisc simple_smp_defconfig arc randconfig-r043-20221018 s390 randconfig-r044-20221018 riscvrandconfig-r042-20221018 x86_64 rhel-8.3-func x86_64rhel-8.3-kselftests i386 allyesconfig i386defconfig x86_64 defconfig x86_64 allyesconfig x86_64 rhel-8.3 i386 randconfig-c001 m68k allyesconfig m68k allmodconfig arc allyesconfig alphaallyesconfig arm64allyesconfig arm defconfig arm allyesconfig i386 randconfig-a012 i386 randconfig-a014 i386 randconfig-a016 powerpc stx_gp3_defconfig powerpc currituck_defconfig powerpc mpc834x_mds_defconfig ia64 allmodconfig x86_64randconfig-a006 x86_64randconfig-a004 x86_64randconfig-a002 armspear6xx_defconfig arm assabet_defconfig mips decstation_r4k_defconfig armmvebu_v7_defconfig nios2 defconfig m68k amiga_defconfig openrisc alldefconfig arm jornada720_defconfig sh r7780mp_defconfig arm axm55xx_defconfig ia64generic_defconfig arm tegra_defconfig powerpc chrp32_defconfig mips db1xxx_defconfig powerpc storcenter_defconfig powerpc canyonlands_defconfig sh urquell_defconfig clang tested configs: i386 randconfig-a002 i386 randconfig-a006 i386 randconfig-a004 x86_64randconfig-a005 x86_64randconfig-a003 x86_64randconfig-a001 x86_64randconfig-k001 x86_64randconfig-c007 mips randconfig-c004-20221018 i386 randconfig-c001 s390 randconfig-c005-20221018 arm randconfig-c002-20221018 riscvrandconfig-c006-20221018 powerpc randconfig-c003-20221018 arm tct_hammer_defconfig riscv allnoconfig i386 randconfig-a013-20221017 i386 randconfig-a015-20221017 i386 randconfig-a016-20221017 i386 randconfig-a011-20221017 i386 randconfig-a014-20221017 i386 randconfig-a012-20221017 -- 0-DAY CI Kernel Test Service https://01.org/lkp
Re: [PATCH] powerpc/perf: Fix hv-24x7 metric events for power10
Em Tue, Oct 18, 2022 at 09:24:44AM +0530, Madhavan Srinivasan escreveu:
>
> On 10/17/22 7:03 PM, Arnaldo Carvalho de Melo wrote:
> > Em Fri, Oct 14, 2022 at 07:32:20PM +0530, Kajol Jain escreveu:
> > > Testcase stat_all_metrics.sh fails in powerpc:
> > >
> > > 90: perf all metrics test : FAILED!
> > >
> > > The testcase "stat_all_metrics.sh" verifies perf stat
> > > result for all the metric events present in perf list.
> > > It runs perf metric events with various commands and
> > > expects non-empty metric result.
> > >
> > > Incase of powerpc:hv-24x7 events, some of the event count can
> > > be 0 based on system configuration. And if that event used as
> > > denominator in divide equation, it can cause divide by 0
> > > error. The current nest_metric.json file creating divide by 0
> > > issue for some of the metric events, which results in failure
> > > of the "stat_all_metrics.sh" test case.
> > >
> > > Most of the metrics events have cycles or an event which
> > > expect to have a larger value as denominator, so adding 1
> > > to the denominator of the metric expression as a fix.
> > >
> > > Result in powerpc box after this patch changes:
> > >
> > > 90: perf all metrics test : Ok
> > Looks ok, applied. Next time please try to ask others to provide a
> > Reviewed-by or at least an Acked-by.
> Reviewed-by: Madhavan Srinivasan
> I did review this patch yesterday. But missed to send my reviewed-by. My
> bad.
No problem, thanks for reviewing, since the patch is still in my local
tree, I just added your Reviewed-by.
Thanks!
- Arnaldo
> Maddy
> >
> > - Arnaldo
> >
> > > Fixes: a3cbcadfdfc3 ("perf vendor events power10: Adds 24x7 nest
> > > metric events for power10 platform")
> > > Signed-off-by: Kajol Jain
> > > ---
> > > .../arch/powerpc/power10/nest_metrics.json| 72 +--
> > > 1 file changed, 36 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> > > b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> > > index 8ba3e81c9808..fe050d44374b 100644
> > > --- a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> > > +++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> > > @@ -1,13 +1,13 @@
> > > [
> > > {
> > > "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> > > - "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ /
> > > hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
> > > + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / (1 +
> > > hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@)) * 100",
> > > "ScaleUnit": "1%",
> > > "AggregationMode": "PerChip"
> > > },
> > > {
> > > "MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> > > - "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ /
> > > hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
> > > + "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / (1 +
> > > hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@)) * 100",
> > > "ScaleUnit": "1%",
> > > "AggregationMode": "PerChip"
> > > },
> > > @@ -61,13 +61,13 @@
> > > },
> > > {
> > > "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> > > - "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ /
> > > hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
> > > + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / (1 +
> > > hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@)) * 100",
> > > "ScaleUnit": "1%",
> > > "AggregationMode": "PerChip"
> > > },
> > > {
> > > "MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> > > - "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ /
> > > hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
> > > + "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / (1 +
> > > hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@)) * 100",
> > > "ScaleUnit": "1%",
> > > "AggregationMode": "PerChip"
> > > },
> > > @@ -151,193 +151,193 @@
> > > },
> > > {
> > > "MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
> > > - "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@
> > > + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) /
> > > (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ +
> > > hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> > > + "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@
> > > + hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (1 +
> > > hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ +
> > > hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> > > "ScaleUnit": "1%",
> > > "AggregationMode": "PerChip"
> > > },
> > > {
> > > "MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
> > > - "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@
> > > + hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) /
> > >
[PATCH v7 2/8] dt-bindings: phy: Add Lynx 10G phy binding
This adds a binding for the SerDes module found on QorIQ processors. Each phy is a subnode of the top-level device, possibly supporting multiple lanes and protocols. This "thick" #phy-cells is used due to allow for better organization of parameters. Note that the particular parameters necessary to select a protocol-controller/lane combination vary across different SoCs, and even within different SerDes on the same SoC. The driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski --- Changes in v7: - Use double quotes everywhere in yaml Changes in v6: - fsl,type -> phy-type Changes in v4: - Use subnodes to describe lane configuration, instead of describing PCCRs. This is the same style used by phy-cadence-sierra et al. Changes in v3: - Manually expand yaml references - Add mode configuration to device tree Changes in v2: - Rename to fsl,lynx-10g.yaml - Refer to the device in the documentation, rather than the binding - Move compatible first - Document phy cells in the description - Allow a value of 1 for phy-cells. This allows for compatibility with the similar (but according to Ioana Ciornei different enough) lynx-28g binding. - Remove minItems - Use list for clock-names - Fix example binding having too many cells in regs - Add #clock-cells. This will allow using assigned-clocks* to configure the PLLs. - Document the structure of the compatible strings .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 236 ++ 1 file changed, 236 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index ..f326fdc159c5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx 10G SerDes + +maintainers: + - Sean Anderson + +description: | + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The + SerDes provides up to eight lanes. Each lane may be configured individually, + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and + others. The specific protocols supported for each lane depend on the + particular SoC. + +properties: + compatible: +items: + - enum: + - fsl,ls1046a-serdes + - fsl,ls1088a-serdes + - const: fsl,lynx-10g + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + "#clock-cells": +const: 1 +description: | + The cell contains an ID as described in dt-bindings/clock/fsl,lynx-10g.h. + Note that when assigning a rate to a PLL, the PLL's rate is divided by + 1000 to avoid overflow. A rate of 500 corresponds to 5GHz. + + clocks: +maxItems: 2 +description: | + Clock for each PLL reference clock input. + + clock-names: +minItems: 2 +maxItems: 2 +items: + enum: +- ref0 +- ref1 + + reg: +maxItems: 1 + +patternProperties: + "^phy@": +type: object + +description: | + A contiguous group of lanes which will be configured together. Each group + corresponds to one phy device. Lanes not described by any group will be + left as-is. + +properties: + "#phy-cells": +const: 0 + + reg: +minItems: 1 +maxItems: 8 +description: + The lanes in the group. These must be listed in order. The first lane + will have the FIRST_LANE bit set in GCR0. The order of lanes also + determines the reset order (TRSTDIR). + +patternProperties: + "^(q?sgmii|xfi)": +type: object + +description: | + A protocol controller which may control the group of lanes. Each + controller is selected through the PCCRs. In addition to protocols + desired for use by the OS, protocols which may have been configured + by the bootloader must also be described. This ensures that only one + protocol controller is attached to a group of lanes at once. + +properties: + fsl,pccr: +$ref: /schemas/types.yaml#/definitions/uint32 +description: | + The index of the PCCR which configures
[PATCH v7 8/8] [WIP] arm64: dts: ls1088ardb: Add serdes bindings
This is a first stab at adding serdes support on the LS1088A. Linux
hangs around when the serdes is initialized if the si5341 is enabled, so
it's commented out. The MC firmware needs to be fairly new (it must
support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE), and the DPC needs to set the
macs to MAC_LINK_TYPE_BACKPLANE. For this reason, I think this will be
difficult to do in a backwards-compatible manner. I have not finished
testing this, but hopefully it can be a good starting point.
Signed-off-by: Sean Anderson
---
(no changes since v4)
Changes in v4:
- Convert to new bindings
.../boot/dts/freescale/fsl-ls1088a-rdb.dts| 161 ++
1 file changed, 161 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 1bfbce69cc8b..5c502048d887 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -10,17 +10,138 @@
/dts-v1/;
+#include
+
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clocks {
+ si5341_xtal: clock-48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4800>;
+ };
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625>;
+ };
+ };
+
+ ovdd: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ovdd";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+
+ dvdd: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+};
+
+ {
+ //clocks = < 0 8>, < 0 9>;
+ clocks = <_100mhz>, <_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+
+ serdes1_0: phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* SG2 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+
+ /* XFI2 */
+ xfi-1 {
+ fsl,pccr = <0xb>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_1: phy@1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* SG1 */
+ sgmii-2 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+
+ /*
+* XFI2
+* Table 23-1 and section 23.5.16.4 disagree; this reflects the
+* table.
+*/
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_2: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* QSGb */
+ qsgmii-1 {
+ fsl,pccr = <0x9>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_3: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* QSGa */
+ qsgmii-0 {
+ fsl,pccr = <0x9>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+};
+
+ {
+ phys = <_1>;
};
{
phy-handle = <_aquantia_phy>;
phy-connection-type = "10gbase-r";
pcs-handle = <>;
+ phys = <_0>;
};
{
@@ -28,6 +149,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_0>;
+ phys = <_3>;
};
{
@@ -35,6 +157,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_1>;
+ phys = <_3>;
};
{
@@ -42,6 +165,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle =
[PATCH v7 7/8] arm64: dts: ls1046ardb: Add serdes bindings
This adds appropriate bindings for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Because this will break ethernet if the serdes is not enabled, enable
the serdes driver by default on Layerscape.
Signed-off-by: Sean Anderson
---
This depends on [1].
[1]
https://lore.kernel.org/netdev/20220804194705.459670-4-sean.ander...@seco.com/
(no changes since v6)
Changes in v6:
- XGI.9 -> XFI.9
Changes in v4:
- Convert to new bindings
.../boot/dts/freescale/fsl-ls1046a-rdb.dts| 112 ++
drivers/phy/freescale/Kconfig | 1 +
2 files changed, 113 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 7025aad8ae89..81d725a15e27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -10,6 +10,8 @@
/dts-v1/;
+#include
+
#include "fsl-ls1046a.dtsi"
/ {
@@ -26,8 +28,110 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ clocks {
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625>;
+ };
+ };
};
+ {
+ clocks = <_100mhz>, <_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+
+ /*
+* XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin
+* numbers are _reversed_. In addition, the PCCR documentation is
+* _inconsistent_ in its usage of these terms!
+*
+* PCCR "Lane 0" refers to...
+* =
+*0 Lane A
+*2 Lane A
+*8 Lane A
+*9 Lane A
+*B Lane D!
+*/
+ serdes1_0: phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* SGMII.6 */
+ sgmii-0 {
+ fsl,pccr = <0x8>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_1: phy@1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* SGMII.5 */
+ sgmii-1 {
+ fsl,pccr = <0x8>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_2: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* SGMII.10 */
+ sgmii-2 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+
+ /* XFI.10 */
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ phy-type = ;
+ };
+ };
+
+ serdes1_3: phy@3 {
+ #phy-cells = <0>;
+ reg = <3>;
+
+ /* SGMII.9 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+
+ /* XFI.9 */
+ xfi-9 {
+ fsl,pccr = <0xb>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = ;
+ };
+ };
+};
+
+
{
status = "okay";
};
@@ -140,21 +244,29 @@ ethernet@e6000 {
ethernet@e8000 {
phy-handle = <_phy1>;
phy-connection-type = "sgmii";
+ phys = <_1>;
+ phy-names = "serdes";
};
ethernet@ea000 {
phy-handle = <_phy2>;
phy-connection-type = "sgmii";
+ phys = <_0>;
+ phy-names = "serdes";
};
ethernet@f { /* 10GEC1 */
phy-handle = <_phy>;
phy-connection-type = "xgmii";
+ phys = <_3>;
+ phy-names = "serdes";
};
[PATCH v7 6/8] arm64: dts: ls1088a: Add serdes bindings
This adds bindings for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v4)
Changes in v4:
- Convert to new bindings
Changes in v3:
- New
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 421d879013d7..3810d66f8725 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -238,6 +238,24 @@ reset: syscon@1e6 {
reg = <0x0 0x1e6 0x0 0x1>;
};
+ serdes1: serdes@1ea {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea 0x0 0x2000>;
+ status = "disabled";
+ };
+
+ serdes2: serdes@1eb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1eb 0x0 0x2000>;
+ status = "disabled";
+ };
+
isc: syscon@1f7 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f7 0x0 0x1>;
--
2.35.1.1320.gc452695387.dirty
[PATCH v7 5/8] arm64: dts: ls1046a: Add serdes bindings
This adds bindings for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v4)
Changes in v4:
- Convert to new bindings
Changes in v3:
- Describe modes in device tree
Changes in v2:
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3d9e29824bb2..8f986b4f5efc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -423,6 +423,24 @@ sfp: efuse@1e8 {
clock-names = "sfp";
};
+ serdes1: serdes@1ea {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea 0x0 0x2000>;
+ status = "disabled";
+ };
+
+ serdes2: serdes@1eb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1eb 0x0 0x2000>;
+ status = "disabled";
+ };
+
dcfg: dcfg@1ee {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee 0x0 0x1000>;
--
2.35.1.1320.gc452695387.dirty
[PATCH v7 4/8] phy: fsl: Add Lynx 10G SerDes driver
This adds support for the Lynx 10G "SerDes" devices found on various NXP QorIQ SoCs. There may be up to four SerDes devices on each SoC, each supporting up to eight lanes. Protocol support for each SerDes is highly heterogeneous, with each SoC typically having a totally different selection of supported protocols for each lane. Additionally, the SerDes devices on each SoC also have differing support. One SerDes will typically support Ethernet on most lanes, while the other will typically support PCIe on most lanes. There is wide hardware support for this SerDes. It is present on QorIQ T-Series and Layerscape processors. Because each SoC typically has specific instructions and exceptions for its SerDes, I have limited the initial scope of this module to just the LS1046A and LS1088A. Additionally, I have only added support for Ethernet protocols. There is not a great need for dynamic reconfiguration for other protocols (except perhaps for M.2 cards), so support for them may never be added. Nevertheless, I have tried to provide an obvious path for adding support for other SoCs as well as other protocols. SATA just needs support for configuring LNmSSCR0. PCIe may need to configure the equalization registers. It also uses multiple lanes. I have tried to write the driver with multi-lane support in mind, so there should not need to be any large changes. Although there are 6 protocols supported, I have only tested SGMII and XFI. The rest have been implemented as described in the datasheet. Most of these protocols should work "as-is", but 10GBASE-KR will need PCS support for link training. The PLLs are modeled as clocks proper. This lets us take advantage of the existing clock infrastructure. I have not given the same treatment to the per-lane clocks because they need to be programmed in-concert with the rest of the lane settings. One tricky thing is that the VCO (PLL) rate exceeds 2^32 (maxing out at around 5GHz). This will be a problem on 32-bit platforms, since clock rates are stored as unsigned longs. To work around this, the pll clock rate is generally treated in units of kHz. The PLLs are configured rather interestingly. Instead of the usual direct programming of the appropriate divisors, the input and output clock rates are selected directly. Generally, the only restriction is that the input and output must be integer multiples of each other. This suggests some kind of internal look-up table. The datasheets generally list out the supported combinations explicitly, and not all input/output combinations are documented. I'm not sure if this is due to lack of support, or due to an oversight. If this becomes an issue, then some combinations can be blacklisted (or whitelisted). This may also be necessary for other SoCs which have more stringent clock requirements. Unlike some other phys where e.g. PCIe x4 will use 4 separate phys all configured for PCIe, this driver uses one phy configured to use 4 lanes. This is because while the individual lanes may be configured individually, the protocol selection acts on all lanes at once. Additionally, the order which lanes should be configured in is specified by the datasheet. To coordinate this, lanes are reserved in phy_init, and released in phy_exit. This driver was written with reference to the LS1046A reference manual. However, it was informed by reference manuals for all processors with mEMACs, especially the T4240 (which appears to have a "maxed-out" configuration). The earlier P-series processors appear to be similar, but have a different overall register layout (using "banks" instead of separate SerDes). Perhaps this those use a "5G Lynx SerDes." Signed-off-by: Sean Anderson --- Changes in v7: - Break out call order into generic documentation - Refuse to switch "major" protocols - Update Kconfig to reflect restrictions - Remove set/clear of "pcs reset" bit, since it doesn't seem to fix anything. Changes in v6: - Update MAINTAINERS to include new files - Include bitfield.h and slab.h to allow compilation on non-arm64 arches. - Depend on COMMON_CLK and either layerscape/ppc Changes in v5: - Remove references to PHY_INTERFACE_MODE_1000BASEKX to allow this series to be applied directly to linux/master. - Add fsl,lynx-10g.h to MAINTAINERS Changes in v4: - Rework all debug statements to remove use of __func__. Additional information has been provided as necessary. - Consider alternative parent rates in round_rate and not in set_rate. Trying to modify out parent's rate in set_rate will deadlock. - Explicitly perform a stop/reset sequence in set_rate. This way we always ensure that the PLL is properly stopped. - Set the power-down bit when disabling the PLL. We can do this now that enable/disable aren't abused during the set rate sequence. - Fix typos in QSGMII_OFFSET and XFI_OFFSET - Rename LNmTECR0_TEQ_TYPE_PRE to LNmTECR0_TEQ_TYPE_POST to better reflect its function (adding post-cursor equalization). - Use of_clk_hw_onecell_get instead of a
[PATCH v7 3/8] dt-bindings: clock: Add ids for Lynx 10g PLLs
This adds ids for the Lynx 10g SerDes's internal PLLs. These may be used with assigned-clock* to specify a particular frequency to use. For example, to set the second PLL (at offset 0x20)'s frequency, use LYNX10G_PLLa(1). These are for use only in the device tree, and are not otherwise used by the driver. Signed-off-by: Sean Anderson Acked-by: Rob Herring --- (no changes since v6) Changes in v6: - frequence -> frequency Changes in v5: - Update commit description - Dual id header Changes in v4: - New include/dt-bindings/clock/fsl,lynx-10g.h | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/fsl,lynx-10g.h diff --git a/include/dt-bindings/clock/fsl,lynx-10g.h b/include/dt-bindings/clock/fsl,lynx-10g.h new file mode 100644 index ..15362ae85304 --- /dev/null +++ b/include/dt-bindings/clock/fsl,lynx-10g.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#ifndef __DT_BINDINGS_CLK_LYNX_10G_H +#define __DT_BINDINGS_CLK_LYNX_10G_H + +#define LYNX10G_CLKS_PER_PLL 2 + +#define LYNX10G_PLLa(a)((a) * LYNX10G_CLKS_PER_PLL) +#define LYNX10G_PLLa_EX_DLY(a) ((a) * LYNX10G_CLKS_PER_PLL + 1) + +#endif /* __DT_BINDINGS_CLK_LYNX_10G_H */ -- 2.35.1.1320.gc452695387.dirty
[PATCH v7 0/8] phy: Add support for Lynx 10G SerDes
This adds support for the Lynx 10G SerDes found on the QorIQ T-series and Layerscape series. Due to limited time and hardware, only support for the LS1046ARDB is added in this initial series. There is a sketch for LS1088ARDB support, but it is incomplete. Dynamic reconfiguration does not work. That is, the configuration must match what is set in the RCW. From my testing, SerDes register settings appear identical. The issue appears to be between the PCS and the MAC. The link itself comes up at both ends, and a mac loopback succeeds. However, a PCS loopback results in dropped packets. Perhaps there is some undocumented register in the PCS? I suspect this driver is around 95% complete, but, unfortunately, I no longer have time to investigate this further. At the very least it is useful for two cases: - Although this is untested, it should support 2.5G SGMII as well as 1000BASE-KX. The latter needs MAC and PCS support, but the former should work out of the box. - It allows for clock configurations not supported by the RCW. This is very useful if you want to use e.g. SRDS_PRTCL_S1=0x and =0x1133 on the same board. This is because the former setting will use PLL1 as the 1G reference, but the latter will use PLL1 as the 10G reference. Because we can reconfigure the PLLs, it is possible to always use PLL1 as the 1G reference. Changes in v7: - Use double quotes everywhere in yaml - Break out call order into generic documentation - Refuse to switch "major" protocols - Update Kconfig to reflect restrictions - Remove set/clear of "pcs reset" bit, since it doesn't seem to fix anything. Changes in v6: - Bump PHY_TYPE_2500BASEX to 13, since PHY_TYPE_USXGMII was added in the meantime - fsl,type -> phy-type - frequence -> frequency - Update MAINTAINERS to include new files - Include bitfield.h and slab.h to allow compilation on non-arm64 arches. - Depend on COMMON_CLK and either layerscape/ppc - XGI.9 -> XFI.9 Changes in v5: - Update commit description - Dual id header - Remove references to PHY_INTERFACE_MODE_1000BASEKX to allow this series to be applied directly to linux/master. - Add fsl,lynx-10g.h to MAINTAINERS Changes in v4: - Add 2500BASE-X and 10GBASE-R phy types - Use subnodes to describe lane configuration, instead of describing PCCRs. This is the same style used by phy-cadence-sierra et al. - Add ids for Lynx 10g PLLs - Rework all debug statements to remove use of __func__. Additional information has been provided as necessary. - Consider alternative parent rates in round_rate and not in set_rate. Trying to modify out parent's rate in set_rate will deadlock. - Explicitly perform a stop/reset sequence in set_rate. This way we always ensure that the PLL is properly stopped. - Set the power-down bit when disabling the PLL. We can do this now that enable/disable aren't abused during the set rate sequence. - Fix typos in QSGMII_OFFSET and XFI_OFFSET - Rename LNmTECR0_TEQ_TYPE_PRE to LNmTECR0_TEQ_TYPE_POST to better reflect its function (adding post-cursor equalization). - Use of_clk_hw_onecell_get instead of a custom function. - Return struct clks from lynx_clks_init instead of embedding lynx_clk in lynx_priv. - Rework PCCR helper functions; T-series SoCs differ from Layerscape SoCs primarily in the layout and offset of the PCCRs. This will help bring a cleaner abstraction layer. The caps have been removed, since this handles the only current usage. - Convert to use new binding format. As a result of this, we no longer need to have protocols for PCIe or SATA. Additionally, modes now live in lynx_group instead of lynx_priv. - Remove teq from lynx_proto_params, since it can be determined from preq_ratio/postq_ratio. - Fix an early return from lynx_set_mode not releasing serdes->lock. - Rename lynx_priv.conf to .cfg, since I kept mistyping it. Changes in v3: - Manually expand yaml references - Add mode configuration to device tree - Rename remaining references to QorIQ SerDes to Lynx 10G - Fix PLL enable sequence by waiting for our reset request to be cleared before continuing. Do the same for the lock, even though it isn't as critical. Because we will delay for 1.5ms on average, use prepare instead of enable so we can sleep. - Document the status of each protocol - Fix offset of several bitfields in RECR0 - Take into account PLLRST_B, SDRST_B, and SDEN when considering whether a PLL is "enabled." - Only power off unused lanes. - Split mode lane mask into first/last lane (like group) - Read modes from device tree - Use caps to determine whether KX/KR are supported - Move modes to lynx_priv - Ensure that the protocol controller is not already in-use when we try to configure a new mode. This should only occur if the device tree is misconfigured (e.g. when QSGMII is selected on two lanes but there is only one QSGMII controller). - Split PLL drivers off into their own file - Add clock for "ext_dly" instead of writing the bit directly (and racing
[PATCH v7 1/8] dt-bindings: phy: Add 2500BASE-X and 10GBASE-R
This adds some modes necessary for Lynx 10G support. 2500BASE-X, also known as 2.5G SGMII, is 1000BASE-X/SGMII overclocked to 3.125 GHz, with autonegotiation disabled. 10GBASE-R, also known as XFI, is the protocol spoken between the PMA and PMD ethernet layers for 10GBASE-T and 10GBASE-S/L/E. It is typically used to communicate directly with SFP+ modules, or with 10GBASE-T phys. Signed-off-by: Sean Anderson Acked-by: Rob Herring --- PR increasing phy-type maximum [1]. If this commit could be applied sooner rather than later, I'd appreciate it. This should help avoid another respin if someone else adds another phy type. [1] https://github.com/devicetree-org/dt-schema/pull/85 (no changes since v6) Changes in v6: - Bump PHY_TYPE_2500BASEX to 13, since PHY_TYPE_USXGMII was added in the meantime Changes in v4: - New include/dt-bindings/phy/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 6b901b342348..5b2b674d8d25 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -23,5 +23,7 @@ #define PHY_TYPE_DPHY 10 #define PHY_TYPE_CPHY 11 #define PHY_TYPE_USXGMII 12 +#define PHY_TYPE_2500BASEX 13 +#define PHY_TYPE_10GBASER 14 #endif /* _DT_BINDINGS_PHY */ -- 2.35.1.1320.gc452695387.dirty
Re: [PATCH] mm: remove kern_addr_valid() completely
On 2022/10/18 15:40, Kefeng Wang wrote:
Most architectures(except arm64/x86/sparc) simply return 1 for
one space before the opening parens
kern_addr_valid(), which is only used in read_kcore(), and it
calls copy_from_kernel_nofault() which could check whether the
address is a valid kernel address, so no need kern_addr_valid(),
minor grammatical nit:
"... which already checks whether the address is a valid kernel address.
So kern_addr_valid is unnecessary, let's remove it."
let's remove unneeded kern_addr_valid() completely.
Signed-off-by: Kefeng Wang
---
arch/alpha/include/asm/pgtable.h | 2 -
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 -
arch/arm/include/asm/pgtable-nommu.h | 2 -
arch/arm/include/asm/pgtable.h| 4 --
arch/arm64/include/asm/pgtable.h | 2 -
arch/arm64/mm/mmu.c | 47 ---
arch/arm64/mm/pageattr.c | 3 +-
arch/csky/include/asm/pgtable.h | 3 --
arch/hexagon/include/asm/page.h | 7
arch/ia64/include/asm/pgtable.h | 16
arch/loongarch/include/asm/pgtable.h | 2 -
arch/m68k/include/asm/pgtable_mm.h| 2 -
arch/m68k/include/asm/pgtable_no.h| 1 -
arch/microblaze/include/asm/pgtable.h | 3 --
arch/mips/include/asm/pgtable.h | 2 -
arch/nios2/include/asm/pgtable.h | 2 -
arch/openrisc/include/asm/pgtable.h | 2 -
arch/parisc/include/asm/pgtable.h | 15
arch/powerpc/include/asm/pgtable.h| 7
arch/riscv/include/asm/pgtable.h | 2 -
arch/s390/include/asm/pgtable.h | 2 -
arch/sh/include/asm/pgtable.h | 2 -
arch/sparc/include/asm/pgtable_32.h | 6 ---
arch/sparc/mm/init_32.c | 3 +-
arch/sparc/mm/init_64.c | 1 -
arch/um/include/asm/pgtable.h | 2 -
arch/x86/include/asm/pgtable_32.h | 9 -
arch/x86/include/asm/pgtable_64.h | 1 -
arch/x86/mm/init_64.c | 41
arch/xtensa/include/asm/pgtable.h | 2 -
fs/proc/kcore.c | 26 +
31 files changed, 11 insertions(+), 210 deletions(-)
diff --git a/arch/loongarch/include/asm/pgtable.h
b/arch/loongarch/include/asm/pgtable.h
index 946704bee599..fc70b7041b76 100644
--- a/arch/loongarch/include/asm/pgtable.h
+++ b/arch/loongarch/include/asm/pgtable.h
@@ -421,8 +421,6 @@ static inline void update_mmu_cache_pmd(struct
vm_area_struct *vma,
__update_tlb(vma, address, (pte_t *)pmdp);
}
-#define kern_addr_valid(addr) (1)
-
static inline unsigned long pmd_pfn(pmd_t pmd)
{
return (pmd_val(pmd) & _PFN_MASK) >> _PFN_SHIFT;
Acked-by: WANG Xuerui # loongarch
Thanks!
--
WANG "xen0n" Xuerui
Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/
Re: [PATCH] mm: remove kern_addr_valid() completely
On 10/18/22 09:40, Kefeng Wang wrote:
Most architectures(except arm64/x86/sparc) simply return 1 for
kern_addr_valid(), which is only used in read_kcore(), and it
calls copy_from_kernel_nofault() which could check whether the
address is a valid kernel address, so no need kern_addr_valid(),
let's remove unneeded kern_addr_valid() completely.
Signed-off-by: Kefeng Wang
Acked-by: Helge Deller # parisc
Thanks!
Helge
---
arch/alpha/include/asm/pgtable.h | 2 -
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 -
arch/arm/include/asm/pgtable-nommu.h | 2 -
arch/arm/include/asm/pgtable.h| 4 --
arch/arm64/include/asm/pgtable.h | 2 -
arch/arm64/mm/mmu.c | 47 ---
arch/arm64/mm/pageattr.c | 3 +-
arch/csky/include/asm/pgtable.h | 3 --
arch/hexagon/include/asm/page.h | 7
arch/ia64/include/asm/pgtable.h | 16
arch/loongarch/include/asm/pgtable.h | 2 -
arch/m68k/include/asm/pgtable_mm.h| 2 -
arch/m68k/include/asm/pgtable_no.h| 1 -
arch/microblaze/include/asm/pgtable.h | 3 --
arch/mips/include/asm/pgtable.h | 2 -
arch/nios2/include/asm/pgtable.h | 2 -
arch/openrisc/include/asm/pgtable.h | 2 -
arch/parisc/include/asm/pgtable.h | 15
arch/powerpc/include/asm/pgtable.h| 7
arch/riscv/include/asm/pgtable.h | 2 -
arch/s390/include/asm/pgtable.h | 2 -
arch/sh/include/asm/pgtable.h | 2 -
arch/sparc/include/asm/pgtable_32.h | 6 ---
arch/sparc/mm/init_32.c | 3 +-
arch/sparc/mm/init_64.c | 1 -
arch/um/include/asm/pgtable.h | 2 -
arch/x86/include/asm/pgtable_32.h | 9 -
arch/x86/include/asm/pgtable_64.h | 1 -
arch/x86/mm/init_64.c | 41
arch/xtensa/include/asm/pgtable.h | 2 -
fs/proc/kcore.c | 26 +
31 files changed, 11 insertions(+), 210 deletions(-)
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 3ea9661c09ff..9e45f6735d5d 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -313,8 +313,6 @@ extern inline pte_t mk_swap_pte(unsigned long type,
unsigned long offset)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
-
#define pte_ERROR(e) \
printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h
b/arch/arc/include/asm/pgtable-bits-arcv2.h
index b23be557403e..515e82db519f 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -120,8 +120,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned
long address,
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
-
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#include
#endif
diff --git a/arch/arm/include/asm/pgtable-nommu.h
b/arch/arm/include/asm/pgtable-nommu.h
index d16aba48fa0a..25d8c7bb07e0 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -21,8 +21,6 @@
#define pgd_none(pgd) (0)
#define pgd_bad(pgd) (0)
#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-/* FIXME */
/*
* PMD_SHIFT determines the size of the area a second-level page table can map
* PGDIR_SHIFT determines what a third-level page table entry can map
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 78a532068fec..00954ab1a039 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -298,10 +298,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
*/
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
__SWP_TYPE_BITS)
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-/* FIXME: this is not correct */
-#define kern_addr_valid(addr) (1)
-
/*
* We provide our own arch_get_unmapped_area to cope with VIPT caches.
*/
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 71a1af42f0e8..4873c1d6e7d0 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -1021,8 +1021,6 @@ static inline pmd_t pmdp_establish(struct vm_area_struct
*vma,
*/
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
__SWP_TYPE_BITS)
-extern int kern_addr_valid(unsigned long addr);
-
#ifdef CONFIG_ARM64_MTE
#define __HAVE_ARCH_PREPARE_TO_SWAP
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index
Re: [PATCH] mm: remove kern_addr_valid() completely
Thanks, this is long overdue! Acked-by: Christoph Hellwig
Re: [PATCH] mm: remove kern_addr_valid() completely
On Tue, Oct 18, 2022 at 03:40:14PM +0800, Kefeng Wang wrote: > Most architectures(except arm64/x86/sparc) simply return 1 for > kern_addr_valid(), which is only used in read_kcore(), and it > calls copy_from_kernel_nofault() which could check whether the > address is a valid kernel address, so no need kern_addr_valid(), > let's remove unneeded kern_addr_valid() completely. > > Signed-off-by: Kefeng Wang > --- ... > arch/s390/include/asm/pgtable.h | 2 - For s390: Acked-by: Heiko Carstens
Re: [PATCH] mm: remove kern_addr_valid() completely
On Tue, Oct 18, 2022 at 9:25 AM Kefeng Wang wrote:
> Most architectures(except arm64/x86/sparc) simply return 1 for
> kern_addr_valid(), which is only used in read_kcore(), and it
> calls copy_from_kernel_nofault() which could check whether the
> address is a valid kernel address, so no need kern_addr_valid(),
> let's remove unneeded kern_addr_valid() completely.
>
> Signed-off-by: Kefeng Wang
> arch/m68k/include/asm/pgtable_mm.h| 2 -
> arch/m68k/include/asm/pgtable_no.h| 1 -
Acked-by: Geert Uytterhoeven [m68k]
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH] mm: remove kern_addr_valid() completely
Most architectures(except arm64/x86/sparc) simply return 1 for
kern_addr_valid(), which is only used in read_kcore(), and it
calls copy_from_kernel_nofault() which could check whether the
address is a valid kernel address, so no need kern_addr_valid(),
let's remove unneeded kern_addr_valid() completely.
Signed-off-by: Kefeng Wang
---
arch/alpha/include/asm/pgtable.h | 2 -
arch/arc/include/asm/pgtable-bits-arcv2.h | 2 -
arch/arm/include/asm/pgtable-nommu.h | 2 -
arch/arm/include/asm/pgtable.h| 4 --
arch/arm64/include/asm/pgtable.h | 2 -
arch/arm64/mm/mmu.c | 47 ---
arch/arm64/mm/pageattr.c | 3 +-
arch/csky/include/asm/pgtable.h | 3 --
arch/hexagon/include/asm/page.h | 7
arch/ia64/include/asm/pgtable.h | 16
arch/loongarch/include/asm/pgtable.h | 2 -
arch/m68k/include/asm/pgtable_mm.h| 2 -
arch/m68k/include/asm/pgtable_no.h| 1 -
arch/microblaze/include/asm/pgtable.h | 3 --
arch/mips/include/asm/pgtable.h | 2 -
arch/nios2/include/asm/pgtable.h | 2 -
arch/openrisc/include/asm/pgtable.h | 2 -
arch/parisc/include/asm/pgtable.h | 15
arch/powerpc/include/asm/pgtable.h| 7
arch/riscv/include/asm/pgtable.h | 2 -
arch/s390/include/asm/pgtable.h | 2 -
arch/sh/include/asm/pgtable.h | 2 -
arch/sparc/include/asm/pgtable_32.h | 6 ---
arch/sparc/mm/init_32.c | 3 +-
arch/sparc/mm/init_64.c | 1 -
arch/um/include/asm/pgtable.h | 2 -
arch/x86/include/asm/pgtable_32.h | 9 -
arch/x86/include/asm/pgtable_64.h | 1 -
arch/x86/mm/init_64.c | 41
arch/xtensa/include/asm/pgtable.h | 2 -
fs/proc/kcore.c | 26 +
31 files changed, 11 insertions(+), 210 deletions(-)
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 3ea9661c09ff..9e45f6735d5d 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -313,8 +313,6 @@ extern inline pte_t mk_swap_pte(unsigned long type,
unsigned long offset)
#define __pte_to_swp_entry(pte)((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
-
#define pte_ERROR(e) \
printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
diff --git a/arch/arc/include/asm/pgtable-bits-arcv2.h
b/arch/arc/include/asm/pgtable-bits-arcv2.h
index b23be557403e..515e82db519f 100644
--- a/arch/arc/include/asm/pgtable-bits-arcv2.h
+++ b/arch/arc/include/asm/pgtable-bits-arcv2.h
@@ -120,8 +120,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned
long address,
#define __pte_to_swp_entry(pte)((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-#define kern_addr_valid(addr) (1)
-
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#include
#endif
diff --git a/arch/arm/include/asm/pgtable-nommu.h
b/arch/arm/include/asm/pgtable-nommu.h
index d16aba48fa0a..25d8c7bb07e0 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -21,8 +21,6 @@
#define pgd_none(pgd) (0)
#define pgd_bad(pgd) (0)
#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-/* FIXME */
/*
* PMD_SHIFT determines the size of the area a second-level page table can map
* PGDIR_SHIFT determines what a third-level page table entry can map
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 78a532068fec..00954ab1a039 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -298,10 +298,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
*/
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
__SWP_TYPE_BITS)
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-/* FIXME: this is not correct */
-#define kern_addr_valid(addr) (1)
-
/*
* We provide our own arch_get_unmapped_area to cope with VIPT caches.
*/
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 71a1af42f0e8..4873c1d6e7d0 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -1021,8 +1021,6 @@ static inline pmd_t pmdp_establish(struct vm_area_struct
*vma,
*/
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT >
__SWP_TYPE_BITS)
-extern int kern_addr_valid(unsigned long addr);
-
#ifdef CONFIG_ARM64_MTE
#define __HAVE_ARCH_PREPARE_TO_SWAP
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 9a7c38965154..556154d821bf 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -814,53 +814,6 @@ void __init paging_init(void)
Re: [PATCH] ASoC: fsl_micfil: Add Hardware Voice Activity Detector support
On Fri, 23 Sep 2022 17:31:34 +0800, Shengjiu Wang wrote: > The Hardware Voice Activity Detector (HWVAD) is a block > responsible for detect voice activity in a channel selected > by the user. It can be configured in Envelope-based or > Energy-based mode. > > There are additional two interrupts for HWVAD, one is event > interrupt, another is error interrupt. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl_micfil: Add Hardware Voice Activity Detector support commit: 29dbfeecab85fc998d8c5c29473da33d272d0c85 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: [PATCH v3 0/7] Create a new sound card to access MICFIL based on rpmsg channel
On Fri, 30 Sep 2022 14:44:34 +0800, Chancel Liu wrote: > At a previous time, we have successfully created a virtual sound card > based on rpmsg. The sound card works under this mechanism Cortex-A core > tells the Cortex-M core the format, rate, channel, .etc configuration > of the PCM parameters and Cortex-M controls real hardware devices such > as SAI and DMA. From the view of Linux side, the sound card is bound to > a rpmsg channel through which it can access SAI. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/7] ASoC: dt-bindings: fsl_rpmsg: Add a property to assign the rpmsg channel commit: 3570e6873b1a506bca4b5788d71141944c55132c [2/7] ASoC: imx-audio-rpmsg: Create rpmsg channel for MICFIL commit: f04189e0b85f6bbd10679e71061bf6d1ced5c539 [3/7] ASoC: imx-pcm-rpmsg: Register different platform drivers commit: b2c2a947b3412f6edb9a86f5b12d6420958e67ba [4/7] ASoC: imx-pcm-rpmsg: Multi-channel support for sound card based on rpmsg commit: bdc0f6ca1c079ba790e0e227cff6164feae90460 [5/7] ASoC: fsl_rpmsg: Register different ASoC machine devices commit: 76a874caeab596972f529968aa0d19d4ba1d2197 [6/7] ASoC: fsl_rpmsg: Multi-channel support in CPU DAI driver commit: f26c1bb8a8ebe72748a3bb6f5d75079b642a33e8 [7/7] ASoC: imx-rpmsg: Assign platform driver used by machine driver to link with commit: 4b48440ea390bada41928920446928beb3652a76 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
Re: sched/debug: CPU hotplug operation suffers in a large cpu systems
On Tue, Oct 18, 2022 at 04:07:06PM +0530, Vishal Chourasia wrote: > On Mon, Oct 17, 2022 at 04:54:11PM +0200, Greg Kroah-Hartman wrote: > > On Mon, Oct 17, 2022 at 04:19:31PM +0200, Peter Zijlstra wrote: > > > > > > +GregKH who actually knows about debugfs. > > > > > > On Mon, Oct 17, 2022 at 06:40:49PM +0530, Vishal Chourasia wrote: > > > > smt=off operation on system with 1920 CPUs is taking approx 59 mins on > > > > v5.14 > > > > versus 29 mins on v5.11 measured using: > > > > # time ppc64_cpu --smt=off > > > > > > > > > > > > |++--| > > > > | method | sysctl | debugfs | > > > > |++--| > > > > | unregister_sysctl_table| 0.020050 s | NA | > > > > | build_sched_domains| 3.090563 s | 3.119130 s | > > > > | register_sched_domain_sysctl | 0.065487 s | NA | > > > > | update_sched_domain_debugfs| NA | 2.791232 s | > > > > | partition_sched_domains_locked | 3.195958 s | 5.933254 s | > > > > |++--| > > > > > > > > Note: partition_sched_domains_locked internally calls > > > > build_sched_domains > > > > and calls other functions respective to what's being currently > > > > used to > > > > export information i.e. sysctl or debugfs > > > > > > > > Above numbers are quoted from the case where we tried offlining 1 cpu > > > > in system > > > > with 1920 online cpus. > > > > > > > > From the above table, register_sched_domain_sysctl and > > > > unregister_sysctl_table collectively took ~0.085 secs, whereas > > > > update_sched_domain_debugfs took ~2.79 secs. > > > > > > > > Root cause: > > > > > > > > The observed regression stems from the way these two pseudo-filesystems > > > > handle > > > > creation and deletion of files and directories internally. > > > > Yes, debugfs is not optimized for speed or memory usage at all. This > > happens to be the first code path I have seen that cares about this for > > debugfs files. > > > > You can either work on not creating so many debugfs files (do you really > > really need all of them all the time?) Or you can work on moving > > debugfs to use kernfs as the backend logic, which will save you both > > speed and memory usage overall as kernfs is used to being used on > > semi-fast paths. > > > > Maybe do both? > > > > hope this helps, > > > > greg k-h > > Yes, we need to create 7-8 files per domain per CPU, eventually ending up > creating a lot of files. Why do you need to? What tools require these debugfs files to be present? And if you only have 7-8 files per CPU, that does not seem like a lot of files overall (14000-16000)? If you only offline 1 cpu, how is removing 7 or 8 files a bottleneck? Do you really offline 1999 cpus for a 2k system? > Is there a possibility of reverting back to /proc/sys/kernel/sched_domain/? No, these are debugging-only things, they do not belong in /proc/ If you rely on them for real functionality, that's a different story, but I want to know what tool uses them and for what functionality as debugfs should never be relied on for normal operation of a system. thanks, greg k-h
Re: [PATCH] mm: remove kern_addr_valid() completely
Kefeng Wang writes: > Most architectures(except arm64/x86/sparc) simply return 1 for > kern_addr_valid(), which is only used in read_kcore(), and it > calls copy_from_kernel_nofault() which could check whether the > address is a valid kernel address, so no need kern_addr_valid(), > let's remove unneeded kern_addr_valid() completely. > > Signed-off-by: Kefeng Wang > --- > arch/alpha/include/asm/pgtable.h | 2 - > arch/arc/include/asm/pgtable-bits-arcv2.h | 2 - > arch/arm/include/asm/pgtable-nommu.h | 2 - > arch/arm/include/asm/pgtable.h| 4 -- > arch/arm64/include/asm/pgtable.h | 2 - > arch/arm64/mm/mmu.c | 47 --- > arch/arm64/mm/pageattr.c | 3 +- > arch/csky/include/asm/pgtable.h | 3 -- > arch/hexagon/include/asm/page.h | 7 > arch/ia64/include/asm/pgtable.h | 16 > arch/loongarch/include/asm/pgtable.h | 2 - > arch/m68k/include/asm/pgtable_mm.h| 2 - > arch/m68k/include/asm/pgtable_no.h| 1 - > arch/microblaze/include/asm/pgtable.h | 3 -- > arch/mips/include/asm/pgtable.h | 2 - > arch/nios2/include/asm/pgtable.h | 2 - > arch/openrisc/include/asm/pgtable.h | 2 - > arch/parisc/include/asm/pgtable.h | 15 > arch/powerpc/include/asm/pgtable.h| 7 Acked-by: Michael Ellerman (powerpc) cheers
Re: [PATCH AUTOSEL 5.10 04/16] powerpc/hw_breakpoint: Avoid relying on caller synchronization
Hi! > From: Marco Elver > > [ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ] > > Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint > implementation have relied on nr_bp_mutex serializing access to them. > > Before overhauling synchronization of kernel/events/hw_breakpoint.c, > introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively, > thus avoiding reliance on callers synchronizing powerpc's > hw_breakpoint. This is preparation, not a bugfix, not sure why it was picked for 5.10. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany signature.asc Description: PGP signature
[PATCH 2/2] tools/perf: Fix printing field separator in CSV metrics output
In perf stat with CSV output option, number of fields
in metrics output is not matching with number of fields
in other event output lines.
Sample output below after applying patch to fix
printing os->prefix.
# ./perf stat -x, --per-socket -a -C 1 ls
S0,1,1.89,msec,cpu-clock,1887692,100.00,1.013,CPUs utilized
S0,1,2,,context-switches,1885842,100.00,1.060,K/sec
S0,1,0,,cpu-migrations,1885374,100.00,0.000,/sec
S0,1,2,,page-faults,1884880,100.00,1.060,K/sec
S0,1,189544,,cycles,1263158,67.00,0.100,GHz
S0,1,64602,,stalled-cycles-frontend,1876146,100.00,34.08,frontend
cycles idle
S0,1,128241,,stalled-cycles-backend,1875512,100.00,67.66,backend cycles
idle
S0,1,95578,,instructions,1874676,100.00,0.50,insn per cycle
===>S0,1,,,1.34,stalled cycles per insn
The above command line uses field separator as ","
via "-x," option and per-socket option displays
socket value as first field. But here the last line
for "stalled cycles per insn" has more separators.
Each csv output line is expected to have 8 field
separatorsi (for the 9 fields), where as last line
has 10 "," in the result. Patch fixes this issue.
The counter stats are displayed by function
"perf_stat__print_shadow_stats" in code
"util/stat-shadow.c". While printing the stats info
for "stalled cycles per insn", function "new_line_csv"
is used as new_line callback.
The fields printed in each line contains:
"Socket_id,aggr nr,Avg,unit,event_name,run,enable_percent,ratio,unit"
The metric output prints Socket_id, aggr nr, ratio
and unit. It has to skip through remaining five fields
ie, Avg,unit,event_name,run,enable_percent. The csv
line callback uses "os->nfields" to know the number of
fields to skip to match with other lines.
Currently it is set as:
os.nfields = 3 + aggr_fields[config->aggr_mode] + (counter->cgrp ? 1 :
0);
But in case of aggregation modes, csv_sep already
gets printed along with each field (Function "aggr_printout"
in util/stat-display.c). So aggr_fields can be
removed from nfields. And fixed number of fields to
skip has to be "4". This is to skip fields for:
"avg, unit, event name, run, enable_percent"
Example from line for instructions:
"1.89,msec,cpu-clock,1887692,100.00"
This needs 4 csv separators. Patch removes aggr_fields
and uses 4 as fixed number of os->nfields to skip.
After the patch:
# ./perf stat -x, --per-socket -a -C 1 ls
S0,1,1.92,msec,cpu-clock,1917648,100.00,1.010,CPUs utilized
S0,1,54,,context-switches,1916762,100.00,28.176,K/sec
---
S0,1,528693,,instructions,1908854,100.00,0.36,insn per cycle
S0,1,,1.81,stalled cycles per insn
Fixes: 92a61f6412d3 ("perf stat: Implement CSV metrics output")
Reported-by: Disha Goel
Signed-off-by: Athira Rajeev
---
tools/perf/util/stat-display.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c
index 879874a4bc07..5ca151adf826 100644
--- a/tools/perf/util/stat-display.c
+++ b/tools/perf/util/stat-display.c
@@ -551,20 +551,9 @@ static void printout(struct perf_stat_config *config,
struct aggr_cpu_id id, int
new_line_t nl;
if (config->csv_output) {
- static const int aggr_fields[AGGR_MAX] = {
- [AGGR_NONE] = 1,
- [AGGR_GLOBAL] = 0,
- [AGGR_SOCKET] = 2,
- [AGGR_DIE] = 2,
- [AGGR_CORE] = 2,
- [AGGR_THREAD] = 1,
- [AGGR_UNSET] = 0,
- [AGGR_NODE] = 0,
- };
-
pm = config->metric_only ? print_metric_only_csv :
print_metric_csv;
nl = config->metric_only ? new_line_metric : new_line_csv;
- os.nfields = 3 + aggr_fields[config->aggr_mode] +
(counter->cgrp ? 1 : 0);
+ os.nfields = 4 + (counter->cgrp ? 1 : 0);
} else if (config->json_output) {
pm = config->metric_only ? print_metric_only_json :
print_metric_json;
nl = config->metric_only ? new_line_metric : new_line_json;
--
2.31.1
[PATCH 1/2] tools/perf: Fix printing os->prefix in CSV metrics output
Perf stat with CSV output option prints an extra empty
string as first field in metrics output line.
Sample output below:
# ./perf stat -x, --per-socket -a -C 1 ls
S0,1,1.78,msec,cpu-clock,1785146,100.00,0.973,CPUs utilized
S0,1,26,,context-switches,1781750,100.00,0.015,M/sec
S0,1,1,,cpu-migrations,1780526,100.00,0.561,K/sec
S0,1,1,,page-faults,1779060,100.00,0.561,K/sec
S0,1,875807,,cycles,1769826,100.00,0.491,GHz
S0,1,85281,,stalled-cycles-frontend,1767512,100.00,9.74,frontend cycles
idle
S0,1,576839,,stalled-cycles-backend,1766260,100.00,65.86,backend cycles
idle
S0,1,288430,,instructions,1762246,100.00,0.33,insn per cycle
> ,S0,1,,,2.00,stalled cycles per insn
The above command line uses field separator as ","
via "-x," option and per-socket option displays
socket value as first field. But here the last line
for "stalled cycles per insn" has "," in the
beginning.
Sample output using interval mode:
# ./perf stat -I 1000 -x, --per-socket -a -C 1 ls
0.001813453,S0,1,1.87,msec,cpu-clock,1872052,100.00,0.002,CPUs utilized
0.001813453,S0,1,2,,context-switches,1868028,100.00,1.070,K/sec
--
0.001813453,S0,1,85379,,instructions,1856754,100.00,0.32,insn per cycle
> 0.001813453,,S0,1,,,1.34,stalled cycles per insn
Above result also has an extra csv separator after
the timestamp. Patch addresses extra field separator
in the beginning of the metric output line.
The counter stats are displayed by function
"perf_stat__print_shadow_stats" in code
"util/stat-shadow.c". While printing the stats info
for "stalled cycles per insn", function "new_line_csv"
is used as new_line callback.
The new_line_csv function has check for "os->prefix"
and if prefix is not null, it will be printed along
with cvs separator.
Snippet from "new_line_csv":
if (os->prefix)
fprintf(os->fh, "%s%s", os->prefix, config->csv_sep);
Here os->prefix gets printed followed by ","
which is the cvs separator. The os->prefix is
used in interval mode option ( -I ), to print
time stamp on every new line. But prefix is
already set to contain csv separator when used
in interval mode for csv option.
Reference: Function "static void print_interval"
Snippet:
sprintf(prefix, "%6lu.%09lu%s", ts->tv_sec, ts->tv_nsec,
config->csv_sep);
Also if prefix is not assigned (if not used with
-I option), it gets set to empty string.
Reference: function printout() in util/stat-display.c
Snippet:
.prefix = prefix ? prefix : "",
Since prefix already set to contain cvs_sep in interval
option, patch removes printing config->csv_sep in
new_line_csv function to avoid printing extra field.
After the patch:
# ./perf stat -x, --per-socket -a -C 1 ls
S0,1,2.04,msec,cpu-clock,2045202,100.00,1.013,CPUs utilized
S0,1,2,,context-switches,2041444,100.00,979.289,/sec
S0,1,0,,cpu-migrations,2040820,100.00,0.000,/sec
S0,1,2,,page-faults,2040288,100.00,979.289,/sec
S0,1,254589,,cycles,2036066,100.00,0.125,GHz
S0,1,82481,,stalled-cycles-frontend,2032420,100.00,32.40,frontend
cycles idle
S0,1,113170,,stalled-cycles-backend,2031722,100.00,44.45,backend cycles
idle
S0,1,88766,,instructions,2030942,100.00,0.35,insn per cycle
S0,1,,,1.27,stalled cycles per insn
Fixes: 92a61f6412d3 ("perf stat: Implement CSV metrics output")
Reported-by: Disha Goel
Signed-off-by: Athira Rajeev
---
tools/perf/util/stat-display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c
index 5c47ee9963a7..879874a4bc07 100644
--- a/tools/perf/util/stat-display.c
+++ b/tools/perf/util/stat-display.c
@@ -273,7 +273,7 @@ static void new_line_csv(struct perf_stat_config *config,
void *ctx)
fputc('\n', os->fh);
if (os->prefix)
- fprintf(os->fh, "%s%s", os->prefix, config->csv_sep);
+ fprintf(os->fh, "%s", os->prefix);
aggr_printout(config, os->evsel, os->id, os->nr);
for (i = 0; i < os->nfields; i++)
fputs(config->csv_sep, os->fh);
--
2.31.1
Re: [PATCH] powerpc/hv-gpci: Fix hv_gpci event list
Kajol Jain writes:
> Based on getPerfCountInfo v1.018 documentation, some of the
> hv_gpci events got deprecated for platforms firmware that
> supports counter_info_version 0x8 or above.
>
> Patch fixes the hv_gpci event list by adding a new attribute
> group called "hv_gpci_event_attrs_v6" and a "EVENT_ENABLE"
> macro to enable these events for platform firmware
> that supports counter_info_version 0x6 or below.
Does this handle CPUs booted in compat mode?
ie. where the firmware is newer but the kernel is told to behave as if
the CPU is an older version - so cpu_has_feature() doesn't necessarily
match the underlying hardware.
Is there some reason the event list is populated based on the CPU
features rather than by calling the hypervisor and asking what version
is supported?
> Fixes: 97bf2640184f4 ("powerpc/perf/hv-gpci: add the remaining gpci
> requests")
Please don't wrap the fixes tag.
cheers
> Signed-off-by: Kajol Jain
> ---
> arch/powerpc/perf/hv-gpci-requests.h | 4
> arch/powerpc/perf/hv-gpci.c | 9 +++--
> arch/powerpc/perf/hv-gpci.h | 1 +
> arch/powerpc/perf/req-gen/perf.h | 17 +
> 4 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/perf/hv-gpci-requests.h
> b/arch/powerpc/perf/hv-gpci-requests.h
> index 8965b4463d43..baef3d082de9 100644
> --- a/arch/powerpc/perf/hv-gpci-requests.h
> +++ b/arch/powerpc/perf/hv-gpci-requests.h
> @@ -79,6 +79,7 @@ REQUEST(__field(0, 8, partition_id)
> )
> #include I(REQUEST_END)
>
> +#ifdef EVENT_ENABLE
> /*
> * Not available for counter_info_version >= 0x8, use
> * run_instruction_cycles_by_partition(0x100) instead.
> @@ -92,6 +93,7 @@ REQUEST(__field(0, 8, partition_id)
> __count(0x10, 8, cycles)
> )
> #include I(REQUEST_END)
> +#endif
>
> #define REQUEST_NAME system_performance_capabilities
> #define REQUEST_NUM 0x40
> @@ -103,6 +105,7 @@ REQUEST(__field(0,1, perf_collect_privileged)
> )
> #include I(REQUEST_END)
>
> +#ifdef EVENT_ENABLE
> #define REQUEST_NAME processor_bus_utilization_abc_links
> #define REQUEST_NUM 0x50
> #define REQUEST_IDX_KIND "hw_chip_id=?"
> @@ -194,6 +197,7 @@ REQUEST(__field(0,4, phys_processor_idx)
> __count(0x28, 8, instructions_completed)
> )
> #include I(REQUEST_END)
> +#endif
>
> /* Processor_core_power_mode (0x95) skipped, no counters */
> /* Affinity_domain_information_by_virtual_processor (0xA0) skipped,
> diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c
> index 5eb60ed5b5e8..065a01812b3e 100644
> --- a/arch/powerpc/perf/hv-gpci.c
> +++ b/arch/powerpc/perf/hv-gpci.c
> @@ -70,9 +70,9 @@ static const struct attribute_group format_group = {
> .attrs = format_attrs,
> };
>
> -static const struct attribute_group event_group = {
> +static struct attribute_group event_group = {
> .name = "events",
> - .attrs = hv_gpci_event_attrs,
> + /* .attrs is set in init */
> };
>
> #define HV_CAPS_ATTR(_name, _format) \
> @@ -353,6 +353,11 @@ static int hv_gpci_init(void)
> /* sampling not supported */
> h_gpci_pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
>
> + if (cpu_has_feature(CPU_FTR_ARCH_207S))
> + event_group.attrs = hv_gpci_event_attrs;
> + else
> + event_group.attrs = hv_gpci_event_attrs_v6;
> +
> r = perf_pmu_register(_gpci_pmu, h_gpci_pmu.name, -1);
> if (r)
> return r;
> diff --git a/arch/powerpc/perf/hv-gpci.h b/arch/powerpc/perf/hv-gpci.h
> index 4d108262bed7..866172c1651c 100644
> --- a/arch/powerpc/perf/hv-gpci.h
> +++ b/arch/powerpc/perf/hv-gpci.h
> @@ -26,6 +26,7 @@ enum {
> #define REQUEST_FILE "../hv-gpci-requests.h"
> #define NAME_LOWER hv_gpci
> #define NAME_UPPER HV_GPCI
> +#define EVENT_ENABLE 1
> #include "req-gen/perf.h"
> #undef REQUEST_FILE
> #undef NAME_LOWER
> diff --git a/arch/powerpc/perf/req-gen/perf.h
> b/arch/powerpc/perf/req-gen/perf.h
> index fa9bc804e67a..78d407e3fcc6 100644
> --- a/arch/powerpc/perf/req-gen/perf.h
> +++ b/arch/powerpc/perf/req-gen/perf.h
> @@ -139,6 +139,23 @@ PMU_EVENT_ATTR_STRING(
> \
> #define REQUEST_(r_name, r_value, r_idx_1, r_fields) \
> r_fields
>
> +/* Generate event list for platforms with counter_info_version 0x6 or below
> */
> +static __maybe_unused struct attribute *hv_gpci_event_attrs_v6[] = {
> +#include REQUEST_FILE
> + NULL
> +};
> +
> +/*
> + * Based on getPerfCountInfo v1.018 documentation, some of the hv-gpci
> + * events got deprecated for platforms firmware that supports
> + * counter_info_version 0x8 or above.
> + * Undefining macro EVENT_ENABLE, to disable the addition of deprecated
> + * events in "hv_gpci_event_attrs" attribute group, for platforms that
> + * supports counter_info_version 0x8 or above.
> + */
> +#undef EVENT_ENABLE
> +
> +/* Generate
Re: [PATCH] powerpc/hv-gpci: Fix hv_gpci event list
> On 20-Sep-2022, at 10:08 PM, Kajol Jain wrote:
>
> Based on getPerfCountInfo v1.018 documentation, some of the
> hv_gpci events got deprecated for platforms firmware that
> supports counter_info_version 0x8 or above.
>
> Patch fixes the hv_gpci event list by adding a new attribute
> group called "hv_gpci_event_attrs_v6" and a "EVENT_ENABLE"
> macro to enable these events for platform firmware
> that supports counter_info_version 0x6 or below.
>
> Fixes: 97bf2640184f4 ("powerpc/perf/hv-gpci: add the remaining gpci
> requests")
> Signed-off-by: Kajol Jain
> ---
Reviewed-by: Athira Rajeev
Thanks
Athira
> arch/powerpc/perf/hv-gpci-requests.h | 4
> arch/powerpc/perf/hv-gpci.c | 9 +++--
> arch/powerpc/perf/hv-gpci.h | 1 +
> arch/powerpc/perf/req-gen/perf.h | 17 +
> 4 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/perf/hv-gpci-requests.h
> b/arch/powerpc/perf/hv-gpci-requests.h
> index 8965b4463d43..baef3d082de9 100644
> --- a/arch/powerpc/perf/hv-gpci-requests.h
> +++ b/arch/powerpc/perf/hv-gpci-requests.h
> @@ -79,6 +79,7 @@ REQUEST(__field(0, 8, partition_id)
> )
> #include I(REQUEST_END)
>
> +#ifdef EVENT_ENABLE
> /*
> * Not available for counter_info_version >= 0x8, use
> * run_instruction_cycles_by_partition(0x100) instead.
> @@ -92,6 +93,7 @@ REQUEST(__field(0, 8, partition_id)
> __count(0x10, 8, cycles)
> )
> #include I(REQUEST_END)
> +#endif
>
> #define REQUEST_NAME system_performance_capabilities
> #define REQUEST_NUM 0x40
> @@ -103,6 +105,7 @@ REQUEST(__field(0,1, perf_collect_privileged)
> )
> #include I(REQUEST_END)
>
> +#ifdef EVENT_ENABLE
> #define REQUEST_NAME processor_bus_utilization_abc_links
> #define REQUEST_NUM 0x50
> #define REQUEST_IDX_KIND "hw_chip_id=?"
> @@ -194,6 +197,7 @@ REQUEST(__field(0,4, phys_processor_idx)
> __count(0x28, 8, instructions_completed)
> )
> #include I(REQUEST_END)
> +#endif
>
> /* Processor_core_power_mode (0x95) skipped, no counters */
> /* Affinity_domain_information_by_virtual_processor (0xA0) skipped,
> diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c
> index 5eb60ed5b5e8..065a01812b3e 100644
> --- a/arch/powerpc/perf/hv-gpci.c
> +++ b/arch/powerpc/perf/hv-gpci.c
> @@ -70,9 +70,9 @@ static const struct attribute_group format_group = {
> .attrs = format_attrs,
> };
>
> -static const struct attribute_group event_group = {
> +static struct attribute_group event_group = {
> .name = "events",
> - .attrs = hv_gpci_event_attrs,
> + /* .attrs is set in init */
> };
>
> #define HV_CAPS_ATTR(_name, _format) \
> @@ -353,6 +353,11 @@ static int hv_gpci_init(void)
> /* sampling not supported */
> h_gpci_pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
>
> + if (cpu_has_feature(CPU_FTR_ARCH_207S))
> + event_group.attrs = hv_gpci_event_attrs;
> + else
> + event_group.attrs = hv_gpci_event_attrs_v6;
> +
> r = perf_pmu_register(_gpci_pmu, h_gpci_pmu.name, -1);
> if (r)
> return r;
> diff --git a/arch/powerpc/perf/hv-gpci.h b/arch/powerpc/perf/hv-gpci.h
> index 4d108262bed7..866172c1651c 100644
> --- a/arch/powerpc/perf/hv-gpci.h
> +++ b/arch/powerpc/perf/hv-gpci.h
> @@ -26,6 +26,7 @@ enum {
> #define REQUEST_FILE "../hv-gpci-requests.h"
> #define NAME_LOWER hv_gpci
> #define NAME_UPPER HV_GPCI
> +#define EVENT_ENABLE 1
> #include "req-gen/perf.h"
> #undef REQUEST_FILE
> #undef NAME_LOWER
> diff --git a/arch/powerpc/perf/req-gen/perf.h
> b/arch/powerpc/perf/req-gen/perf.h
> index fa9bc804e67a..78d407e3fcc6 100644
> --- a/arch/powerpc/perf/req-gen/perf.h
> +++ b/arch/powerpc/perf/req-gen/perf.h
> @@ -139,6 +139,23 @@ PMU_EVENT_ATTR_STRING(
> \
> #define REQUEST_(r_name, r_value, r_idx_1, r_fields) \
> r_fields
>
> +/* Generate event list for platforms with counter_info_version 0x6 or below
> */
> +static __maybe_unused struct attribute *hv_gpci_event_attrs_v6[] = {
> +#include REQUEST_FILE
> + NULL
> +};
> +
> +/*
> + * Based on getPerfCountInfo v1.018 documentation, some of the hv-gpci
> + * events got deprecated for platforms firmware that supports
> + * counter_info_version 0x8 or above.
> + * Undefining macro EVENT_ENABLE, to disable the addition of deprecated
> + * events in "hv_gpci_event_attrs" attribute group, for platforms that
> + * supports counter_info_version 0x8 or above.
> + */
> +#undef EVENT_ENABLE
> +
> +/* Generate event list for platforms with counter_info_version 0x8 or above*/
> static __maybe_unused struct attribute *hv_gpci_event_attrs[] = {
> #include REQUEST_FILE
> NULL
> --
> 2.31.1
>
Re: [PATCH v3 4/5] vfio: Remove CONFIG_VFIO_SPAPR_EEH
> +#if IS_ENABLED(CONFIG_EEH) && IS_ENABLED(CONFIG_VFIO_IOMMU_SPAPR_TCE) > #include > #endif > > @@ -689,7 +689,7 @@ void vfio_pci_core_close_device(struct vfio_device > *core_vdev) > vdev->sriov_pf_core_dev->vf_token->users--; > mutex_unlock(>sriov_pf_core_dev->vf_token->lock); > } > -#if IS_ENABLED(CONFIG_VFIO_SPAPR_EEH) > +#if IS_ENABLED(CONFIG_EEH) && IS_ENABLED(CONFIG_VFIO_IOMMU_SPAPR_TCE) So while this preserves the existing behavior, I wonder if checking CONFIG_EEH only would make more sense here.
