Re: [PATCH net-next 0/7] Remove three Sun net drivers

[Karl Volz]

On 1/6/23 15:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.

In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.

The idea behind putting out this series is to either establish that these
drivers are used and should be maintained, or remove them.

Anirudh,

The Sun LDOM vswitch and sunvnet drivers are still in use, please do not 
remove them or the event tracing.
We use them internally and you don't see any discussions because they 
generally work fine (AFAIK).
I think you are also going to break things by removing Sun Cassini 
support, but I am not using it personally.

What user visible bugs are you referring to here?


Thanks
Karl


While the bulk of the code removal is in the networking s, and so
multiple subsystem lists are cc'd. Here's a quick breakdown:

   - patches 1/7 and 5/7 remove the drivers (netdev)
   - patch 2/7 removes Sun device IDs from pci_ids.h (linux-pci)
   - patch 3/7 changes ppc6xx_defconfig (linuxppc)
   - patch 4/7 changes MIPS mtx1_defconfig (linux-mips)
   - patch 6/7 removes the event tracing header sunvnet.h (linux-trace)
   - patch 7/7 changes sparc64_defconfig (sparclinux)

This series was compile tested as follows:

make O=b1 ARCH=mips CROSS_COMPILE=mips64-linux-gnu- defconfig
make -j$(nproc) O=b1 ARCH=mips CROSS_COMPILE=mips64-linux-gnu- all

make O=b2 ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- defconfig
make -j$(nproc) O=b2 ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- all

make O=b3 ARCH=powerpc CROSS_COMPILE=ppc64-linux-gnu- ppc6xx_defconfig
make -j$(nproc) O=b3 ARCH=powerpc CROSS_COMPILE=ppc64-linux-gnu- all

[1] 
https://lore.kernel.org/netdev/99629223-ac1b-0f82-50b8-ea307b3b0...@intel.com/T/#t

Suggested-by: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 

Anirudh Venkataramanan (7):
   ethernet: Remove the Sun Cassini driver
   PCI: Remove PCI IDs used by the Sun Cassini driver
   powerpc: configs: Remove reference to CONFIG_CASSINI
   mips: configs: Remove reference to CONFIG_CASSINI
   ethernet: Remove the Sun LDOM vswitch and sunvnet drivers
   sunvnet: Remove event tracing file
   sparc: configs: Remove references to CONFIG_SUNVNET and CONFIG_LDMVSW

  arch/mips/configs/mtx1_defconfig  |1 -
  arch/powerpc/configs/ppc6xx_defconfig |1 -
  arch/sparc/configs/sparc64_defconfig  |2 -
  drivers/net/ethernet/sun/Kconfig  |   35 -
  drivers/net/ethernet/sun/Makefile |4 -
  drivers/net/ethernet/sun/cassini.c| 5215 -
  drivers/net/ethernet/sun/cassini.h| 2900 
  drivers/net/ethernet/sun/ldmvsw.c |  476 --
  drivers/net/ethernet/sun/sunvnet.c|  567 ---
  drivers/net/ethernet/sun/sunvnet_common.c | 1813 ---
  drivers/net/ethernet/sun/sunvnet_common.h |  157 -
  include/linux/pci_ids.h   |2 -
  include/trace/events/sunvnet.h|  140 -
  13 files changed, 11313 deletions(-)
  delete mode 100644 drivers/net/ethernet/sun/cassini.c
  delete mode 100644 drivers/net/ethernet/sun/cassini.h
  delete mode 100644 drivers/net/ethernet/sun/ldmvsw.c
  delete mode 100644 drivers/net/ethernet/sun/sunvnet.c
  delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.c
  delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.h
  delete mode 100644 include/trace/events/sunvnet.h


base-commit: 6bd4755c7c499dbcef46eaaeafa1a319da583b29

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[Karl Volz]

On 1/6/23 16:10, Anirudh Venkataramanan wrote:

On 1/6/2023 2:44 PM, Karl Volz wrote:



On 1/6/23 15:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.

In a recent patch series that touched these drivers [1], it was 
suggested

that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or 
fixes
to user-visible bugs in a while. A web search didn't indicate any 
recent
discussions or any evidence that there are users out there who care 
about

these drivers.

The idea behind putting out this series is to either establish that 
these

drivers are used and should be maintained, or remove them.

Anirudh,

The Sun LDOM vswitch and sunvnet drivers are still in use, please do 
not remove them or the event tracing.
We use them internally and you don't see any discussions because they 
generally work fine (AFAIK).


Hello Karl,

Thanks for chiming in.

Are there recent platforms where these drivers are used? If yes, do 
you know which ones? Or are these drivers useful in old/legacy 
platforms that are still around but perhaps no longer in production?


These drivers work on older T4, T5, etc  to the latest T7, T8 Sun 
servers (e.g. T8-2, T8-4, note, T7/T8 are still in production).
They may also work on T2/T3  (but I don't use those anymore, though 
Adrian (John Paul Adrian Glaubitz ) might).
You might have missed a lot of the linux SPARC developers since they are 
on the debian-sp...@lists.debian.org list, hence I'd ask there also.


I think you are also going to break things by removing Sun Cassini 
support, but I am not using it personally.


You suspect there are users for this driver as well?


Yes, they may not have seen this yet or recognized the servers this card 
goes in (post on debian-sp...@lists.debian.org list).





What user visible bugs are you referring to here?


I was saying I don't see any evidence of recent bug fixes, which would 
make sense if these drivers "just work".


ok, no worries.

Cheers
Karl



Ani

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[John Paul Adrian Glaubitz]

On 1/7/23 03:04, Anirudh Venkataramanan wrote:

On 1/6/2023 5:36 PM, John Paul Adrian Glaubitz wrote:

Hello!

On 1/6/23 23:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.


This would affect a large number of Linux on SPARC users. Please don't!


Thanks for chiming in. Does your statement above apply to all 3 drivers?


Yes!


We're still maintaining an active sparc64 port for Debian, see [1]. So
does Gentoo [2].


In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.


Well, these drivers just work and I don't see why there should be regular
discussions about them or changes.


That's fair, but lack of discussion can also be signs of disuse, and that's
really the hunch I was following up on. Given what you and Karl have said,
I agree that we shouldn't remove these drivers. I'll stop pursuing this unless
there are new arguments to the contrary.


It's a common problem in my opinion on the LKML that many kernel developers 
assume
that users of certain drivers and kernel subsystems are present and active on 
the
kernel mailing lists to be able to raise their voices in these discussions.

If you want to find out whether some parts of the kernel are actively being 
used,
it's better to ask on distribution mailing lists because it's way more likely
to find any users there.

I try to be present on as many kernel mailing lists as I can to be able to 
answer
these questions, but sometimes there is just too much traffic for me to handle.

Adrian

--
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer
`. `'   Physicist
  `-GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[Jakub Kicinski]

On Fri, 6 Jan 2023 18:04:54 -0800 Anirudh Venkataramanan wrote:
> >> In a recent patch series that touched these drivers [1], it was suggested
> >> that these drivers should be removed completely. git logs suggest that
> >> there hasn't been any significant feature addition, improvement or fixes
> >> to user-visible bugs in a while. A web search didn't indicate any recent
> >> discussions or any evidence that there are users out there who care about
> >> these drivers.  
> > 
> > Well, these drivers just work and I don't see why there should be regular
> > discussions about them or changes.  
> 
> That's fair, but lack of discussion can also be signs of disuse, and 
> that's really the hunch I was following up on.

Lack of feedback, too. Some of these drivers are missing entries 
in MAINTAINERS and patches don't get review tags from anyone.

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[Anirudh Venkataramanan]

On 1/6/2023 5:36 PM, John Paul Adrian Glaubitz wrote:

Hello!

On 1/6/23 23:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.


This would affect a large number of Linux on SPARC users. Please don't!


Thanks for chiming in. Does your statement above apply to all 3 drivers?



We're still maintaining an active sparc64 port for Debian, see [1]. So
does Gentoo [2].


In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.


Well, these drivers just work and I don't see why there should be regular
discussions about them or changes.


That's fair, but lack of discussion can also be signs of disuse, and 
that's really the hunch I was following up on. Given what you and Karl 
have said, I agree that we shouldn't remove these drivers. I'll stop 
pursuing this unless there are new arguments to the contrary.


Ani

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[John Paul Adrian Glaubitz]

Hello!

On 1/6/23 23:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.


This would affect a large number of Linux on SPARC users. Please don't!

We're still maintaining an active sparc64 port for Debian, see [1]. So
does Gentoo [2].


In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.


Well, these drivers just work and I don't see why there should be regular
discussions about them or changes.

Adrian


[1] https://cdimage.debian.org/cdimage/ports/snapshots/2022-12-09/
[2] https://www.gentoo.org/downloads/


--
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer
`. `'   Physicist
  `-GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

Re: [PATCH net-next 0/7] Remove three Sun net drivers

[Anirudh Venkataramanan]

On 1/6/2023 2:44 PM, Karl Volz wrote:



On 1/6/23 15:00, Anirudh Venkataramanan wrote:

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.

In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.

The idea behind putting out this series is to either establish that these
drivers are used and should be maintained, or remove them.

Anirudh,

The Sun LDOM vswitch and sunvnet drivers are still in use, please do not 
remove them or the event tracing.
We use them internally and you don't see any discussions because they 
generally work fine (AFAIK).


Hello Karl,

Thanks for chiming in.

Are there recent platforms where these drivers are used? If yes, do you 
know which ones? Or are these drivers useful in old/legacy platforms 
that are still around but perhaps no longer in production?


I think you are also going to break things by removing Sun Cassini 
support, but I am not using it personally.


You suspect there are users for this driver as well?


What user visible bugs are you referring to here?


I was saying I don't see any evidence of recent bug fixes, which would 
make sense if these drivers "just work".


Ani

[PATCH net-next 6/7] sunvnet: Remove event tracing file

[Anirudh Venkataramanan]

An earlier patch removed the Sun LDOM vswitch and sunvnet drivers, and
as a result, nothing includes sunvnet.h anymore. Remove it.

Note:

checkpatch complains "WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?". The file being removed doesn't have its
own entry in the MAINTAINERS file, so there's nothing to remove.

Cc: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 include/trace/events/sunvnet.h | 140 -
 1 file changed, 140 deletions(-)
 delete mode 100644 include/trace/events/sunvnet.h

diff --git a/include/trace/events/sunvnet.h b/include/trace/events/sunvnet.h
deleted file mode 100644
index 8d444f1..
--- a/include/trace/events/sunvnet.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM sunvnet
-
-#if !defined(_TRACE_SUNVNET_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_SUNVNET_H
-
-#include 
-
-TRACE_EVENT(vnet_rx_one,
-
-   TP_PROTO(int lsid, int rsid, int index, int needs_ack),
-
-   TP_ARGS(lsid, rsid, index, needs_ack),
-
-   TP_STRUCT__entry(
-   __field(int, lsid)
-   __field(int, rsid)
-   __field(int, index)
-   __field(int, needs_ack)
-   ),
-
-   TP_fast_assign(
-   __entry->lsid = lsid;
-   __entry->rsid = rsid;
-   __entry->index = index;
-   __entry->needs_ack = needs_ack;
-   ),
-
-   TP_printk("(%x:%x) walk_rx_one index %d; needs_ack %d",
-   __entry->lsid, __entry->rsid,
-   __entry->index, __entry->needs_ack)
-);
-
-DECLARE_EVENT_CLASS(vnet_tx_stopped_ack_template,
-
-   TP_PROTO(int lsid, int rsid, int ack_end, int npkts),
-
-   TP_ARGS(lsid, rsid, ack_end, npkts),
-
-   TP_STRUCT__entry(
-   __field(int, lsid)
-   __field(int, rsid)
-   __field(int, ack_end)
-   __field(int, npkts)
-   ),
-
-   TP_fast_assign(
-   __entry->lsid = lsid;
-   __entry->rsid = rsid;
-   __entry->ack_end = ack_end;
-   __entry->npkts = npkts;
-   ),
-
-   TP_printk("(%x:%x) stopped ack for %d; npkts %d",
-   __entry->lsid, __entry->rsid,
-   __entry->ack_end, __entry->npkts)
-);
-DEFINE_EVENT(vnet_tx_stopped_ack_template, vnet_tx_send_stopped_ack,
-TP_PROTO(int lsid, int rsid, int ack_end, int npkts),
-TP_ARGS(lsid, rsid, ack_end, npkts));
-DEFINE_EVENT(vnet_tx_stopped_ack_template, vnet_tx_defer_stopped_ack,
-TP_PROTO(int lsid, int rsid, int ack_end, int npkts),
-TP_ARGS(lsid, rsid, ack_end, npkts));
-DEFINE_EVENT(vnet_tx_stopped_ack_template, vnet_tx_pending_stopped_ack,
-TP_PROTO(int lsid, int rsid, int ack_end, int npkts),
-TP_ARGS(lsid, rsid, ack_end, npkts));
-
-TRACE_EVENT(vnet_rx_stopped_ack,
-
-   TP_PROTO(int lsid, int rsid, int end),
-
-   TP_ARGS(lsid, rsid, end),
-
-   TP_STRUCT__entry(
-   __field(int, lsid)
-   __field(int, rsid)
-   __field(int, end)
-   ),
-
-   TP_fast_assign(
-   __entry->lsid = lsid;
-   __entry->rsid = rsid;
-   __entry->end = end;
-   ),
-
-   TP_printk("(%x:%x) stopped ack for index %d",
-   __entry->lsid, __entry->rsid, __entry->end)
-);
-
-TRACE_EVENT(vnet_tx_trigger,
-
-   TP_PROTO(int lsid, int rsid, int start, int err),
-
-   TP_ARGS(lsid, rsid, start, err),
-
-   TP_STRUCT__entry(
-   __field(int, lsid)
-   __field(int, rsid)
-   __field(int, start)
-   __field(int, err)
-   ),
-
-   TP_fast_assign(
-   __entry->lsid = lsid;
-   __entry->rsid = rsid;
-   __entry->start = start;
-   __entry->err = err;
-   ),
-
-   TP_printk("(%x:%x) Tx trigger for %d sent with err %d %s",
-   __entry->lsid, __entry->rsid, __entry->start,
-   __entry->err, __entry->err > 0 ? "(ok)" : " ")
-);
-
-TRACE_EVENT(vnet_skip_tx_trigger,
-
-   TP_PROTO(int lsid, int rsid, int last),
-
-   TP_ARGS(lsid, rsid, last),
-
-   TP_STRUCT__entry(
-   __field(int, lsid)
-   __field(int, rsid)
-   __field(int, last)
-   ),
-
-   TP_fast_assign(
-   __entry->lsid = lsid;
-   __entry->rsid = rsid;
-   __entry->last = last;
-   ),
-
-   TP_printk("(%x:%x) Skip Tx trigger. Last trigger sent was %d",
-   __entry->lsid, __entry->rsid, __entry->last)
-);
-#endif /* _TRACE_SOCK_H */
-
-/* This part must be outside protection */
-#include 
-- 
2.37.2

[PATCH net-next 7/7] sparc: configs: Remove references to CONFIG_SUNVNET and CONFIG_LDMVSW

[Anirudh Venkataramanan]

An earlier patch removed the Sun LDOM vswitch and sunvnet drivers. Remove
references to CONFIG_SUNVNET and CONFIG_LDMVSW from the sparc64 defconfig.

Cc: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 arch/sparc/configs/sparc64_defconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/sparc/configs/sparc64_defconfig 
b/arch/sparc/configs/sparc64_defconfig
index 1809909..a2c76e8 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -95,8 +95,6 @@ CONFIG_MII=m
 CONFIG_SUNLANCE=m
 CONFIG_HAPPYMEAL=y
 CONFIG_SUNGEM=m
-CONFIG_SUNVNET=m
-CONFIG_LDMVSW=m
 CONFIG_NET_PCI=y
 CONFIG_E1000=m
 CONFIG_E1000E=m
-- 
2.37.2

[PATCH net-next 5/7] ethernet: Remove the Sun LDOM vswitch and sunvnet drivers

[Anirudh Venkataramanan]

In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes to
user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers, and so remove these drivers.

Notes:

checkpatch complains "WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?". The files being removed don't have their own
entries in the MAINTAINERS file, so there's nothing to remove.

checkpatch also complains about the long lore link below.

[1] 
https://lore.kernel.org/netdev/99629223-ac1b-0f82-50b8-ea307b3b0...@intel.com/T/#t

Suggested-by: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 drivers/net/ethernet/sun/Kconfig  |   27 -
 drivers/net/ethernet/sun/Makefile |3 -
 drivers/net/ethernet/sun/ldmvsw.c |  476 --
 drivers/net/ethernet/sun/sunvnet.c|  567 ---
 drivers/net/ethernet/sun/sunvnet_common.c | 1813 -
 drivers/net/ethernet/sun/sunvnet_common.h |  157 --
 6 files changed, 3043 deletions(-)
 delete mode 100644 drivers/net/ethernet/sun/ldmvsw.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.h

diff --git a/drivers/net/ethernet/sun/Kconfig b/drivers/net/ethernet/sun/Kconfig
index 57eb168..26472e4 100644
--- a/drivers/net/ethernet/sun/Kconfig
+++ b/drivers/net/ethernet/sun/Kconfig
@@ -62,33 +62,6 @@ config SUNGEM
  Support for the Sun GEM chip, aka Sun GigabitEthernet/P 2.0.  See also
  .
 
-config SUNVNET_COMMON
-   tristate "Common routines to support Sun Virtual Networking"
-   depends on SUN_LDOMS
-   depends on INET
-   default m
-
-config SUNVNET
-   tristate "Sun Virtual Network support"
-   default m
-   depends on SUN_LDOMS
-   depends on SUNVNET_COMMON
-   help
- Support for virtual network devices under Sun Logical Domains.
-
-config LDMVSW
-   tristate "Sun4v LDoms Virtual Switch support"
-   default m
-   depends on SUN_LDOMS
-   depends on SUNVNET_COMMON
-   help
- Support for virtual switch devices under Sun4v Logical Domains.
- This driver adds a network interface for every vsw-port node
- found in the machine description of a service domain.
- Linux bridge/switch software can use these interfaces for
- guest domain network interconnectivity or guest domain
- connection to a physical network on a service domain.
-
 config NIU
tristate "Sun Neptune 10Gbit Ethernet support"
depends on PCI
diff --git a/drivers/net/ethernet/sun/Makefile 
b/drivers/net/ethernet/sun/Makefile
index fd77810..35469d1 100644
--- a/drivers/net/ethernet/sun/Makefile
+++ b/drivers/net/ethernet/sun/Makefile
@@ -7,7 +7,4 @@ obj-$(CONFIG_HAPPYMEAL) += sunhme.o
 obj-$(CONFIG_SUNQE) += sunqe.o
 obj-$(CONFIG_SUNBMAC) += sunbmac.o
 obj-$(CONFIG_SUNGEM) += sungem.o
-obj-$(CONFIG_SUNVNET_COMMON) += sunvnet_common.o
-obj-$(CONFIG_SUNVNET) += sunvnet.o
-obj-$(CONFIG_LDMVSW) += ldmvsw.o
 obj-$(CONFIG_NIU) += niu.o
diff --git a/drivers/net/ethernet/sun/ldmvsw.c 
b/drivers/net/ethernet/sun/ldmvsw.c
deleted file mode 100644
index 8addee6..
--- a/drivers/net/ethernet/sun/ldmvsw.c
+++ /dev/null
@@ -1,476 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* ldmvsw.c: Sun4v LDOM Virtual Switch Driver.
- *
- * Copyright (C) 2016-2017 Oracle. All rights reserved.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#if defined(CONFIG_IPV6)
-#include 
-#endif
-
-#include 
-#include 
-#include 
-
-#include 
-#include 
-
-/* This driver makes use of the common code in sunvnet_common.c */
-#include "sunvnet_common.h"
-
-/* Length of time before we decide the hardware is hung,
- * and dev->tx_timeout() should be called to fix the problem.
- */
-#define VSW_TX_TIMEOUT (10 * HZ)
-
-/* Static HW Addr used for the network interfaces representing vsw ports */
-static u8 vsw_port_hwaddr[ETH_ALEN] = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-
-#define DRV_MODULE_NAME"ldmvsw"
-#define DRV_MODULE_VERSION "1.2"
-#define DRV_MODULE_RELDATE "March 4, 2017"
-
-static char version[] =
-   DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
-MODULE_AUTHOR("Oracle");
-MODULE_DESCRIPTION("Sun4v LDOM Virtual Switch Driver");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRV_MODULE_VERSION);
-
-/* Ordered from largest major to lowest */
-static struct vio_version vsw_versions[] = {
-   { .major = 1, .minor = 8 },
-   { 

[PATCH net-next 4/7] mips: configs: Remove reference to CONFIG_CASSINI

[Anirudh Venkataramanan]

An earlier patch removed the Sun Cassnini driver. Remove references to
CONFIG_CASSINI from the mtx1 defconfig

Cc: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 arch/mips/configs/mtx1_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 89a1511..17d88a0 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -305,7 +305,6 @@ CONFIG_PCMCIA_SMC91C92=m
 CONFIG_EPIC100=m
 CONFIG_HAPPYMEAL=m
 CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
 CONFIG_TLAN=m
 CONFIG_VIA_RHINE=m
 CONFIG_VIA_VELOCITY=m
-- 
2.37.2

[PATCH net-next 3/7] powerpc: configs: Remove reference to CONFIG_CASSINI

[Anirudh Venkataramanan]

An earlier patch removed the Sun Cassnini driver. Remove references to
CONFIG_CASSINI from the ppc6xx defconfig.

Cc: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 arch/powerpc/configs/ppc6xx_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/powerpc/configs/ppc6xx_defconfig 
b/arch/powerpc/configs/ppc6xx_defconfig
index 1102582..0eba1de 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -487,7 +487,6 @@ CONFIG_PCMCIA_SMC91C92=m
 CONFIG_EPIC100=m
 CONFIG_HAPPYMEAL=m
 CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
 CONFIG_NIU=m
 CONFIG_TEHUTI=m
 CONFIG_TLAN=m
-- 
2.37.2

[PATCH net-next 2/7] PCI: Remove PCI IDs used by the Sun Cassini driver

[Anirudh Venkataramanan]

The previous patch removed the Cassini driver (drivers/net/ethernet/sun).
With this, PCI_DEVICE_ID_NS_SATURN and PCI_DEVICE_ID_SUN_CASSINI are
unused. Remove them.

Cc: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 
---
 include/linux/pci_ids.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index b362d90..eca2340 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -433,7 +433,6 @@
 #define PCI_DEVICE_ID_NS_CS5535_AUDIO  0x002e
 #define PCI_DEVICE_ID_NS_CS5535_USB0x002f
 #define PCI_DEVICE_ID_NS_GX_VIDEO  0x0030
-#define PCI_DEVICE_ID_NS_SATURN0x0035
 #define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500
 #define PCI_DEVICE_ID_NS_SCx200_SMI0x0501
 #define PCI_DEVICE_ID_NS_SCx200_IDE0x0502
@@ -1047,7 +1046,6 @@
 #define PCI_DEVICE_ID_SUN_SABRE0xa000
 #define PCI_DEVICE_ID_SUN_HUMMINGBIRD  0xa001
 #define PCI_DEVICE_ID_SUN_TOMATILLO0xa801
-#define PCI_DEVICE_ID_SUN_CASSINI  0xabba
 
 #define PCI_VENDOR_ID_NI   0x1093
 #define PCI_DEVICE_ID_NI_PCI2322   0xd130
-- 
2.37.2

[PATCH net-next 0/7] Remove three Sun net drivers

[Anirudh Venkataramanan]

This series removes the Sun Cassini, LDOM vswitch and sunvnet drivers.

In a recent patch series that touched these drivers [1], it was suggested
that these drivers should be removed completely. git logs suggest that
there hasn't been any significant feature addition, improvement or fixes
to user-visible bugs in a while. A web search didn't indicate any recent
discussions or any evidence that there are users out there who care about
these drivers.

The idea behind putting out this series is to either establish that these
drivers are used and should be maintained, or remove them.

While the bulk of the code removal is in the networking s, and so
multiple subsystem lists are cc'd. Here's a quick breakdown:

  - patches 1/7 and 5/7 remove the drivers (netdev)
  - patch 2/7 removes Sun device IDs from pci_ids.h (linux-pci)
  - patch 3/7 changes ppc6xx_defconfig (linuxppc)
  - patch 4/7 changes MIPS mtx1_defconfig (linux-mips)
  - patch 6/7 removes the event tracing header sunvnet.h (linux-trace)
  - patch 7/7 changes sparc64_defconfig (sparclinux)

This series was compile tested as follows:

make O=b1 ARCH=mips CROSS_COMPILE=mips64-linux-gnu- defconfig
make -j$(nproc) O=b1 ARCH=mips CROSS_COMPILE=mips64-linux-gnu- all

make O=b2 ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- defconfig
make -j$(nproc) O=b2 ARCH=sparc64 CROSS_COMPILE=sparc64-linux-gnu- all

make O=b3 ARCH=powerpc CROSS_COMPILE=ppc64-linux-gnu- ppc6xx_defconfig
make -j$(nproc) O=b3 ARCH=powerpc CROSS_COMPILE=ppc64-linux-gnu- all

[1] 
https://lore.kernel.org/netdev/99629223-ac1b-0f82-50b8-ea307b3b0...@intel.com/T/#t

Suggested-by: Leon Romanovsky 
Signed-off-by: Anirudh Venkataramanan 

Anirudh Venkataramanan (7):
  ethernet: Remove the Sun Cassini driver
  PCI: Remove PCI IDs used by the Sun Cassini driver
  powerpc: configs: Remove reference to CONFIG_CASSINI
  mips: configs: Remove reference to CONFIG_CASSINI
  ethernet: Remove the Sun LDOM vswitch and sunvnet drivers
  sunvnet: Remove event tracing file
  sparc: configs: Remove references to CONFIG_SUNVNET and CONFIG_LDMVSW

 arch/mips/configs/mtx1_defconfig  |1 -
 arch/powerpc/configs/ppc6xx_defconfig |1 -
 arch/sparc/configs/sparc64_defconfig  |2 -
 drivers/net/ethernet/sun/Kconfig  |   35 -
 drivers/net/ethernet/sun/Makefile |4 -
 drivers/net/ethernet/sun/cassini.c| 5215 -
 drivers/net/ethernet/sun/cassini.h| 2900 
 drivers/net/ethernet/sun/ldmvsw.c |  476 --
 drivers/net/ethernet/sun/sunvnet.c|  567 ---
 drivers/net/ethernet/sun/sunvnet_common.c | 1813 ---
 drivers/net/ethernet/sun/sunvnet_common.h |  157 -
 include/linux/pci_ids.h   |2 -
 include/trace/events/sunvnet.h|  140 -
 13 files changed, 11313 deletions(-)
 delete mode 100644 drivers/net/ethernet/sun/cassini.c
 delete mode 100644 drivers/net/ethernet/sun/cassini.h
 delete mode 100644 drivers/net/ethernet/sun/ldmvsw.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.c
 delete mode 100644 drivers/net/ethernet/sun/sunvnet_common.h
 delete mode 100644 include/trace/events/sunvnet.h


base-commit: 6bd4755c7c499dbcef46eaaeafa1a319da583b29
-- 
2.37.2

[PATCH v2 10/10] MAINTAINERS: add the Freescale QMC audio entry

[Herve Codina]

After contributing the component, add myself as the maintainer
for the Freescale QMC audio ASoC component.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 480f90db699d..a15997c2cc05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8440,6 +8440,14 @@ F:   sound/soc/fsl/fsl*
 F: sound/soc/fsl/imx*
 F: sound/soc/fsl/mpc8610_hpcd.c
 
+FREESCALE SOC SOUND QMC DRIVER
+M: Herve Codina 
+L: alsa-de...@alsa-project.org (moderated for non-subscribers)
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
+F: sound/soc/fsl/fsl_qmc_audio.c
+
 FREESCALE USB PERIPHERAL DRIVERS
 M: Li Yang 
 L: linux-...@vger.kernel.org
-- 
2.38.1

[PATCH v2 09/10] ASoC: fsl: Add support for QMC audio

[Herve Codina]

The QMC audio is an ASoC component which provides DAIs
that use the QMC (QUICC Multichannel Controller) to transfer
the audio data.

It provides as many DAIs as the number of QMC channels it
references.

Signed-off-by: Herve Codina 
---
 sound/soc/fsl/Kconfig |   9 +
 sound/soc/fsl/Makefile|   2 +
 sound/soc/fsl/fsl_qmc_audio.c | 731 ++
 3 files changed, 742 insertions(+)
 create mode 100644 sound/soc/fsl/fsl_qmc_audio.c

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 614eceda6b9e..17db29c25d96 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -172,6 +172,15 @@ config SND_MPC52xx_DMA
 config SND_SOC_POWERPC_DMA
tristate
 
+config SND_SOC_POWERPC_QMC_AUDIO
+   tristate "QMC ALSA SoC support"
+   depends on CPM_QMC
+   help
+ ALSA SoC Audio support using the Freescale QUICC Multichannel
+ Controller (QMC).
+ Say Y or M if you want to add support for SoC audio using Freescale
+ QMC.
+
 comment "SoC Audio support for Freescale PPC boards:"
 
 config SND_SOC_MPC8610_HPCD
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b54beb1a66fa..8db7e97d0bd5 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -28,6 +28,7 @@ snd-soc-fsl-easrc-objs := fsl_easrc.o
 snd-soc-fsl-xcvr-objs := fsl_xcvr.o
 snd-soc-fsl-aud2htx-objs := fsl_aud2htx.o
 snd-soc-fsl-rpmsg-objs := fsl_rpmsg.o
+snd-soc-fsl-qmc-audio-objs := fsl_qmc_audio.o
 
 obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
 obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
 obj-$(CONFIG_SND_SOC_FSL_AUD2HTX) += snd-soc-fsl-aud2htx.o
 obj-$(CONFIG_SND_SOC_FSL_RPMSG) += snd-soc-fsl-rpmsg.o
+obj-$(CONFIG_SND_SOC_POWERPC_QMC_AUDIO) += snd-soc-fsl-qmc-audio.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
new file mode 100644
index ..6d651e6efa09
--- /dev/null
+++ b/sound/soc/fsl/fsl_qmc_audio.c
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ALSA SoC using the QUICC Multichannel Controller (QMC)
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct qmc_dai {
+   char *name;
+   int id;
+   struct device *dev;
+   struct qmc_chan *qmc_chan;
+   unsigned int nb_tx_ts;
+   unsigned int nb_rx_ts;
+};
+
+struct qmc_audio {
+   struct device *dev;
+   unsigned int num_dais;
+   struct qmc_dai *dais;
+   struct snd_soc_dai_driver *dai_drivers;
+};
+
+struct qmc_dai_prtd {
+   struct qmc_dai *qmc_dai;
+   dma_addr_t dma_buffer_start;
+   dma_addr_t period_ptr_submitted;
+   dma_addr_t period_ptr_ended;
+   dma_addr_t dma_buffer_end;
+   size_t period_size;
+   struct snd_pcm_substream *substream;
+};
+
+static int qmc_audio_pcm_construct(struct snd_soc_component *component,
+  struct snd_soc_pcm_runtime *rtd)
+{
+   struct snd_card *card = rtd->card->snd_card;
+   int ret;
+
+   ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
+   if (ret)
+   return ret;
+
+   snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, card->dev,
+  64*1024, 64*1024);
+   return 0;
+}
+
+static int qmc_audio_pcm_hw_params(struct snd_soc_component *component,
+  struct snd_pcm_substream *substream,
+  struct snd_pcm_hw_params *params)
+{
+   struct snd_pcm_runtime *runtime = substream->runtime;
+   struct qmc_dai_prtd *prtd = substream->runtime->private_data;
+
+   prtd->dma_buffer_start = runtime->dma_addr;
+   prtd->dma_buffer_end = runtime->dma_addr + params_buffer_bytes(params);
+   prtd->period_size = params_period_bytes(params);
+   prtd->period_ptr_submitted = prtd->dma_buffer_start;
+   prtd->period_ptr_ended = prtd->dma_buffer_start;
+   prtd->substream = substream;
+
+   return 0;
+}
+
+static void qmc_audio_pcm_write_complete(void *context)
+{
+   struct qmc_dai_prtd *prtd = context;
+   int ret;
+
+   prtd->period_ptr_ended += prtd->period_size;
+   if (prtd->period_ptr_ended >= prtd->dma_buffer_end)
+   prtd->period_ptr_ended = prtd->dma_buffer_start;
+
+   prtd->period_ptr_submitted += prtd->period_size;
+   if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
+   prtd->period_ptr_submitted = prtd->dma_buffer_start;
+
+   ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
+   prtd->period_ptr_submitted, prtd->period_size,
+   qmc_audio_pcm_write_complete, 

[PATCH v2 08/10] dt-bindings: sound: Add support for QMC audio

[Herve Codina]

The QMC (QUICC mutichannel controller) is a controller
present in some PowerQUICC SoC such as MPC885.
The QMC audio is an ASoC component that uses the QMC
controller to transfer the audio data.

Signed-off-by: Herve Codina 
---
 .../bindings/sound/fsl,qmc-audio.yaml | 110 ++
 1 file changed, 110 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml

diff --git a/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml 
b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
new file mode 100644
index ..b3774be36c19
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QMC audio
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The QMC audio is an ASoC component which uses QMC (QUICC Multichannel
+  Controller) channels to transfer the audio data.
+  It provides as many DAI as the number of QMC channel used.
+
+properties:
+  compatible:
+items:
+  - const: fsl,qmc-audio
+
+  '#address-cells':
+const: 1
+  '#size-cells':
+const: 0
+  '#sound-dai-cells':
+const: 1
+
+patternProperties:
+  "^dai@([0-9]|[1-5][0-9]|6[0-3])$":
+description:
+  A DAI managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 63
+description:
+  The DAI number
+
+  qmc-chan:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: phandle to the QMC channel
+maxItems: 1
+
+required:
+  - reg
+  - qmc-chan
+
+required:
+  - compatible
+  - '#address-cells'
+  - '#size-cells'
+  - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+qmc_audio: qmc_audio {
+compatible = "fsl,qmc-audio";
+#address-cells = <1>;
+#size-cells = <0>;
+#sound-dai-cells = <1>;
+dai@16 {
+reg = <16>;
+qmc-chan = <_qmc 16>;
+};
+dai@17 {
+reg = <17>;
+qmc-chan = <_qmc 17>;
+};
+};
+
+sound {
+compatible = "simple-audio-card";
+#address-cells = <1>;
+#size-cells = <0>;
+simple-audio-card,dai-link@0 {
+reg = <0>;
+format = "dsp_b";
+cpu {
+sound-dai = <_audio 16>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 3, 5, 7, 9 */
+dai-tdm-slot-tx-mask = <0 0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 0 1 0 1 0 1 0 1>;
+};
+};
+simple-audio-card,dai-link@1 {
+reg = <1>;
+format = "dsp_b";
+cpu {
+sound-dai = <_audio 17>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 2, 4, 6, 8 */
+dai-tdm-slot-tx-mask = <0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 1 0 1 0 1 0 1>;
+};
+};
+};
-- 
2.38.1

[PATCH v2 07/10] MAINTAINERS: add the Freescale QMC controller entry

[Herve Codina]

After contributing the driver, add myself as the maintainer
for the Freescale QMC controller.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2b4f5fe7ebad..480f90db699d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8372,6 +8372,14 @@ S:   Maintained
 F: drivers/soc/fsl/qe/
 F: include/soc/fsl/qe/
 
+FREESCALE QUICC ENGINE QMC DRIVER
+M: Herve Codina 
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
+F: drivers/soc/fsl/qe/qmc.c
+F: include/soc/fsl/qe/qmc.h
+
 FREESCALE QUICC ENGINE TSA DRIVER
 M: Herve Codina 
 L: linuxppc-dev@lists.ozlabs.org
-- 
2.38.1

[PATCH v2 06/10] soc: fsl: qe: Add support for QMC

[Herve Codina]

The QMC (QUICC Multichannel Controller) is available on some
PowerQUICC SoC such as the MPC885 or MPC866.

It emulates up to 64 channels within one serial controller
using the same TDM physical interface routed from the TSA.

Signed-off-by: Herve Codina 
---
 drivers/soc/fsl/qe/Kconfig  |   12 +
 drivers/soc/fsl/qe/Makefile |1 +
 drivers/soc/fsl/qe/qmc.c| 1493 +++
 include/soc/fsl/qe/qmc.h|   71 ++
 4 files changed, 1577 insertions(+)
 create mode 100644 drivers/soc/fsl/qe/qmc.c
 create mode 100644 include/soc/fsl/qe/qmc.h

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 60ec11c9f4d9..25b218351ae3 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -44,6 +44,18 @@ config CPM_TSA
  This option enables support for this
  controller
 
+config CPM_QMC
+   tristate "CPM QMC support"
+   depends on OF && HAS_IOMEM
+   depends on CPM1 || (PPC && COMPILE_TEST)
+   depends on CPM_TSA
+   help
+ Freescale CPM QUICC Multichannel Controller
+ (QMC)
+
+ This option enables support for this
+ controller
+
 config QE_TDM
bool
default y if FSL_UCC_HDLC
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 45c961acc81b..ec8506e13113 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
 obj-$(CONFIG_CPM)  += qe_common.o
 obj-$(CONFIG_CPM_TSA)  += tsa.o
+obj-$(CONFIG_CPM_QMC)  += qmc.o
 obj-$(CONFIG_UCC)  += ucc.o
 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
new file mode 100644
index ..87e788e2a8ce
--- /dev/null
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -0,0 +1,1493 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * QMC driver
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "tsa.h"
+
+/* SCC general mode register high (32 bits) */
+#define SCC_GSMRL  0x00
+#define SCC_GSMRL_ENR  (1 << 5)
+#define SCC_GSMRL_ENT  (1 << 4)
+#define SCC_GSMRL_MODE_QMC (0x0A << 0)
+
+/* SCC general mode register low (32 bits) */
+#define SCC_GSMRH  0x04
+#define   SCC_GSMRH_CTSS   (1 << 7)
+#define   SCC_GSMRH_CDS(1 << 8)
+#define   SCC_GSMRH_CTSP   (1 << 9)
+#define   SCC_GSMRH_CDP(1 << 10)
+
+/* SCC event register (16 bits) */
+#define SCC_SCCE   0x10
+#define   SCC_SCCE_IQOV(1 << 3)
+#define   SCC_SCCE_GINT(1 << 2)
+#define   SCC_SCCE_GUN (1 << 1)
+#define   SCC_SCCE_GOV (1 << 0)
+
+/* SCC mask register (16 bits) */
+#define SCC_SCCM   0x14
+/* Multichannel base pointer (32 bits) */
+#define QMC_GBL_MCBASE 0x00
+/* Multichannel controller state (16 bits) */
+#define QMC_GBL_QMCSTATE   0x04
+/* Maximum receive buffer length (16 bits) */
+#define QMC_GBL_MRBLR  0x06
+/* Tx time-slot assignment table pointer (16 bits) */
+#define QMC_GBL_TX_S_PTR   0x08
+/* Rx pointer (16 bits) */
+#define QMC_GBL_RXPTR  0x0A
+/* Global receive frame threshold (16 bits) */
+#define QMC_GBL_GRFTHR 0x0C
+/* Global receive frame count (16 bits) */
+#define QMC_GBL_GRFCNT 0x0E
+/* Multichannel interrupt base address (32 bits) */
+#define QMC_GBL_INTBASE0x10
+/* Multichannel interrupt pointer (32 bits) */
+#define QMC_GBL_INTPTR 0x14
+/* Rx time-slot assignment table pointer (16 bits) */
+#define QMC_GBL_RX_S_PTR   0x18
+/* Tx pointer (16 bits) */
+#define QMC_GBL_TXPTR  0x1A
+/* CRC constant (32 bits) */
+#define QMC_GBL_C_MASK32   0x1C
+/* Time slot assignment table Rx (32 x 16 bits) */
+#define QMC_GBL_TSATRX 0x20
+/* Time slot assignment table Tx (32 x 16 bits) */
+#define QMC_GBL_TSATTX 0x60
+/* CRC constant (16 bits) */
+#define QMC_GBL_C_MASK16   0xA0
+
+/* TSA entry (16bit entry in TSATRX and TSATTX) */
+#define QMC_TSA_VALID  (1 << 15)
+#define QMC_TSA_WRAP   (1 << 14)
+#define QMC_TSA_MASK   (0x303F)
+#define QMC_TSA_CHANNEL(x) ((x) << 6)
+
+/* Tx buffer descriptor base address (16 bits, offset from MCBASE) */
+#define QMC_SPE_TBASE  0x00
+
+/* Channel mode register (16 bits) */
+#define QMC_SPE_CHAMR  0x02
+#define   QMC_SPE_CHAMR_MODE_HDLC  (1 << 15)
+#define   QMC_SPE_CHAMR_MODE_TRANSP((0 << 15) | (1 << 13))
+#define   QMC_SPE_CHAMR_ENT(1 << 12)
+#define   QMC_SPE_CHAMR_POL(1 << 8)
+#define   QMC_SPE_CHAMR_HDLC_IDLM  (1 << 13)
+#define   QMC_SPE_CHAMR_HDLC_CRC   (1 << 7)
+#define   QMC_SPE_CHAMR_HDLC_NOF   (0x0f << 0)
+#define   QMC_SPE_CHAMR_TRANSP_RD  (1 << 14)
+#define   

[PATCH v2 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller

[Herve Codina]

Add support for the QMC (QUICC Multichannel Controller)
available in some PowerQUICC SoC such as MPC885 or MPC866.

Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml  | 167 ++
 1 file changed, 167 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
new file mode 100644
index ..caf71f3a3f3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
+  one serial controller using the same TDM physical interface routed from
+  TSA.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - fsl,mpc885-scc-qmc
+  - fsl,mpc866-scc-qmc
+  - const: fsl,cpm1-scc-qmc
+
+  reg:
+items:
+  - description: SCC (Serial communication controller) register base
+  - description: SCC parameter ram base
+  - description: Dual port ram base
+
+  reg-names:
+items:
+  - const: scc_regs
+  - const: scc_pram
+  - const: dpram
+
+  interrupts:
+description: SCC interrupt line in the CPM interrupt controller
+
+  fsl,cpm-command:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Cf. soc/fsl/cpm_qe/cpm.txt
+
+  tsa:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: phandle to the TSA
+
+  tsa-cell-id:
+enum: [1, 2, 3]
+description: |
+  TSA cell ID (dt-bindings/soc/fsl-tsa.h defines these values)
+   - 1: SCC2
+   - 2: SCC3
+   - 3: SCC4
+
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+  '#chan-cells':
+const: 1
+
+patternProperties:
+  "^channel@([0-9]|[1-5][0-9]|6[0-3])$":
+description:
+  A channel managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 63
+description:
+  The channel number
+
+  fsl,mode:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [transparent, hdlc]
+default: transparent
+description: Operational mode
+
+  fsl,reverse-data:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  The bit order as seen on the channels is reversed,
+  transmitting/receiving the MSB of each octet first.
+  This flag is used only in 'transparent' mode.
+
+  tx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+  Channel assigned Tx time-slots within the Tx time-slots routed
+  by the TSA to this cell.
+
+  rx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+  Channel assigned Rx time-slots within the Rx time-slots routed
+  by the TSA to this cell.
+
+required:
+  - reg
+  - tx-ts-mask
+  - rx-ts-mask
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - tsa
+  - tsa-cell-id
+  - '#address-cells'
+  - '#size-cells'
+  - '#chan-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+scc_qmc@a60 {
+compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
+reg = <0xa60 0x20>,
+  <0x3f00 0xc0>,
+  <0x2000 0x1000>;
+reg-names = "scc_regs", "scc_pram", "dpram";
+interrupts = <27>;
+interrupt-parent = <_PIC>;
+fsl,cpm-command = <0xc0>;
+
+#address-cells = <1>;
+#size-cells = <0>;
+#chan-cells = <1>;
+
+tsa = <>;
+tsa-cell-id = ;
+
+channel@16 {
+/* Ch16 : First 4 even TS from all routed from TSA */
+reg = <16>;
+fsl,mode = "transparent";
+fsl,reverse-data;
+tx-ts-mask = <0x 0x00AA>;
+rx-ts-mask = <0x 0x00AA>;
+};
+
+channel@17 {
+/* Ch17 : First 4 odd TS from all routed from TSA */
+reg = <17>;
+fsl,mode = "transparent";
+fsl,reverse-data;
+tx-ts-mask = <0x 0x0055>;
+rx-ts-mask = <0x 0x0055>;
+};
+
+channel@19 {
+/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
+reg = <19>;
+fsl,mode = "hdlc";
+tx-ts-mask = <0x 0xFF00>;
+rx-ts-mask = <0x 0xFF00>;
+};
+};
-- 
2.38.1

[PATCH v2 04/10] powerpc/8xx: Use a larger CPM1 command check mask

[Herve Codina]

The CPM1 command mask is defined for use with the standard
CPM1 command register as described in the user's manual:
  0  |13|47|8   11|12  14| 15|
  RST|- |OPCODE|CH_NUM| -|FLG|

In the QMC extension the CPM1 command register is redefined
(QMC supplement user's manuel) with the following mapping:
  0  |13|47|8   13|14| 15|
  RST|QMC OPCODE|  1110|CHANNEL_NUMBER| -|FLG|

Extend the check command mask in order to support both the
standard CH_NUM field and the QMC extension CHANNEL_NUMBER
field.

Signed-off-by: Herve Codina 
---
 arch/powerpc/platforms/8xx/cpm1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/8xx/cpm1.c 
b/arch/powerpc/platforms/8xx/cpm1.c
index 8ef1f4392086..6b828b9f90d9 100644
--- a/arch/powerpc/platforms/8xx/cpm1.c
+++ b/arch/powerpc/platforms/8xx/cpm1.c
@@ -100,7 +100,7 @@ int cpm_command(u32 command, u8 opcode)
int i, ret;
unsigned long flags;
 
-   if (command & 0xff0f)
+   if (command & 0xff03)
return -EINVAL;
 
spin_lock_irqsave(_lock, flags);
-- 
2.38.1

[PATCH v2 02/10] soc: fsl: qe: Add support for TSA

[Herve Codina]

The TSA (Time Slot Assigner) is available in some
PowerQUICC SoC such as the MPC885 or MPC866.

Its purpose is to route some TDM time-slots to other
internal serial controllers.

Signed-off-by: Herve Codina 
---
 drivers/soc/fsl/qe/Kconfig  |  11 +
 drivers/soc/fsl/qe/Makefile |   1 +
 drivers/soc/fsl/qe/tsa.c| 783 
 drivers/soc/fsl/qe/tsa.h|  43 ++
 4 files changed, 838 insertions(+)
 create mode 100644 drivers/soc/fsl/qe/tsa.c
 create mode 100644 drivers/soc/fsl/qe/tsa.h

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 357c5800b112..60ec11c9f4d9 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -33,6 +33,17 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
 
+config CPM_TSA
+   tristate "CPM TSA support"
+   depends on OF && HAS_IOMEM
+   depends on CPM1 || (PPC && COMPILE_TEST)
+   help
+ Freescale CPM Time Slot Assigner (TSA)
+ controller.
+
+ This option enables support for this
+ controller
+
 config QE_TDM
bool
default y if FSL_UCC_HDLC
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 55a555304f3a..45c961acc81b 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -4,6 +4,7 @@
 #
 obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
 obj-$(CONFIG_CPM)  += qe_common.o
+obj-$(CONFIG_CPM_TSA)  += tsa.o
 obj-$(CONFIG_UCC)  += ucc.o
 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
new file mode 100644
index ..ed4a92e82fa1
--- /dev/null
+++ b/drivers/soc/fsl/qe/tsa.c
@@ -0,0 +1,783 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TSA driver
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include "tsa.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* TSA SI RAM routing tables entry */
+#define TSA_SIRAM_ENTRY_LAST   (1 << 16)
+#define TSA_SIRAM_ENTRY_BYTE   (1 << 17)
+#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18)
+#define TSA_SIRAM_ENTRY_CSEL_MASK  (0x7 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_NU(0x0 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC2  (0x2 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC3  (0x3 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC4  (0x4 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC1  (0x5 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC2  (0x6 << 22)
+
+/* SI mode register (32 bits) */
+#define TSA_SIMODE 0x00
+#define   TSA_SIMODE_SMC2  0x8000
+#define   TSA_SIMODE_SMC1  0x8000
+#define   TSA_SIMODE_TDMA(x)   ((x) << 0)
+#define   TSA_SIMODE_TDMB(x)   ((x) << 16)
+#define TSA_SIMODE_TDM_MASK0x0fff
+#define TSA_SIMODE_TDM_SDM_MASK0x0c00
+#define   TSA_SIMODE_TDM_SDM_NORM  0x
+#define   TSA_SIMODE_TDM_SDM_ECHO  0x0400
+#define   TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800
+#define   TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00
+#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8)
+#define TSA_SIMODE_TDM_DSC 0x0080
+#define TSA_SIMODE_TDM_CRT 0x0040
+#define TSA_SIMODE_TDM_STZ 0x0020
+#define TSA_SIMODE_TDM_CE  0x0010
+#define TSA_SIMODE_TDM_FE  0x0008
+#define TSA_SIMODE_TDM_GM  0x0004
+#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0)
+
+/* SI global mode register (8 bits) */
+#define TSA_SIGMR  0x04
+#define TSA_SIGMR_ENB  (1<<3)
+#define TSA_SIGMR_ENA  (1<<2)
+#define TSA_SIGMR_RDM_MASK 0x03
+#define   TSA_SIGMR_RDM_STATIC_TDMA0x00
+#define   TSA_SIGMR_RDM_DYN_TDMA   0x01
+#define   TSA_SIGMR_RDM_STATIC_TDMAB   0x02
+#define   TSA_SIGMR_RDM_DYN_TDMAB  0x03
+
+/* SI status register (8 bits) */
+#define TSA_SISTR  0x06
+
+/* SI command register (8 bits) */
+#define TSA_SICMR  0x07
+
+/* SI clock route register (32 bits) */
+#define TSA_SICR   0x0C
+#define   TSA_SICR_SCC2(x) ((x) << 8)
+#define   TSA_SICR_SCC3(x) ((x) << 16)
+#define   TSA_SICR_SCC4(x) ((x) << 24)
+#define TSA_SICR_SCC_MASK  0x0ff
+#define TSA_SICR_SCC_GRX   (1 << 7)
+#define TSA_SICR_SCC_SCX_TSA   (1 << 6)
+#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG1   (0x0 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG2   (0x1 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG3   (0x2 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG4   (0x3 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK15  (0x4 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK26  (0x5 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK37  (0x6 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK48  (0x7 

[PATCH v2 03/10] MAINTAINERS: add the Freescale TSA controller entry

[Herve Codina]

After contributing the driver, add myself as the maintainer
for the Freescale TSA controller.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7f86d02cb427..2b4f5fe7ebad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8372,6 +8372,15 @@ S:   Maintained
 F: drivers/soc/fsl/qe/
 F: include/soc/fsl/qe/
 
+FREESCALE QUICC ENGINE TSA DRIVER
+M: Herve Codina 
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
+F: drivers/soc/fsl/qe/tsa.c
+F: drivers/soc/fsl/qe/tsa.h
+F: include/dt-bindings/soc/fsl-tsa.h
+
 FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
 M: Li Yang 
 L: net...@vger.kernel.org
-- 
2.38.1

[PATCH v2 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller

[Herve Codina]

Add support for the time slot assigner (TSA)
available in some PowerQUICC SoC such as MPC885
or MPC866.

Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml  | 262 ++
 include/dt-bindings/soc/fsl-tsa.h |  15 +
 2 files changed, 277 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
 create mode 100644 include/dt-bindings/soc/fsl-tsa.h

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
new file mode 100644
index ..7542c0fd8435
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM Time-slot assigner (TSA) controller
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The TSA is the time-slot assigner that can be found on some
+  PowerQUICC SoC.
+  Its purpose is to route some TDM time-slots to other internal
+  serial controllers.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - fsl,mpc885-tsa
+  - fsl,mpc866-tsa
+  - const: fsl,cpm1-tsa
+
+  reg:
+items:
+  - description: SI (Serial Interface) register base
+  - description: SI RAM base
+
+  reg-names:
+items:
+  - const: si_regs
+  - const: si_ram
+
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+patternProperties:
+  "^tdm@[0-1]$":
+description:
+  The TDM managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 1
+description:
+  The TDM number for this TDM, 0 for TDMa and 1 for TDMb
+
+  fsl,common-rxtx-pins:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Use common pins for both transmit and receive
+
+  clocks: true
+  clock-names: true
+
+  fsl,mode:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [normal, echo, internal-loopback, control-loopback]
+default: normal
+description: |
+  Operational mode:
+- normal:
+Normal operation
+- echo:
+Automatic echo. Rx data is resent on Tx
+- internal-loopback:
+The TDM transmitter is connected to the receiver.
+Data appears on Tx pin.
+- control-loopback:
+The TDM transmitter is connected to the receiver.
+The Tx pin is disconnected.
+
+  fsl,rx-frame-sync-delay:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+  Receive frame sync delay.
+  Indicates the delay between the Rx sync and the first bit of the
+  Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+  fsl,tx-frame-sync-delay:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+  Transmit frame sync delay.
+  Indicates the delay between the Tx sync and the first bit of the
+  Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+  fsl,clock-falling-edge:
+$ref: /schemas/types.yaml#/definitions/flag
+description: |
+  Data is sent on falling edge of the clock (and received on the
+  rising edge).
+  If 'clock-falling-edge' is not present, data is sent on the
+  rising edge (and received on the falling edge).
+
+  fsl,fsync-rising-edge:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Frame sync pulses are sampled with the rising edge of the channel
+  clock. If 'fsync-rising-edge' is not present, pulses are sample
+  with e falling edge.
+
+  fsl,double-speed-clock:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  The channel clock is twice the data rate.
+
+  fsl,grant-mode:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Grant mode enabled.
+
+  tx_ts_routes:
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+description: |
+  A list of tupple that indicates the Tx time-slots routes.
+tx_ts_routes =
+   < 2 0 0>, /* The first 2 time slots are not used */
+   < 3 1 0>, /* The next 3 ones are route to SCC2 */
+   < 4 0 0>, /* The next 4 ones are not used */
+   < 2 2 0>; /* The nest 2 ones are route to SCC3 */
+items:
+  items:
+- description:
+The number of time-slots
+  minimum: 1
+  maximum: 64
+  

[PATCH v2 00/10] Add the PowerQUICC audio support using the QMC

[Herve Codina]

Hi,

This series adds support for audio using the QMC controller
available in some Freescale PowerQUICC SoCs.

This series contains three parts in order to show the different
blocks hierarchy and their usage in this support.

The first one is related to TSA (Time Slot Assigner).
The TSA handles the data present at the pin level (TDM with up
to 64 time slots) and dispatchs them to one or more serial
controller (SCC).

The second is related to QMC (QUICC Multichannel Controller).
The QMC handles the data at the serial controller (SCC) level
and splits again the data to creates some virtual channels.

The last one is related to the audio component (QMC audio).
It is the glue between the QMC controller and the ASoC
component. It handles one or more QMC virtual channels and
creates one DAI per QMC virtual channels handled.

Compared to the v1 series, this v2 series fixes errors raised
by the test kernel robot.

Best regards,
Herve Codina

Changes v1 -> v2:
  - patch 2 and 6
Fix kernel test robot errors

  - other patches
No changes

Herve Codina (10):
  dt-bindings: soc: fsl: cpm_qe: Add TSA controller
  soc: fsl: qe: Add support for TSA
  MAINTAINERS: add the Freescale TSA controller entry
  powerpc/8xx: Use a larger CPM1 command check mask
  dt-bindings: soc: fsl: cpm_qe: Add QMC controller
  soc: fsl: qe: Add support for QMC
  MAINTAINERS: add the Freescale QMC controller entry
  dt-bindings: sound: Add support for QMC audio
  ASoC: fsl: Add support for QMC audio
  MAINTAINERS: add the Freescale QMC audio entry

 .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml  |  167 ++
 .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml  |  262 +++
 .../bindings/sound/fsl,qmc-audio.yaml |  110 ++
 MAINTAINERS   |   25 +
 arch/powerpc/platforms/8xx/cpm1.c |2 +-
 drivers/soc/fsl/qe/Kconfig|   23 +
 drivers/soc/fsl/qe/Makefile   |2 +
 drivers/soc/fsl/qe/qmc.c  | 1493 +
 drivers/soc/fsl/qe/tsa.c  |  783 +
 drivers/soc/fsl/qe/tsa.h  |   43 +
 include/dt-bindings/soc/fsl-tsa.h |   15 +
 include/soc/fsl/qe/qmc.h  |   71 +
 sound/soc/fsl/Kconfig |9 +
 sound/soc/fsl/Makefile|2 +
 sound/soc/fsl/fsl_qmc_audio.c |  731 
 15 files changed, 3737 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
 create mode 100644 drivers/soc/fsl/qe/qmc.c
 create mode 100644 drivers/soc/fsl/qe/tsa.c
 create mode 100644 drivers/soc/fsl/qe/tsa.h
 create mode 100644 include/dt-bindings/soc/fsl-tsa.h
 create mode 100644 include/soc/fsl/qe/qmc.h
 create mode 100644 sound/soc/fsl/fsl_qmc_audio.c

-- 
2.38.1

Re: Build regressions/improvements in v6.2-rc1

[Alex Deucher]

On Tue, Dec 27, 2022 at 10:34 AM Geert Uytterhoeven
 wrote:
>
> On Tue, 27 Dec 2022, Geert Uytterhoeven wrote:
> > Below is the list of build error/warning regressions/improvements in
> > v6.2-rc1[1] compared to v6.1[2].
> >
> > Summarized:
> >  - build errors: +11/-13
>
> amd-...@lists.freedesktop.org
> linux-arm-ker...@lists.infradead.org
> linux-me...@vger.kernel.org
> linux-wirel...@vger.kernel.org
> linux-m...@vger.kernel.org
> linux...@vger.kernel.org
> linux-f2fs-de...@lists.sourceforge.net
> linuxppc-dev@lists.ozlabs.org
> kasan-...@googlegroups.com
> linux-xte...@linux-xtensa.org
>
>+ 
> /kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:
>  error: the frame size of 2224 bytes is larger than 2048 bytes 
> [-Werror=frame-larger-than=]:  => 7082:1
>+ 
> /kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.c:
>  error: the frame size of 2208 bytes is larger than 2048 bytes 
> [-Werror=frame-larger-than=]:  => 7127:1
>

@Siqueira, Rodrigo @Mahfooz, Hamza

Can you take a look at fixing the DML stack size here up?

Alex


> arm64-gcc5/arm64-allmodconfig
>
>+ /kisskb/src/drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c: error: array 
> subscript 2 is above array bounds of 'u32[2]' {aka 'unsigned int[2]'} 
> [-Werror=array-bounds]:  => 641:28
>+ /kisskb/src/drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c: error: array 
> subscript 3 is above array bounds of 'u32[2]' {aka 'unsigned int[2]'} 
> [-Werror=array-bounds]:  => 641:28
>
> m68k-gcc8/m68k-allmodconfig
> See also 
> https://lore.kernel.org/all/camuhmdwppx2mpqfewjjbjsqvdbqoxyjjdpknqu9qurauvzx...@mail.gmail.com
>
>+ /kisskb/src/include/linux/bitfield.h: error: call to '__field_overflow' 
> declared with attribute error: value doesn't fit into mask:  => 151:3
>
> In function 'u32_encode_bits',
>  inlined from 'ieee80211_mlo_multicast_tx' at 
> /kisskb/src/net/mac80211/tx.c:4435:17,
>  inlined from 'ieee80211_subif_start_xmit' at 
> /kisskb/src/net/mac80211/tx.c:4483:3:
>
> mipsel-gcc5/mips-allmodconfig
>
>+ /kisskb/src/include/linux/compiler_types.h: error: call to 
> '__compiletime_assert_262' declared with attribute error: Unsupported access 
> size for {READ,WRITE}_ONCE().:  => 358:45
>+ /kisskb/src/include/linux/compiler_types.h: error: call to 
> '__compiletime_assert_263' declared with attribute error: Unsupported access 
> size for {READ,WRITE}_ONCE().:  => 358:45
>
> In function 'follow_pmd_mask',
>  inlined from 'follow_pud_mask' at /kisskb/src/mm/gup.c:735:9,
>  inlined from 'follow_p4d_mask' at /kisskb/src/mm/gup.c:752:9,
>  inlined from 'follow_page_mask' at /kisskb/src/mm/gup.c:809:9:
>
> sh4-gcc11/sh-defconfig (Günter wondered if pmd_t should use union)
>
>+ /kisskb/src/include/linux/fortify-string.h: error: '__builtin_memcpy' 
> offset [0, 127] is out of the bounds [0, 0] [-Werror=array-bounds]:  => 57:33
>
> /kisskb/src/arch/s390/kernel/setup.c: In function 'setup_lowcore_dat_on':
> s390x-gcc11/s390-all{mod,yes}config
>
>+ /kisskb/src/include/linux/fortify-string.h: error: '__builtin_memset' 
> pointer overflow between offset [28, 898293814] and size [-898293787, -1] 
> [-Werror=array-bounds]:  => 59:33
>
> /kisskb/src/fs/f2fs/inline.c: In function 'f2fs_move_inline_dirents':
>
> powerpc-gcc11/ppc64_book3e_allmodconfig
> powerpc-gcc11/powerpc-all{mod,yes}config
>
>+ /kisskb/src/kernel/kcsan/kcsan_test.c: error: the frame size of 1680 
> bytes is larger than 1536 bytes [-Werror=frame-larger-than=]:  => 257:1
>
> xtensa-gcc11/xtensa-allmodconfig (patch available)
>
>+ {standard input}: Error: unknown pseudo-op: `.cfi_def_c':  => 1718
>
> sh4-gcc11/sh-allmodconfig (ICE = internal compiler error)
>
> > [1] 
> > http://kisskb.ellerman.id.au/kisskb/branch/linus/head/1b929c02afd37871d5afb9d498426f83432e71c2/
> >  (all 152 configs)
> > [2] 
> > http://kisskb.ellerman.id.au/kisskb/branch/linus/head/830b3c68c1fb1e9176028d02ef86f3cf76aa2476/
> >  (all 152 configs)
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds

Re: Build regressions/improvements in v6.2-rc1

[Geert Uytterhoeven]

On Fri, Jan 6, 2023 at 4:17 PM Geert Uytterhoeven  wrote:
>
> Hi John,

Bummer, "Hi Adrian", ofc ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2] ALSA: aoa: make remove callback of soundbus driver void returned

[Dawei Li]

Since commit fc7a6209d571 ("bus: Make remove callback return void")
forces bus_type::remove be void-returned, it doesn't make much sense
for any bus based driver implementing remove callbalk to return
non-void to its caller.

As such, change the remove function for soundbus based drivers to
return void.

Signed-off-by: Dawei Li 
---
v1 -> v2
- Update commit message.
- Rebased to latest sound/for-next.

v1
- 
https://lore.kernel.org/all/tycp286mb2323bbfce929111043e60d3bca...@tycp286mb2323.jpnp286.prod.outlook.com/
---
 sound/aoa/fabrics/layout.c| 3 +--
 sound/aoa/soundbus/soundbus.h | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/sound/aoa/fabrics/layout.c b/sound/aoa/fabrics/layout.c
index ec4ef18555bc..850dc8c53e9b 100644
--- a/sound/aoa/fabrics/layout.c
+++ b/sound/aoa/fabrics/layout.c
@@ -1094,7 +1094,7 @@ static int aoa_fabric_layout_probe(struct soundbus_dev 
*sdev)
return -ENODEV;
 }
 
-static int aoa_fabric_layout_remove(struct soundbus_dev *sdev)
+static void aoa_fabric_layout_remove(struct soundbus_dev *sdev)
 {
struct layout_dev *ldev = dev_get_drvdata(>ofdev.dev);
int i;
@@ -1123,7 +1123,6 @@ static int aoa_fabric_layout_remove(struct soundbus_dev 
*sdev)
kfree(ldev);
sdev->pcmid = -1;
sdev->pcmname = NULL;
-   return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/sound/aoa/soundbus/soundbus.h b/sound/aoa/soundbus/soundbus.h
index 3a99c1f1a3ca..db40f9d042b4 100644
--- a/sound/aoa/soundbus/soundbus.h
+++ b/sound/aoa/soundbus/soundbus.h
@@ -185,7 +185,7 @@ struct soundbus_driver {
/* we don't implement any matching at all */
 
int (*probe)(struct soundbus_dev* dev);
-   int (*remove)(struct soundbus_dev* dev);
+   void(*remove)(struct soundbus_dev *dev);
 
int (*shutdown)(struct soundbus_dev* dev);
 
-- 
2.25.1

Re: Build regressions/improvements in v6.2-rc1

[Geert Uytterhoeven]

Hi John,

On Fri, Jan 6, 2023 at 4:10 PM John Paul Adrian Glaubitz
 wrote:
> On 12/27/22 09:35, Geert Uytterhoeven wrote:
> >+ /kisskb/src/include/linux/compiler_types.h: error: call to 
> > '__compiletime_assert_262' declared with attribute error: Unsupported 
> > access size for {READ,WRITE}_ONCE().:  => 358:45
> >+ /kisskb/src/include/linux/compiler_types.h: error: call to 
> > '__compiletime_assert_263' declared with attribute error: Unsupported 
> > access size for {READ,WRITE}_ONCE().:  => 358:45
> >
> > In function 'follow_pmd_mask',
> >  inlined from 'follow_pud_mask' at /kisskb/src/mm/gup.c:735:9,
> >  inlined from 'follow_p4d_mask' at /kisskb/src/mm/gup.c:752:9,
> >  inlined from 'follow_page_mask' at /kisskb/src/mm/gup.c:809:9:
> >
> > sh4-gcc11/sh-defconfig (Günter wondered if pmd_t should use union)
>
> I'm seeing this, too. Also for sh7785lcr_defconfig.
>
> > sh4-gcc11/sh-allmodconfig (ICE = internal compiler error)
>
> I'm not seeing this one, but I am getting this one instead:
>
> In file included from ./arch/sh/include/asm/hw_irq.h:6,
>   from ./include/linux/irq.h:596,
>   from ./include/asm-generic/hardirq.h:17,
>   from ./arch/sh/include/asm/hardirq.h:9,
>   from ./include/linux/hardirq.h:11,
>   from ./include/linux/interrupt.h:11,
>   from ./include/linux/serial_core.h:13,
>   from ./include/linux/serial_sci.h:6,
>   from arch/sh/kernel/cpu/sh2/setup-sh7619.c:11:
> ./include/linux/sh_intc.h:100:63: error: division 'sizeof (void *) / sizeof 
> (void)' does not compute the number of array elements 
> [-Werror=sizeof-pointer-div]
>100 | #define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : 
> sizeof(a)/sizeof(*a)
>|   ^
> ./include/linux/sh_intc.h:105:31: note: in expansion of macro '_INTC_ARRAY'
>105 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups),  \
>|   ^~~

The easiest fix for the latter is to disable CONFIG_WERROR.
Unfortunately I don't know a simple solution to get rid of the warning.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: Build regressions/improvements in v6.2-rc1

[John Paul Adrian Glaubitz]

Hi Geert!

On 12/27/22 09:35, Geert Uytterhoeven wrote:

   + /kisskb/src/include/linux/compiler_types.h: error: call to 
'__compiletime_assert_262' declared with attribute error: Unsupported access size 
for {READ,WRITE}_ONCE().:  => 358:45
   + /kisskb/src/include/linux/compiler_types.h: error: call to 
'__compiletime_assert_263' declared with attribute error: Unsupported access size 
for {READ,WRITE}_ONCE().:  => 358:45

In function 'follow_pmd_mask',
 inlined from 'follow_pud_mask' at /kisskb/src/mm/gup.c:735:9,
 inlined from 'follow_p4d_mask' at /kisskb/src/mm/gup.c:752:9,
 inlined from 'follow_page_mask' at /kisskb/src/mm/gup.c:809:9:

sh4-gcc11/sh-defconfig (Günter wondered if pmd_t should use union)


I'm seeing this, too. Also for sh7785lcr_defconfig.


sh4-gcc11/sh-allmodconfig (ICE = internal compiler error)


I'm not seeing this one, but I am getting this one instead:

In file included from ./arch/sh/include/asm/hw_irq.h:6,
 from ./include/linux/irq.h:596,
 from ./include/asm-generic/hardirq.h:17,
 from ./arch/sh/include/asm/hardirq.h:9,
 from ./include/linux/hardirq.h:11,
 from ./include/linux/interrupt.h:11,
 from ./include/linux/serial_core.h:13,
 from ./include/linux/serial_sci.h:6,
 from arch/sh/kernel/cpu/sh2/setup-sh7619.c:11:
./include/linux/sh_intc.h:100:63: error: division 'sizeof (void *) / sizeof 
(void)' does not compute the number of array elements 
[-Werror=sizeof-pointer-div]
  100 | #define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : 
sizeof(a)/sizeof(*a)
  |   ^
./include/linux/sh_intc.h:105:31: note: in expansion of macro '_INTC_ARRAY'
  105 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups),  \
  |   ^~~

Adrian

--
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer
`. `'   Physicist
  `-GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

Re: [PASEMI] Nemo board doesn't reboot anymore after the commit "HID: usbhid: Add ALWAYS_POLL quirk for some mice"

[Jiri Kosina]

On Fri, 6 Jan 2023, Christian Zigotzky wrote:

> Hello,
> 
> The reboot issue is still present in the RC2 of kernel 6.2. We still need the
> usbhid.patch. [1]
> 
> Please check the bad commit. [2]

Ankit,

have you tested with all the devices that you added the quirk for in your 
original patch?

Unless I hear otherwise, I will just drop 
the quirk for USB_DEVICE_ID_CHERRY_MOUSE_000C before this gets clarified.

Thanks,

-- 
Jiri Kosina
SUSE Labs

[PASEMI] Nemo board doesn't reboot anymore after the commit "HID: usbhid: Add ALWAYS_POLL quirk for some mice"

[Christian Zigotzky]

Hello,

The reboot issue is still present in the RC2 of kernel 6.2. We still 
need the usbhid.patch. [1]


Please check the bad commit. [2]

Thanks,
Christian

[1] https://forum.hyperion-entertainment.com/viewtopic.php?p=56303#p56303
[2] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v6.1=f6d910a89a2391e5ce1f275d205023880a33d3f8 




On 22 December 2022 at 11:42 am, Christian Zigotzky wrote:

Hello,

The Nemo board [1] doesn't reboot anymore since the final kernel 6.1. 
The reboot works with the RC8 of kernel 6.1.
Actually, a reboot works but the CFE firmware is not loaded. Maybe 
there is still something in the memory after the reboot.


I bisected today. [2]

The commit "HID: usbhid: Add ALWAYS_POLL quirk for some mice". [3] is 
the problem.


I was able to revert this commit and the reboot works without any 
problems again.


I created a patch for reverting the bad commit. [4]

Then I compiled the kernel with this patch. After that, the X1000 
reboots without any problems.


I use a Cherry USB mouse. [5]

Please check the bad commit.

Thanks,
Christian


[1] https://en.wikipedia.org/wiki/AmigaOne_X1000
[2] https://forum.hyperion-entertainment.com/viewtopic.php?p=56303#p56303
[3] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v6.1=f6d910a89a2391e5ce1f275d205023880a33d3f8

[4] usbhid.patch:

diff -rupN a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
--- a/drivers/hid/hid-ids.h    2022-12-22 10:24:06.842881276 +0100
+++ b/drivers/hid/hid-ids.h    2022-12-22 10:23:35.903328869 +0100
@@ -274,7 +274,6 @@
 #define USB_DEVICE_ID_CH_AXIS_295    0x001c

 #define USB_VENDOR_ID_CHERRY        0x046a
-#define USB_DEVICE_ID_CHERRY_MOUSE_000C    0x000c
 #define USB_DEVICE_ID_CHERRY_CYMOTION    0x0023
 #define USB_DEVICE_ID_CHERRY_CYMOTION_SOLAR    0x0027

@@ -919,7 +918,6 @@
 #define USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER    0x02fd
 #define USB_DEVICE_ID_MS_PIXART_MOUSE    0x00cb
 #define USB_DEVICE_ID_8BITDO_SN30_PRO_PLUS  0x02e0
-#define USB_DEVICE_ID_MS_MOUSE_0783  0x0783

 #define USB_VENDOR_ID_MOJO        0x8282
 #define USB_DEVICE_ID_RETRO_ADAPTER    0x3201
@@ -1388,7 +1386,6 @@

 #define USB_VENDOR_ID_PRIMAX    0x0461
 #define USB_DEVICE_ID_PRIMAX_MOUSE_4D22    0x4d22
-#define USB_DEVICE_ID_PRIMAX_MOUSE_4E2A    0x4e2a
 #define USB_DEVICE_ID_PRIMAX_KEYBOARD    0x4e05
 #define USB_DEVICE_ID_PRIMAX_REZEL    0x4e72
 #define USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4D0F    0x4d0f
diff -rupN a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
--- a/drivers/hid/hid-quirks.c    2022-12-22 10:24:06.844881247 +0100
+++ b/drivers/hid/hid-quirks.c    2022-12-22 10:23:35.904328855 +0100
@@ -54,7 +54,6 @@ static const struct hid_device_id hid_qu
 { HID_USB_DEVICE(USB_VENDOR_ID_CH, 
USB_DEVICE_ID_CH_FLIGHT_SIM_YOKE), HID_QUIRK_NOGET },
 { HID_USB_DEVICE(USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_PRO_PEDALS), 
HID_QUIRK_NOGET },
 { HID_USB_DEVICE(USB_VENDOR_ID_CH, 
USB_DEVICE_ID_CH_PRO_THROTTLE), HID_QUIRK_NOGET },
-    { HID_USB_DEVICE(USB_VENDOR_ID_CHERRY, 
USB_DEVICE_ID_CHERRY_MOUSE_000C), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, 
USB_DEVICE_ID_CORSAIR_K65RGB), HID_QUIRK_NO_INIT_REPORTS },
 { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, 
USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE), HID_QUIRK_NO_INIT_REPORTS | 
HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, 
USB_DEVICE_ID_CORSAIR_K70RGB), HID_QUIRK_NO_INIT_REPORTS },

@@ -123,7 +122,6 @@ static const struct hid_device_id hid_qu
 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 
USB_DEVICE_ID_LOGITECH_MOUSE_C05A), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 
USB_DEVICE_ID_LOGITECH_MOUSE_C06A), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_MCS, 
USB_DEVICE_ID_MCS_GAMEPADBLOCK), HID_QUIRK_MULTI_INPUT },
-    { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, 
USB_DEVICE_ID_MS_MOUSE_0783), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, 
USB_DEVICE_ID_MS_PIXART_MOUSE), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, 
USB_DEVICE_ID_MS_POWER_COVER), HID_QUIRK_NO_INIT_REPORTS },
 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, 
USB_DEVICE_ID_MS_SURFACE3_COVER), HID_QUIRK_NO_INIT_REPORTS },

@@ -148,7 +146,6 @@ static const struct hid_device_id hid_qu
 { HID_USB_DEVICE(USB_VENDOR_ID_PIXART, 
USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN), HID_QUIRK_NO_INIT_REPORTS },
 { HID_USB_DEVICE(USB_VENDOR_ID_PIXART, 
USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, 
USB_DEVICE_ID_PRIMAX_MOUSE_4D22), HID_QUIRK_ALWAYS_POLL },
-    { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, 
USB_DEVICE_ID_PRIMAX_MOUSE_4E2A), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, 
USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4D0F), HID_QUIRK_ALWAYS_POLL },
 { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, 
USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4D65), HID_QUIRK_ALWAYS_POLL 

Re: [PATCH] ASoC: fsl_micfil: Correct the number of steps on SX controls

[Mark Brown]

On Wed, 04 Jan 2023 10:57:54 +0800, Chancel Liu wrote:
> The parameter "max" of SOC_SINGLE_SX_TLV() means the number of steps
> rather than maximum value. This patch corrects the minimum value to -8
> and the number of steps to 15.
> 
> 

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: fsl_micfil: Correct the number of steps on SX controls
  commit: cdfa92eb90f5770b26a79824ef213ebdbbd988b1

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

[PATCH 10/10] MAINTAINERS: add the Freescale QMC audio entry

[Herve Codina]

After contributing the component, add myself as the maintainer
for the Freescale QMC audio ASoC component.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 480f90db699d..a15997c2cc05 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8440,6 +8440,14 @@ F:   sound/soc/fsl/fsl*
 F: sound/soc/fsl/imx*
 F: sound/soc/fsl/mpc8610_hpcd.c
 
+FREESCALE SOC SOUND QMC DRIVER
+M: Herve Codina 
+L: alsa-de...@alsa-project.org (moderated for non-subscribers)
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
+F: sound/soc/fsl/fsl_qmc_audio.c
+
 FREESCALE USB PERIPHERAL DRIVERS
 M: Li Yang 
 L: linux-...@vger.kernel.org
-- 
2.38.1

[PATCH 09/10] ASoC: fsl: Add support for QMC audio

[Herve Codina]

The QMC audio is an ASoC component which provides DAIs
that use the QMC (QUICC Multichannel Controller) to transfer
the audio data.

It provides as many DAIs as the number of QMC channels it
references.

Signed-off-by: Herve Codina 
---
 sound/soc/fsl/Kconfig |   9 +
 sound/soc/fsl/Makefile|   2 +
 sound/soc/fsl/fsl_qmc_audio.c | 731 ++
 3 files changed, 742 insertions(+)
 create mode 100644 sound/soc/fsl/fsl_qmc_audio.c

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 614eceda6b9e..17db29c25d96 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -172,6 +172,15 @@ config SND_MPC52xx_DMA
 config SND_SOC_POWERPC_DMA
tristate
 
+config SND_SOC_POWERPC_QMC_AUDIO
+   tristate "QMC ALSA SoC support"
+   depends on CPM_QMC
+   help
+ ALSA SoC Audio support using the Freescale QUICC Multichannel
+ Controller (QMC).
+ Say Y or M if you want to add support for SoC audio using Freescale
+ QMC.
+
 comment "SoC Audio support for Freescale PPC boards:"
 
 config SND_SOC_MPC8610_HPCD
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b54beb1a66fa..8db7e97d0bd5 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -28,6 +28,7 @@ snd-soc-fsl-easrc-objs := fsl_easrc.o
 snd-soc-fsl-xcvr-objs := fsl_xcvr.o
 snd-soc-fsl-aud2htx-objs := fsl_aud2htx.o
 snd-soc-fsl-rpmsg-objs := fsl_rpmsg.o
+snd-soc-fsl-qmc-audio-objs := fsl_qmc_audio.o
 
 obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
 obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
 obj-$(CONFIG_SND_SOC_FSL_AUD2HTX) += snd-soc-fsl-aud2htx.o
 obj-$(CONFIG_SND_SOC_FSL_RPMSG) += snd-soc-fsl-rpmsg.o
+obj-$(CONFIG_SND_SOC_POWERPC_QMC_AUDIO) += snd-soc-fsl-qmc-audio.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
new file mode 100644
index ..6d651e6efa09
--- /dev/null
+++ b/sound/soc/fsl/fsl_qmc_audio.c
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ALSA SoC using the QUICC Multichannel Controller (QMC)
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct qmc_dai {
+   char *name;
+   int id;
+   struct device *dev;
+   struct qmc_chan *qmc_chan;
+   unsigned int nb_tx_ts;
+   unsigned int nb_rx_ts;
+};
+
+struct qmc_audio {
+   struct device *dev;
+   unsigned int num_dais;
+   struct qmc_dai *dais;
+   struct snd_soc_dai_driver *dai_drivers;
+};
+
+struct qmc_dai_prtd {
+   struct qmc_dai *qmc_dai;
+   dma_addr_t dma_buffer_start;
+   dma_addr_t period_ptr_submitted;
+   dma_addr_t period_ptr_ended;
+   dma_addr_t dma_buffer_end;
+   size_t period_size;
+   struct snd_pcm_substream *substream;
+};
+
+static int qmc_audio_pcm_construct(struct snd_soc_component *component,
+  struct snd_soc_pcm_runtime *rtd)
+{
+   struct snd_card *card = rtd->card->snd_card;
+   int ret;
+
+   ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
+   if (ret)
+   return ret;
+
+   snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, card->dev,
+  64*1024, 64*1024);
+   return 0;
+}
+
+static int qmc_audio_pcm_hw_params(struct snd_soc_component *component,
+  struct snd_pcm_substream *substream,
+  struct snd_pcm_hw_params *params)
+{
+   struct snd_pcm_runtime *runtime = substream->runtime;
+   struct qmc_dai_prtd *prtd = substream->runtime->private_data;
+
+   prtd->dma_buffer_start = runtime->dma_addr;
+   prtd->dma_buffer_end = runtime->dma_addr + params_buffer_bytes(params);
+   prtd->period_size = params_period_bytes(params);
+   prtd->period_ptr_submitted = prtd->dma_buffer_start;
+   prtd->period_ptr_ended = prtd->dma_buffer_start;
+   prtd->substream = substream;
+
+   return 0;
+}
+
+static void qmc_audio_pcm_write_complete(void *context)
+{
+   struct qmc_dai_prtd *prtd = context;
+   int ret;
+
+   prtd->period_ptr_ended += prtd->period_size;
+   if (prtd->period_ptr_ended >= prtd->dma_buffer_end)
+   prtd->period_ptr_ended = prtd->dma_buffer_start;
+
+   prtd->period_ptr_submitted += prtd->period_size;
+   if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
+   prtd->period_ptr_submitted = prtd->dma_buffer_start;
+
+   ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
+   prtd->period_ptr_submitted, prtd->period_size,
+   qmc_audio_pcm_write_complete, 

[PATCH 07/10] MAINTAINERS: add the Freescale QMC controller entry

[Herve Codina]

After contributing the driver, add myself as the maintainer
for the Freescale QMC controller.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2b4f5fe7ebad..480f90db699d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8372,6 +8372,14 @@ S:   Maintained
 F: drivers/soc/fsl/qe/
 F: include/soc/fsl/qe/
 
+FREESCALE QUICC ENGINE QMC DRIVER
+M: Herve Codina 
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
+F: drivers/soc/fsl/qe/qmc.c
+F: include/soc/fsl/qe/qmc.h
+
 FREESCALE QUICC ENGINE TSA DRIVER
 M: Herve Codina 
 L: linuxppc-dev@lists.ozlabs.org
-- 
2.38.1

[PATCH 08/10] dt-bindings: sound: Add support for QMC audio

[Herve Codina]

The QMC (QUICC mutichannel controller) is a controller
present in some PowerQUICC SoC such as MPC885.
The QMC audio is an ASoC component that uses the QMC
controller to transfer the audio data.

Signed-off-by: Herve Codina 
---
 .../bindings/sound/fsl,qmc-audio.yaml | 110 ++
 1 file changed, 110 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml

diff --git a/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml 
b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
new file mode 100644
index ..b3774be36c19
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QMC audio
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The QMC audio is an ASoC component which uses QMC (QUICC Multichannel
+  Controller) channels to transfer the audio data.
+  It provides as many DAI as the number of QMC channel used.
+
+properties:
+  compatible:
+items:
+  - const: fsl,qmc-audio
+
+  '#address-cells':
+const: 1
+  '#size-cells':
+const: 0
+  '#sound-dai-cells':
+const: 1
+
+patternProperties:
+  "^dai@([0-9]|[1-5][0-9]|6[0-3])$":
+description:
+  A DAI managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 63
+description:
+  The DAI number
+
+  qmc-chan:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: phandle to the QMC channel
+maxItems: 1
+
+required:
+  - reg
+  - qmc-chan
+
+required:
+  - compatible
+  - '#address-cells'
+  - '#size-cells'
+  - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+qmc_audio: qmc_audio {
+compatible = "fsl,qmc-audio";
+#address-cells = <1>;
+#size-cells = <0>;
+#sound-dai-cells = <1>;
+dai@16 {
+reg = <16>;
+qmc-chan = <_qmc 16>;
+};
+dai@17 {
+reg = <17>;
+qmc-chan = <_qmc 17>;
+};
+};
+
+sound {
+compatible = "simple-audio-card";
+#address-cells = <1>;
+#size-cells = <0>;
+simple-audio-card,dai-link@0 {
+reg = <0>;
+format = "dsp_b";
+cpu {
+sound-dai = <_audio 16>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 3, 5, 7, 9 */
+dai-tdm-slot-tx-mask = <0 0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 0 1 0 1 0 1 0 1>;
+};
+};
+simple-audio-card,dai-link@1 {
+reg = <1>;
+format = "dsp_b";
+cpu {
+sound-dai = <_audio 17>;
+};
+codec {
+sound-dai = <>;
+dai-tdm-slot-num = <4>;
+dai-tdm-slot-width = <8>;
+/* TS 2, 4, 6, 8 */
+dai-tdm-slot-tx-mask = <0 0 1 0 1 0 1 0 1>;
+dai-tdm-slot-rx-mask = <0 0 1 0 1 0 1 0 1>;
+};
+};
+};
-- 
2.38.1

[PATCH 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller

[Herve Codina]

Add support for the QMC (QUICC Multichannel Controller)
available in some PowerQUICC SoC such as MPC885 or MPC866.

Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml  | 167 ++
 1 file changed, 167 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
new file mode 100644
index ..caf71f3a3f3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within
+  one serial controller using the same TDM physical interface routed from
+  TSA.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - fsl,mpc885-scc-qmc
+  - fsl,mpc866-scc-qmc
+  - const: fsl,cpm1-scc-qmc
+
+  reg:
+items:
+  - description: SCC (Serial communication controller) register base
+  - description: SCC parameter ram base
+  - description: Dual port ram base
+
+  reg-names:
+items:
+  - const: scc_regs
+  - const: scc_pram
+  - const: dpram
+
+  interrupts:
+description: SCC interrupt line in the CPM interrupt controller
+
+  fsl,cpm-command:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Cf. soc/fsl/cpm_qe/cpm.txt
+
+  tsa:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: phandle to the TSA
+
+  tsa-cell-id:
+enum: [1, 2, 3]
+description: |
+  TSA cell ID (dt-bindings/soc/fsl-tsa.h defines these values)
+   - 1: SCC2
+   - 2: SCC3
+   - 3: SCC4
+
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+  '#chan-cells':
+const: 1
+
+patternProperties:
+  "^channel@([0-9]|[1-5][0-9]|6[0-3])$":
+description:
+  A channel managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 63
+description:
+  The channel number
+
+  fsl,mode:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [transparent, hdlc]
+default: transparent
+description: Operational mode
+
+  fsl,reverse-data:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  The bit order as seen on the channels is reversed,
+  transmitting/receiving the MSB of each octet first.
+  This flag is used only in 'transparent' mode.
+
+  tx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+  Channel assigned Tx time-slots within the Tx time-slots routed
+  by the TSA to this cell.
+
+  rx-ts-mask:
+$ref: /schemas/types.yaml#/definitions/uint64
+description:
+  Channel assigned Rx time-slots within the Rx time-slots routed
+  by the TSA to this cell.
+
+required:
+  - reg
+  - tx-ts-mask
+  - rx-ts-mask
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - tsa
+  - tsa-cell-id
+  - '#address-cells'
+  - '#size-cells'
+  - '#chan-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+scc_qmc@a60 {
+compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
+reg = <0xa60 0x20>,
+  <0x3f00 0xc0>,
+  <0x2000 0x1000>;
+reg-names = "scc_regs", "scc_pram", "dpram";
+interrupts = <27>;
+interrupt-parent = <_PIC>;
+fsl,cpm-command = <0xc0>;
+
+#address-cells = <1>;
+#size-cells = <0>;
+#chan-cells = <1>;
+
+tsa = <>;
+tsa-cell-id = ;
+
+channel@16 {
+/* Ch16 : First 4 even TS from all routed from TSA */
+reg = <16>;
+fsl,mode = "transparent";
+fsl,reverse-data;
+tx-ts-mask = <0x 0x00AA>;
+rx-ts-mask = <0x 0x00AA>;
+};
+
+channel@17 {
+/* Ch17 : First 4 odd TS from all routed from TSA */
+reg = <17>;
+fsl,mode = "transparent";
+fsl,reverse-data;
+tx-ts-mask = <0x 0x0055>;
+rx-ts-mask = <0x 0x0055>;
+};
+
+channel@19 {
+/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
+reg = <19>;
+fsl,mode = "hdlc";
+tx-ts-mask = <0x 0xFF00>;
+rx-ts-mask = <0x 0xFF00>;
+};
+};
-- 
2.38.1

[PATCH 04/10] powerpc/8xx: Use a larger CPM1 command check mask

[Herve Codina]

The CPM1 command mask is defined for use with the standard
CPM1 command register as described in the user's manual:
  0  |13|47|8   11|12  14| 15|
  RST|- |OPCODE|CH_NUM| -|FLG|

In the QMC extension the CPM1 command register is redefined
(QMC supplement user's manuel) with the following mapping:
  0  |13|47|8   13|14| 15|
  RST|QMC OPCODE|  1110|CHANNEL_NUMBER| -|FLG|

Extend the check command mask in order to support both the
standard CH_NUM field and the QMC extension CHANNEL_NUMBER
field.

Signed-off-by: Herve Codina 
---
 arch/powerpc/platforms/8xx/cpm1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/8xx/cpm1.c 
b/arch/powerpc/platforms/8xx/cpm1.c
index 8ef1f4392086..6b828b9f90d9 100644
--- a/arch/powerpc/platforms/8xx/cpm1.c
+++ b/arch/powerpc/platforms/8xx/cpm1.c
@@ -100,7 +100,7 @@ int cpm_command(u32 command, u8 opcode)
int i, ret;
unsigned long flags;
 
-   if (command & 0xff0f)
+   if (command & 0xff03)
return -EINVAL;
 
spin_lock_irqsave(_lock, flags);
-- 
2.38.1

[PATCH 06/10] soc: fsl: qe: Add support for QMC

[Herve Codina]

The QMC (QUICC Multichannel Controller) is available on some
PowerQUICC SoC such as the MPC885 or MPC866.

It emulates up to 64 channels within one serial controller
using the same TDM physical interface routed from the TSA.

Signed-off-by: Herve Codina 
---
 drivers/soc/fsl/qe/Kconfig  |   12 +
 drivers/soc/fsl/qe/Makefile |1 +
 drivers/soc/fsl/qe/qmc.c| 1493 +++
 include/soc/fsl/qe/qmc.h|   71 ++
 4 files changed, 1577 insertions(+)
 create mode 100644 drivers/soc/fsl/qe/qmc.c
 create mode 100644 include/soc/fsl/qe/qmc.h

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index b0088495c323..34c7a9d65507 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -44,6 +44,18 @@ config CPM_TSA
  This option enables support for this
  controller
 
+config CPM_QMC
+   tristate "CPM QMC support"
+   depends on OF && HAS_IOMEM
+   depends on CPM1 || COMPILE_TEST
+   depends on CPM_TSA
+   help
+ Freescale CPM QUICC Multichannel Controller
+ (QMC)
+
+ This option enables support for this
+ controller
+
 config QE_TDM
bool
default y if FSL_UCC_HDLC
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 45c961acc81b..ec8506e13113 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
 obj-$(CONFIG_CPM)  += qe_common.o
 obj-$(CONFIG_CPM_TSA)  += tsa.o
+obj-$(CONFIG_CPM_QMC)  += qmc.o
 obj-$(CONFIG_UCC)  += ucc.o
 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
new file mode 100644
index ..87e788e2a8ce
--- /dev/null
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -0,0 +1,1493 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * QMC driver
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "tsa.h"
+
+/* SCC general mode register high (32 bits) */
+#define SCC_GSMRL  0x00
+#define SCC_GSMRL_ENR  (1 << 5)
+#define SCC_GSMRL_ENT  (1 << 4)
+#define SCC_GSMRL_MODE_QMC (0x0A << 0)
+
+/* SCC general mode register low (32 bits) */
+#define SCC_GSMRH  0x04
+#define   SCC_GSMRH_CTSS   (1 << 7)
+#define   SCC_GSMRH_CDS(1 << 8)
+#define   SCC_GSMRH_CTSP   (1 << 9)
+#define   SCC_GSMRH_CDP(1 << 10)
+
+/* SCC event register (16 bits) */
+#define SCC_SCCE   0x10
+#define   SCC_SCCE_IQOV(1 << 3)
+#define   SCC_SCCE_GINT(1 << 2)
+#define   SCC_SCCE_GUN (1 << 1)
+#define   SCC_SCCE_GOV (1 << 0)
+
+/* SCC mask register (16 bits) */
+#define SCC_SCCM   0x14
+/* Multichannel base pointer (32 bits) */
+#define QMC_GBL_MCBASE 0x00
+/* Multichannel controller state (16 bits) */
+#define QMC_GBL_QMCSTATE   0x04
+/* Maximum receive buffer length (16 bits) */
+#define QMC_GBL_MRBLR  0x06
+/* Tx time-slot assignment table pointer (16 bits) */
+#define QMC_GBL_TX_S_PTR   0x08
+/* Rx pointer (16 bits) */
+#define QMC_GBL_RXPTR  0x0A
+/* Global receive frame threshold (16 bits) */
+#define QMC_GBL_GRFTHR 0x0C
+/* Global receive frame count (16 bits) */
+#define QMC_GBL_GRFCNT 0x0E
+/* Multichannel interrupt base address (32 bits) */
+#define QMC_GBL_INTBASE0x10
+/* Multichannel interrupt pointer (32 bits) */
+#define QMC_GBL_INTPTR 0x14
+/* Rx time-slot assignment table pointer (16 bits) */
+#define QMC_GBL_RX_S_PTR   0x18
+/* Tx pointer (16 bits) */
+#define QMC_GBL_TXPTR  0x1A
+/* CRC constant (32 bits) */
+#define QMC_GBL_C_MASK32   0x1C
+/* Time slot assignment table Rx (32 x 16 bits) */
+#define QMC_GBL_TSATRX 0x20
+/* Time slot assignment table Tx (32 x 16 bits) */
+#define QMC_GBL_TSATTX 0x60
+/* CRC constant (16 bits) */
+#define QMC_GBL_C_MASK16   0xA0
+
+/* TSA entry (16bit entry in TSATRX and TSATTX) */
+#define QMC_TSA_VALID  (1 << 15)
+#define QMC_TSA_WRAP   (1 << 14)
+#define QMC_TSA_MASK   (0x303F)
+#define QMC_TSA_CHANNEL(x) ((x) << 6)
+
+/* Tx buffer descriptor base address (16 bits, offset from MCBASE) */
+#define QMC_SPE_TBASE  0x00
+
+/* Channel mode register (16 bits) */
+#define QMC_SPE_CHAMR  0x02
+#define   QMC_SPE_CHAMR_MODE_HDLC  (1 << 15)
+#define   QMC_SPE_CHAMR_MODE_TRANSP((0 << 15) | (1 << 13))
+#define   QMC_SPE_CHAMR_ENT(1 << 12)
+#define   QMC_SPE_CHAMR_POL(1 << 8)
+#define   QMC_SPE_CHAMR_HDLC_IDLM  (1 << 13)
+#define   QMC_SPE_CHAMR_HDLC_CRC   (1 << 7)
+#define   QMC_SPE_CHAMR_HDLC_NOF   (0x0f << 0)
+#define   QMC_SPE_CHAMR_TRANSP_RD  (1 << 14)
+#define   

[PATCH 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller

[Herve Codina]

Add support for the time slot assigner (TSA)
available in some PowerQUICC SoC such as MPC885
or MPC866.

Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml  | 262 ++
 include/dt-bindings/soc/fsl-tsa.h |  15 +
 2 files changed, 277 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
 create mode 100644 include/dt-bindings/soc/fsl-tsa.h

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
new file mode 100644
index ..7542c0fd8435
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
@@ -0,0 +1,262 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PowerQUICC CPM Time-slot assigner (TSA) controller
+
+maintainers:
+  - Herve Codina 
+
+description: |
+  The TSA is the time-slot assigner that can be found on some
+  PowerQUICC SoC.
+  Its purpose is to route some TDM time-slots to other internal
+  serial controllers.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - fsl,mpc885-tsa
+  - fsl,mpc866-tsa
+  - const: fsl,cpm1-tsa
+
+  reg:
+items:
+  - description: SI (Serial Interface) register base
+  - description: SI RAM base
+
+  reg-names:
+items:
+  - const: si_regs
+  - const: si_ram
+
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+patternProperties:
+  "^tdm@[0-1]$":
+description:
+  The TDM managed by this controller
+type: object
+
+properties:
+  reg:
+minimum: 0
+maximum: 1
+description:
+  The TDM number for this TDM, 0 for TDMa and 1 for TDMb
+
+  fsl,common-rxtx-pins:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Use common pins for both transmit and receive
+
+  clocks: true
+  clock-names: true
+
+  fsl,mode:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [normal, echo, internal-loopback, control-loopback]
+default: normal
+description: |
+  Operational mode:
+- normal:
+Normal operation
+- echo:
+Automatic echo. Rx data is resent on Tx
+- internal-loopback:
+The TDM transmitter is connected to the receiver.
+Data appears on Tx pin.
+- control-loopback:
+The TDM transmitter is connected to the receiver.
+The Tx pin is disconnected.
+
+  fsl,rx-frame-sync-delay:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+  Receive frame sync delay.
+  Indicates the delay between the Rx sync and the first bit of the
+  Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+  fsl,tx-frame-sync-delay:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3]
+default: 0
+description: |
+  Transmit frame sync delay.
+  Indicates the delay between the Tx sync and the first bit of the
+  Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
+
+  fsl,clock-falling-edge:
+$ref: /schemas/types.yaml#/definitions/flag
+description: |
+  Data is sent on falling edge of the clock (and received on the
+  rising edge).
+  If 'clock-falling-edge' is not present, data is sent on the
+  rising edge (and received on the falling edge).
+
+  fsl,fsync-rising-edge:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Frame sync pulses are sampled with the rising edge of the channel
+  clock. If 'fsync-rising-edge' is not present, pulses are sample
+  with e falling edge.
+
+  fsl,double-speed-clock:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  The channel clock is twice the data rate.
+
+  fsl,grant-mode:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Grant mode enabled.
+
+  tx_ts_routes:
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+description: |
+  A list of tupple that indicates the Tx time-slots routes.
+tx_ts_routes =
+   < 2 0 0>, /* The first 2 time slots are not used */
+   < 3 1 0>, /* The next 3 ones are route to SCC2 */
+   < 4 0 0>, /* The next 4 ones are not used */
+   < 2 2 0>; /* The nest 2 ones are route to SCC3 */
+items:
+  items:
+- description:
+The number of time-slots
+  minimum: 1
+  maximum: 64
+  

[PATCH 03/10] MAINTAINERS: add the Freescale TSA controller entry

[Herve Codina]

After contributing the driver, add myself as the maintainer
for the Freescale TSA controller.

Signed-off-by: Herve Codina 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7f86d02cb427..2b4f5fe7ebad 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8372,6 +8372,15 @@ S:   Maintained
 F: drivers/soc/fsl/qe/
 F: include/soc/fsl/qe/
 
+FREESCALE QUICC ENGINE TSA DRIVER
+M: Herve Codina 
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
+F: drivers/soc/fsl/qe/tsa.c
+F: drivers/soc/fsl/qe/tsa.h
+F: include/dt-bindings/soc/fsl-tsa.h
+
 FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
 M: Li Yang 
 L: net...@vger.kernel.org
-- 
2.38.1

[PATCH 00/10] Add the PowerQUICC audio support using the QMC

[Herve Codina]

Hi,

This series adds support for audio using the QMC controller
available in some Freescale PowerQUICC SoCs.

This series contains three parts in order to show the different
blocks hierarchy and their usage in this support.

The first one is related to TSA (Time Slot Assigner).
The TSA handles the data present at the pin level (TDM with up
to 64 time slots) and dispatchs them to one or more serial
controller (SCC).

The second is related to QMC (QUICC Multichannel Controller).
The QMC handles the data at the serial controller (SCC) level
and splits again the data to creates some virtual channels.

The last one is related to the audio component (QMC audio).
It is the glue between the QMC controller and the ASoC
component. It handles one or more QMC virtual channels and
creates one DAI per QMC virtual channels handled.

Best regards,
Herve Codina

Herve Codina (10):
  dt-bindings: soc: fsl: cpm_qe: Add TSA controller
  soc: fsl: qe: Add support for TSA
  MAINTAINERS: add the Freescale TSA controller entry
  powerpc/8xx: Use a larger CPM1 command check mask
  dt-bindings: soc: fsl: cpm_qe: Add QMC controller
  soc: fsl: qe: Add support for QMC
  MAINTAINERS: add the Freescale QMC controller entry
  dt-bindings: sound: Add support for QMC audio
  ASoC: fsl: Add support for QMC audio
  MAINTAINERS: add the Freescale QMC audio entry

 .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml  |  167 ++
 .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml  |  262 +++
 .../bindings/sound/fsl,qmc-audio.yaml |  110 ++
 MAINTAINERS   |   25 +
 arch/powerpc/platforms/8xx/cpm1.c |2 +-
 drivers/soc/fsl/qe/Kconfig|   23 +
 drivers/soc/fsl/qe/Makefile   |2 +
 drivers/soc/fsl/qe/qmc.c  | 1493 +
 drivers/soc/fsl/qe/tsa.c  |  783 +
 drivers/soc/fsl/qe/tsa.h  |   43 +
 include/dt-bindings/soc/fsl-tsa.h |   15 +
 include/soc/fsl/qe/qmc.h  |   71 +
 sound/soc/fsl/Kconfig |9 +
 sound/soc/fsl/Makefile|2 +
 sound/soc/fsl/fsl_qmc_audio.c |  731 
 15 files changed, 3737 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml
 create mode 100644 
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/fsl,qmc-audio.yaml
 create mode 100644 drivers/soc/fsl/qe/qmc.c
 create mode 100644 drivers/soc/fsl/qe/tsa.c
 create mode 100644 drivers/soc/fsl/qe/tsa.h
 create mode 100644 include/dt-bindings/soc/fsl-tsa.h
 create mode 100644 include/soc/fsl/qe/qmc.h
 create mode 100644 sound/soc/fsl/fsl_qmc_audio.c

-- 
2.38.1

[PATCH 02/10] soc: fsl: qe: Add support for TSA

[Herve Codina]

The TSA (Time Slot Assigner) is available in some
PowerQUICC SoC such as the MPC885 or MPC866.

Its purpose is to route some TDM time-slots to other
internal serial controllers.

Signed-off-by: Herve Codina 
---
 drivers/soc/fsl/qe/Kconfig  |  11 +
 drivers/soc/fsl/qe/Makefile |   1 +
 drivers/soc/fsl/qe/tsa.c| 783 
 drivers/soc/fsl/qe/tsa.h|  43 ++
 4 files changed, 838 insertions(+)
 create mode 100644 drivers/soc/fsl/qe/tsa.c
 create mode 100644 drivers/soc/fsl/qe/tsa.h

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 357c5800b112..b0088495c323 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -33,6 +33,17 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
 
+config CPM_TSA
+   tristate "CPM TSA support"
+   depends on OF && HAS_IOMEM
+   depends on CPM1 || COMPILE_TEST
+   help
+ Freescale CPM Time Slot Assigner (TSA)
+ controller.
+
+ This option enables support for this
+ controller
+
 config QE_TDM
bool
default y if FSL_UCC_HDLC
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index 55a555304f3a..45c961acc81b 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -4,6 +4,7 @@
 #
 obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
 obj-$(CONFIG_CPM)  += qe_common.o
+obj-$(CONFIG_CPM_TSA)  += tsa.o
 obj-$(CONFIG_UCC)  += ucc.o
 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
new file mode 100644
index ..ed4a92e82fa1
--- /dev/null
+++ b/drivers/soc/fsl/qe/tsa.c
@@ -0,0 +1,783 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TSA driver
+ *
+ * Copyright 2022 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include "tsa.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* TSA SI RAM routing tables entry */
+#define TSA_SIRAM_ENTRY_LAST   (1 << 16)
+#define TSA_SIRAM_ENTRY_BYTE   (1 << 17)
+#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18)
+#define TSA_SIRAM_ENTRY_CSEL_MASK  (0x7 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_NU(0x0 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC2  (0x2 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC3  (0x3 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SCC4  (0x4 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC1  (0x5 << 22)
+#define TSA_SIRAM_ENTRY_CSEL_SMC2  (0x6 << 22)
+
+/* SI mode register (32 bits) */
+#define TSA_SIMODE 0x00
+#define   TSA_SIMODE_SMC2  0x8000
+#define   TSA_SIMODE_SMC1  0x8000
+#define   TSA_SIMODE_TDMA(x)   ((x) << 0)
+#define   TSA_SIMODE_TDMB(x)   ((x) << 16)
+#define TSA_SIMODE_TDM_MASK0x0fff
+#define TSA_SIMODE_TDM_SDM_MASK0x0c00
+#define   TSA_SIMODE_TDM_SDM_NORM  0x
+#define   TSA_SIMODE_TDM_SDM_ECHO  0x0400
+#define   TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800
+#define   TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00
+#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8)
+#define TSA_SIMODE_TDM_DSC 0x0080
+#define TSA_SIMODE_TDM_CRT 0x0040
+#define TSA_SIMODE_TDM_STZ 0x0020
+#define TSA_SIMODE_TDM_CE  0x0010
+#define TSA_SIMODE_TDM_FE  0x0008
+#define TSA_SIMODE_TDM_GM  0x0004
+#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0)
+
+/* SI global mode register (8 bits) */
+#define TSA_SIGMR  0x04
+#define TSA_SIGMR_ENB  (1<<3)
+#define TSA_SIGMR_ENA  (1<<2)
+#define TSA_SIGMR_RDM_MASK 0x03
+#define   TSA_SIGMR_RDM_STATIC_TDMA0x00
+#define   TSA_SIGMR_RDM_DYN_TDMA   0x01
+#define   TSA_SIGMR_RDM_STATIC_TDMAB   0x02
+#define   TSA_SIGMR_RDM_DYN_TDMAB  0x03
+
+/* SI status register (8 bits) */
+#define TSA_SISTR  0x06
+
+/* SI command register (8 bits) */
+#define TSA_SICMR  0x07
+
+/* SI clock route register (32 bits) */
+#define TSA_SICR   0x0C
+#define   TSA_SICR_SCC2(x) ((x) << 8)
+#define   TSA_SICR_SCC3(x) ((x) << 16)
+#define   TSA_SICR_SCC4(x) ((x) << 24)
+#define TSA_SICR_SCC_MASK  0x0ff
+#define TSA_SICR_SCC_GRX   (1 << 7)
+#define TSA_SICR_SCC_SCX_TSA   (1 << 6)
+#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG1   (0x0 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG2   (0x1 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG3   (0x2 << 3)
+#define   TSA_SICR_SCC_RXCS_BRG4   (0x3 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK15  (0x4 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK26  (0x5 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK37  (0x6 << 3)
+#define   TSA_SICR_SCC_RXCS_CLK48  (0x7 << 3)

Re: [PATCH 4/4] powerpc/pseries: Implement signed update for PLPKS objects

[Michael Ellerman]

Andrew Donnellan  writes:
> From: Nayna Jain 
>
> The Platform Keystore provides a signed update interface which can be used
> to create, replace or append to certain variables in the PKS in a secure
> fashion, with the hypervisor requiring that the update be signed using the
> Platform Key.
>
> Implement an interface to the H_PKS_SIGNED_UPDATE hcall in the plpks
> driver to allow signed updates to PKS objects.
>
> (The plpks driver doesn't need to do any cryptography or otherwise handle
> the actual signed variable contents - that will be handled by userspace
> tooling.)
>
> Signed-off-by: Nayna Jain 
> [ajd: split patch, rewrite commit message, add timeout handling]
> Co-developed-by: Andrew Donnellan 
> Signed-off-by: Andrew Donnellan 
> ---
>  arch/powerpc/include/asm/hvcall.h  |  3 +-
>  arch/powerpc/platforms/pseries/plpks.c | 81 +++---
>  arch/powerpc/platforms/pseries/plpks.h |  5 ++
>  3 files changed, 79 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/hvcall.h 
> b/arch/powerpc/include/asm/hvcall.h
> index 95fd7f9485d5..33b26c0cb69b 100644
> --- a/arch/powerpc/include/asm/hvcall.h
> +++ b/arch/powerpc/include/asm/hvcall.h
> @@ -336,7 +336,8 @@
>  #define H_SCM_FLUSH  0x44C
>  #define H_GET_ENERGY_SCALE_INFO  0x450
>  #define H_WATCHDOG   0x45C
> -#define MAX_HCALL_OPCODE H_WATCHDOG
> +#define H_PKS_SIGNED_UPDATE  0x454
> +#define MAX_HCALL_OPCODE H_PKS_SIGNED_UPDATE
>  
>  /* Scope args for H_SCM_UNBIND_ALL */
>  #define H_UNBIND_SCOPE_ALL (0x1)
> diff --git a/arch/powerpc/platforms/pseries/plpks.c 
> b/arch/powerpc/platforms/pseries/plpks.c
> index c5ae00a8a968..9e4401aabf4f 100644
> --- a/arch/powerpc/platforms/pseries/plpks.c
> +++ b/arch/powerpc/platforms/pseries/plpks.c
> @@ -30,9 +30,9 @@
>  #define MAX_NAME_SIZE239
>  #define MAX_DATA_SIZE4000
>  
> -#define PKS_FLUSH_MAX_TIMEOUT 5000 //msec
> -#define PKS_FLUSH_SLEEP10 //msec
> -#define PKS_FLUSH_SLEEP_RANGE 400
> +#define PKS_MAX_TIMEOUT  5000 // msec
> +#define PKS_FLUSH_SLEEP  10 // msec
> +#define PKS_FLUSH_SLEEP_RANGE400
>  
>  static u8 *ospassword;
>  static u16 ospasswordlength;
> @@ -95,6 +95,12 @@ static int pseries_status_to_err(int rc)
>   err = -ENOENT;
>   break;
>   case H_BUSY:
> + case H_LONG_BUSY_ORDER_1_MSEC:
> + case H_LONG_BUSY_ORDER_10_MSEC:
> + case H_LONG_BUSY_ORDER_100_MSEC:
> + case H_LONG_BUSY_ORDER_1_SEC:
> + case H_LONG_BUSY_ORDER_10_SEC:
> + case H_LONG_BUSY_ORDER_100_SEC:
>   err = -EBUSY;
>   break;
>   case H_AUTHORITY:
> @@ -198,14 +204,17 @@ static struct label *construct_label(char *component, 
> u8 varos, u8 *name,
>u16 namelen)
>  {
>   struct label *label;
> - size_t slen;
> + size_t slen = 0;
>  
>   if (!name || namelen > MAX_NAME_SIZE)
>   return ERR_PTR(-EINVAL);
>  
> - slen = strlen(component);
> - if (component && slen > sizeof(label->attr.prefix))
> - return ERR_PTR(-EINVAL);
> + // Support NULL component for signed updates
> + if (component) {
> + slen = strlen(component);
> + if (slen > sizeof(label->attr.prefix))
> + return ERR_PTR(-EINVAL);
> + }
>  
>   // The label structure must not cross a page boundary, so we align to 
> the next power of 2
>   label = kzalloc(roundup_pow_of_two(sizeof(*label)), GFP_KERNEL);
> @@ -372,7 +381,7 @@ static int plpks_confirm_object_flushed(struct label 
> *label,
>   usleep_range(PKS_FLUSH_SLEEP,
>PKS_FLUSH_SLEEP + PKS_FLUSH_SLEEP_RANGE);
>   timeout = timeout + PKS_FLUSH_SLEEP;
> - } while (timeout < PKS_FLUSH_MAX_TIMEOUT);
> + } while (timeout < PKS_MAX_TIMEOUT);
>  
>   if (timed_out)
>   rc = -ETIMEDOUT;
> @@ -382,6 +391,60 @@ static int plpks_confirm_object_flushed(struct label 
> *label,
>   return rc;
>  }
>  
> +int plpks_signed_update_var(struct plpks_var var, u64 flags)
> +{

I don't see a reason why var is passed by value here? A pointer would be
more typical.

cheers

Re: [PATCH v2 7/7] powerpc/pseries: Implement secvars for dynamic secure boot

[Michael Ellerman]

Russell Currey  writes:
> The pseries platform can support dynamic secure boot (i.e. secure boot
> using user-defined keys) using variables contained with the PowerVM LPAR
> Platform KeyStore (PLPKS).  Using the powerpc secvar API, expose the
> relevant variables for pseries dynamic secure boot through the existing
> secvar filesystem layout.
>
> The relevant variables for dynamic secure boot are signed in the
> keystore, and can only be modified using the H_PKS_SIGNED_UPDATE hcall.
> Object labels in the keystore are encoded using ucs2 format.  With our
> fixed variable names we don't have to care about encoding outside of the
> necessary byte padding.
>
> When a user writes to a variable, the first 8 bytes of data must contain
> the signed update flags as defined by the hypervisor.
>
> When a user reads a variable, the first 4 bytes of data contain the
> policies defined for the object.
>
> Limitations exist due to the underlying implementation of sysfs binary
> attributes, as is the case for the OPAL secvar implementation -
> partial writes are unsupported and writes cannot be larger than PAGE_SIZE.
>
> Co-developed-by: Nayna Jain 
> Signed-off-by: Nayna Jain 
> Co-developed-by: Andrew Donnellan 
> Signed-off-by: Andrew Donnellan 
> Signed-off-by: Russell Currey 
> ---
> v2: Remove unnecessary config vars from sysfs and document the others,
> thanks to review from Greg.  If we end up needing to expose more, we
> can add them later and update the docs.
>
> Use sysfs_emit() instead of sprintf(), thanks to Greg.
>
> Change the size of the sysfs binary attributes to include the 8-byte
> flags header, preventing truncation of large writes.
>
>  Documentation/ABI/testing/sysfs-secvar|  67 -
>  arch/powerpc/platforms/pseries/Kconfig|  13 +
>  arch/powerpc/platforms/pseries/Makefile   |   4 +-
>  arch/powerpc/platforms/pseries/plpks-secvar.c | 245 ++
>  4 files changed, 326 insertions(+), 3 deletions(-)
>  create mode 100644 arch/powerpc/platforms/pseries/plpks-secvar.c
>
> diff --git a/Documentation/ABI/testing/sysfs-secvar 
> b/Documentation/ABI/testing/sysfs-secvar
> index feebb8c57294..466a8cb92b92 100644
> --- a/Documentation/ABI/testing/sysfs-secvar
> +++ b/Documentation/ABI/testing/sysfs-secvar
> @@ -34,7 +34,7 @@ Description:An integer representation of the size 
> of the content of the
>  
>  What:/sys/firmware/secvar/vars//data
>  Date:August 2019
> -Contact: Nayna Jain h
> +Contact: Nayna Jain 
>  Description: A read-only file containing the value of the variable. The size
>   of the file represents the maximum size of the variable data.
>  
> @@ -44,3 +44,68 @@ Contact:   Nayna Jain 
>  Description: A write-only file that is used to submit the new value for the
>   variable. The size of the file represents the maximum size of
>   the variable data that can be written.
> +
> +What:/sys/firmware/secvar/config
> +Date:December 2022
> +Contact: Nayna Jain 
> +Description: This optional directory contains read-only config attributes as
> + defined by the secure variable implementation.  All data is in
> + ASCII format. The directory is only created if the backing
> + implementation provides variables to populate it, which at
> + present is only PLPKS on the pseries platform.

I think it's OK to mention that currently this only exists for PLPKS ...

> +What:/sys/firmware/secvar/config/version
> +Date:December 2022
> +Contact: Nayna Jain 
> +Description: RO file, only present if the secvar implementation is PLPKS.

... but I don't think we want to specify that files are only present for PLPKS. 

Because if another backend wanted to create them in future, that would
technically be an ABI change.

> + Contains the config version as reported by the hypervisor in
> + ASCII decimal format.
> +
> +What:/sys/firmware/secvar/config/max_object_size
> +Date:December 2022
> +Contact: Nayna Jain 
> +Description: RO file, only present if the secvar implementation is PLPKS.
> +
> + Contains the maximum allowed size of objects in the keystore
> + in bytes, represented in ASCII decimal format.
> +
> + This is not necessarily the same as the max size that can be
> + written to an update file as writes can contain more than
> + object data, you should use the size of the update file for
> + that purpose.
> +
> +What:/sys/firmware/secvar/config/total_size
> +Date:December 2022
> +Contact: Nayna Jain 
> +Description: RO file, only present if the secvar implementation is PLPKS.
> +
> + Contains the total size of the PLPKS in bytes, represented in
> + ASCII decimal format.