[PATCH 5/9] powerpc/dexcr: Support custom default DEXCR value
Make the DEXCR value configurable at config time. Intentionally don't
limit possible values to support future aspects without needing kernel
updates.
The default config value enables hashst/hashchk in problem state.
This should be safe, as generally software needs to request these
instructions be included in the first place.
Signed-off-by: Benjamin Gray
---
New in v1
Preface with: I'm note sure on the best place to put the config.
I also don't think there's any need to zero out unknown/unsupported
bits. Reserved implies they are ignored by the hardware (from my
understanding of the ISA). Current P10s boot with all bits set; lsdexcr
(later patch) reports
uDEXCR: ff00 (SBHE, IBRTPD, SRAPD, NPHIE, PHIE, unknown)
when you try to read it back. Leaving them be also makes it easier to
support newer aspects without a kernel update.
If arbitrary value support isn't important, it's probably a nicer
interface to make each aspect an entry in a menu.
Future work may include dynamic DEXCR controls via prctl() and sysfs.
The dynamic controls would be able to override this default DEXCR on a
per-process basis. A stronger "PPC_ENFORCE_USER_ROP_PROCTETION" config
may be required at such a time to prevent dynamically disabling the
hash checks.
---
arch/powerpc/Kconfig | 14 ++
arch/powerpc/kernel/cpu_setup_power.c | 3 ++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a6c4407d3ec8..18ffb18fa70f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -1036,6 +1036,20 @@ config PPC_MEM_KEYS
If unsure, say y.
+config PPC_DEXCR_DEFAULT
+ hex "Default DEXCR value"
+ default 0x0400
+ depends on PPC_BOOK3S_64
+ help
+ Power10 introduces the Dynamic Execution Control Register (DEXCR)
+ to provide fine grained control over various speculation and
+ security capabilities. This is used as the default DEXCR value.
+
+ It is a 64 bit value that splits into 32 bits for supervisor mode
+ and 32 bits for problem state. The default config value enables
+ the hashst/hashck instructions in userspace. See the ISA for
+ specifics of what each bit controls.
+
config PPC_SECURE_BOOT
prompt "Enable secure boot support"
bool
diff --git a/arch/powerpc/kernel/cpu_setup_power.c
b/arch/powerpc/kernel/cpu_setup_power.c
index c00721801a1b..814c825a0661 100644
--- a/arch/powerpc/kernel/cpu_setup_power.c
+++ b/arch/powerpc/kernel/cpu_setup_power.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
@@ -128,7 +129,7 @@ static void init_PMU_ISA31(void)
static void init_DEXCR(void)
{
- mtspr(SPRN_DEXCR, 0);
+ mtspr(SPRN_DEXCR, CONFIG_PPC_DEXCR_DEFAULT);
mtspr(SPRN_HASHKEYR, 0);
}
--
2.39.2
[PATCH 8/9] selftests/powerpc/dexcr: Add hashst/hashchk test
Test the kernel DEXCR[NPHIE] interface and hashchk exception handling.
Introduces with it a DEXCR utils library for common DEXCR operations.
Volatile is used to prevent the compiler optimising away the signal
tests.
Signed-off-by: Benjamin Gray
---
v1: * Clean up dexcr makefile
* Include kernel headers in CFLAGS
* Use numeric literals for hashst/hashchk to support older
toolchains
* A lot of other refactoring
---
tools/testing/selftests/powerpc/Makefile | 1 +
.../selftests/powerpc/dexcr/.gitignore| 1 +
.../testing/selftests/powerpc/dexcr/Makefile | 7 +
tools/testing/selftests/powerpc/dexcr/dexcr.c | 132 ++
tools/testing/selftests/powerpc/dexcr/dexcr.h | 49
.../selftests/powerpc/dexcr/hashchk_test.c| 227 ++
tools/testing/selftests/powerpc/include/reg.h | 4 +
.../testing/selftests/powerpc/include/utils.h | 4 +
tools/testing/selftests/powerpc/utils.c | 24 ++
9 files changed, 449 insertions(+)
create mode 100644 tools/testing/selftests/powerpc/dexcr/.gitignore
create mode 100644 tools/testing/selftests/powerpc/dexcr/Makefile
create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.c
create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.h
create mode 100644 tools/testing/selftests/powerpc/dexcr/hashchk_test.c
diff --git a/tools/testing/selftests/powerpc/Makefile
b/tools/testing/selftests/powerpc/Makefile
index 6ba95cd19e42..00dbd000ee01 100644
--- a/tools/testing/selftests/powerpc/Makefile
+++ b/tools/testing/selftests/powerpc/Makefile
@@ -17,6 +17,7 @@ SUB_DIRS = alignment \
benchmarks \
cache_shape \
copyloops\
+ dexcr\
dscr \
mm \
nx-gzip \
diff --git a/tools/testing/selftests/powerpc/dexcr/.gitignore
b/tools/testing/selftests/powerpc/dexcr/.gitignore
new file mode 100644
index ..d12e4560aca9
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/.gitignore
@@ -0,0 +1 @@
+hashchk_test
diff --git a/tools/testing/selftests/powerpc/dexcr/Makefile
b/tools/testing/selftests/powerpc/dexcr/Makefile
new file mode 100644
index ..16c8b489948a
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/Makefile
@@ -0,0 +1,7 @@
+TEST_GEN_PROGS := hashchk_test
+
+include ../../lib.mk
+
+$(OUTPUT)/hashchk_test: CFLAGS += -fno-pie $(call cc-option,-mno-rop-protect)
+
+$(TEST_GEN_PROGS): ../harness.c ../utils.c ./dexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/dexcr.c
b/tools/testing/selftests/powerpc/dexcr/dexcr.c
new file mode 100644
index ..65ec5347de98
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/dexcr.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dexcr.h"
+#include "reg.h"
+#include "utils.h"
+
+static jmp_buf generic_signal_jump_buf;
+
+static void generic_signal_handler(int signum, siginfo_t *info, void *context)
+{
+ longjmp(generic_signal_jump_buf, 0);
+}
+
+bool dexcr_exists(void)
+{
+ struct sigaction old;
+ volatile bool exists;
+
+ old = push_signal_handler(SIGILL, generic_signal_handler);
+ if (setjmp(generic_signal_jump_buf))
+ goto out;
+
+ /*
+* If the SPR is not recognised by the hardware it triggers
+* a hypervisor emulation interrupt. If the kernel does not
+* recognise/try to emulate it, we receive a SIGILL signal.
+*
+* If we do not receive a signal, assume we have the SPR or the
+* kernel is trying to emulate it correctly.
+*/
+ exists = false;
+ mfspr(SPRN_DEXCR_RO);
+ exists = true;
+
+out:
+ pop_signal_handler(SIGILL, old);
+ return exists;
+}
+
+/*
+ * Just test if a bad hashchk triggers a signal, without checking
+ * for support or if the NPHIE aspect is enabled.
+ */
+bool hashchk_triggers(void)
+{
+ struct sigaction old;
+ volatile bool triggers;
+
+ old = push_signal_handler(SIGILL, generic_signal_handler);
+ if (setjmp(generic_signal_jump_buf))
+ goto out;
+
+ triggers = true;
+ do_bad_hashchk();
+ triggers = false;
+
+out:
+ pop_signal_handler(SIGILL, old);
+ return triggers;
+}
+
+unsigned int get_dexcr(enum dexcr_source source)
+{
+ switch (source) {
+ case DEXCR:
+ return mfspr(SPRN_DEXCR_RO);
+ case HDEXCR:
+ return mfspr(SPRN_HDEXCR_RO);
+ case EFFECTIVE:
+ return mfspr(SPRN_DEXCR_RO) | mfspr(SPRN_HDEXCR_RO);
+ default:
+ FAIL_IF_EXIT_MSG(true, "bad enum dexcr_source");
+ }
+}
+
+void await_child_success(pid_t pid)
+{
+ int wstatus;
+
+ FAIL_IF_EXIT_MSG(pid == -1, "fork failed");
+ FAIL_IF_EXIT_MSG(waitpid(pid, , 0) == -1,
[PATCH 9/9] selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr
Add a utility 'lsdexcr' to print the current DEXCR status. Useful for
quickly checking the status such as when debugging test failures or
verifying the new default DEXCR does what you want (for userspace at
least). Example output:
# ./lsdexcr
uDEXCR: 0400 (NPHIE)
HDEXCR:
Effective: 0400 (NPHIE)
SBHE (0): clear (Speculative branch hint enable)
IBRTPD (3): clear (Indirect branch recurrent target ...)
SRAPD (4): clear (Subroutine return address ...)
NPHIE * (5): set (Non-privileged hash instruction enable)
PHIE (6): clear (Privileged hash instruction enable)
DEXCR[NPHIE] enabled: hashst/hashchk working
Signed-off-by: Benjamin Gray
---
v1: * Report if hashst/hashchk actually does something
---
.../selftests/powerpc/dexcr/.gitignore| 1 +
.../testing/selftests/powerpc/dexcr/Makefile | 2 +
.../testing/selftests/powerpc/dexcr/lsdexcr.c | 141 ++
3 files changed, 144 insertions(+)
create mode 100644 tools/testing/selftests/powerpc/dexcr/lsdexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/.gitignore
b/tools/testing/selftests/powerpc/dexcr/.gitignore
index d12e4560aca9..b82f45dd46b9 100644
--- a/tools/testing/selftests/powerpc/dexcr/.gitignore
+++ b/tools/testing/selftests/powerpc/dexcr/.gitignore
@@ -1 +1,2 @@
hashchk_test
+lsdexcr
diff --git a/tools/testing/selftests/powerpc/dexcr/Makefile
b/tools/testing/selftests/powerpc/dexcr/Makefile
index 16c8b489948a..76210f2bcec3 100644
--- a/tools/testing/selftests/powerpc/dexcr/Makefile
+++ b/tools/testing/selftests/powerpc/dexcr/Makefile
@@ -1,7 +1,9 @@
TEST_GEN_PROGS := hashchk_test
+TEST_GEN_FILES := lsdexcr
include ../../lib.mk
$(OUTPUT)/hashchk_test: CFLAGS += -fno-pie $(call cc-option,-mno-rop-protect)
$(TEST_GEN_PROGS): ../harness.c ../utils.c ./dexcr.c
+$(TEST_GEN_FILES): ../utils.c ./dexcr.c
diff --git a/tools/testing/selftests/powerpc/dexcr/lsdexcr.c
b/tools/testing/selftests/powerpc/dexcr/lsdexcr.c
new file mode 100644
index ..94abbfcc389e
--- /dev/null
+++ b/tools/testing/selftests/powerpc/dexcr/lsdexcr.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+
+#include "dexcr.h"
+#include "utils.h"
+
+static unsigned int dexcr;
+static unsigned int hdexcr;
+static unsigned int effective;
+
+struct dexcr_aspect {
+ const char *name;
+ const char *desc;
+ unsigned int index;
+};
+
+static const struct dexcr_aspect aspects[] = {
+ {
+ .name = "SBHE",
+ .desc = "Speculative branch hint enable",
+ .index = 0,
+ },
+ {
+ .name = "IBRTPD",
+ .desc = "Indirect branch recurrent target prediction disable",
+ .index = 3,
+ },
+ {
+ .name = "SRAPD",
+ .desc = "Subroutine return address prediction disable",
+ .index = 4,
+ },
+ {
+ .name = "NPHIE",
+ .desc = "Non-privileged hash instruction enable",
+ .index = 5,
+ },
+ {
+ .name = "PHIE",
+ .desc = "Privileged hash instruction enable",
+ .index = 6,
+ },
+};
+
+static void print_list(const char *list[], size_t len)
+{
+ for (size_t i = 0; i < len; i++) {
+ printf("%s", list[i]);
+ if (i + 1 < len)
+ printf(", ");
+ }
+}
+
+static void print_dexcr(char *name, unsigned int bits)
+{
+ const char *enabled_aspects[ARRAY_SIZE(aspects) + 1] = {NULL};
+ size_t j = 0;
+
+ printf("%s: %08x", name, bits);
+
+ if (bits == 0) {
+ printf("\n");
+ return;
+ }
+
+ for (size_t i = 0; i < ARRAY_SIZE(aspects); i++) {
+ unsigned int mask = DEXCR_PR_BIT(aspects[i].index);
+
+ if (bits & mask) {
+ enabled_aspects[j++] = aspects[i].name;
+ bits &= ~mask;
+ }
+ }
+
+ if (bits)
+ enabled_aspects[j++] = "unknown";
+
+ printf(" (");
+ print_list(enabled_aspects, j);
+ printf(")\n");
+}
+
+static void print_aspect(const struct dexcr_aspect *aspect)
+{
+ const char *attributes[8] = {NULL};
+ size_t j = 0;
+ unsigned long mask;
+
+ mask = DEXCR_PR_BIT(aspect->index);
+ if (dexcr & mask)
+ attributes[j++] = "set";
+ if (hdexcr & mask)
+ attributes[j++] = "set (hypervisor)";
+ if (!(effective & mask))
+ attributes[j++] = "clear";
+
+ printf("%12s %c (%d): ", aspect->name, effective & mask ? '*' : ' ',
aspect->index);
+ print_list(attributes, j);
+ printf(" \t(%s)\n", aspect->desc);
+}
+
+int main(int argc, char *argv[])
+{
+ if (!dexcr_exists()) {
+
[PATCH 7/9] selftests/powerpc: Add more utility macros
* Include unistd.h for _exit()
* Include stdio.h for fprintf()
* Adds _MSG assertion variants to provide more context behind why a
failure occurred.
* Move ARRAY_SIZE macro to utils.h
The _MSG variants and ARRAY_SIZE will be used by the following
DEXCR selftests.
Signed-off-by: Benjamin Gray
---
v1: * Remove the signal handler variants
* Describe why headers are included
---
.../testing/selftests/powerpc/include/utils.h | 27 ++-
.../powerpc/pmu/sampling_tests/misc.h | 2 --
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/tools/testing/selftests/powerpc/include/utils.h
b/tools/testing/selftests/powerpc/include/utils.h
index eed7dd7582b2..65b242842ff5 100644
--- a/tools/testing/selftests/powerpc/include/utils.h
+++ b/tools/testing/selftests/powerpc/include/utils.h
@@ -9,11 +9,17 @@
#define __cacheline_aligned __attribute__((aligned(128)))
#include
+#include
#include
#include
#include
#include
#include "reg.h"
+#include
+
+#ifndef ARRAY_SIZE
+# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
/* Avoid headaches with PRI?64 - just use %ll? always */
typedef unsigned long long u64;
@@ -64,7 +70,6 @@ struct perf_event_read {
};
#if !defined(__GLIBC_PREREQ) || !__GLIBC_PREREQ(2, 30)
-#include
#include
static inline pid_t gettid(void)
@@ -113,6 +118,16 @@ do {
\
} \
} while (0)
+#define FAIL_IF_MSG(x, msg)\
+do { \
+ if ((x)) { \
+ fprintf(stderr, \
+ "[FAIL] Test FAILED on line %d: %s\n", \
+ __LINE__, msg); \
+ return 1; \
+ } \
+} while (0)
+
#define FAIL_IF_EXIT(x)\
do { \
if ((x)) { \
@@ -122,6 +137,16 @@ do {
\
} \
} while (0)
+#define FAIL_IF_EXIT_MSG(x, msg) \
+do { \
+ if ((x)) { \
+ fprintf(stderr, \
+ "[FAIL] Test FAILED on line %d: %s\n", \
+ __LINE__, msg); \
+ _exit(1); \
+ } \
+} while (0)
+
/* The test harness uses this, yes it's gross */
#define MAGIC_SKIP_RETURN_VALUE99
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
index 4181755cf5a0..64e25cce1435 100644
--- a/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
+++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/misc.h
@@ -18,8 +18,6 @@
#define MMCR1_RSQ 0x2000ULL /* radix scope qual field */
#define BHRB_DISABLE0x20ULL /* MMCRA BHRB DISABLE bit */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
extern int ev_mask_pmcxsel, ev_shift_pmcxsel;
extern int ev_mask_marked, ev_shift_marked;
extern int ev_mask_comb, ev_shift_comb;
--
2.39.2
[PATCH 6/9] Documentation: Document PowerPC kernel DEXCR interface
Describe the DEXCR and document how to configure it.
Signed-off-by: Benjamin Gray
---
v1: * Remove the dynamic control docs, describe the static config
option
This documentation is a little bare for now, but will be expanded on
when dynamic DEXCR control is added.
---
Documentation/powerpc/dexcr.rst | 41 +
Documentation/powerpc/index.rst | 1 +
2 files changed, 42 insertions(+)
create mode 100644 Documentation/powerpc/dexcr.rst
diff --git a/Documentation/powerpc/dexcr.rst b/Documentation/powerpc/dexcr.rst
new file mode 100644
index ..21cbc59e6aa4
--- /dev/null
+++ b/Documentation/powerpc/dexcr.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+==
+DEXCR (Dynamic Execution Control Register)
+==
+
+Overview
+
+
+The DEXCR is a privileged special purpose register (SPR) introduced in
+PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic
+execution behaviours. These behaviours include speculation (e.g., indirect
+branch target prediction) and enabling return-oriented programming (ROP)
+protection instructions.
+
+The execution control is exposed in hardware as up to 32 bits ('aspects') in
+the DEXCR. Each aspect controls a certain behaviour, and can be set or cleared
+to enable/disable the aspect. There are several variants of the DEXCR for
+different purposes:
+
+DEXCR
+A privileged SPR that can control aspects for userspace and kernel space
+HDEXCR
+A hypervisor-privileged SPR that can control aspects for the hypervisor and
+enforce aspects for the kernel and userspace.
+UDEXCR
+An optional ultravisor-privileged SPR that can control aspects for the
ultravisor.
+
+Userspace can examine the current DEXCR state using a dedicated SPR that
+provides a non-privileged read-only view of the userspace DEXCR aspects.
+There is also an SPR that provides a read-only view of the hypervisor enforced
+aspects, which ORed with the userspace DEXCR view gives the effective DEXCR
+state for a process.
+
+
+Kernel Config
+=
+
+The kernel supports a static default DEXCR value determined at config time.
+Set the ``PPC_DEXCR_DEFAULT`` config to the value you want all processes to
+use.
diff --git a/Documentation/powerpc/index.rst b/Documentation/powerpc/index.rst
index 85e80e30160b..d33b554ca7ba 100644
--- a/Documentation/powerpc/index.rst
+++ b/Documentation/powerpc/index.rst
@@ -15,6 +15,7 @@ powerpc
cxl
cxlflash
dawr-power9
+dexcr
dscr
eeh-pci-error-recovery
elf_hwcaps
--
2.39.2
[PATCH 1/9] powerpc/book3s: Add missing include
The functions here use struct thread_struct fields, so need to import the full definition from . The header that defines current only forward declares struct thread_struct. Failing to include this header leads to a compilation error when a translation unit does not also include indirectly. Signed-off-by: Benjamin Gray Reviewed-by: Nicholas Piggin --- v1: * Add npiggin reviewed-by --- arch/powerpc/include/asm/book3s/64/kup.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/book3s/64/kup.h b/arch/powerpc/include/asm/book3s/64/kup.h index 54cf46808157..84c09e546115 100644 --- a/arch/powerpc/include/asm/book3s/64/kup.h +++ b/arch/powerpc/include/asm/book3s/64/kup.h @@ -194,6 +194,7 @@ #else /* !__ASSEMBLY__ */ #include +#include DECLARE_STATIC_KEY_FALSE(uaccess_flush_key); -- 2.39.2
[PATCH 3/9] powerpc/dexcr: Handle hashchk exception
Recognise and pass the appropriate signal to the user program when a
hashchk instruction triggers. This is independent of allowing
configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect
regardless of the kernel.
The signal mirrors how ARM reports their similar check failure. For
example, their FPAC handler in arch/arm64/kernel/traps.c do_el0_fpac()
does this. When we fail to read the instruction that caused the fault
we send a segfault, similar to how emulate_math() does it.
Signed-off-by: Benjamin Gray
---
v1: * Refactor the hashchk check to return 0 on success, an error
code on failure. Determine what to do based on specific error
code.
* Motivate signal and code
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/include/asm/processor.h | 9 +++
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/dexcr.c | 36 +++
arch/powerpc/kernel/traps.c | 10
5 files changed, 57 insertions(+)
create mode 100644 arch/powerpc/kernel/dexcr.c
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 21e33e46f4b8..89b316466ed1 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -215,6 +215,7 @@
#define OP_31_XOP_STFSX663
#define OP_31_XOP_STFSUX695
#define OP_31_XOP_STFDX 727
+#define OP_31_XOP_HASHCHK 754
#define OP_31_XOP_STFDUX759
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_LFIWAX855
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index e96c9b8c2a60..bad64d6a5d36 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -455,6 +455,15 @@ int exit_vmx_usercopy(void);
int enter_vmx_ops(void);
void *exit_vmx_ops(void *dest);
+#ifdef CONFIG_PPC_BOOK3S_64
+int check_hashchk_trap(struct pt_regs const *regs);
+#else
+static inline int check_hashchk_trap(struct pt_regs const *regs)
+{
+ return -EINVAL;
+}
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9bf2be123093..07181e508754 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_DAWR) += dawr.o
obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o
obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_power.o
+obj-$(CONFIG_PPC_BOOK3S_64)+= dexcr.o
obj-$(CONFIG_PPC_BOOK3S_64)+= mce.o mce_power.o
obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o idle_64e.o
obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
diff --git a/arch/powerpc/kernel/dexcr.c b/arch/powerpc/kernel/dexcr.c
new file mode 100644
index ..f263e5439cc6
--- /dev/null
+++ b/arch/powerpc/kernel/dexcr.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DEXCR infrastructure
+ *
+ * Copyright 2023, Benjamin Gray, IBM Corporation.
+ */
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int check_hashchk_trap(struct pt_regs const *regs)
+{
+ ppc_inst_t insn;
+
+ if (!cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ return -EINVAL;
+
+ if (!user_mode(regs))
+ return -EINVAL;
+
+ if (get_user_instr(insn, (void __user *)regs->nip))
+ return -EFAULT;
+
+ if (ppc_inst_primary_opcode(insn) != 31 ||
+ get_xop(ppc_inst_val(insn)) != OP_31_XOP_HASHCHK)
+ return -EINVAL;
+
+ return 0;
+}
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 9bdd79aa51cf..ade67e23b974 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1516,6 +1516,16 @@ static void do_program_check(struct pt_regs *regs)
return;
}
}
+
+ switch (check_hashchk_trap(regs)) {
+ case 0:
+ _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
+ return;
+ case -EFAULT:
+ _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
+ return;
+ }
+
_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
return;
}
--
2.39.2
[PATCH 2/9] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support
ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR). It
is a per-cpu register that allows control over various CPU behaviours
including branch hint usage, indirect branch speculation, and
hashst/hashchk support.
Add some definitions and basic support for the DEXCR in the kernel.
Right now it just
* Zero initialises the DEXCR and HASHKEYR when a CPU onlines.
* Clears them in reset_sprs().
* Detects when the NPHIE aspect is supported (the others don't get
looked at in this series, so there's no need to waste a CPU_FTR
on them).
We initialise the HASHKEYR to ensure that all cores have the same key,
so an HV enforced NPHIE + swapping cores doesn't randomly crash a
process using hash instructions. The stores to HASHKEYR are
unconditional because the ISA makes no mention of the SPR being missing
if support for doing the hashes isn't present. So all that would happen
is the HASHKEYR value gets ignored. This helps slightly if NPHIE
detection fails; e.g., we currently only detect it on pseries.
Signed-off-by: Benjamin Gray
---
v1: * Only make a CPU feature for NPHIE. We only need to know if the
hashst/hashchk functionality is supported for a static DEXCR.
* Initialise the DEXCR to 0 when each CPU comes online. Remove
the dexcr_init() and get_thread_dexcr() functions.
* No longer track the DEXCR in a per-thread field.
* Remove the made-up Opal features
---
arch/powerpc/include/asm/book3s/64/kexec.h | 5 +
arch/powerpc/include/asm/cputable.h| 4 +++-
arch/powerpc/include/asm/reg.h | 7 +++
arch/powerpc/kernel/cpu_setup_power.c | 8
arch/powerpc/kernel/prom.c | 1 +
5 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/book3s/64/kexec.h
b/arch/powerpc/include/asm/book3s/64/kexec.h
index d4b9d476ecba..df37a76c1e9f 100644
--- a/arch/powerpc/include/asm/book3s/64/kexec.h
+++ b/arch/powerpc/include/asm/book3s/64/kexec.h
@@ -21,6 +21,11 @@ static inline void reset_sprs(void)
plpar_set_ciabr(0);
}
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ mtspr(SPRN_DEXCR, 0);
+ mtspr(SPRN_HASHKEYR, 0);
+ }
+
/* Do we need isync()? We are going via a kexec reset */
isync();
}
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 757dbded11dc..443a9d482b15 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -192,6 +192,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002)
#define CPU_FTR_ARCH_31
LONG_ASM_CONST(0x0004)
#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008)
+#define CPU_FTR_DEXCR_NPHIELONG_ASM_CONST(0x0010)
#ifndef __ASSEMBLY__
@@ -451,7 +452,8 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
- CPU_FTR_DAWR | CPU_FTR_DAWR1)
+ CPU_FTR_DAWR | CPU_FTR_DAWR1 | \
+ CPU_FTR_DEXCR_NPHIE)
#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1e8b2e04e626..0cebfefe0d5c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -384,7 +384,14 @@
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
+#define SPRN_HASHKEYR 0x1D4 /* Non-privileged hashst/hashchk key register */
#define SPRN_ASDR 0x330 /* Access segment descriptor register */
+#define SPRN_DEXCR 0x33C /* Dynamic execution control register */
+#define DEXCR_PR_BIT(aspect) PPC_BIT(32 + (aspect))
+#define DEXCR_PR_SBHEDEXCR_PR_BIT(0) /* Speculative Branch
Hint Enable */
+#define DEXCR_PR_IBRTPD DEXCR_PR_BIT(3) /* Indirect Branch Recurrent
Target Prediction Disable */
+#define DEXCR_PR_SRAPD DEXCR_PR_BIT(4) /* Subroutine Return Address
Prediction Disable */
+#define DEXCR_PR_NPHIE DEXCR_PR_BIT(5) /* Non-Privileged Hash
Instruction Enable */
#define SPRN_IC0x350 /* Virtual Instruction Count */
#define SPRN_VTB 0x351 /* Virtual Time Base */
#define SPRN_LDBAR 0x352 /* LD Base Address Register */
diff --git a/arch/powerpc/kernel/cpu_setup_power.c
b/arch/powerpc/kernel/cpu_setup_power.c
index 097c033668f0..c00721801a1b 100644
--- a/arch/powerpc/kernel/cpu_setup_power.c
+++ b/arch/powerpc/kernel/cpu_setup_power.c
[PATCH 4/9] powerpc/dexcr: Support userspace ROP protection
The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR HASHKEYR
to hold a key used in the hash calculation. This key should be different
for each process to make it harder for a malicious process to recreate
valid hash values for a victim process.
Add support for storing a per-thread hash key, and setting/clearing
HASHKEYR appropriately.
Signed-off-by: Benjamin Gray
---
v1: * Guard HASHKEYR update behind change check
* HASHKEYR reset moved earlier to patch 2
---
arch/powerpc/include/asm/processor.h | 1 +
arch/powerpc/kernel/process.c| 17 +
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index bad64d6a5d36..666d4e9804a8 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -264,6 +264,7 @@ struct thread_struct {
unsigned long mmcr3;
unsigned long sier2;
unsigned long sier3;
+ unsigned long hashkeyr;
#endif
};
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 4b29ac5ddac6..62762795e24e 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1182,6 +1182,9 @@ static inline void save_sprs(struct thread_struct *t)
*/
t->tar = mfspr(SPRN_TAR);
}
+
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ t->hashkeyr = mfspr(SPRN_HASHKEYR);
#endif
}
@@ -1260,6 +1263,10 @@ static inline void restore_sprs(struct thread_struct
*old_thread,
if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
old_thread->tidr != new_thread->tidr)
mtspr(SPRN_TIDR, new_thread->tidr);
+
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) &&
+ old_thread->hashkeyr != new_thread->hashkeyr)
+ mtspr(SPRN_HASHKEYR, new_thread->hashkeyr);
#endif
}
@@ -1844,6 +1851,10 @@ int copy_thread(struct task_struct *p, const struct
kernel_clone_args *args)
childregs->ppr = DEFAULT_PPR;
p->thread.tidr = 0;
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
+ p->thread.hashkeyr = current->thread.hashkeyr;
#endif
/*
* Run with the current AMR value of the kernel
@@ -1972,6 +1983,12 @@ void start_thread(struct pt_regs *regs, unsigned long
start, unsigned long sp)
current->thread.tm_tfiar = 0;
current->thread.load_tm = 0;
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+#ifdef CONFIG_PPC_BOOK3S_64
+ if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) {
+ current->thread.hashkeyr = get_random_long();
+ mtspr(SPRN_HASHKEYR, current->thread.hashkeyr);
+ }
+#endif /* CONFIG_PPC_BOOK3S_64 */
}
EXPORT_SYMBOL(start_thread);
--
2.39.2
[PATCH 0/9] Add static DEXCR support
This series is a partial iteration of the RFC [1]. It strips out the dynamic support and just adds the supporting infrastructure and static DEXCR configuration. It should therefore not be introducing any new userspace ABI. I could keep iterating and refactoring, but I figure there's enough here to get useful feedback on the design. [1]: https://lore.kernel.org/all/20221128024458.46121-1-bg...@linux.ibm.com/ Benjamin Gray (9): powerpc/book3s: Add missing include powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support powerpc/dexcr: Handle hashchk exception powerpc/dexcr: Support userspace ROP protection powerpc/dexcr: Support custom default DEXCR value Documentation: Document PowerPC kernel DEXCR interface selftests/powerpc: Add more utility macros selftests/powerpc/dexcr: Add hashst/hashchk test selftests/powerpc/dexcr: Add DEXCR status utility lsdexcr Documentation/powerpc/dexcr.rst | 41 Documentation/powerpc/index.rst | 1 + arch/powerpc/Kconfig | 14 ++ arch/powerpc/include/asm/book3s/64/kexec.h| 5 + arch/powerpc/include/asm/book3s/64/kup.h | 1 + arch/powerpc/include/asm/cputable.h | 4 +- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/include/asm/processor.h | 10 + arch/powerpc/include/asm/reg.h| 7 + arch/powerpc/kernel/Makefile | 1 + arch/powerpc/kernel/cpu_setup_power.c | 9 + arch/powerpc/kernel/dexcr.c | 36 +++ arch/powerpc/kernel/process.c | 17 ++ arch/powerpc/kernel/prom.c| 1 + arch/powerpc/kernel/traps.c | 10 + tools/testing/selftests/powerpc/Makefile | 1 + .../selftests/powerpc/dexcr/.gitignore| 2 + .../testing/selftests/powerpc/dexcr/Makefile | 9 + tools/testing/selftests/powerpc/dexcr/dexcr.c | 132 ++ tools/testing/selftests/powerpc/dexcr/dexcr.h | 49 .../selftests/powerpc/dexcr/hashchk_test.c| 227 ++ .../testing/selftests/powerpc/dexcr/lsdexcr.c | 141 +++ tools/testing/selftests/powerpc/include/reg.h | 4 + .../testing/selftests/powerpc/include/utils.h | 31 ++- .../powerpc/pmu/sampling_tests/misc.h | 2 - tools/testing/selftests/powerpc/utils.c | 24 ++ 26 files changed, 776 insertions(+), 4 deletions(-) create mode 100644 Documentation/powerpc/dexcr.rst create mode 100644 arch/powerpc/kernel/dexcr.c create mode 100644 tools/testing/selftests/powerpc/dexcr/.gitignore create mode 100644 tools/testing/selftests/powerpc/dexcr/Makefile create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.c create mode 100644 tools/testing/selftests/powerpc/dexcr/dexcr.h create mode 100644 tools/testing/selftests/powerpc/dexcr/hashchk_test.c create mode 100644 tools/testing/selftests/powerpc/dexcr/lsdexcr.c base-commit: 065ffaee73892e8a3629b4cfbe635697807a3c6f -- 2.39.2
[PATCH] powerpc/iommu: Fix notifiers being shared by PCI and VIO buses
fail_iommu_setup() registers the fail_iommu_bus_notifier struct to both
PCI and VIO buses. struct notifier_block is a linked list node, so this
causes any notifiers later registered to either bus type to also be
registered to the other since they share the same node.
This causes issues in (at least) the vgaarb code, which registers a
notifier for PCI buses. pci_notify() ends up being called on a vio
device, converted with to_pci_dev() even though it's not a PCI device,
and finally makes a bad access in vga_arbiter_add_pci_device() as
discovered with KASAN:
BUG: KASAN: slab-out-of-bounds in vga_arbiter_add_pci_device+0x60/0xe00
Read of size 4 at addr c00264c26fdc by task swapper/0/1
Call Trace:
[c00263607520] [c00010f7023c] dump_stack_lvl+0x1bc/0x2b8 (unreliable)
[c00263607560] [cf142a64] print_report+0x3f4/0xc60
[c00263607640] [cf142144] kasan_report+0x244/0x698
[c00263607740] [cf1460e8] __asan_load4+0xe8/0x250
[c00263607760] [cff4b850] vga_arbiter_add_pci_device+0x60/0xe00
[c00263607850] [cff4c678] pci_notify+0x88/0x444
[c002636078b0] [ce94dfc4] notifier_call_chain+0x104/0x320
[c00263607950] [ce94f050] blocking_notifier_call_chain+0xa0/0x140
[c00263607990] [c000100cb3b8] device_add+0xac8/0x1d30
[c00263607aa0] [c000100ccd98] device_register+0x58/0x80
[c00263607ad0] [ce84247c] vio_register_device_node+0x9ac/0xce0
[c00263607ba0] [c000126c95d8] vio_bus_scan_register_devices+0xc4/0x13c
[c00263607bd0] [c000126c96e4]
__machine_initcall_pseries_vio_device_init+0x94/0xf0
[c00263607c00] [ce69467c] do_one_initcall+0x12c/0xaa8
[c00263607cf0] [c0001268b8a8] kernel_init_freeable+0xa48/0xba8
[c00263607dd0] [ce695f24] kernel_init+0x64/0x400
[c00263607e50] [ce68e0e4] ret_from_kernel_thread+0x5c/0x64
Fix this by creating separate notifier_block structs for each bus type.
Fixes: d6b9a81b2a45 ("powerpc: IOMMU fault injection")
Reported-by: Nageswara R Sastry
Signed-off-by: Russell Currey
---
arch/powerpc/kernel/iommu.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index ee95937bdaf1..6f1117fe3870 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -171,17 +171,26 @@ static int fail_iommu_bus_notify(struct notifier_block
*nb,
return 0;
}
-static struct notifier_block fail_iommu_bus_notifier = {
+/*
+ * PCI and VIO buses need separate notifier_block structs, since they're linked
+ * list nodes. Sharing a notifier_block would mean that any notifiers later
+ * registered for PCI buses would also get called by VIO buses and vice versa.
+ */
+static struct notifier_block fail_iommu_pci_bus_notifier = {
+ .notifier_call = fail_iommu_bus_notify
+};
+
+static struct notifier_block fail_iommu_vio_bus_notifier = {
.notifier_call = fail_iommu_bus_notify
};
static int __init fail_iommu_setup(void)
{
#ifdef CONFIG_PCI
- bus_register_notifier(_bus_type, _iommu_bus_notifier);
+ bus_register_notifier(_bus_type, _iommu_pci_bus_notifier);
#endif
#ifdef CONFIG_IBMVIO
- bus_register_notifier(_bus_type, _iommu_bus_notifier);
+ bus_register_notifier(_bus_type, _iommu_vio_bus_notifier);
#endif
return 0;
--
2.39.2
[PATCH] powerpc/mpc5xxx: Add missing fwnode_handle_put()
In mpc5xxx_fwnode_get_bus_frequency(), we should add
fwnode_handle_put() when break out of the iteration
fwnode_for_each_parent_node() as it will automatically
increase and decrease the refcounter.
Fixes: de06fba62af6 ("powerpc/mpc5xxx: Switch mpc5xxx_get_bus_frequency() to
use fwnode")
Signed-off-by: Liang He
---
arch/powerpc/sysdev/mpc5xxx_clocks.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c
b/arch/powerpc/sysdev/mpc5xxx_clocks.c
index c5bf7e1b3780..58cee28e2399 100644
--- a/arch/powerpc/sysdev/mpc5xxx_clocks.c
+++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c
@@ -25,8 +25,10 @@ unsigned long mpc5xxx_fwnode_get_bus_frequency(struct
fwnode_handle *fwnode)
fwnode_for_each_parent_node(fwnode, parent) {
ret = fwnode_property_read_u32(parent, "bus-frequency",
_freq);
- if (!ret)
+ if (!ret) {
+ fwnode_handle_put(parent);
return bus_freq;
+ }
}
return 0;
--
2.25.1
Re: [PATCH v12 03/13] dt-bindings: Convert gpio-mmio to yaml
On Tue, 21 Mar 2023 16:13:02 -0400, Sean Anderson wrote:
> This is a generic binding for simple MMIO GPIO controllers. Although we
> have a single driver for these controllers, they were previously spread
> over several files. Consolidate them. The register descriptions are
> adapted from the comments in the source. There is no set order for the
> registers, and some registers may be omitted. Because of this, reg-names
> is mandatory, and no order is specified.
>
> Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
> has moved.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Linus Walleij
> ---
> Linus or Bartosz, feel free to pick this up as the rest of this series
> may not be merged any time soon.
>
> Changes in v12:
> - Put compatible first
> - Keep gpio-controller to one line
> - Add little-endian property
> - Alphabetize compatibles
> - Remove some comments
> - Remove some examples with insufficient novelty
>
> Changes in v11:
> - Keep empty (or almost-empty) properties on a single line
> - Don't use | unnecessarily
> - Use gpio as the node name for examples
> - Rename brcm,bcm6345-gpio.yaml to brcm,bcm63xx-gpio.yaml
>
> Changes in v10:
> - New
>
> ...m6345-gpio.yaml => brcm,bcm63xx-gpio.yaml} | 16 +--
> .../devicetree/bindings/gpio/gpio-mmio.yaml | 117 ++
> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 --
> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 --
> 4 files changed, 118 insertions(+), 91 deletions(-)
> rename Documentation/devicetree/bindings/gpio/{brcm,bcm6345-gpio.yaml =>
> brcm,bcm63xx-gpio.yaml} (78%)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
> delete mode 100644
> Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml: $id: relative
path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/gpio/brcm,bcm63xx-gpio.yaml#
./Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
./Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
./Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
./Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
./Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
./Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml
doc reference errors (make refcheckdocs):
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Warning: Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml
references a file that doesn't exist:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml:
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems
Timothy Pearson writes: > - Original Message - >> From: "Michael Ellerman" >> To: "Timothy Pearson" , "Timothy Pearson" >> >> Cc: "kvm" , "linuxppc-dev" >> >> Sent: Tuesday, March 21, 2023 5:33:57 AM >> Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems > >> Timothy Pearson writes: >>> - Original Message - From: "Timothy Pearson" To: "Michael Ellerman" Cc: "Timothy Pearson" , "kvm" , "linuxppc-dev" Sent: Thursday, March 9, 2023 1:28:20 PM Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems >>> - Original Message - > From: "Michael Ellerman" > To: "Timothy Pearson" , "kvm" > > Cc: "linuxppc-dev" > Sent: Thursday, March 9, 2023 5:40:01 AM > Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems > Timothy Pearson writes: >> This patch series reenables VFIO support on POWER systems. It >> is based on Alexey Kardashevskiys's patch series, rebased and >> successfully tested under QEMU with a Marvell PCIe SATA controller >> on a POWER9 Blackbird host. >> >> Alexey Kardashevskiy (3): >> powerpc/iommu: Add "borrowing" iommu_table_group_ops >> powerpc/pci_64: Init pcibios subsys a bit later >> powerpc/iommu: Add iommu_ops to report capabilities and allow blocking >> domains > > As sent the patches had lost Alexey's authorship (no From: line), I > fixed it up when applying so the first 3 are authored by Alexey. > > cheers Thanks for catching that, it wasn't intentional. Probably used a wrong Git command... >>> >>> Just wanted to touch base on the patches, since they're still listed as >>> Under >>> Review on patchwork. Are we good to go for the 6.4 merge window? >> >> They've been in my next (and so linux-next), since last week. I just >> haven't updated patchwork yet. >> >> So yeah they are on track to go into mainline during the v6.4 merge window. >> >> cheers > > Sounds great, thanks! Saw them in the next tree but wasn't sure if the > patchwork status was more reflective of overall status. Yeah I guess patchwork is more reflective. I sometimes put things in next for a few days to see if any issues shake out, before I update patchwork. Mainly because it's a pain to un-update patchwork if the patch needs to be backed out, but also as a signal that the patch isn't quite locked into next yet. cheers
Re: (subset) [PATCH 000/173] ALSA/ASoC: Convert to platform remove callback returning void
On Wed, 15 Mar 2023 16:04:52 +0100, Uwe Kleine-König wrote: > this series adapts the platform drivers below sound/ to use the .remove_new() > callback. Compared to the traditional .remove() callback .remove_new() returns > no value. This is a good thing because the driver core doesn't (and cannot) > cope for errors during remove. The only effect of a non-zero return value in > .remove() is that the driver core emits a warning. The device is removed > anyhow > and an early return from .remove() usually yields a resource leak. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [001/173] ALSA: sh: aica: Drop if blocks with always false condition commit: e3a8459d726532be70fa917e39812570618b857e [002/173] ASoC: amd: acp: rembrandt: Drop if blocks with always false condition commit: 9ac0d69ee5891c2d0f0425acbb13993ceef9cd12 [003/173] ALSA: pxa2xx: Convert to platform remove callback returning void commit: 3210e62ab2f63b3ecdacc2c06ca8c8a91d1bf656 [004/173] ALSA: atmel: ac97: Convert to platform remove callback returning void commit: 45cc35e81322117dfc27fbfded2e0263018175a0 [005/173] ALSA: mts64: Convert to platform remove callback returning void commit: 5909d9e5b6c927ea91ace61365049a2f365a7d7e [006/173] ALSA: portman2x4: Convert to platform remove callback returning void commit: 962bdc9645036b1300c4930e147b5e9a0c587c81 [007/173] ALSA: mips/hal2: Convert to platform remove callback returning void commit: b54a2377ec02d52b7bb5dab381e9a45ba0bc617a [008/173] ALSA: mips/sgio2audio: Convert to platform remove callback returning void commit: 0505c87c00e8e0adb64c9cfb97ea4882899bea3e [009/173] ALSA: hda/tegra: Convert to platform remove callback returning void commit: d8a3441b53682883c16d6997d059e1cc2ac739c8 [010/173] ALSA: ppc/powermac: Convert to platform remove callback returning void commit: c3d8cb1929fc64e8c3d14f27e9540e72aee8ed08 [011/173] ALSA: sh: aica: Convert to platform remove callback returning void commit: de0f49b86d12384e8f3ddf7dc651a93c2c0c551b [012/173] ALSA: sh_dac_audio: Convert to platform remove callback returning void commit: a0f4aa0a9f841693a6487315751c12a2f5773574 [013/173] ASoC: adi: axi-i2s: Convert to platform remove callback returning void commit: 711c5b4e36a3345cd0de597a9c5b7f5911abfd51 [014/173] ASoC: adi: axi-spdif: Convert to platform remove callback returning void commit: a0d18db09ca5b43e832c913b2375f3f6d124cc3b [015/173] ASoC: amd: acp-pcm-dma: Convert to platform remove callback returning void commit: 6c24eb02518e3c5140b80144ec000bfa5bf7 [016/173] ASoC: amd: acp: rembrandt: Convert to platform remove callback returning void commit: 37846af6d08ccdca8308e3d4bfec9f6d97e8eec2 [017/173] ASoC: amd: acp: renoir: Convert to platform remove callback returning void commit: da8a3ceb45be5d711f109df5bb12261adb790391 [018/173] ASoC: amd: ps: Convert to platform remove callback returning void commit: 5b6bacfa1a7bc353d14189a628d8617a26e8381b [019/173] ASoC: amd: raven: acp3x-pcm-dma: Convert to platform remove callback returning void commit: 599914e146a772f7ceb39912a73565d90336e5e3 [020/173] ASoC: amd: raven: acp3x-pdm-dma: Convert to platform remove callback returning void commit: 725d4edfa528f07acfda3e080bf1827e5eea0399 [021/173] ASoC: amd: vangogh: acp5x-pcm-dma: Convert to platform remove callback returning void commit: 8564d4f22ce7cbf989af4ba004b44b1878d1b984 [022/173] ASoC: amd: yc: acp6x-pdm-dma: Convert to platform remove callback returning void commit: 0e940c75e307f61fdf049ee7ac21d672f91883f3 [023/173] ASoC: apple: mca: Convert to platform remove callback returning void commit: eb5a9cf29f1e5b6290e168d405eef98b42f158a4 [024/173] ASoC: atmel: atmel-i2s: Convert to platform remove callback returning void commit: d0486266a6ba028fe0197c721994f3de5d21550a [025/173] ASoC: atmel: atmel_wm8904: Convert to platform remove callback returning void commit: 0278eb3275df6121ecbab848269495f9ca7f5c7a [026/173] ASoC: atmel: mchp-i2s-mcc: Convert to platform remove callback returning void commit: b0570709d123ee8bfed32f968d665366fb1a6d2d [027/173] ASoC: atmel: mchp-pdmc: Convert to platform remove callback returning void commit: 86fdd4825459db4ec831d2d41a5e27d45dff2641 [028/173] ASoC: atmel: mchp-spdifrx: Convert to platform remove callback returning void commit: 879f2ce0a95701695f2b7648ca81aff543631b1d [029/173] ASoC: atmel: mchp-spdiftx: Convert to platform remove callback returning void commit: c1d51c27d22af56e53e2d739cf533182c2a3fca3 [030/173] ASoC: atmel: mikroe-proto: Convert to platform remove callback returning void commit: 2328c4871bd33ce3be5c56a413a79c6b23535217 [031/173] ASoC: atmel: sam9g20_wm8731: Convert to platform remove
Re: [PATCH v12 03/13] dt-bindings: Convert gpio-mmio to yaml
On 3/21/23 16:13, Sean Anderson wrote:
> This is a generic binding for simple MMIO GPIO controllers. Although we
> have a single driver for these controllers, they were previously spread
> over several files. Consolidate them. The register descriptions are
> adapted from the comments in the source. There is no set order for the
> registers, and some registers may be omitted. Because of this, reg-names
> is mandatory, and no order is specified.
>
> Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
> has moved.
>
> Signed-off-by: Sean Anderson
> Reviewed-by: Linus Walleij
> ---
> Linus or Bartosz, feel free to pick this up as the rest of this series
> may not be merged any time soon.
>
> Changes in v12:
> - Put compatible first
> - Keep gpio-controller to one line
> - Add little-endian property
> - Alphabetize compatibles
> - Remove some comments
> - Remove some examples with insufficient novelty
>
> Changes in v11:
> - Keep empty (or almost-empty) properties on a single line
> - Don't use | unnecessarily
> - Use gpio as the node name for examples
> - Rename brcm,bcm6345-gpio.yaml to brcm,bcm63xx-gpio.yaml
>
> Changes in v10:
> - New
>
> ...m6345-gpio.yaml => brcm,bcm63xx-gpio.yaml} | 16 +--
> .../devicetree/bindings/gpio/gpio-mmio.yaml | 117 ++
> .../bindings/gpio/ni,169445-nand-gpio.txt | 38 --
> .../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 --
> 4 files changed, 118 insertions(+), 91 deletions(-)
> rename Documentation/devicetree/bindings/gpio/{brcm,bcm6345-gpio.yaml =>
> brcm,bcm63xx-gpio.yaml} (78%)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
> delete mode 100644
> Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
> delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt
>
> diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
> b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
> similarity index 78%
> rename from Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
> rename to Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
I forgot to update references to this file. Will fix for v13.
--Sean
> index 4d69f79df859..e11f4af49c52 100644
> --- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
> @@ -4,7 +4,7 @@
> $id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Broadcom BCM6345 GPIO controller
> +title: Broadcom BCM63xx GPIO controller
>
> maintainers:
>- Álvaro Fernández Rojas
> @@ -18,8 +18,6 @@ description: |+
>
>BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
>and/or written, and the direction changed from input to output.
> - BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
> - and/or written, and the direction changed from input to output.
>BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
>and dirout registers, where GPIO state can be read and/or written, and the
>direction changed from input to output.
> @@ -29,7 +27,6 @@ properties:
> enum:
>- brcm,bcm6318-gpio
>- brcm,bcm6328-gpio
> - - brcm,bcm6345-gpio
>- brcm,bcm6358-gpio
>- brcm,bcm6362-gpio
>- brcm,bcm6368-gpio
> @@ -63,17 +60,6 @@ required:
> additionalProperties: false
>
> examples:
> - - |
> -gpio@fffe0406 {
> - compatible = "brcm,bcm6345-gpio";
> - reg-names = "dirout", "dat";
> - reg = <0xfffe0406 2>, <0xfffe040a 2>;
> - native-endian;
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -};
> -
>- |
> gpio@0 {
>compatible = "brcm,bcm63268-gpio";
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
> b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
> new file mode 100644
> index ..b394e058256e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Generic MMIO GPIO
> +
> +maintainers:
> + - Linus Walleij
> + - Bartosz Golaszewski
> +
> +description:
> + Some simple GPIO controllers may consist of a single data register or a
> pair
> + of set/clear-bit registers. Such controllers are common for glue logic in
> + FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
> + NAND-style parallel busses.
> +
> +properties:
> + compatible:
> +enum:
> + - brcm,bcm6345-gpio
> + - ni,169445-nand-gpio
> + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO
> controller
> +
> + big-endian: true
> +
> + '#gpio-cells':
> +
[PATCH v12 12/13] arm64: dts: ls1088a: Prevent PCSs from probing as phys
The internal PCSs are not always accessible during boot (such as if the
serdes has deselected the appropriate link mode). Give them appropriate
compatible strings so they don't automatically (fail to) probe as
genphys.
Signed-off-by: Sean Anderson
---
(no changes since v8)
Changes in v8:
- New
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 30 ---
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 59b401daad4d..bbc714f84577 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -932,7 +932,8 @@ pcs_mdio1: mdio@8c07000 {
#size-cells = <0>;
status = "disabled";
- pcs1: ethernet-phy@0 {
+ pcs1: ethernet-pcs@0 {
+ compatible = "fsl,lynx-pcs";
reg = <0>;
};
};
@@ -945,7 +946,8 @@ pcs_mdio2: mdio@8c0b000 {
#size-cells = <0>;
status = "disabled";
- pcs2: ethernet-phy@0 {
+ pcs2: ethernet-pcs@0 {
+ compatible = "fsl,lynx-pcs";
reg = <0>;
};
};
@@ -958,19 +960,23 @@ pcs_mdio3: mdio@8c0f000 {
#size-cells = <0>;
status = "disabled";
- pcs3_0: ethernet-phy@0 {
+ pcs3_0: ethernet-pcs@0 {
+ compatible = "fsl,lynx-pcs";
reg = <0>;
};
- pcs3_1: ethernet-phy@1 {
+ pcs3_1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
reg = <1>;
};
- pcs3_2: ethernet-phy@2 {
+ pcs3_2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
reg = <2>;
};
- pcs3_3: ethernet-phy@3 {
+ pcs3_3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
reg = <3>;
};
};
@@ -983,19 +989,23 @@ pcs_mdio7: mdio@8c1f000 {
#size-cells = <0>;
status = "disabled";
- pcs7_0: ethernet-phy@0 {
+ pcs7_0: ethernet-pcs@0 {
+ compatible = "fsl,lynx-pcs";
reg = <0>;
};
- pcs7_1: ethernet-phy@1 {
+ pcs7_1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
reg = <1>;
};
- pcs7_2: ethernet-phy@2 {
+ pcs7_2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
reg = <2>;
};
- pcs7_3: ethernet-phy@3 {
+ pcs7_3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
reg = <3>;
};
};
--
2.35.1.1320.gc452695387.dirty
[PATCH v12 13/13] arm64: dts: ls1088ardb: Add serdes descriptions
This adds serdes support to the LS1088ARDB. I have tested the QSGMII
ports as well as the two 10G ports. The SFP slot is now fully supported,
instead of being modeled as a fixed-link.
Linux hangs around when the serdes is initialized if the si5341 is
enabled with the in-tree driver, so I have modeled it as a two fixed
clocks instead. There are a few registers in the QIXIS FPGA which
control the SFP GPIOs; I have modeled them as discrete GPIO controllers
for now. I never saw the AQR105 interrupt fire; not sure what was going
on, but I have removed it to force polling.
To enable serdes support, the DPC needs to set the macs to
MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be
converted at once. Additionally, in order to change interface types, the
MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Use "descriptions" instead of "bindings"
- Don't use /clocks
- Add missing gpio-controller properties
Changes in v9:
- Add fsl,unused-lanes-reserved to allow a gradual transition, depending
on the mac link type.
- Remove unused clocks
- Fix some phy mode node names
- phy-type -> fsl,phy
Changes in v8:
- Rename serdes phy handles like the LS1046A
- Add SFP slot binding
- Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in
the LS1046A).
- Fix duplicated lane 2 (it should have been lane 3).
- Fix incorrectly-documented value for XFI1.
- Remove interrupt for aquantia phy. It never fired for whatever reason,
preventing the link from coming up.
- Add GPIOs for QIXIS FPGA.
- Enable MAC1 PCS
- Remove si5341 binding
Changes in v4:
- Convert to new bindings
.../boot/dts/freescale/fsl-ls1088a-rdb.dts| 82 ++-
1 file changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index ee8e932628d1..ede537b644e8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -10,17 +10,55 @@
/dts-v1/;
+#include
+
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625>;
+ };
+
+ sfp_slot: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <_i2c>;
+ los-gpios = <_stat 5 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <_stat 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = < 4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+ {
+ clocks = <_100mhz>, <_156mhz>;
+ clock-names = "ref0", "ref1";
+ fsl,unused-lanes-reserved;
+ status = "okay";
+};
+
+ {
+ managed = "in-band-status";
+ pcs-handle = <>;
+ phys = <_C>;
+ sfp = <_slot>;
};
{
phy-handle = <_aquantia_phy>;
phy-connection-type = "10gbase-r";
+ managed = "in-band-status";
pcs-handle = <>;
+ phys = <_D>;
};
{
@@ -28,6 +66,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_0>;
+ phys = <_A>;
};
{
@@ -35,6 +74,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_1>;
+ phys = <_A>;
};
{
@@ -42,6 +82,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_2>;
+ phys = <_A>;
};
{
@@ -49,6 +90,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_3>;
+ phys = <_A>;
};
{
@@ -56,6 +98,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_0>;
+ phys = <_B>;
};
{
@@ -63,6 +106,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_1>;
+ phys = <_B>;
};
{
@@ -70,6 +114,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_2>;
+ phys = <_B>;
};
{
@@ -77,6 +122,7 @@ {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <_3>;
+ phys = <_B>;
};
{
@@ -128,7 +174,6 @@ {
mdio2_aquantia_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts-extended = < 2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x0>;
};
};
@@ -171,6 +216,12 @@ rtc@51 {
interrupts-extended = < 0
IRQ_TYPE_LEVEL_LOW>;
[PATCH v12 09/13] arm64: dts: ls1046a: Add serdes nodes
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes" instead of "bindings"
- Move compatible/reg first
Changes in v4:
- Convert to new bindings
Changes in v3:
- Describe modes in device tree
Changes in v2:
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 111 ++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index a01e3cfec77f..f6361fafaef7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/ {
compatible = "fsl,ls1046a";
@@ -424,6 +425,116 @@ sfp: efuse@1e8 {
clock-names = "sfp";
};
+ serdes1: serdes@1ea {
+ compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ status = "disabled";
+
+ /*
+* XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane
+* numbers and pin numbers are _reversed_. In addition,
+* the PCCR documentation is _inconsistent_ in its
+* usage of these terms!
+*
+* PCCR "Lane 0" refers to...
+* =
+*0 Lane A
+*2 Lane A
+*8 Lane A
+*9 Lane A
+*B Lane D!
+*/
+ serdes1_A: phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* SGMII.6 */
+ sgmii-0 {
+ fsl,pccr = <0x8>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+ };
+
+ serdes1_B: phy@1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* SGMII.5 */
+ sgmii-1 {
+ fsl,pccr = <0x8>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* QSGMII.6,5,10,1 */
+ qsgmii-1 {
+ fsl,pccr = <0x9>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* TODO: PCIe.1 */
+ };
+
+ serdes1_C: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* SGMII.10 */
+ sgmii-2 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* XFI.10 */
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ fsl,type = ;
+ };
+ };
+
+ serdes1_D: phy@3 {
+ #phy-cells = <0>;
+ reg = <3>;
+
+ /* SGMII.9 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+
[PATCH v12 10/13] arm64: dts: ls1046ardb: Add serdes descriptions
This adds appropriate descriptions for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes descriptions to SoC dtsi
- Don't use /clocks
- Use "descriptions" instead of "bindings"
- Split off defconfig change into separate patch
Changes in v9:
- Fix name of phy mode node
- phy-type -> fsl,phy
Changes in v8:
- Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
This should help remind readers that the numbering corresponds to the
physical layout of the registers, and not the lane (pin) number.
Changes in v6:
- XGI.9 -> XFI.9
Changes in v4:
- Convert to new bindings
.../boot/dts/freescale/fsl-ls1046a-rdb.dts| 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 07f6cc6e354a..0d6dcfd1630a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,24 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625>;
+ };
+};
+
+ {
+ clocks = <_100mhz>, <_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
};
{
@@ -140,21 +158,29 @@ ethernet@e6000 {
ethernet@e8000 {
phy-handle = <_phy1>;
phy-connection-type = "sgmii";
+ phys = <_B>;
+ phy-names = "serdes";
};
ethernet@ea000 {
phy-handle = <_phy2>;
phy-connection-type = "sgmii";
+ phys = <_A>;
+ phy-names = "serdes";
};
ethernet@f { /* 10GEC1 */
phy-handle = <_phy>;
phy-connection-type = "xgmii";
+ phys = <_D>;
+ phy-names = "serdes";
};
ethernet@f2000 { /* 10GEC2 */
phy-connection-type = "10gbase-r";
managed = "in-band-status";
+ phys = <_C>;
+ phy-names = "serdes";
};
mdio@fc000 {
--
2.35.1.1320.gc452695387.dirty
[PATCH v12 11/13] arm64: dts: ls1088a: Add serdes nodes
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes" instead of "bindings"
- Move compatible/reg first
Changes in v4:
- Convert to new bindings
Changes in v3:
- New
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 126 ++
1 file changed, 126 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index e5fb137ac02b..59b401daad4d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -9,6 +9,7 @@
*/
#include
#include
+#include
#include
/ {
@@ -238,6 +239,131 @@ reset: syscon@1e6 {
reg = <0x0 0x1e6 0x0 0x1>;
};
+ serdes1: serdes@1ea {
+ compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ status = "disabled";
+
+ /*
+* XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane
+* numbers and pin numbers are _reversed_.
+*/
+ serdes1_A: phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* SG3 */
+ sgmii-0 {
+ fsl,pccr = <0x8>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* QSGb */
+ qsgmii-0 {
+ fsl,pccr = <0x9>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+ };
+
+ serdes1_B: phy@1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* SG7 */
+ sgmii-1 {
+ fsl,pccr = <0x8>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* QSGa */
+ qsgmii-1 {
+ fsl,pccr = <0x9>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /* TODO: PCIe1 */
+ };
+
+ serdes1_C: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* SG1 */
+ sgmii-2 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,type = ;
+ };
+
+ /*
+* XFI1
+* Table 23-1 and section 23.5.16.4 disagree;
+* this reflects the table.
+*
+* fsl,cfg is documented as 1, but it is set to
+* 2 by the RCW! This is the same as the
+* LS1046A.
+*/
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ fsl,type = ;
+ };
+ };
+
+ serdes1_D: phy@3 {
+ #phy-cells = <0>;
+ reg = <3>;
+
+ /* SG2 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+
[PATCH v12 08/13] phy: lynx10g: Enable by default on Layerscape
The next few patches will break ethernet if the serdes is not enabled, so enable the serdes driver by default on Layerscape. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - New drivers/phy/freescale/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 6bebe00f5889..b396162dc859 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -54,6 +54,7 @@ config PHY_FSL_LYNX_10G depends on ARCH_LAYERSCAPE || PPC || COMPILE_TEST select GENERIC_PHY select REGMAP_MMIO + default y if ARCH_LAYERSCAPE help This adds support for the Lynx "SerDes" devices found on various QorIQ SoCs. There may be up to four SerDes devices on each SoC, and each -- 2.35.1.1320.gc452695387.dirty
[PATCH v12 06/13] clk: Add Lynx 10G SerDes PLL driver
This adds support for the PLLs found in Lynx 10G "SerDes" devices found on various NXP QorIQ SoCs. There are two PLLs in each SerDes. This driver has been split from the main PHY driver to allow for better review, even though these PLLs are not present anywhere else besides the SerDes. An auxiliary device is not used as it offers no benefits over a function call (and there is no need to have a separate device). The PLLs are modeled as clocks proper to let us take advantage of the existing clock infrastructure. I have not given the same treatment to the per-lane clocks because they need to be programmed in-concert with the rest of the lane settings. One tricky thing is that the VCO (PLL) rate exceeds 2^32 (maxing out at around 5GHz). This will be a problem on 32-bit platforms, since clock rates are stored as unsigned longs. To work around this, the pll clock rate is generally treated in units of kHz. The PLLs are configured rather interestingly. Instead of the usual direct programming of the appropriate divisors, the input and output clock rates are selected directly. Generally, the only restriction is that the input and output must be integer multiples of each other. This suggests some kind of internal look-up table. The datasheets generally list out the supported combinations explicitly, and not all input/output combinations are documented. I'm not sure if this is due to lack of support, or due to an oversight. If this becomes an issue, then some combinations can be blacklisted (or whitelisted). This may also be necessary for other SoCs which have more stringent clock requirements. Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Remove unnecessary inclusion of clk.h - Don't gate clocks in compatibility mode Changes in v9: - Convert some u32s to unsigned long to match arguments - Switch from round_rate to determine_rate - Drop explicit reference to reference clock - Use .parent_names when requesting parents - Use devm_clk_hw_get_clk to pass clocks back to serdes - Fix indentation - Split off from following patch to allow for better review MAINTAINERS| 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-fsl-lynx-10g.c | 510 + drivers/phy/freescale/Kconfig | 6 + include/linux/phy/lynx-10g.h | 16 ++ 5 files changed, 540 insertions(+) create mode 100644 drivers/clk/clk-fsl-lynx-10g.c create mode 100644 include/linux/phy/lynx-10g.h diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..1098ad283eb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12202,6 +12202,13 @@ S: Maintained W: http://linux-test-project.github.io/ T: git https://github.com/linux-test-project/ltp.git +LYNX 10G SERDES DRIVER +M: Sean Anderson +S: Maintained +F: drivers/clk/clk-fsl-lynx-10g.c +F: include/dt-bindings/clock/fsl,lynx-10g.h +F: include/linux/phy/lynx-10g.h + LYNX 28G SERDES PHY DRIVER M: Ioana Ciornei L: net...@vger.kernel.org diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..eebed69f6c58 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523)+= clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)+= clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o +obj-$(CONFIG_PHY_FSL_LYNX_10G) += clk-fsl-lynx-10g.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI)+= clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED)+= clk-aspeed.o diff --git a/drivers/clk/clk-fsl-lynx-10g.c b/drivers/clk/clk-fsl-lynx-10g.c new file mode 100644 index ..78357303b578 --- /dev/null +++ b/drivers/clk/clk-fsl-lynx-10g.c @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Sean Anderson + * + * This file contains the implementation for the PLLs found on Lynx 10G phys. + * + * XXX: The VCO rate of the PLLs can exceed ~4GHz, which is the maximum rate + * expressable in an unsigned long. To work around this, rates are specified in + * kHz. This is as if there was a division by 1000 in the PLL. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLL_STRIDE 0x20 +#define PLLa(a, off) ((a) * PLL_STRIDE + (off)) +#define PLLaRSTCTL(a) PLLa(a, 0x00) +#define PLLaCR0(a) PLLa(a, 0x04) + +#define PLLaRSTCTL_RSTREQ BIT(31) +#define PLLaRSTCTL_RST_DONEBIT(30) +#define PLLaRSTCTL_RST_ERR BIT(29) +#define PLLaRSTCTL_PLLRST_BBIT(7) +#define PLLaRSTCTL_SDRST_B BIT(6) +#define PLLaRSTCTL_SDENBIT(5) + +#define PLLaRSTCTL_ENABLE_SET (PLLaRSTCTL_RST_DONE | PLLaRSTCTL_PLLRST_B | \ +PLLaRSTCTL_SDRST_B | PLLaRSTCTL_SDEN) +#define PLLaRSTCTL_ENABLE_MASK (PLLaRSTCTL_ENABLE_SET |
[PATCH v12 03/13] dt-bindings: Convert gpio-mmio to yaml
This is a generic binding for simple MMIO GPIO controllers. Although we
have a single driver for these controllers, they were previously spread
over several files. Consolidate them. The register descriptions are
adapted from the comments in the source. There is no set order for the
registers, and some registers may be omitted. Because of this, reg-names
is mandatory, and no order is specified.
Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
has moved.
Signed-off-by: Sean Anderson
Reviewed-by: Linus Walleij
---
Linus or Bartosz, feel free to pick this up as the rest of this series
may not be merged any time soon.
Changes in v12:
- Put compatible first
- Keep gpio-controller to one line
- Add little-endian property
- Alphabetize compatibles
- Remove some comments
- Remove some examples with insufficient novelty
Changes in v11:
- Keep empty (or almost-empty) properties on a single line
- Don't use | unnecessarily
- Use gpio as the node name for examples
- Rename brcm,bcm6345-gpio.yaml to brcm,bcm63xx-gpio.yaml
Changes in v10:
- New
...m6345-gpio.yaml => brcm,bcm63xx-gpio.yaml} | 16 +--
.../devicetree/bindings/gpio/gpio-mmio.yaml | 117 ++
.../bindings/gpio/ni,169445-nand-gpio.txt | 38 --
.../devicetree/bindings/gpio/wd,mbl-gpio.txt | 38 --
4 files changed, 118 insertions(+), 91 deletions(-)
rename Documentation/devicetree/bindings/gpio/{brcm,bcm6345-gpio.yaml =>
brcm,bcm63xx-gpio.yaml} (78%)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
delete mode 100644
Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
delete mode 100644 Documentation/devicetree/bindings/gpio/wd,mbl-gpio.txt
diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
similarity index 78%
rename from Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
rename to Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
index 4d69f79df859..e11f4af49c52 100644
--- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/brcm,bcm63xx-gpio.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Broadcom BCM6345 GPIO controller
+title: Broadcom BCM63xx GPIO controller
maintainers:
- Álvaro Fernández Rojas
@@ -18,8 +18,6 @@ description: |+
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
- BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
- and/or written, and the direction changed from input to output.
BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
and dirout registers, where GPIO state can be read and/or written, and the
direction changed from input to output.
@@ -29,7 +27,6 @@ properties:
enum:
- brcm,bcm6318-gpio
- brcm,bcm6328-gpio
- - brcm,bcm6345-gpio
- brcm,bcm6358-gpio
- brcm,bcm6362-gpio
- brcm,bcm6368-gpio
@@ -63,17 +60,6 @@ required:
additionalProperties: false
examples:
- - |
-gpio@fffe0406 {
- compatible = "brcm,bcm6345-gpio";
- reg-names = "dirout", "dat";
- reg = <0xfffe0406 2>, <0xfffe040a 2>;
- native-endian;
-
- gpio-controller;
- #gpio-cells = <2>;
-};
-
- |
gpio@0 {
compatible = "brcm,bcm63268-gpio";
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
new file mode 100644
index ..b394e058256e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic MMIO GPIO
+
+maintainers:
+ - Linus Walleij
+ - Bartosz Golaszewski
+
+description:
+ Some simple GPIO controllers may consist of a single data register or a pair
+ of set/clear-bit registers. Such controllers are common for glue logic in
+ FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
+ NAND-style parallel busses.
+
+properties:
+ compatible:
+enum:
+ - brcm,bcm6345-gpio
+ - ni,169445-nand-gpio
+ - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
+
+ big-endian: true
+
+ '#gpio-cells':
+const: 2
+
+ gpio-controller: true
+
+ little-endian: true
+
+ reg:
+minItems: 1
+description:
+ A list of registers in the controller. The width of each register is
+ determined by its size. All registers must have the same width. The
number
+ of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
+items:
+ - description:
+
[PATCH v12 07/13] phy: fsl: Add Lynx 10G SerDes driver
This adds support for the Lynx 10G "SerDes" devices found on various NXP QorIQ SoCs. There may be up to four SerDes devices on each SoC, each supporting up to eight lanes. Protocol support for each SerDes is highly heterogeneous, with each SoC typically having a totally different selection of supported protocols for each lane. Additionally, the SerDes devices on each SoC also have differing support. One SerDes will typically support Ethernet on most lanes, while the other will typically support PCIe on most lanes. There is wide hardware support for this SerDes. It is present on QorIQ T-Series and Layerscape processors. Because each SoC typically has specific instructions and exceptions for its SerDes, I have limited the initial scope of this module to just the LS1046A and LS1088A. Additionally, I have only added support for Ethernet protocols. There is not a great need for dynamic reconfiguration for other protocols (except perhaps for M.2 cards), so support for them may never be added. Nevertheless, I have tried to provide an obvious path for adding support for other SoCs as well as other protocols. SATA just needs support for configuring LNmSSCR0. PCIe may need to configure the equalization registers. It also uses multiple lanes. I have tried to write the driver with multi-lane support in mind, so there should not need to be any large changes. Although there are 6 protocols supported, I have only tested SGMII and XFI. The rest have been implemented as described in the datasheet. Most of these protocols should work "as-is", but 10GBASE-KR will need PCS support for link training. Unlike some other phys where e.g. PCIe x4 will use 4 separate phys all configured for PCIe, this driver uses one phy configured to use 4 lanes. This is because while the individual lanes may be configured individually, the protocol selection acts on all lanes at once. Additionally, the order which lanes should be configured in is specified by the datasheet. To coordinate this, lanes are reserved in phy_init, and released in phy_exit. This driver was written with reference to the LS1046A reference manual. However, it was informed by reference manuals for all processors with mEMACs, especially the T4240 (which appears to have a "maxed-out" configuration). The earlier P-series processors appear to be similar, but have a different overall register layout (using "banks" instead of separate SerDes). Perhaps this those use a "5G Lynx SerDes." Signed-off-by: Sean Anderson --- (no changes since v10) Changes in v10: - Fix debugging print with incorrect error variable Changes in v9: - Split off clock "driver" into its own patch to allow for better review. - Add ability to defer lane initialization to phy_init. This allows for easier transitioning between firmware-managed serdes and Linux- managed serdes, as the consumer (such as dpaa2, which knows what the firmware is doing) has the last say on who gets control. - phy-type -> fsl,phy Changes in v8: - Remove unused variable from lynx_ls_mode_init Changes in v7: - Break out call order into generic documentation - Refuse to switch "major" protocols - Update Kconfig to reflect restrictions - Remove set/clear of "pcs reset" bit, since it doesn't seem to fix anything. Changes in v6: - Update MAINTAINERS to include new files - Include bitfield.h and slab.h to allow compilation on non-arm64 arches. - Depend on COMMON_CLK and either layerscape/ppc Changes in v5: - Remove references to PHY_INTERFACE_MODE_1000BASEKX to allow this series to be applied directly to linux/master. - Add fsl,lynx-10g.h to MAINTAINERS Changes in v4: - Rework all debug statements to remove use of __func__. Additional information has been provided as necessary. - Consider alternative parent rates in round_rate and not in set_rate. Trying to modify out parent's rate in set_rate will deadlock. - Explicitly perform a stop/reset sequence in set_rate. This way we always ensure that the PLL is properly stopped. - Set the power-down bit when disabling the PLL. We can do this now that enable/disable aren't abused during the set rate sequence. - Fix typos in QSGMII_OFFSET and XFI_OFFSET - Rename LNmTECR0_TEQ_TYPE_PRE to LNmTECR0_TEQ_TYPE_POST to better reflect its function (adding post-cursor equalization). - Use of_clk_hw_onecell_get instead of a custom function. - Return struct clks from lynx_clks_init instead of embedding lynx_clk in lynx_priv. - Rework PCCR helper functions; T-series SoCs differ from Layerscape SoCs primarily in the layout and offset of the PCCRs. This will help bring a cleaner abstraction layer. The caps have been removed, since this handles the only current usage. - Convert to use new binding format. As a result of this, we no longer need to have protocols for PCIe or SATA. Additionally, modes now live in lynx_group instead of lynx_priv. - Remove teq from lynx_proto_params, since it can be determined from preq_ratio/postq_ratio. - Fix an early return from
[PATCH v12 04/13] dt-bindings: gpio-mmio: Add compatible for QIXIS
NXP has a "QIXIS" FPGA on several of their reference design boards. On the LS1088ARDB there are several registers which control GPIOs. These can be modeled with the MMIO GPIO driver. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- (no changes since v10) Changes in v10: - New .../devicetree/bindings/gpio/gpio-mmio.yaml| 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index b394e058256e..5abf3dabcf39 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -18,10 +18,16 @@ description: properties: compatible: -enum: - - brcm,bcm6345-gpio - - ni,169445-nand-gpio - - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller +oneOf: + - enum: + - brcm,bcm6345-gpio + - ni,169445-nand-gpio + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + - items: + - enum: + - fsl,fpga-qixis-los-stat + - fsl,fpga-qixis-brdcfg9 + - const: ni,169445-nand-gpio big-endian: true -- 2.35.1.1320.gc452695387.dirty
[PATCH v12 05/13] dt-bindings: clock: Add ids for Lynx 10g PLLs
This adds ids for the Lynx 10g SerDes's internal PLLs. These may be used with assigned-clock* to specify a particular frequency to use. For example, to set the second PLL (at offset 0x20)'s frequency, use LYNX10G_PLLa(1). These are for use only in the device tree, and are not otherwise used by the driver. Signed-off-by: Sean Anderson Acked-by: Rob Herring --- (no changes since v6) Changes in v6: - frequence -> frequency Changes in v5: - Update commit description - Dual id header Changes in v4: - New include/dt-bindings/clock/fsl,lynx-10g.h | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/fsl,lynx-10g.h diff --git a/include/dt-bindings/clock/fsl,lynx-10g.h b/include/dt-bindings/clock/fsl,lynx-10g.h new file mode 100644 index ..15362ae85304 --- /dev/null +++ b/include/dt-bindings/clock/fsl,lynx-10g.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2022 Sean Anderson + */ + +#ifndef __DT_BINDINGS_CLK_LYNX_10G_H +#define __DT_BINDINGS_CLK_LYNX_10G_H + +#define LYNX10G_CLKS_PER_PLL 2 + +#define LYNX10G_PLLa(a)((a) * LYNX10G_CLKS_PER_PLL) +#define LYNX10G_PLLa_EX_DLY(a) ((a) * LYNX10G_CLKS_PER_PLL + 1) + +#endif /* __DT_BINDINGS_CLK_LYNX_10G_H */ -- 2.35.1.1320.gc452695387.dirty
[PATCH v12 02/13] dt-bindings: phy: Add Lynx 10G phy binding
This adds a binding for the SerDes module found on QorIQ processors. Each phy is a subnode of the top-level device, possibly supporting multiple lanes and protocols. This "thick" #phy-cells is used due to allow for better organization of parameters. Note that the particular parameters necessary to select a protocol-controller/lane combination vary across different SoCs, and even within different SerDes on the same SoC. The driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- (no changes since v9) Changes in v9: - Add fsl,unused-lanes-reserved to allow for a gradual transition between firmware and Linux control of the SerDes - Change phy-type back to fsl,type, as I was getting the error '#phy-cells' is a dependency of 'phy-type' Changes in v7: - Use double quotes everywhere in yaml Changes in v6: - fsl,type -> phy-type Changes in v4: - Use subnodes to describe lane configuration, instead of describing PCCRs. This is the same style used by phy-cadence-sierra et al. Changes in v3: - Manually expand yaml references - Add mode configuration to device tree Changes in v2: - Rename to fsl,lynx-10g.yaml - Refer to the device in the documentation, rather than the binding - Move compatible first - Document phy cells in the description - Allow a value of 1 for phy-cells. This allows for compatibility with the similar (but according to Ioana Ciornei different enough) lynx-28g binding. - Remove minItems - Use list for clock-names - Fix example binding having too many cells in regs - Add #clock-cells. This will allow using assigned-clocks* to configure the PLLs. - Document the structure of the compatible strings .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 248 ++ 1 file changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index ..7c364f7de85c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx 10G SerDes + +maintainers: + - Sean Anderson + +description: | + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The + SerDes provides up to eight lanes. Each lane may be configured individually, + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and + others. The specific protocols supported for each lane depend on the + particular SoC. + +properties: + compatible: +items: + - enum: + - fsl,ls1046a-serdes + - fsl,ls1088a-serdes + - const: fsl,lynx-10g + + "#address-cells": +const: 1 + + "#size-cells": +const: 0 + + "#clock-cells": +const: 1 +description: | + The cell contains an ID as described in dt-bindings/clock/fsl,lynx-10g.h. + Note that when assigning a rate to a PLL, the PLL's rate is divided by + 1000 to avoid overflow. A rate of 500 corresponds to 5GHz. + + clocks: +maxItems: 2 +description: | + Clock for each PLL reference clock input. + + clock-names: +minItems: 2 +maxItems: 2 +items: + enum: +- ref0 +- ref1 + + fsl,unused-lanes-reserved: +$ref: /schemas/types.yaml#/definitions/flag +description: | + Unused lanes are reserved for firmware use, and should not be disabled. + Normally, groups containing unused lanes may be reconfigured or disabled + to save power. However, when this property is present, unused lanes will + not be touched until they are used by another driver. This allows + migrating from firmware control of lanes to driver control. + + Lanes not present in any group will never be modified, regardless of the + presence of this property. + + reg: +maxItems: 1 + +patternProperties: + "^phy@": +type: object + +description: | + A contiguous group of lanes which will be configured together. Each group + corresponds to one phy device. Lanes not described by any group will be + left as-is. + +properties: + "#phy-cells": +const: 0 + + reg: +minItems: 1 +maxItems: 8 +description: + The lanes in the group. These
[PATCH v12 01/13] dt-bindings: phy: Add 2500BASE-X and 10GBASE-R
This adds some modes necessary for Lynx 10G support. 2500BASE-X, also known as 2.5G SGMII, is 1000BASE-X/SGMII overclocked to 3.125 GHz, with autonegotiation disabled. 10GBASE-R, also known as XFI, is the protocol spoken between the PMA and PMD ethernet layers for 10GBASE-T and 10GBASE-S/L/E. It is typically used to communicate directly with SFP+ modules, or with 10GBASE-T phys. Signed-off-by: Sean Anderson Acked-by: Rob Herring --- PR increasing phy-type maximum [1]. If this commit could be applied sooner rather than later, I'd appreciate it. This should help avoid another respin if someone else adds another phy type. [1] https://github.com/devicetree-org/dt-schema/pull/85 (no changes since v6) Changes in v6: - Bump PHY_TYPE_2500BASEX to 13, since PHY_TYPE_USXGMII was added in the meantime Changes in v4: - New include/dt-bindings/phy/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 6b901b342348..5b2b674d8d25 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -23,5 +23,7 @@ #define PHY_TYPE_DPHY 10 #define PHY_TYPE_CPHY 11 #define PHY_TYPE_USXGMII 12 +#define PHY_TYPE_2500BASEX 13 +#define PHY_TYPE_10GBASER 14 #endif /* _DT_BINDINGS_PHY */ -- 2.35.1.1320.gc452695387.dirty
[PATCH v12 00/13] phy: Add support for Lynx 10G SerDes
This adds support for the Lynx 10G SerDes found on the QorIQ T-series and Layerscape series. Due to limited time and hardware, only support for the LS1046ARDB and LS1088ARDB is added in this initial series. This series is ready for review by the phy maintainers. I have addressed all known feedback and there are no outstanding issues. Major reconfiguration of baud rate (e.g. 1G->10G) does not work. From my testing, SerDes register settings appear identical. The issue appears to be between the PCS and the MAC. The link itself comes up at both ends, and a mac loopback succeeds. However, a PCS loopback results in dropped packets. Perhaps there is some undocumented register in the PCS? I suspect this driver is around 95% complete, but I don't have the documentation to make it work completely. At the very least it is useful for two cases: - Although this is untested, it should support 2.5G SGMII as well as 1000BASE-KX. The latter needs MAC and PCS support, but the former should work out of the box. - It allows for clock configurations not supported by the RCW. This is very useful if you want to use e.g. SRDS_PRTCL_S1=0x and =0x1133 on the same board. This is because the former setting will use PLL1 as the 1G reference, but the latter will use PLL1 as the 10G reference. Because we can reconfigure the PLLs, it is possible to always use PLL1 as the 1G reference. Changes in v12: - Put compatible first - Keep gpio-controller to one line - Add little-endian property - Alphabetize compatibles - Remove some comments - Remove some examples with insufficient novelty Changes in v11: - Keep empty (or almost-empty) properties on a single line - Don't use | unnecessarily - Use gpio as the node name for examples - Rename brcm,bcm6345-gpio.yaml to brcm,bcm63xx-gpio.yaml Changes in v10: - Convert gpio-mmio to yaml - Add compatible for QIXIS - Remove unnecessary inclusion of clk.h - Don't gate clocks in compatibility mode - Fix debugging print with incorrect error variable - Move serdes bindings to SoC dtsi - Add support for all (ethernet) serdes modes - Refer to "nodes" instead of "bindings" - Move compatible/reg first Changes in v9: - Add fsl,unused-lanes-reserved to allow for a gradual transition between firmware and Linux control of the SerDes - Change phy-type back to fsl,type, as I was getting the error '#phy-cells' is a dependency of 'phy-type' - Convert some u32s to unsigned long to match arguments - Switch from round_rate to determine_rate - Drop explicit reference to reference clock - Use .parent_names when requesting parents - Use devm_clk_hw_get_clk to pass clocks back to serdes - Fix indentation - Split off clock "driver" into its own patch to allow for better review. - Add ability to defer lane initialization to phy_init. This allows for easier transitioning between firmware-managed serdes and Linux- managed serdes, as the consumer (such as dpaa2, which knows what the firmware is doing) has the last say on who gets control. - Fix name of phy mode node - Add fsl,unused-lanes-reserved to allow a gradual transition, depending on the mac link type. - Remove unused clocks - Fix some phy mode node names Changes in v8: - Remove unused variable from lynx_ls_mode_init - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc. This should help remind readers that the numbering corresponds to the physical layout of the registers, and not the lane (pin) number. - Prevent PCSs from probing as phys - Rename serdes phy handles like the LS1046A - Add SFP slot binding - Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in the LS1046A). - Fix duplicated lane 2 (it should have been lane 3). - Fix incorrectly-documented value for XFI1. - Remove interrupt for aquantia phy. It never fired for whatever reason, preventing the link from coming up. - Add GPIOs for QIXIS FPGA. - Enable MAC1 PCS - Remove si5341 binding Changes in v7: - Use double quotes everywhere in yaml - Break out call order into generic documentation - Refuse to switch "major" protocols - Update Kconfig to reflect restrictions - Remove set/clear of "pcs reset" bit, since it doesn't seem to fix anything. Changes in v6: - Bump PHY_TYPE_2500BASEX to 13, since PHY_TYPE_USXGMII was added in the meantime - fsl,type -> phy-type - frequence -> frequency - Update MAINTAINERS to include new files - Include bitfield.h and slab.h to allow compilation on non-arm64 arches. - Depend on COMMON_CLK and either layerscape/ppc - XGI.9 -> XFI.9 Changes in v5: - Update commit description - Dual id header - Remove references to PHY_INTERFACE_MODE_1000BASEKX to allow this series to be applied directly to linux/master. - Add fsl,lynx-10g.h to MAINTAINERS Changes in v4: - Add 2500BASE-X and 10GBASE-R phy types - Use subnodes to describe lane configuration, instead of describing PCCRs. This is the same style used by phy-cadence-sierra et al. - Add ids for Lynx 10g PLLs - Rework all debug
[linux-next:master] BUILD REGRESSION f3594f0204b756638267242e26d9de611435c3ba
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: f3594f0204b756638267242e26d9de611435c3ba Add linux-next specific files for 20230321 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303161521.jbgbafjj-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303190142.tjyypbba-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303211332.milzgukq-...@intel.com https://lore.kernel.org/oe-kbuild-all/202303212204.3g5mratj-...@intel.com Error/Warning: (recently discovered and may have been fixed) Warning: MAINTAINERS references a file that doesn't exist: Documentation/ABI/obsolete/sysfs-selinux-checkreqprot Warning: MAINTAINERS references a file that doesn't exist: Documentation/ABI/obsolete/sysfs-selinux-disable drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c:309:17: sparse: int drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c:309:17: sparse: void drivers/gpu/drm/imx/lcdc/imx-lcdc.c:411:11: error: call to undeclared function 'devm_drm_of_get_bridge'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] drivers/gpu/drm/imx/lcdc/imx-lcdc.c:411:18: error: implicit declaration of function 'devm_drm_of_get_bridge' [-Werror=implicit-function-declaration] drivers/gpu/drm/imx/lcdc/imx-lcdc.c:411:9: error: incompatible integer to pointer conversion assigning to 'struct drm_bridge *' from 'int' [-Wint-conversion] drivers/gpu/drm/imx/lcdc/imx-lcdc.c:449:15: error: implicit declaration of function 'drm_bridge_attach' [-Werror=implicit-function-declaration] drivers/gpu/drm/imx/lcdc/imx-lcdc.c:449:61: error: use of undeclared identifier 'DRM_BRIDGE_ATTACH_NO_CONNECTOR' drivers/gpu/drm/imx/lcdc/imx-lcdc.c:449:68: error: 'DRM_BRIDGE_ATTACH_NO_CONNECTOR' undeclared (first use in this function) drivers/gpu/drm/imx/lcdc/imx-lcdc.c:449:8: error: call to undeclared function 'drm_bridge_attach'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] drivers/net/wireless/legacy/ray_cs.c:628:17: warning: 'strncpy' specified bound 32 equals destination size [-Wstringop-truncation] include/linux/compiler_types.h:338:27: error: expression in static assertion is not an integer include/linux/container_of.h:20:54: error: invalid use of undefined type 'struct module' include/linux/rculist.h:392:21: error: invalid use of undefined type 'struct module' include/linux/stddef.h:16:33: error: invalid use of undefined type 'struct module' kernel/bpf/../module/internal.h:205:2: error: assigning to 'struct module *' from incompatible type 'void' kernel/bpf/../module/internal.h:205:2: error: incomplete definition of type 'struct module' kernel/bpf/../module/internal.h:205:2: error: offsetof of incomplete type 'typeof (*mod)' (aka 'struct module') kernel/bpf/../module/internal.h:205:2: error: operand of type 'void' where arithmetic or pointer type is required Unverified Error/Warning (likely false positive, please contact us if interested): drivers/iommu/iommufd/selftest.c:295:21: sparse: sparse: symbol 'mock_iommu_device' was not declared. Should it be static? drivers/soc/fsl/qe/tsa.c:140:26: sparse: sparse: incorrect type in argument 2 (different address spaces) drivers/soc/fsl/qe/tsa.c:150:27: sparse: sparse: incorrect type in argument 1 (different address spaces) drivers/soc/fsl/qe/tsa.c:189:26: sparse: sparse: dereference of noderef expression drivers/soc/fsl/qe/tsa.c:663:22: sparse: sparse: incorrect type in assignment (different address spaces) drivers/soc/fsl/qe/tsa.c:673:21: sparse: sparse: incorrect type in assignment (different address spaces) drivers/watchdog/imx2_wdt.c:442:22: sparse: sparse: symbol 'imx_wdt' was not declared. Should it be static? drivers/watchdog/imx2_wdt.c:446:22: sparse: sparse: symbol 'imx_wdt_legacy' was not declared. Should it be static? io_uring/io_uring.c:432 io_prep_async_work() error: we previously assumed 'req->file' could be null (see line 425) io_uring/kbuf.c:221 __io_remove_buffers() warn: variable dereferenced before check 'bl->buf_ring' (see line 219) Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | `-- drivers-net-wireless-legacy-ray_cs.c:warning:strncpy-specified-bound-equals-destination-size |-- arc-randconfig-r043-20230319 | |-- include-linux-compiler_types.h:error:expression-in-static-assertion-is-not-an-integer | |-- include-linux-container_of.h:error:invalid-use-of-undefined-type-struct-module | |-- include-linux-rculist.h:error:invalid-use-of-undefined-type-struct-module | `-- include-linux-stddef.h:error:invalid-use-of-undefined-type-struct-module |-- arm64-randconfig-r035-20230319 | |-- include-linux-compiler_types.h:error:expression-in-static-assertion-is-not-an-integer | |-- include-linux-container_of.h:error:invalid-use-of-und
Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems
- Original Message - > From: "Michael Ellerman" > To: "Timothy Pearson" , "Timothy Pearson" > > Cc: "kvm" , "linuxppc-dev" > > Sent: Tuesday, March 21, 2023 5:33:57 AM > Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems > Timothy Pearson writes: >> - Original Message - >>> From: "Timothy Pearson" >>> To: "Michael Ellerman" >>> Cc: "Timothy Pearson" , "kvm" >>> , "linuxppc-dev" >>> >>> Sent: Thursday, March 9, 2023 1:28:20 PM >>> Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems >> >>> - Original Message - From: "Michael Ellerman" To: "Timothy Pearson" , "kvm" Cc: "linuxppc-dev" Sent: Thursday, March 9, 2023 5:40:01 AM Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems >>> Timothy Pearson writes: > This patch series reenables VFIO support on POWER systems. It > is based on Alexey Kardashevskiys's patch series, rebased and > successfully tested under QEMU with a Marvell PCIe SATA controller > on a POWER9 Blackbird host. > > Alexey Kardashevskiy (3): > powerpc/iommu: Add "borrowing" iommu_table_group_ops > powerpc/pci_64: Init pcibios subsys a bit later > powerpc/iommu: Add iommu_ops to report capabilities and allow blocking > domains As sent the patches had lost Alexey's authorship (no From: line), I fixed it up when applying so the first 3 are authored by Alexey. cheers >>> >>> Thanks for catching that, it wasn't intentional. Probably used a wrong Git >>> command... >> >> Just wanted to touch base on the patches, since they're still listed as Under >> Review on patchwork. Are we good to go for the 6.4 merge window? > > They've been in my next (and so linux-next), since last week. I just > haven't updated patchwork yet. > > So yeah they are on track to go into mainline during the v6.4 merge window. > > cheers Sounds great, thanks! Saw them in the next tree but wasn't sure if the patchwork status was more reflective of overall status.
[PATCH v3 4/4] of: address: Always use dma_default_coherent for default coherency
As for now all arches have dma_default_coherent reflecting default
DMA coherency for of devices, so there is no need to have a standalone
config option.
Signed-off-by: Jiaxun Yang
---
v3: Squash setting ARCH_DMA_DEFAULT_COHERENT into this patch.
---
arch/powerpc/Kconfig | 2 +-
arch/riscv/Kconfig | 2 +-
drivers/of/Kconfig | 4
drivers/of/address.c | 10 +-
4 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 57f5d2f53d06..824e00a1277b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -113,6 +113,7 @@ config PPC
#
select ARCH_32BIT_OFF_T if PPC32
select ARCH_DISABLE_KASAN_INLINEif PPC_RADIX_MMU
+ select ARCH_DMA_DEFAULT_COHERENTif !NOT_COHERENT_CACHE
select ARCH_ENABLE_MEMORY_HOTPLUG
select ARCH_ENABLE_MEMORY_HOTREMOVE
select ARCH_HAS_COPY_MC if PPC64
@@ -273,7 +274,6 @@ config PPC
select NEED_PER_CPU_PAGE_FIRST_CHUNKif PPC64
select NEED_SG_DMA_LENGTH
select OF
- select OF_DMA_DEFAULT_COHERENT if !NOT_COHERENT_CACHE
select OF_EARLY_FLATTREE
select OLD_SIGACTIONif PPC32
select OLD_SIGSUSPEND
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 36a5b6fed0d3..6425b5c5d6d4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -12,6 +12,7 @@ config 32BIT
config RISCV
def_bool y
+ select ARCH_DMA_DEFAULT_COHERENT
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
@@ -121,7 +122,6 @@ config RISCV
select MODULES_USE_ELF_RELA if MODULES
select MODULE_SECTIONS if MODULES
select OF
- select OF_DMA_DEFAULT_COHERENT
select OF_EARLY_FLATTREE
select OF_IRQ
select PCI_DOMAINS_GENERIC if PCI
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 644386833a7b..e40f10bf2ba4 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -102,8 +102,4 @@ config OF_OVERLAY
config OF_NUMA
bool
-config OF_DMA_DEFAULT_COHERENT
- # arches should select this if DMA is coherent by default for OF devices
- bool
-
endif # OF
diff --git a/drivers/of/address.c b/drivers/of/address.c
index c105d66a1fa4..23ade4919853 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1103,15 +1103,7 @@ phys_addr_t __init of_dma_get_max_cpu_address(struct
device_node *np)
bool of_dma_is_coherent(struct device_node *np)
{
struct device_node *node;
- bool is_coherent = IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT);
-
- /*
-* DT-based MIPS doesn't use OF_DMA_DEFAULT_COHERENT, but
-* might override the system-wide default at runtime.
-*/
-#if defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT)
- is_coherent = dma_default_coherent;
-#endif
+ bool is_coherent = dma_default_coherent;
node = of_node_get(np);
--
2.37.1 (Apple Git-137.1)
[PATCH v3 3/4] dma-mapping: Provide CONFIG_ARCH_DMA_DEFAULT_COHERENT
Provide a kconfig option to allow arches to manipulate default value of dma_default_coherent in Kconfig. Signed-off-by: Jiaxun Yang --- v3: Add comments --- kernel/dma/Kconfig | 7 +++ kernel/dma/mapping.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 56866aaa2ae1..6677d0e64d27 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -76,6 +76,13 @@ config ARCH_HAS_DMA_PREP_COHERENT config ARCH_HAS_FORCE_DMA_UNENCRYPTED bool +# +# Select this option if the architecture assumes DMA devices are coherent +# by default. +# +config ARCH_DMA_DEFAULT_COHERENT + bool + config SWIOTLB bool select NEED_DMA_MAP_STATE diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 80f9663ffe26..9a4db5cce600 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -20,7 +20,7 @@ #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -bool dma_default_coherent; +bool dma_default_coherent = IS_ENABLED(CONFIG_ARCH_DMA_DEFAULT_COHERENT); #endif /* -- 2.37.1 (Apple Git-137.1)
[PATCH v3 2/4] dma-mapping: Provide a fallback dma_default_coherent
dma_default_coherent was decleared unconditionally at kernel/dma/mapping.c
but only decleared when any of non-coherent options is enabled in
dma-map-ops.h.
Guard the declaration in mapping.c with non-coherent options and provide
a fallback definition.
Signed-off-by: Jiaxun Yang
---
v3: Style fix
---
include/linux/dma-map-ops.h | 2 ++
kernel/dma/mapping.c| 4
2 files changed, 6 insertions(+)
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index 41bf4bdb117a..31f114f486c4 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -269,6 +269,8 @@ static inline bool dev_is_dma_coherent(struct device *dev)
return dev->dma_coherent;
}
#else
+#define dma_default_coherent true
+
static inline bool dev_is_dma_coherent(struct device *dev)
{
return true;
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 68106e3791f6..80f9663ffe26 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -17,7 +17,11 @@
#include "debug.h"
#include "direct.h"
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
bool dma_default_coherent;
+#endif
/*
* Managed DMA API
--
2.37.1 (Apple Git-137.1)
[PATCH v3 0/4] Use dma_default_coherent for devicetree default coherency
Hi all, This series split out second half of my previous series "[PATCH 0/4] MIPS DMA coherence fixes". It intends to use dma_default_coherent to determine the default coherency of devicetree probed devices instead of hardcoding it with Kconfig options. For some MIPS systems, dma_default_coherent is determined with either bootloader or hardware registers in platform initilization code, and devicetree does not explicility specify the coherency of the device, so we need the ability to change the default coherency of devicetree probed devices. For other platforms that supports noncoherent, dma_default_coherent is a fixed value set by arch code. It's defaulted to false for most archs except RISC-V. Thanks - Jiaxun --- v2: - Add PATCH 1 to help with backporting - Use Kconfig option to set dma_default_coherent v3: - Style fixes - Squash setting ARCH_DMA_DEFAULT_COHERENT into PATCH 4 - Setting ARCH_DMA_DEFAULT_COHERENT for PowerPC Jiaxun Yang (4): of: address: Fix default coherency for MIPS dma-mapping: Provide a fallback dma_default_coherent dma-mapping: Provide CONFIG_ARCH_DMA_DEFAULT_COHERENT of: address: Always use dma_default_coherent for default coherency arch/powerpc/Kconfig| 2 +- arch/riscv/Kconfig | 2 +- drivers/of/Kconfig | 4 drivers/of/address.c| 2 +- include/linux/dma-map-ops.h | 2 ++ kernel/dma/Kconfig | 7 +++ kernel/dma/mapping.c| 6 +- 7 files changed, 17 insertions(+), 8 deletions(-) -- 2.37.1 (Apple Git-137.1)
[PATCH v3 1/4] of: address: Fix default coherency for MIPS
DT-based MIPS doesn't use OF_DMA_DEFAULT_COHERENT, but
might override the system-wide default at runtime.
Use dma_default_coherent to override default coherence for
MIPS.
Signed-off-by: Jiaxun Yang
---
drivers/of/address.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 4c0b169ef9bf..c105d66a1fa4 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1105,6 +1105,14 @@ bool of_dma_is_coherent(struct device_node *np)
struct device_node *node;
bool is_coherent = IS_ENABLED(CONFIG_OF_DMA_DEFAULT_COHERENT);
+ /*
+* DT-based MIPS doesn't use OF_DMA_DEFAULT_COHERENT, but
+* might override the system-wide default at runtime.
+*/
+#if defined(CONFIG_MIPS) && defined(CONFIG_DMA_NONCOHERENT)
+ is_coherent = dma_default_coherent;
+#endif
+
node = of_node_get(np);
while (node) {
--
2.37.1 (Apple Git-137.1)
[PATCH v2 2/2] powerpc/pseries: Fix exception handling in pSeries_reconfig_add_node()
Date: Tue, 21 Mar 2023 10:50:08 +0100
The label “out_err” was used to jump to another pointer check despite of
the detail in the implementation of the function “pSeries_reconfig_add_node”
that it was determined already that the corresponding variable contained
a null pointer (because of a failed function call in two cases).
1. Thus return directly after a call of the function “kzalloc” failed.
2. Use more appropriate labels instead.
3. Delete a redundant check.
4. Omit an explicit initialisation for the local variable “err”.
This issue was detected by using the Coccinelle software.
Fixes: 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 ("Linux-2.6.12-rc2")
Signed-off-by: Markus Elfring
---
V2:
This update step was based on a previous change.
arch/powerpc/platforms/pseries/reconfig.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/reconfig.c
b/arch/powerpc/platforms/pseries/reconfig.c
index 44f8ebc2ec0d..14154f48ef63 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -23,15 +23,17 @@
static int pSeries_reconfig_add_node(const char *path, struct property
*proplist)
{
struct device_node *np;
- int err = -ENOMEM;
+ int err;
np = kzalloc(sizeof(*np), GFP_KERNEL);
if (!np)
- goto out_err;
+ return -ENOMEM;
np->full_name = kstrdup(kbasename(path), GFP_KERNEL);
- if (!np->full_name)
- goto out_err;
+ if (!np->full_name) {
+ err = -ENOMEM;
+ goto free_device_node;
+ }
np->properties = proplist;
of_node_set_flag(np, OF_DYNAMIC);
@@ -46,20 +48,19 @@ static int pSeries_reconfig_add_node(const char *path,
struct property *proplist
err = of_attach_node(np);
if (err) {
printk(KERN_ERR "Failed to add device node %s\n", path);
- goto out_err;
+ goto put_node;
}
of_node_put(np->parent);
return 0;
-out_err:
- if (np) {
- of_node_put(np->parent);
+put_node:
+ of_node_put(np->parent);
free_name:
- kfree(np->full_name);
- kfree(np);
- }
+ kfree(np->full_name);
+free_device_node:
+ kfree(np);
return err;
}
--
2.40.0
[PATCH v2 1/2] powerpc/pseries: Do not pass an error pointer to of_node_put() in pSeries_reconfig_add_node()
Date: Tue, 21 Mar 2023 10:30:23 +0100
It can be determined in the implementation of the function
“pSeries_reconfig_add_node” that an error code would occasionally
be provided by a call of a function like pseries_of_derive_parent().
This error indication was passed to an of_node_put() call according to
an attempt for exception handling so far.
Thus fix the risk for undesirable software behaviour by using
an additional label for this error case.
Link: https://lists.ozlabs.org/pipermail/linuxppc-dev/2023-March/256025.html
Link: https://lore.kernel.org/lkml/87pm9377qt@linux.ibm.com/
Reported-by: Nathan Lynch
Fixes: 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 ("Linux-2.6.12-rc2")
Signed-off-by: Markus Elfring
---
V2:
This update step was added according to another change request.
arch/powerpc/platforms/pseries/reconfig.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/reconfig.c
b/arch/powerpc/platforms/pseries/reconfig.c
index 599bd2c78514..44f8ebc2ec0d 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -40,7 +40,7 @@ static int pSeries_reconfig_add_node(const char *path, struct
property *proplist
np->parent = pseries_of_derive_parent(path);
if (IS_ERR(np->parent)) {
err = PTR_ERR(np->parent);
- goto out_err;
+ goto free_name;
}
err = of_attach_node(np);
@@ -56,6 +56,7 @@ static int pSeries_reconfig_add_node(const char *path, struct
property *proplist
out_err:
if (np) {
of_node_put(np->parent);
+free_name:
kfree(np->full_name);
kfree(np);
}
--
2.40.0
Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems
Timothy Pearson writes: > - Original Message - >> From: "Timothy Pearson" >> To: "Michael Ellerman" >> Cc: "Timothy Pearson" , "kvm" >> , "linuxppc-dev" >> >> Sent: Thursday, March 9, 2023 1:28:20 PM >> Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems > >> - Original Message - >>> From: "Michael Ellerman" >>> To: "Timothy Pearson" , "kvm" >>> >>> Cc: "linuxppc-dev" >>> Sent: Thursday, March 9, 2023 5:40:01 AM >>> Subject: Re: [PATCH v2 0/4] Reenable VFIO support on POWER systems >> >>> Timothy Pearson writes: This patch series reenables VFIO support on POWER systems. It is based on Alexey Kardashevskiys's patch series, rebased and successfully tested under QEMU with a Marvell PCIe SATA controller on a POWER9 Blackbird host. Alexey Kardashevskiy (3): powerpc/iommu: Add "borrowing" iommu_table_group_ops powerpc/pci_64: Init pcibios subsys a bit later powerpc/iommu: Add iommu_ops to report capabilities and allow blocking domains >>> >>> As sent the patches had lost Alexey's authorship (no From: line), I >>> fixed it up when applying so the first 3 are authored by Alexey. >>> >>> cheers >> >> Thanks for catching that, it wasn't intentional. Probably used a wrong Git >> command... > > Just wanted to touch base on the patches, since they're still listed as Under > Review on patchwork. Are we good to go for the 6.4 merge window? They've been in my next (and so linux-next), since last week. I just haven't updated patchwork yet. So yeah they are on track to go into mainline during the v6.4 merge window. cheers
[PATCH v2 0/2] powerpc/pseries: Fixes for exception handling in pSeries_reconfig_add_node()
Date: Tue, 21 Mar 2023 11:26:32 +0100 A few update suggestions were taken into account from static source code analysis. Markus Elfring (2): Do not pass an error pointer to of_node_put() Fix exception handling arch/powerpc/platforms/pseries/reconfig.c | 26 --- 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.40.0
Re: [PATCH v3 2/2] arch/powerpc/kvm: kvmppc_hv_entry: remove r4 argument
On 2023-03-21 10:24:36, Kautuk Consul wrote: > > Is r4 there only used for CONFIG_KVM_BOOK3S_HV_P8_TIMING? Could put it > > under there. Although you then lose the barrier if it's disabled, that > > is okay if you're sure that's the only memory operation being ordered. > r4 is also used by the secondary_too_late label. So I decided against > moving it inside the CONFIG_KVM_BOOK3S_HV_P8_TIMING #ifdef as then I > would need to again load from HSTATE_KVM_VCPU(r13) in secondary_too_late. > > Sorry, forgot to mention, r4 is also being used in the 10f label. Thats one more reason to not shift the r4 load into the #ifdef. > > I'm not sure how much new work we want to put into changing this asm > > code, since it's POWER7/8 only. I would love to move this (and the > > other) KVM implementations to C like we did with P9. It's a pretty big > > job though. > Yeah. I was just reviewing this code and decided to send this small > improvement to the mailing list. I will check with my team and ask > them if we could move this implementation to C. > > > > Thanks, > > Nick > > > > > > > > Signed-off-by: Kautuk Consul > > > --- > > > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 11 ++- > > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > > > diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S > > > b/arch/powerpc/kvm/book3s_hv_rmhandlers.S > > > index b81ba4ee0521..b61f0b2c677b 100644 > > > --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S > > > +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S > > > @@ -85,7 +85,7 @@ _GLOBAL_TOC(kvmppc_hv_entry_trampoline) > > > RFI_TO_KERNEL > > > > > > kvmppc_call_hv_entry: > > > - ld r4, HSTATE_KVM_VCPU(r13) > > > + /* Enter guest. */ > > > bl kvmppc_hv_entry > > > > > > /* Back from guest - restore host state and return to caller */ > > > @@ -352,9 +352,7 @@ kvm_secondary_got_guest: > > > mtspr SPRN_LDBAR, r0 > > > isync > > > 63: > > > - /* Order load of vcpu after load of vcore */ > > > - lwsync > > > - ld r4, HSTATE_KVM_VCPU(r13) > > > + /* Enter guest. */ > > > bl kvmppc_hv_entry > > > > > > /* Back from the guest, go back to nap */ > > > @@ -506,7 +504,6 @@ SYM_INNER_LABEL(kvmppc_hv_entry, SYM_L_LOCAL) > > > > > > /* Required state: > > >* > > > - * R4 = vcpu pointer (or NULL) > > >* MSR = ~IR|DR > > >* R13 = PACA > > >* R1 = host R1 > > > @@ -524,6 +521,10 @@ SYM_INNER_LABEL(kvmppc_hv_entry, SYM_L_LOCAL) > > > li r6, KVM_GUEST_MODE_HOST_HV > > > stb r6, HSTATE_IN_GUEST(r13) > > > > > > + /* Order load of vcpu after load of vcore */ > > > + lwsync > > > + ld r4, HSTATE_KVM_VCPU(r13) > > > + > > > #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING > > > /* Store initial timestamp */ > > > cmpdi r4, 0 > > > -- > > > 2.39.2 > >
Re: powerpc/pseries: Fix exception handling in pSeries_reconfig_add_node()
> It's been brought to my attention that there is in fact a crash bug > in this function's error path: How do you think about to mention any other contributors for attribution according to this issue? > np->parent can be an encoded error value, we don't want to of_node_put() that. Will the development attention grow for any more cases? > I believe the patch as written happens to fix the issue. Is it interesting how many details can still be improved (by my change suggestion) also for the discussed function implementation? > Will you please write it up as a bug fix and resubmit? Another proposal will follow. Regards, Markus
Re: [kvm-unit-tests v2 00/10] powerpc: updates, P10, PNV support
On Mon Mar 20, 2023 at 5:03 PM AEST, Nicholas Piggin wrote: > Since v1 series, I fixed the sleep API and implementation in patch 2 > as noted by Thomas. Added usleep and msleep variants to match [um]delay > we already have. > > Also some minor tidy ups and fixes mainly with reporting format in the > sprs test rework. > > And added PowerNV support to the harness with the 3 new patches at the > end because it didn't turn out to be too hard. We could parse the dt to > get a console UART directly for a really minimal firmware, but it is > better for us to have a test harness like this that can also be used for > skiboot testing. I'll send out one more series, I have a couple of fixes for PowerNV code (I didn't make the OPAL call to set interrupts little endian for LE builds, for one). I'll wait for a week or so for more feedback though. Thanks, Nick
Re: [PATCH] powerpc: Use of_address_to_resource()
Hi Rob,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on powerpc/fixes linus/master v6.3-rc3 next-20230321]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Rob-Herring/powerpc-Use-of_address_to_resource/20230320-003601
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
patch link:
https://lore.kernel.org/r/20230319163154.225597-1-robh%40kernel.org
patch subject: [PATCH] powerpc: Use of_address_to_resource()
config: powerpc-mpc7448_hpc2_defconfig
(https://download.01.org/0day-ci/archive/20230321/202303211421.vzx1l2qw-...@intel.com/config)
compiler: powerpc-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/intel-lab-lkp/linux/commit/f382770f629740b86b433db077440e9b5059628a
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review
Rob-Herring/powerpc-Use-of_address_to_resource/20230320-003601
git checkout f382770f629740b86b433db077440e9b5059628a
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1
O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1
O=build_dir ARCH=powerpc SHELL=/bin/bash arch/powerpc/sysdev/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot
| Link:
https://lore.kernel.org/oe-kbuild-all/202303211421.vzx1l2qw-...@intel.com/
All errors (new ones prefixed by >>):
arch/powerpc/sysdev/tsi108_dev.c: In function 'get_csrbase':
>> arch/powerpc/sysdev/tsi108_dev.c:50:38: error: invalid type argument of '->'
>> (have 'struct resource')
50 | tsi108_csr_base = res->start;
| ^~
vim +50 arch/powerpc/sysdev/tsi108_dev.c
38
39 phys_addr_t get_csrbase(void)
40 {
41 struct device_node *tsi;
42
43 if (tsi108_csr_base != -1)
44 return tsi108_csr_base;
45
46 tsi = of_find_node_by_type(NULL, "tsi-bridge");
47 if (tsi) {
48 struct resource res;
49 of_address_to_resource(tsi, 0, );
> 50 tsi108_csr_base = res->start;
51 of_node_put(tsi);
52 }
53 return tsi108_csr_base;
54 }
55 EXPORT_SYMBOL(get_csrbase);
56
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
