[PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
We use property sdhci,auto-cmd12 instead of fsl,sdhci-auto-cmd12
to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
index 5180d9d..0c0efa9 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -130,7 +130,7 @@ usb@22000 {
/include/ pq3-esdhc-0.dtsi
sdhc@2e000 {
- fsl,sdhci-auto-cmd12;
+ sdhci,auto-cmd12;
interrupts = 41 0x2 0 0;
};
--
1.8.0
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[PATCH] Powerpc/eSDCH: Specify voltage for T4240QDS
Freescale T4240QDS reference board has extra voltage shifters added
to allow 3.3V operation, so add 3.3v voltage support for T4240QDS.
1.8v and 3.3v is recommand for eMMC and SDHC card.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/boot/dts/t4240qds.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..eb3c3de 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -148,6 +148,10 @@
interrupts = 0x1 0x1 0 0;
};
};
+
+ sdhc@114000 {
+ voltage-ranges = 1800 1800 3300 3300;
+ };
};
pci0: pcie@ffe24 {
--
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[PATCH 1/3 V5] mmc:core: parse voltage from device-tree
Add function to support get voltage from device-tree.
If there are voltage-range specified in device-tree node, this function
will parse it and return the available voltage mask.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for v5:
- add binding spec for this device node
changes for v4:
- Add new parameter mask to return voltages.
.../devicetree/bindings/mmc/fsl-esdhc.txt | 4 ++
drivers/mmc/core/core.c| 44 ++
include/linux/mmc/core.h | 2 +
3 files changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b..b7943f3 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -19,6 +19,9 @@ Optional properties:
bus-width = 1 property.
- sdhci,auto-cmd12: specifies that a controller can only handle auto
CMD12.
+ - voltage-ranges : two cells are required, first cell specifies minimum
+slot voltage (mV), second cell specifies maximum slot voltage (mV).
+Several ranges could be specified.
Example:
@@ -29,4 +32,5 @@ sdhci@2e000 {
interrupt-parent = ipic;
/* Filled in by U-Boot */
clock-frequency = 0;
+ voltage-ranges = 3300 3300;
};
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 49a5bca..b9b9fb6 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -27,6 +27,7 @@
#include linux/fault-inject.h
#include linux/random.h
#include linux/slab.h
+#include linux/of.h
#include linux/mmc/card.h
#include linux/mmc/host.h
@@ -1196,6 +1197,49 @@ u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max)
}
EXPORT_SYMBOL(mmc_vddrange_to_ocrmask);
+#ifdef CONFIG_OF
+
+/**
+ * mmc_of_parse_voltage - return mask of supported voltages
+ * @np: The device node need to be parsed.
+ * @mask: mask of voltages available for MMC/SD/SDIO
+ *
+ * 1. Return zero on success.
+ * 2. Return negative errno: voltage-range is invalid.
+ */
+int mmc_of_parse_voltage(struct device_node *np, u32 *mask)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ pr_info(%s: voltage-ranges unspecified\n, np-full_name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 ocr_mask;
+
+ ocr_mask = mmc_vddrange_to_ocrmask(
+ be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!ocr_mask) {
+ pr_err(%s: voltage-range #%d is invalid\n,
+ np-full_name, i);
+ return -EINVAL;
+ }
+ *mask |= ocr_mask;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(mmc_of_parse_voltage);
+
+#endif /* CONFIG_OF */
+
#ifdef CONFIG_REGULATOR
/**
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 443243b..da51bec 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -208,6 +208,8 @@ static inline void mmc_claim_host(struct mmc_host *host)
__mmc_claim_host(host, NULL);
}
+struct device_node;
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
+extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
#endif /* LINUX_MMC_CORE_H */
--
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[PATCH 1/3 V4] mmc:core: parse voltage from device-tree
Add function to support get voltage from device-tree.
If there are voltage-range specified in device-tree node, this function
will parse it and return the available voltage mask.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V4:
- Add new parameter mask to return voltages.
changes for V3:
- Correct the type of return value.
drivers/mmc/core/core.c | 44
include/linux/mmc/core.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 49a5bca..b9b9fb6 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -27,6 +27,7 @@
#include linux/fault-inject.h
#include linux/random.h
#include linux/slab.h
+#include linux/of.h
#include linux/mmc/card.h
#include linux/mmc/host.h
@@ -1196,6 +1197,49 @@ u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max)
}
EXPORT_SYMBOL(mmc_vddrange_to_ocrmask);
+#ifdef CONFIG_OF
+
+/**
+ * mmc_of_parse_voltage - return mask of supported voltages
+ * @np: The device node need to be parsed.
+ * @mask: mask of voltages available for MMC/SD/SDIO
+ *
+ * 1. Return zero on success.
+ * 2. Return negative errno: voltage-range is invalid.
+ */
+int mmc_of_parse_voltage(struct device_node *np, u32 *mask)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ pr_info(%s: voltage-ranges unspecified\n, np-full_name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 ocr_mask;
+
+ ocr_mask = mmc_vddrange_to_ocrmask(
+ be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!ocr_mask) {
+ pr_err(%s: voltage-range #%d is invalid\n,
+ np-full_name, i);
+ return -EINVAL;
+ }
+ *mask |= ocr_mask;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(mmc_of_parse_voltage);
+
+#endif /* CONFIG_OF */
+
#ifdef CONFIG_REGULATOR
/**
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 443243b..da51bec 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -208,6 +208,8 @@ static inline void mmc_claim_host(struct mmc_host *host)
__mmc_claim_host(host, NULL);
}
+struct device_node;
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
+extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
#endif /* LINUX_MMC_CORE_H */
--
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[PATCH V3] mmc:of_spi: Update the code of getting voltage-ranges
Using function mmc_of_parse_voltage() to get voltage-ranges.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- changes the type of ocr_mask and function mmc_of_parse_voltage
drivers/mmc/host/of_mmc_spi.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index d720b5e..fd1928d 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -90,8 +90,7 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct
spi_device *spi)
struct device *dev = spi-dev;
struct device_node *np = dev-of_node;
struct of_mmc_spi *oms;
- const u32 *voltage_ranges;
- int num_ranges;
+ u32 ocr_mask;
int i;
int ret = -EINVAL;
@@ -102,26 +101,10 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct
spi_device *spi)
if (!oms)
return NULL;
- voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
- num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
- if (!voltage_ranges || !num_ranges) {
- dev_err(dev, OF: voltage-ranges unspecified\n);
+ if (mmc_of_parse_voltage(np, ocr_mask))
goto err_ocr;
- }
-
- for (i = 0; i num_ranges; i++) {
- const int j = i * 2;
- u32 mask;
- mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
- be32_to_cpu(voltage_ranges[j +
1]));
- if (!mask) {
- ret = -EINVAL;
- dev_err(dev, OF: voltage-range #%d is invalid\n, i);
- goto err_ocr;
- }
- oms-pdata.ocr_mask |= mask;
- }
+ oms-pdata.ocr_mask |= ocr_mask;
for (i = 0; i ARRAY_SIZE(oms-gpios); i++) {
enum of_gpio_flags gpio_flags;
--
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[PATCH 2/3 V3] mmc:sdhc: get voltage from sdhc host
We use host-ocr_mask to hold the voltage get from device-tree
node, In case host-ocr_mask was available, we use host-ocr_mask
as the final available voltage can be used by MMC/SD/SDIO card.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- changed the type of mask
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..57541e0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3119,6 +3119,9 @@ int sdhci_add_host(struct sdhci_host *host)
SDHCI_MAX_CURRENT_MULTIPLIER;
}
+ if (host-ocr_mask)
+ ocr_avail = host-ocr_mask;
+
mmc-ocr_avail = ocr_avail;
mmc-ocr_avail_sdio = ocr_avail;
if (host-ocr_avail_sdio)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..3e781b8 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -171,6 +171,7 @@ struct sdhci_host {
unsigned intocr_avail_sdio; /* OCR bit masks */
unsigned intocr_avail_sd;
unsigned intocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read
Ready interrupt */
unsigned inttuning_done;/* Condition flag set when
CMD19 succeeds */
--
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[PATCH 3/3 V3] mmc:esdhc: add support to get voltage from device-tree
Add suppport to get voltage from device-tree node for esdhc host, if voltage-ranges was specified in device-tree node we can get ocr_mask instead of read from host capacity register. If not voltages still can be get from host capacity register. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V3: - changed the parameter of function drivers/mmc/host/sdhci-of-esdhc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 15039e2..e328252 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -316,6 +316,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev) /* call to generic mmc_of_parse to support additional capabilities */ mmc_of_parse(host-mmc); + mmc_of_parse_voltage(np, host-ocr_mask); ret = sdhci_add_host(host); if (ret) -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/3 V2] mmc:esdhc: add support to get voltage from device-tree
Add suppport to get voltage from device-tree node for esdhc host, if voltage-ranges was specified in device-tree node we can get ocr_mask instead of read from host capacity register. If not voltages still can be get from host capacity register. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for v2: - Update the parameters of function drivers/mmc/host/sdhci-of-esdhc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 15039e2..8a7e2af 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -316,6 +316,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev) /* call to generic mmc_of_parse to support additional capabilities */ mmc_of_parse(host-mmc); + host-ocr_mask = mmc_of_parse_voltage(np); ret = sdhci_add_host(host); if (ret) -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3 V2] mmc:core: parse voltage from device-tree
Add function to support get voltage from device-tree.
If there are voltage-range specified in device-tree node, this function
will parse it and return the avail voltage mask.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for v2:
- Update the parameters of function
drivers/mmc/core/core.c | 46 ++
include/linux/mmc/core.h | 1 +
2 files changed, 47 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 49a5bca..ce9c957 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -27,6 +27,7 @@
#include linux/fault-inject.h
#include linux/random.h
#include linux/slab.h
+#include linux/of.h
#include linux/mmc/card.h
#include linux/mmc/host.h
@@ -1196,6 +1197,51 @@ u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max)
}
EXPORT_SYMBOL(mmc_vddrange_to_ocrmask);
+#ifdef CONFIG_OF
+
+/*
+ * mmc_of_parse_voltage - return mask of supported voltages
+ * @np: The device node need to be parsed.
+ *
+ * 1. Return zero: voltage-ranges unspecified in device-tree.
+ * 2. Return negative errno: voltage-range is invalid.
+ * 3. Return ocr_mask: a mask of voltages that parse from device-tree
+ * node can be provided to MMC/SD/SDIO devices.
+ */
+
+u32 mmc_of_parse_voltage(struct device_node *np)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+ u32 ocr_mask = 0;
+
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ pr_info(%s: voltage-ranges unspecified\n, np-full_name);
+ return 0;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 mask;
+
+ mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!mask) {
+ pr_err(%s: voltage-range #%d is invalid\n,
+ np-full_name, i);
+ return -EINVAL;
+ }
+ ocr_mask |= mask;
+ }
+
+ return ocr_mask;
+}
+EXPORT_SYMBOL(mmc_of_parse_voltage);
+
+#endif /* CONFIG_OF */
+
#ifdef CONFIG_REGULATOR
/**
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 443243b..e3f8fe3 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -209,5 +209,6 @@ static inline void mmc_claim_host(struct mmc_host *host)
}
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
+extern u32 mmc_of_parse_voltage(struct device_node *np);
#endif /* LINUX_MMC_CORE_H */
--
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[PATCH] mmc:of_spi: Update the code of getting voltage-ranges
Using function mmc_of_parse_voltage() to get voltage-ranges.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/of_mmc_spi.c | 22 --
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index d720b5e..7d10991 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -92,6 +92,7 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct
spi_device *spi)
struct of_mmc_spi *oms;
const u32 *voltage_ranges;
int num_ranges;
+ u32 ocr_mask;
int i;
int ret = -EINVAL;
@@ -102,26 +103,11 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct
spi_device *spi)
if (!oms)
return NULL;
- voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
- num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
- if (!voltage_ranges || !num_ranges) {
- dev_err(dev, OF: voltage-ranges unspecified\n);
+ ocr_mask = mmc_of_parse_voltage(np);
+ if (ocr_mask = 0)
goto err_ocr;
- }
-
- for (i = 0; i num_ranges; i++) {
- const int j = i * 2;
- u32 mask;
- mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
- be32_to_cpu(voltage_ranges[j +
1]));
- if (!mask) {
- ret = -EINVAL;
- dev_err(dev, OF: voltage-range #%d is invalid\n, i);
- goto err_ocr;
- }
- oms-pdata.ocr_mask |= mask;
- }
+ oms-pdata.ocr_mask |= ocr_mask;
for (i = 0; i ARRAY_SIZE(oms-gpios); i++) {
enum of_gpio_flags gpio_flags;
--
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[PATCH 2/3] mmc:sdhc: get voltage from sdhc host
We use host-ocr_mask to hold the voltage get from device-tree
node, In case host-ocr_mask was available, we use host-ocr_mask
as the final available voltage can be used by MMC/SD/SDIO card.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..57541e0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3119,6 +3119,9 @@ int sdhci_add_host(struct sdhci_host *host)
SDHCI_MAX_CURRENT_MULTIPLIER;
}
+ if (host-ocr_mask)
+ ocr_avail = host-ocr_mask;
+
mmc-ocr_avail = ocr_avail;
mmc-ocr_avail_sdio = ocr_avail;
if (host-ocr_avail_sdio)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..3e781b8 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -171,6 +171,7 @@ struct sdhci_host {
unsigned intocr_avail_sdio; /* OCR bit masks */
unsigned intocr_avail_sd;
unsigned intocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read
Ready interrupt */
unsigned inttuning_done;/* Condition flag set when
CMD19 succeeds */
--
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[PATCH 1/3] mmc:core: parse voltage from device-tree
Add function to support get voltage from device-tree.
If there are voltage-range specified in device-tree node, this function
will parse it and return the avail voltage mask.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/core/core.c | 48
include/linux/mmc/core.h | 1 +
2 files changed, 49 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 49a5bca..217cd42 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -27,6 +27,7 @@
#include linux/fault-inject.h
#include linux/random.h
#include linux/slab.h
+#include linux/of.h
#include linux/mmc/card.h
#include linux/mmc/host.h
@@ -1196,6 +1197,53 @@ u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max)
}
EXPORT_SYMBOL(mmc_vddrange_to_ocrmask);
+#ifdef CONFIG_OF
+
+/*
+ * mmc_of_parse_voltage - return mask of supported voltages
+ * @host: host whose node should be parsed.
+ *
+ * 1. Return zero: voltage-ranges unspecified in device-tree.
+ * 2. Return negative errno: voltage-range is invalid.
+ * 3. Return ocr_mask: a mask of voltages that parse from device-tree
+ * node can be provided to MMC/SD/SDIO devices.
+ */
+
+u32 mmc_of_parse_voltage(struct mmc_host *host)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+ struct device_node *np;
+ u32 ocr_mask = 0;
+
+ np = host-parent-of_node;
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ dev_info(host-parent, OF: voltage-ranges unspecified\n);
+ return 0;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 mask;
+
+ mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!mask) {
+ dev_err(host-parent,
+ OF: voltage-range #%d is invalid\n, i);
+ return -EINVAL;
+ }
+ ocr_mask |= mask;
+ }
+
+ return ocr_mask;
+}
+EXPORT_SYMBOL(mmc_of_parse_voltage);
+
+#endif /* CONFIG_OF */
+
#ifdef CONFIG_REGULATOR
/**
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 443243b..107375c 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -209,5 +209,6 @@ static inline void mmc_claim_host(struct mmc_host *host)
}
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
+extern u32 mmc_of_parse_voltage(struct mmc_host *host);
#endif /* LINUX_MMC_CORE_H */
--
1.8.0
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[PATCH 3/3] mmc:esdhc: add support to get voltage from device-tree
Add suppport to get voltage from device-tree node for esdhc host, if voltage-ranges was specified in device-tree node we can get ocr_mask instead of read from host capacity register. If not voltages still can be get from host capacity register. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- drivers/mmc/host/sdhci-of-esdhc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 15039e2..b1a7f54 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -316,6 +316,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev) /* call to generic mmc_of_parse to support additional capabilities */ mmc_of_parse(host-mmc); + host-ocr_mask = mmc_of_parse_voltage(host-mmc); ret = sdhci_add_host(host); if (ret) -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2 V2] mmc: esdhc: get voltage from dts file
Add voltage-range support in esdhc of T4, So we can choose
to read voltages from dts file as one optional.
If we can get a valid voltage-range from device node, we use
this voltage as the final voltage support. Else we still read
from capacity or from other provider.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
changes for V2:
- change dev_info to dev_err
- share function in pltfm.c
drivers/mmc/host/sdhci-of-esdhc.c | 1 +
drivers/mmc/host/sdhci-pltfm.c| 32
drivers/mmc/host/sdhci-pltfm.h| 1 +
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 1 +
5 files changed, 38 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 15039e2..cdfb08b 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -304,6 +304,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
return PTR_ERR(host);
sdhci_get_of_property(pdev);
+ sdhci_get_voltage(pdev);
np = pdev-dev.of_node;
if (of_device_is_compatible(np, fsl,p2020-esdhc)) {
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index e2065a4..4682aba 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -109,10 +109,42 @@ void sdhci_get_of_property(struct platform_device *pdev)
host-mmc-pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
}
}
+
+void sdhci_get_voltage(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+ struct device_node *np;
+
+ np = pdev-dev.of_node;
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ dev_info(pdev-dev, OF: voltage-ranges unspecified\n);
+ return;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 mask;
+
+ mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!mask) {
+ dev_err(pdev-dev,
+ OF: voltage-range #%d is invalid\n, i);
+ return;
+ }
+ host-ocr_mask |= mask;
+ }
+}
#else
void sdhci_get_of_property(struct platform_device *pdev) {}
+void sdhci_get_voltage(struct platform_device *pdev) {}
#endif /* CONFIG_OF */
EXPORT_SYMBOL_GPL(sdhci_get_of_property);
+EXPORT_SYMBOL_GPL(sdhci_get_voltage);
struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index e15ced79..aba8253 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -92,6 +92,7 @@ static inline void sdhci_be32bs_writeb(struct sdhci_host
*host, u8 val, int reg)
#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
extern void sdhci_get_of_property(struct platform_device *pdev);
+extern void sdhci_get_voltage(struct platform_device *pdev);
extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..57541e0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3119,6 +3119,9 @@ int sdhci_add_host(struct sdhci_host *host)
SDHCI_MAX_CURRENT_MULTIPLIER;
}
+ if (host-ocr_mask)
+ ocr_avail = host-ocr_mask;
+
mmc-ocr_avail = ocr_avail;
mmc-ocr_avail_sdio = ocr_avail;
if (host-ocr_avail_sdio)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..3e781b8 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -171,6 +171,7 @@ struct sdhci_host {
unsigned intocr_avail_sdio; /* OCR bit masks */
unsigned intocr_avail_sd;
unsigned intocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read
Ready interrupt */
unsigned inttuning_done;/* Condition flag set when
CMD19 succeeds */
--
1.8.0
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[PATCH 1/2 V2] Powerpc: Add voltage support in dts file
eSDHC of T4240 had 1.8v voltage support. Add this node to specify
eSDHC voltage capacity. If this node not specified eSDHC driver
still can read from eSDHC host capacity register.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
changes for v2:
- rewrite the voltage-ranges description
Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 4
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b..b7943f3 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -19,6 +19,9 @@ Optional properties:
bus-width = 1 property.
- sdhci,auto-cmd12: specifies that a controller can only handle auto
CMD12.
+ - voltage-ranges : two cells are required, first cell specifies minimum
+slot voltage (mV), second cell specifies maximum slot voltage (mV).
+Several ranges could be specified.
Example:
@@ -29,4 +32,5 @@ sdhci@2e000 {
interrupt-parent = ipic;
/* Filled in by U-Boot */
clock-frequency = 0;
+ voltage-ranges = 3300 3300;
};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..567d0fb 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -399,6 +399,7 @@
sdhc@114000 {
compatible = fsl,t4240-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
+ voltage-ranges = 1800 1800;
};
/include/ qoriq-i2c-0.dtsi
/include/ qoriq-i2c-1.dtsi
--
1.8.0
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[PATCH 1/2] Powerpc: Add voltage ranges support for T4
Special voltages that can be support by eSDHC of T4 in esdhc node.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 3 +++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 1 +
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b..4aeae6e 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -19,6 +19,8 @@ Optional properties:
bus-width = 1 property.
- sdhci,auto-cmd12: specifies that a controller can only handle auto
CMD12.
+ - 3300 3300: specifies that eSDHC controller can support voltages ranges
+from 3300 to 3300. This is an optional.
Example:
@@ -29,4 +31,5 @@ sdhci@2e000 {
interrupt-parent = ipic;
/* Filled in by U-Boot */
clock-frequency = 0;
+ voltage-ranges = 3300 3300;
};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..1ef2d2d 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -399,6 +399,7 @@
sdhc@114000 {
compatible = fsl,t4240-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
+ voltage-ranges = 1800 1800 3300 3300;
};
/include/ qoriq-i2c-0.dtsi
/include/ qoriq-i2c-1.dtsi
--
1.8.0
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[PATCH 2/2] mmc: esdhc: get voltage from dts file
Add voltage-range support in esdhc of T4, So we can choose
to read voltages from dts file as one optional.
If we can get a valid voltage-range from device node, we use
this voltage as the final voltage support. Else we still read
from capacity or from other provider.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
drivers/mmc/host/sdhci-of-esdhc.c | 31 +++
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 1 +
3 files changed, 35 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 15039e2..8b4b27a 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -262,6 +262,35 @@ static int esdhc_pltfm_bus_width(struct sdhci_host *host,
int width)
return 0;
}
+static void esdhc_get_voltage(struct sdhci_host *host,
+ struct platform_device *pdev)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+ struct device_node *np;
+ np = pdev-dev.of_node;
+
+ voltage_ranges = of_get_property(np, voltage-ranges, num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ dev_info(pdev-dev, OF: voltage-ranges unspecified\n);
+ return;
+ }
+
+ for (i = 0; i num_ranges; i++) {
+ const int j = i * 2;
+ u32 mask;
+ mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!mask) {
+ dev_info(pdev-dev,
+ OF: false voltage-ranges specified\n);
+ return;
+ }
+ host-ocr_mask |= mask;
+ }
+}
+
static const struct sdhci_ops sdhci_esdhc_ops = {
.read_l = esdhc_readl,
.read_w = esdhc_readw,
@@ -317,6 +346,8 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
/* call to generic mmc_of_parse to support additional capabilities */
mmc_of_parse(host-mmc);
+ esdhc_get_voltage(host, pdev);
+
ret = sdhci_add_host(host);
if (ret)
sdhci_pltfm_free(pdev);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..57541e0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3119,6 +3119,9 @@ int sdhci_add_host(struct sdhci_host *host)
SDHCI_MAX_CURRENT_MULTIPLIER;
}
+ if (host-ocr_mask)
+ ocr_avail = host-ocr_mask;
+
mmc-ocr_avail = ocr_avail;
mmc-ocr_avail_sdio = ocr_avail;
if (host-ocr_avail_sdio)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..3e781b8 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -171,6 +171,7 @@ struct sdhci_host {
unsigned intocr_avail_sdio; /* OCR bit masks */
unsigned intocr_avail_sd;
unsigned intocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read
Ready interrupt */
unsigned inttuning_done;/* Condition flag set when
CMD19 succeeds */
--
1.8.0
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[PATCH 1/2] Powerpc: Add voltage support in dts file
eSDHC of T4240 had 1.8v voltage support. Add this node to specify
eSDHC voltage capacity. If this node not specified eSDHC driver
still can read from eSDHC host capacity register.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
changes for this patch set:
- split from patch [PATCH 1/2] Powerpc: Add
- voltage ranges support for T4
Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 3 +++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 1 +
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b..f1ac253 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -19,6 +19,8 @@ Optional properties:
bus-width = 1 property.
- sdhci,auto-cmd12: specifies that a controller can only handle auto
CMD12.
+ - 3300 3300: specifies that eSDHC controller can support voltages ranges
+from 3300 to 3300.
Example:
@@ -29,4 +31,5 @@ sdhci@2e000 {
interrupt-parent = ipic;
/* Filled in by U-Boot */
clock-frequency = 0;
+ voltage-ranges = 3300 3300;
};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..567d0fb 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -399,6 +399,7 @@
sdhc@114000 {
compatible = fsl,t4240-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
+ voltage-ranges = 1800 1800;
};
/include/ qoriq-i2c-0.dtsi
/include/ qoriq-i2c-1.dtsi
--
1.8.0
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[PATCH 2/2] Powerpc: Add 3.3v voltage support for T4240QDS
Freescale T4240QDS reference board has extra voltage shifters added
to allow 3.3V operation, so add 3.3v voltage support for T4240QDS.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Anton Vorontsov cbouatmai...@gmail.com
---
changes for this patch set:
- split from patch [PATCH 1/2] Powerpc: Add
- voltage ranges support for T4
arch/powerpc/boot/dts/t4240qds.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..5beccdd 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -148,6 +148,11 @@
interrupts = 0x1 0x1 0 0;
};
};
+
+ sdhc@114000 {
+ compatible = fsl,t4240-esdhc, fsl,esdhc;
+ voltage-ranges = 1800 1800 3300 3300;
+ };
};
pci0: pcie@ffe24 {
--
1.8.0
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[PATCH 3/4 V3] mmc: esdhc: Correct host version of T4240-R1.0-R2.0
Vender version and sdhc spec version of T4240-R1.0-R2.0 is incorrect.
The right value should be VVN=0x13, SVN = 0x1. The wrong version number
will break down the ADMA data transfer. This defect only exist in
T4240-R1.0-R2.0.
Also share vvn and svr for public use.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/sdhci-of-esdhc.c | 31 ++-
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index adfaadd..509e10d 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -26,7 +26,7 @@
#define VENDOR_V_220x12
#define VENDOR_V_230x13
-static u32 svr;
+static u32 svr, vvn;
static u32 esdhc_readl(struct sdhci_host *host, int reg)
{
@@ -43,11 +43,9 @@ static u32 esdhc_readl(struct sdhci_host *host, int reg)
* For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
* the verdor version number, oxFE is SDHCI_HOST_VERSION.
*/
- if ((reg == SDHCI_CAPABILITIES) (ret SDHCI_CAN_DO_ADMA1)) {
- u32 tmp = in_be32(host-ioaddr + SDHCI_SLOT_INT_STATUS);
- tmp = (tmp SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
- if (tmp VENDOR_V_22)
- ret |= SDHCI_CAN_DO_ADMA2;
+ if ((reg == SDHCI_CAPABILITIES) (ret SDHCI_CAN_DO_ADMA1)
+ (vvn VENDOR_V_22)) {
+ ret |= SDHCI_CAN_DO_ADMA2;
}
return ret;
@@ -63,6 +61,12 @@ static u16 esdhc_readw(struct sdhci_host *host, int reg)
ret = in_be32(host-ioaddr + base) 0x;
else
ret = (in_be32(host-ioaddr + base) shift) 0x;
+
+ /* T4240-R1.0-R2.0 had a incorrect vendor version and spec version */
+ if ((reg == SDHCI_HOST_VERSION)
+ ((SVR_SOC_VER(svr) == SVR_T4240) (SVR_REV(svr) =
0x20)))
+ ret = (VENDOR_V_23 SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
+
return ret;
}
@@ -175,17 +179,12 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
*/
static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
{
- u32 tmp;
bool applicable;
dma_addr_t dmastart;
dma_addr_t dmanow;
- tmp = esdhc_readl(host, SDHCI_SLOT_INT_STATUS);
- tmp = (tmp SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
-
applicable = (intmask SDHCI_INT_DATA_END)
- (intmask SDHCI_INT_BLK_GAP)
- (tmp == VENDOR_V_23);
+ (intmask SDHCI_INT_BLK_GAP) (vvn == VENDOR_V_23);
if (applicable) {
esdhc_reset(host, SDHCI_RESET_DATA);
@@ -215,7 +214,7 @@ static void esdhci_of_adma_workaround(struct sdhci_host
*host, u32 intmask)
((SVR_SOC_VER(svr) == SVR_P1010) (SVR_REV(svr) == 0x10)) ||
((SVR_SOC_VER(svr) == SVR_P3041) (SVR_REV(svr) = 0x20)) ||
((SVR_SOC_VER(svr) == SVR_P2041) (SVR_REV(svr) = 0x20)) ||
- ((SVR_SOC_VER(svr) == SVR_P5040) SVR_REV(svr) == 0x20)))
+ ((SVR_SOC_VER(svr) == SVR_P5040) (SVR_REV(svr) == 0x20
return;
esdhc_reset(host, SDHCI_RESET_DATA);
@@ -318,10 +317,9 @@ static void esdhc_of_resume(struct sdhci_host *host)
static void esdhc_of_platform_init(struct sdhci_host *host)
{
- u32 vvn;
+ svr = mfspr(SPRN_SVR);
+ vvn = esdhc_readw(host, SDHCI_HOST_VERSION);
- vvn = in_be32(host-ioaddr + SDHCI_SLOT_INT_STATUS);
- vvn = (vvn SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
if (vvn == VENDOR_V_22)
host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
@@ -390,7 +388,6 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
struct device_node *np;
int ret;
- svr = mfspr(SPRN_SVR);
host = sdhci_pltfm_init(pdev, sdhci_esdhc_pdata, 0);
if (IS_ERR(host))
return PTR_ERR(host);
--
1.8.0
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[PATCH 1/4 V4] powerpc/85xx: Add support for 85xx cpu type detection
Add this file to help detect cpu type in runtime. These macros will be more favorable for driver to apply errata and workaround to specified cpu type. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com --- changes for v4: - Add new set of soc arch/powerpc/include/asm/mpc85xx.h | 92 ++ 1 file changed, 92 insertions(+) create mode 100644 arch/powerpc/include/asm/mpc85xx.h diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h new file mode 100644 index 000..736d4ac --- /dev/null +++ b/arch/powerpc/include/asm/mpc85xx.h @@ -0,0 +1,92 @@ +/* + * MPC85xx cpu type detection + * + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_PPC_MPC85XX_H +#define __ASM_PPC_MPC85XX_H + +#define SVR_REV(svr) ((svr) 0xFF) /* SOC design resision */ +#define SVR_MAJ(svr) (((svr) 4) 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) 0) 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) 8) 0xFFF7FF) /* SOC Version fields */ + +#define SVR_8533 0x803400 +#define SVR_8535 0x803701 +#define SVR_8536 0x803700 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8543 0x803200 +#define SVR_8544 0x803401 +#define SVR_8545 0x803102 +#define SVR_8547 0x803101 +#define SVR_8548 0x803100 +#define SVR_8555 0x807100 +#define SVR_8560 0x807000 +#define SVR_8567 0x807501 +#define SVR_8568 0x807500 +#define SVR_8569 0x808000 +#define SVR_8572 0x80E000 +#define SVR_P1010 0x80F100 +#define SVR_P1011 0x80E500 +#define SVR_P1012 0x80E501 +#define SVR_P1013 0x80E700 +#define SVR_P1014 0x80F101 +#define SVR_P1017 0x80F700 +#define SVR_P1020 0x80E400 +#define SVR_P1021 0x80E401 +#define SVR_P1022 0x80E600 +#define SVR_P1023 0x80F600 +#define SVR_P1024 0x80E402 +#define SVR_P1025 0x80E403 +#define SVR_P2010 0x80E300 +#define SVR_P2020 0x80E200 +#define SVR_P2040 0x821000 +#define SVR_P2041 0x821001 +#define SVR_P3041 0x821103 +#define SVR_P4040 0x820100 +#define SVR_P4080 0x82 +#define SVR_P5010 0x822100 +#define SVR_P5020 0x822000 +#define SVR_P5021 0X820500 +#define SVR_P5040 0x820400 +#define SVR_T4240 0x824000 +#define SVR_T4120 0x824001 +#define SVR_T4160 0x824100 +#define SVR_C291 0x85 +#define SVR_C292 0x850020 +#define SVR_C293 0x850030 +#define SVR_B4860 0X868000 +#define SVR_G4860 0x868001 +#define SVR_G4060 0x868003 +#define SVR_B4440 0x868100 +#define SVR_G4440 0x868101 +#define SVR_B4420 0x868102 +#define SVR_B4220 0x868103 +#define SVR_T1040 0x852000 +#define SVR_T1041 0x852001 +#define SVR_T1042 0x852002 +#define SVR_T1020 0x852100 +#define SVR_T1021 0x852101 +#define SVR_T1022 0x852102 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + +#define SVR_9130 0x860001 +#define SVR_9131 0x86 +#define SVR_9132 0x861000 +#define SVR_9232 0x861400 + +#define SVR_Unknown0xFF + +#endif -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/4 V2] mmc: esdhc: workaround for dma err in the last system transaction
A-004388: eSDHC DMA might not stop if error occurs on system transaction
eSDHC DMA(SDMA/ADMA) might not stop if an error occurs in the last system
transaction. It may continue initiating additional transactions until
software reset for data/all is issued during error recovery. There is not
any data corruption to the SD data. The IRQSTAT[DMAE] is set when the
erratum occurs.
The only conditions under which issues occur are the following:
1. SDMA - For SD Write , the error occurs in the last system transaction.
No issue for SD read
2. ADMA
a. Block count is enabled: For SD write, the error occurs in the last system
transaction. There is no issue for SD read when block count is enabled.
b. Block count is disabled: Block count is designated by the ADMA descriptor
table, and the error occurs in the last system transaction when ADMA is
executing last descriptor line of table.
eSDHC may initiate additional system transactions. There is no data integrity
issue for case 1 and 2a described below. For case 2b, system data might be
corrupted.
Workaround: Set eSDHC_SYSCTL[RSTD] when IRQSTAT[DMAE] is set. For cases 2a and
2b above, add an extra descriptor line with zero data next to the last
descriptor line.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Update the svr version list
drivers/mmc/host/sdhci-of-esdhc.c | 112 ++
1 file changed, 102 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 15039e2..adfaadd 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -21,9 +21,13 @@
#include linux/mmc/host.h
#include sdhci-pltfm.h
#include sdhci-esdhc.h
+#include asm/mpc85xx.h
#define VENDOR_V_220x12
#define VENDOR_V_230x13
+
+static u32 svr;
+
static u32 esdhc_readl(struct sdhci_host *host, int reg)
{
u32 ret;
@@ -142,6 +146,26 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val,
int reg)
sdhci_be32bs_writeb(host, val, reg);
}
+static void esdhc_reset(struct sdhci_host *host, u8 mask)
+{
+ u32 ier;
+ u32 uninitialized_var(isav);
+
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+ isav = esdhc_readl(host, SDHCI_INT_ENABLE);
+
+ esdhc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ mdelay(100);
+
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) {
+ ier = esdhc_readl(host, SDHCI_INT_ENABLE);
+ ier = ~SDHCI_INT_ALL_MASK;
+ ier |= isav;
+ esdhc_writel(host, ier, SDHCI_INT_ENABLE);
+ esdhc_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+ }
+}
+
/*
* For Abort or Suspend after Stop at Block Gap, ignore the ADMA
* error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
@@ -156,25 +180,92 @@ static void esdhci_of_adma_workaround(struct sdhci_host
*host, u32 intmask)
dma_addr_t dmastart;
dma_addr_t dmanow;
- tmp = in_be32(host-ioaddr + SDHCI_SLOT_INT_STATUS);
+ tmp = esdhc_readl(host, SDHCI_SLOT_INT_STATUS);
tmp = (tmp SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
applicable = (intmask SDHCI_INT_DATA_END)
(intmask SDHCI_INT_BLK_GAP)
(tmp == VENDOR_V_23);
- if (!applicable)
+ if (applicable) {
+
+ esdhc_reset(host, SDHCI_RESET_DATA);
+ host-data-error = 0;
+ dmastart = sg_dma_address(host-data-sg);
+ dmanow = dmastart + host-data-bytes_xfered;
+
+ /* Force update to the next DMA block boundary. */
+ dmanow = (dmanow ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+ SDHCI_DEFAULT_BOUNDARY_SIZE;
+ host-data-bytes_xfered = dmanow - dmastart;
+ esdhc_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+
return;
+ }
- host-data-error = 0;
- dmastart = sg_dma_address(host-data-sg);
- dmanow = dmastart + host-data-bytes_xfered;
/*
-* Force update to the next DMA block boundary.
+* Check for A-004388: eSDHC DMA might not stop if error
+* occurs on system transaction
+* Impact list:
+* T4240-R1.0 B4860-R1.0 P1010-R1.0
+* P3041-R1.0-R2.0-R1.1 P2041-R1.0-R1.1-R2.0
+* P5040-R2.0
*/
- dmanow = (dmanow ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
- SDHCI_DEFAULT_BOUNDARY_SIZE;
- host-data-bytes_xfered = dmanow - dmastart;
- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+ if (!(((SVR_SOC_VER(svr) == SVR_T4240) (SVR_REV(svr) == 0x10)) ||
+ ((SVR_SOC_VER(svr) == SVR_B4860) (SVR_REV(svr) == 0x10)) ||
+ ((SVR_SOC_VER(svr) == SVR_P1010) (SVR_REV(svr) == 0x10)) ||
+ ((SVR_SOC_VER(svr) == SVR_P3041) (SVR_REV(svr) = 0x20)) ||
+ ((SVR_SOC_VER(svr) == SVR_P2041) (SVR_REV(svr
[PATCH 3/4 V2] mmc: esdhc: Correct host version of T4240-R1.0
Vender version and sdhc spec version of T4240-R1.0 is incorrect.
The right value should be VVN=0x13, SVN = 0x1. The wrong version
number will break down the ADMA data transfer.
This defect only exist in T4240-R1.0. Will be fixed in T4240-R2.0.
Also share vvn and svr for public use.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V2:
- Remove broken ADMA quirk.
- Rebuild patch of Add quirks to support T4240 board
drivers/mmc/host/sdhci-of-esdhc.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index adfaadd..570bca8 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -26,7 +26,7 @@
#define VENDOR_V_220x12
#define VENDOR_V_230x13
-static u32 svr;
+static u32 svr, vvn;
static u32 esdhc_readl(struct sdhci_host *host, int reg)
{
@@ -43,11 +43,9 @@ static u32 esdhc_readl(struct sdhci_host *host, int reg)
* For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
* the verdor version number, oxFE is SDHCI_HOST_VERSION.
*/
- if ((reg == SDHCI_CAPABILITIES) (ret SDHCI_CAN_DO_ADMA1)) {
- u32 tmp = in_be32(host-ioaddr + SDHCI_SLOT_INT_STATUS);
- tmp = (tmp SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
- if (tmp VENDOR_V_22)
- ret |= SDHCI_CAN_DO_ADMA2;
+ if ((reg == SDHCI_CAPABILITIES) (ret SDHCI_CAN_DO_ADMA1)
+ (vvn VENDOR_V_22)) {
+ ret |= SDHCI_CAN_DO_ADMA2;
}
return ret;
@@ -63,6 +61,12 @@ static u16 esdhc_readw(struct sdhci_host *host, int reg)
ret = in_be32(host-ioaddr + base) 0x;
else
ret = (in_be32(host-ioaddr + base) shift) 0x;
+
+ /* T4240-R1.0 had a incorrect vendor version and spec version */
+ if ((reg == SDHCI_HOST_VERSION)
+ ((SVR_SOC_VER(svr) == SVR_T4240) (SVR_REV(svr) == 0x10)))
+ ret = (VENDOR_V_23 SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
+
return ret;
}
@@ -175,17 +179,12 @@ static void esdhc_reset(struct sdhci_host *host, u8 mask)
*/
static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
{
- u32 tmp;
bool applicable;
dma_addr_t dmastart;
dma_addr_t dmanow;
- tmp = esdhc_readl(host, SDHCI_SLOT_INT_STATUS);
- tmp = (tmp SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
-
applicable = (intmask SDHCI_INT_DATA_END)
- (intmask SDHCI_INT_BLK_GAP)
- (tmp == VENDOR_V_23);
+ (intmask SDHCI_INT_BLK_GAP) (vvn == VENDOR_V_23);
if (applicable) {
esdhc_reset(host, SDHCI_RESET_DATA);
@@ -318,10 +317,9 @@ static void esdhc_of_resume(struct sdhci_host *host)
static void esdhc_of_platform_init(struct sdhci_host *host)
{
- u32 vvn;
+ svr = mfspr(SPRN_SVR);
+ vvn = esdhc_readw(host, SDHCI_HOST_VERSION);
- vvn = in_be32(host-ioaddr + SDHCI_SLOT_INT_STATUS);
- vvn = (vvn SDHCI_VENDOR_VER_MASK) SDHCI_VENDOR_VER_SHIFT;
if (vvn == VENDOR_V_22)
host-quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
@@ -390,7 +388,6 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
struct device_node *np;
int ret;
- svr = mfspr(SPRN_SVR);
host = sdhci_pltfm_init(pdev, sdhci_esdhc_pdata, 0);
if (IS_ERR(host))
return PTR_ERR(host);
--
1.8.0
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[PATCH 4/4 V2] mmc: esdhc: Add broken timeout quirk for p4/p5 board
Sometimes command can't be completed within the time give in eSDHC_SYSCTL[DTOCV]. So just give the max value 0x14 to avoid this issue. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for v2: - Rebuild patch of eSDHC host need long time to generate command interrupt drivers/mmc/host/sdhci-of-esdhc.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 570bca8..30bfb5c 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -325,6 +325,12 @@ static void esdhc_of_platform_init(struct sdhci_host *host) if (vvn VENDOR_V_22) host-quirks = ~SDHCI_QUIRK_NO_BUSY_IRQ; + + if ((SVR_SOC_VER(svr) == SVR_B4860) || + (SVR_SOC_VER(svr) == SVR_P5020) || + (SVR_SOC_VER(svr) == SVR_P5040) || + (SVR_SOC_VER(svr) == SVR_P4080)) + host-quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; } static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 1 USB ports
- TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Xie Xiaobo-R63061 x@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for v6:
- change the size of SPI file system
changes for v5:
- change the size of nand file system
arch/powerpc/boot/dts/p1020rdb-pd.dts | 280 ++
1 file changed, 280 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dts
b/arch/powerpc/boot/dts/p1020rdb-pd.dts
new file mode 100644
index 000..ffbda25
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dts
@@ -0,0 +1,280 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash, L2 switch and CPLD */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered
[PATCH V5] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 1 USB ports
- TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Xie Xiaobo-R63061 x@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for v5:
- change the size of nand file system
arch/powerpc/boot/dts/p1020rdb-pd.dts | 280 ++
1 file changed, 280 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dts
b/arch/powerpc/boot/dts/p1020rdb-pd.dts
new file mode 100644
index 000..ffbda25
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dts
@@ -0,0 +1,280 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash, L2 switch and CPLD */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image
[PATCH 1/4 V2] powerpc/85xx: Add support for 85xx cpu type detection
Add this file to help detect cpu type in runtime. These macros will be more favorable for driver to apply errata and workaround to specified cpu type. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com --- changes v2: - Remove inline function - Ignore E bit of SOC - Add Macro to get current soc version arch/powerpc/include/asm/mpc85xx.h | 53 ++ 1 file changed, 53 insertions(+) create mode 100644 arch/powerpc/include/asm/mpc85xx.h diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h new file mode 100644 index 000..20af5e8 --- /dev/null +++ b/arch/powerpc/include/asm/mpc85xx.h @@ -0,0 +1,53 @@ +/* + * MPC85xx cpu type detection + * + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_PPC_MPC85XX_H +#define __ASM_PPC_MPC85XX_H + +#define SVR_REV(svr) ((svr) 0xFF) /* SOC design resision */ +#define SVR_MAJ(svr) (((svr) 4) 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) 0) 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) 8) 0xFFF7FF) /* SOC Version fields */ + +/* Get current SOC Version */ +#define GET_SVR() (mfspr(SPRN_SVR)) + +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == (maj)) (SVR_MIN(svr) == (min))) + +#define SVR_8533 0x803400 +#define SVR_8535 0x803701 +#define SVR_8536 0x803700 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8543 0x803200 +#define SVR_8544 0x803401 +#define SVR_8545 0x803102 +#define SVR_8547 0x803101 +#define SVR_8548 0x803100 +#define SVR_8555 0x807100 +#define SVR_8560 0x807000 +#define SVR_8567 0x807501 +#define SVR_8568 0x807500 +#define SVR_8569 0x808000 +#define SVR_8572 0x80E000 +#define SVR_P1010 0x80f900 +#define SVR_P2041 0x821001 +#define SVR_P3041 0x821103 +#define SVR_P5010 0x822100 +#define SVR_P5020 0x822000 +#define SVR_P5040 0x820400 +#define SVR_T4240 0x824800 +#define SVR_B4860 0x868800 + +#endif -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V3] powerpc/85xx: Add support for 85xx cpu type detection
Add this file to help detect cpu type in runtime. These macros will be more favorable for driver to apply errata and workaround to specified cpu type. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com --- changes for v3: - remove get_svr and is_svr_rev arch/powerpc/include/asm/mpc85xx.h | 47 ++ 1 file changed, 47 insertions(+) create mode 100644 arch/powerpc/include/asm/mpc85xx.h diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h new file mode 100644 index 000..824b619 --- /dev/null +++ b/arch/powerpc/include/asm/mpc85xx.h @@ -0,0 +1,47 @@ +/* + * MPC85xx cpu type detection + * + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_PPC_MPC85XX_H +#define __ASM_PPC_MPC85XX_H + +#define SVR_REV(svr) ((svr) 0xFF) /* SOC design resision */ +#define SVR_MAJ(svr) (((svr) 4) 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) 0) 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) 8) 0xFFF7FF) /* SOC Version fields */ + +#define SVR_8533 0x803400 +#define SVR_8535 0x803701 +#define SVR_8536 0x803700 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8543 0x803200 +#define SVR_8544 0x803401 +#define SVR_8545 0x803102 +#define SVR_8547 0x803101 +#define SVR_8548 0x803100 +#define SVR_8555 0x807100 +#define SVR_8560 0x807000 +#define SVR_8567 0x807501 +#define SVR_8568 0x807500 +#define SVR_8569 0x808000 +#define SVR_8572 0x80E000 +#define SVR_P1010 0x80f900 +#define SVR_P2041 0x821001 +#define SVR_P3041 0x821103 +#define SVR_P5010 0x822100 +#define SVR_P5020 0x822000 +#define SVR_P5040 0x820400 +#define SVR_T4240 0x824800 +#define SVR_B4860 0x868800 + +#endif -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2 V3] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Xie Xiaobo-R63061 x@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for v3:
- Remove some blank and changed the usb node
- Renamed the dts file
- change the cpld name of pd board
arch/powerpc/boot/dts/p1020rdb-pd.dts | 90
arch/powerpc/boot/dts/p1020rdb-pd.dtsi | 257 +
2 files changed, 347 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dts
b/arch/powerpc/boot/dts/p1020rdb-pd.dts
new file mode 100644
index 000..e58bb76
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash, L2 switch and CPLD */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ reg = 0x0 0xffe09000 0x0 0x1000;
+ ranges = 0x200 0x0 0xa000 0x0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0x0 0xffc1 0x0 0x1;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0x0 0xffe0a000 0x0 0x1000;
+ ranges = 0x200 0x0 0x8000 0x0 0x8000 0x0 0x2000
+ 0x100 0x0 0x 0x0 0xffc0 0x0 0x1;
+ pcie@0 {
+ ranges = 0x200 0x0 0x8000
+ 0x200 0x0 0x8000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+};
+
+/include/ p1020rdb-pd.dtsi
+/include/ fsl/p1020si-post.dtsi
diff --git a/arch/powerpc/boot
[PATCH 2/2 V4] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 1 USB ports
- TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Xie Xiaobo-R63061 x@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for V4:
- Combine *.dtsi to dts file
- Remove redundant fs patition
arch/powerpc/boot/dts/p1020rdb-pd.dts | 280 ++
1 file changed, 280 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dts
b/arch/powerpc/boot/dts/p1020rdb-pd.dts
new file mode 100644
index 000..c10d027
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dts
@@ -0,0 +1,280 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash, L2 switch and CPLD */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered */
+ /* 512KB
[PATCH] Powerpc/t4240: change the compatible flags for t4240qds board
In order to make a difference between different T4240 board.
Specify T4240QDS board the unique compatible flags for t4240qds
eSDHC host.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..08b47d0 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -397,7 +397,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
- compatible = fsl,t4240-esdhc, fsl,esdhc;
+ compatible = fsl,t4240qds-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
};
/include/ qoriq-i2c-0.dtsi
--
1.8.0
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[PATCH 3/4 V2] mmc: esdhc: Add quirks to support T4240QDS board
On T4240QDS board controllers has an unusable ADMA engine, so use SDMA instead.
Also 3.0v is support on T4240QDS board even if the capacity detailed only 1.8v
support. Without this quirk SD card will declare voltage not support and
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for v2:
- Change the compatible for t4240qds board
drivers/mmc/host/sdhci-pltfm.c | 7 ++-
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index e2065a4..800e82f 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -92,9 +92,14 @@ void sdhci_get_of_property(struct platform_device *pdev)
if (of_device_is_compatible(np, fsl,p2020-rev1-esdhc))
host-quirks |= SDHCI_QUIRK_BROKEN_DMA;
+ if (of_device_is_compatible(np, fsl,t4240qds-esdhc)) {
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+ host-quirks2 |= SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30;
+ }
+
if (of_device_is_compatible(np, fsl,p2020-esdhc) ||
of_device_is_compatible(np, fsl,p1010-esdhc) ||
- of_device_is_compatible(np, fsl,t4240-esdhc) ||
+ of_device_is_compatible(np, fsl,t4240qds-esdhc) ||
of_device_is_compatible(np, fsl,mpc8536-esdhc))
host-quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..de7fa81 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2797,6 +2797,9 @@ int sdhci_add_host(struct sdhci_host *host)
host-caps1 :
sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ if (host-quirks2 SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30)
+ caps[0] = caps[0] | SDHCI_CAN_VDD_300;
+
if (host-quirks SDHCI_QUIRK_FORCE_DMA)
host-flags |= SDHCI_USE_SDMA;
else if (!(caps[0] SDHCI_CAN_DO_SDMA))
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..dc608d7 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (14)
/* Controller has a non-standard host control register */
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (15)
+/* The host support VS300 even if the capacity detailed not */
+#define SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30 (16)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.8.0
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[PATCH 2/4] mmc: esdhc: workaround for dma err in the last system transaction
A-004388: eSDHC DMA might not stop if error occurs on system transaction
eSDHC DMA(SDMA/ADMA) might not stop if an error occurs in the last system
transaction. It may continue initiating additional transactions until
software reset for data/all is issued during error recovery. There is not
any data corruption to the SD data. The IRQSTAT[DMAE] is set when the
erratum occurs.
The only conditions under which issues occur are the following:
1. SDMA - For SD Write , the error occurs in the last system transaction.
No issue for SD read
2. ADMA
a. Block count is enabled: For SD write, the error occurs in the last system
transaction. There is no issue for SD read when block count is enabled.
b. Block count is disabled: Block count is designated by the ADMA descriptor
table, and the error occurs in the last system transaction when ADMA is
executing last descriptor line of table.
eSDHC may initiate additional system transactions. There is no data integrity
issue for case 1 and 2a described below. For case 2b, system data might be
corrupted.
Workaround: Set eSDHC_SYSCTL[RSTD] when IRQSTAT[DMAE] is set. For cases 2a and
2b above, add an extra descriptor line with zero data next to the last
descriptor line.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/sdhci-of-esdhc.c | 113 +++---
1 file changed, 104 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 15039e2..b22cab0 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -21,6 +21,7 @@
#include linux/mmc/host.h
#include sdhci-pltfm.h
#include sdhci-esdhc.h
+#include asm/mpc85xx.h
#define VENDOR_V_220x12
#define VENDOR_V_230x13
@@ -142,6 +143,26 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val,
int reg)
sdhci_be32bs_writeb(host, val, reg);
}
+static void esdhc_reset(struct sdhci_host *host, u8 mask)
+{
+ u32 ier;
+ u32 uninitialized_var(isav);
+
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+ isav = esdhc_readl(host, SDHCI_INT_ENABLE);
+
+ esdhc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ mdelay(100);
+
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) {
+ ier = esdhc_readl(host, SDHCI_INT_ENABLE);
+ ier = ~SDHCI_INT_ALL_MASK;
+ ier |= isav;
+ esdhc_writel(host, ier, SDHCI_INT_ENABLE);
+ esdhc_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+ }
+}
+
/*
* For Abort or Suspend after Stop at Block Gap, ignore the ADMA
* error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
@@ -162,19 +183,93 @@ static void esdhci_of_adma_workaround(struct sdhci_host
*host, u32 intmask)
applicable = (intmask SDHCI_INT_DATA_END)
(intmask SDHCI_INT_BLK_GAP)
(tmp == VENDOR_V_23);
- if (!applicable)
+ if (applicable) {
+
+ esdhc_reset(host, SDHCI_RESET_DATA);
+ host-data-error = 0;
+ dmastart = sg_dma_address(host-data-sg);
+ dmanow = dmastart + host-data-bytes_xfered;
+ /*
+* Force update to the next DMA block boundary.
+*/
+ dmanow = (dmanow ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+ SDHCI_DEFAULT_BOUNDARY_SIZE;
+ host-data-bytes_xfered = dmanow - dmastart;
+ sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+
return;
+ }
- host-data-error = 0;
- dmastart = sg_dma_address(host-data-sg);
- dmanow = dmastart + host-data-bytes_xfered;
/*
-* Force update to the next DMA block boundary.
+* Check for A-004388: eSDHC DMA might not stop if error
+* occurs on system transaction
+* Impact list:
+* T4240-R1.0 B4860-R1.0 P1010-R1.0
*/
- dmanow = (dmanow ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
- SDHCI_DEFAULT_BOUNDARY_SIZE;
- host-data-bytes_xfered = dmanow - dmastart;
- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+ if (!((fsl_svr_is(SVR_T4240) fsl_svr_rev_is(1, 0)) ||
+ (fsl_svr_is(SVR_B4860) fsl_svr_rev_is(1, 0)) ||
+ (fsl_svr_is(SVR_P1010) fsl_svr_rev_is(1, 0
+ return;
+
+
+ esdhc_reset(host, SDHCI_RESET_DATA);
+
+ if (host-flags SDHCI_USE_ADMA) {
+ u32 mod, i, offset;
+ u8 *desc;
+ dma_addr_t addr;
+ struct scatterlist *sg;
+
+ mod = esdhc_readl(host, SDHCI_TRANSFER_MODE);
+ if (mod SDHCI_TRNS_BLK_CNT_EN) {
+ /*
+* In case read transfer there is no data
+* was corrupted
+*/
+ if (host-data-flags MMC_DATA_READ
[PATCH 3/4] mmc: esdhc: Add quirks to support T4240 board
On T4240 board controllers has an unusable ADMA engine, so use SDMA instead.
Also 3.0v is support on T4240 board even if the capacity detailed only 1.8v
support. Without this quirk SD card will declare voltage not support and
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/sdhci-pltfm.c | 5 +
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 2 ++
3 files changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index e2065a4..02edb3d 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -92,6 +92,11 @@ void sdhci_get_of_property(struct platform_device *pdev)
if (of_device_is_compatible(np, fsl,p2020-rev1-esdhc))
host-quirks |= SDHCI_QUIRK_BROKEN_DMA;
+ if (of_device_is_compatible(np, fsl,t4240-esdhc)) {
+ host-quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+ host-quirks2 |= SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30;
+ }
+
if (of_device_is_compatible(np, fsl,p2020-esdhc) ||
of_device_is_compatible(np, fsl,p1010-esdhc) ||
of_device_is_compatible(np, fsl,t4240-esdhc) ||
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..de7fa81 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2797,6 +2797,9 @@ int sdhci_add_host(struct sdhci_host *host)
host-caps1 :
sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ if (host-quirks2 SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30)
+ caps[0] = caps[0] | SDHCI_CAN_VDD_300;
+
if (host-quirks SDHCI_QUIRK_FORCE_DMA)
host-flags |= SDHCI_USE_SDMA;
else if (!(caps[0] SDHCI_CAN_DO_SDMA))
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..dc608d7 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -98,6 +98,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (14)
/* Controller has a non-standard host control register */
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (15)
+/* The host support VS300 even if the capacity detailed not */
+#define SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30 (16)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.8.0
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[PATCH 1/4] powerpc/85xx: Add support for 85xx cpu type detection
Add this file to help detect cpu type in runtime.
These macros and inline routines will be more favorable for driver
to apply errata and workaround to specified cpu type.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/include/asm/mpc85xx.h | 96 ++
1 file changed, 96 insertions(+)
create mode 100644 arch/powerpc/include/asm/mpc85xx.h
diff --git a/arch/powerpc/include/asm/mpc85xx.h
b/arch/powerpc/include/asm/mpc85xx.h
new file mode 100644
index 000..a49fead
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -0,0 +1,96 @@
+/*
+ * MPC85xx cpu type detection
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_CPU_H
+#define __ASM_PPC_CPU_H
+
+#define SVR_REV(svr) ((svr) 0xFF) /* SOC design resision */
+#define SVR_MAJ(svr) (((svr) 4) 0xF) /* Major revision field*/
+#define SVR_MIN(svr) (((svr) 0) 0xF) /* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) 8) 0xFF) /* SOC Version fields */
+
+#define IS_SVR_REV(svr, maj, min) \
+ ((SVR_MAJ(svr) == (maj)) (SVR_MIN(svr) == (min)))
+
+#define SVR_8533 0x803400
+#define SVR_8533_E 0x803C00
+#define SVR_8535 0x803701
+#define SVR_8535_E 0x803F01
+#define SVR_8536 0x803700
+#define SVR_8536_E 0x803F00
+#define SVR_8540 0x803000
+#define SVR_8541 0x807200
+#define SVR_8541_E 0x807A00
+#define SVR_8543 0x803200
+#define SVR_8543_E 0x803A00
+#define SVR_8544 0x803401
+#define SVR_8544_E 0x803C01
+#define SVR_8545 0x803102
+#define SVR_8545_E 0x803902
+#define SVR_8547 0x803101
+#define SVR_8547_E 0x803901
+#define SVR_8548 0x803100
+#define SVR_8548_E 0x803900
+#define SVR_8555 0x807100
+#define SVR_8555_E 0x807900
+#define SVR_8560 0x807000
+#define SVR_8567 0x807501
+#define SVR_8567_E 0x807D01
+#define SVR_8568 0x807500
+#define SVR_8568_E 0x807D00
+#define SVR_8569 0x808000
+#define SVR_8569_E 0x808800
+#define SVR_8572 0x80E000
+#define SVR_8572_E 0x80E800
+#define SVR_P1010 0x80f900
+#define SVR_P1010_E0x80F100
+#define SVR_P2041 0x821001
+#define SVR_P2041_E0x821801
+#define SVR_P3041 0x821103
+#define SVR_P3041_E0x821903
+#define SVR_P5010 0x822100
+#define SVR_P5010_E0x822900
+#define SVR_P5020 0x822000
+#define SVR_P5020_E0x822800
+#define SVR_P5040 0x820400
+#define SVR_P5040_E0x820B00
+#define SVR_T4240 0x824800
+#define SVR_B4860 0x868800
+
+
+static inline int fsl_svr_is(u32 svr)
+{
+ u32 id = SVR_SOC_VER(mfspr(SPRN_SVR));
+
+ return (id == svr);
+}
+
+/* Check the SOC design version of this board */
+static inline int fsl_svr_rev_is(u8 maj, u8 min)
+{
+ u32 rev = SVR_REV(mfspr(SPRN_SVR));
+ u32 cmp = (maj 4) | min;
+
+ return (rev == cmp);
+}
+
+/* Return true if current SOC revision is prior to (maj, min) */
+static inline int fsl_svr_older_than(u8 maj, u8 min)
+{
+ u32 rev = SVR_REV(mfspr(SPRN_SVR));
+ u32 cmp = (maj 4) | min;
+
+ return (rev cmp);
+}
+
+#endif
--
1.8.0
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[PATCH 4/4] mmc: eSDHC: Some eSDHC host need long time to generate command interrupt
Command complete interrupt not always generate within 10 * HZ. Sometimes
500 * HZ or more. So enlarge this detecting value to ensure the host had
sufficient time to generate command complete interrupt.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/host/sdhci-of-esdhc.c | 3 +++
drivers/mmc/host/sdhci.c | 10 +-
include/linux/mmc/sdhci.h | 2 ++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index b22cab0..b616b03 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -331,6 +331,9 @@ static void esdhc_of_platform_init(struct sdhci_host *host)
if (vvn VENDOR_V_22)
host-quirks = ~SDHCI_QUIRK_NO_BUSY_IRQ;
+
+ if (fsl_svr_is(SVR_B4860) || fsl_svr_is(SVR_T4240))
+ host-quirks2 |= SDHCI_QUIRK2_LONG_TM_CMD_COMPLETE_IRQ;
}
static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index de7fa81..35015ba 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -986,6 +986,7 @@ static void sdhci_send_command(struct sdhci_host *host,
struct mmc_command *cmd)
int flags;
u32 mask;
unsigned long timeout;
+ int timer = 10;
WARN_ON(host-cmd);
@@ -1014,7 +1015,14 @@ static void sdhci_send_command(struct sdhci_host *host,
struct mmc_command *cmd)
mdelay(1);
}
- mod_timer(host-timer, jiffies + 10 * HZ);
+ /*
+* Some eSDHC controller need long time to generate command complete
+* interrupt, 1000 * HZ will be enough.
+*/
+ if (host-quirks2 SDHCI_QUIRK2_LONG_TM_CMD_COMPLETE_IRQ)
+ timer = 1000;
+
+ mod_timer(host-timer, jiffies + timer * HZ);
host-cmd = cmd;
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dc608d7..68e7dd1 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (15)
/* The host support VS300 even if the capacity detailed not */
#define SDHCI_QUIRK2_CIRCUIT_SUPPORT_VS30 (16)
+/* Some controller need long time to generate command complete interrupt */
+#define SDHCI_QUIRK2_LONG_TM_CMD_COMPLETE_IRQ (17)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.8.0
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[PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for v2:
- Remove address cells and size cells for pc/pd board
arch/powerpc/boot/dts/p1020rdb-pc.dtsi| 4 +-
arch/powerpc/boot/dts/p1020rdb-pd.dtsi| 253 ++
arch/powerpc/boot/dts/p1020rdb-pd_32b.dts | 90 +++
3 files changed, 344 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
index c952cd3..9d24501 100644
--- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -131,9 +131,7 @@
};
cpld@3,0 {
- #address-cells = 1;
- #size-cells = 1;
- compatible = cpld;
+ compatible = fsl, p1020rdb-cpld;
reg = 0x3 0x0 0x2;
read-only;
};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
new file mode 100644
index 000..03b308d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
@@ -0,0 +1,253 @@
+/*
+ * P1020RDB-PD Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x03f0 0x0010
[PATCH] DTS: Add compatible list for eSDHC
Add compatible of esdhc for below board:
p2041 p3041 p4080 p5020 p5040
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
CC: Scott Wood scottw...@freescale.com
CC: Fleming Andrew-AFLEMING aflem...@freescale.com
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 1 +
5 files changed, 5 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 531eab8..0a8f1bd 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -299,6 +299,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
+ compatible = fsl,p2041-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index af4ebc8..2165e17 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -326,6 +326,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
+ compatible = fsl,p3041-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 4f9c9f6..cadd81e 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -335,6 +335,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
+ compatible = fsl,p4080-esdhc, fsl,esdhc;
voltage-ranges = 3300 3300;
sdhci,auto-cmd12;
};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 5d7205b..bb0de92 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -329,6 +329,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
+ compatible = fsl,p5020-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index db2c9a7..bcd0f7a 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -292,6 +292,7 @@
/include/ qoriq-esdhc-0.dtsi
sdhc@114000 {
+ compatible = fsl,p5040-esdhc, fsl,esdhc;
sdhci,auto-cmd12;
};
--
1.8.0
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[PATCH 1/2] [PATCH] powerpc/85xx: add P1020RDB-PD platform support
From: Haijun.Zhang haijun.zh...@freescale.com
The p1020rdb-pd has the similar feature as the p1020rdb.
Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board.
Overview of P1020RDB-PD platform:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ede8771..53b6fb0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -160,6 +160,7 @@ machine_arch_initcall(p2020_rdb_pc,
mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices);
machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
@@ -193,6 +194,13 @@ static int __init p1020_rdb_pc_probe(void)
return of_flat_dt_is_compatible(root, fsl,P1020RDB-PC);
}
+static int __init p1020_rdb_pd_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P1020RDB-PD);
+}
+
static int __init p1021_rdb_pc_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -351,6 +359,20 @@ define_machine(p1020_rdb_pc) {
.progress = udbg_progress,
};
+define_machine(p1020_rdb_pd) {
+ .name = P1020RDB-PD,
+ .probe = p1020_rdb_pd_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
define_machine(p1024_rdb) {
.name = P1024 RDB,
.probe = p1024_rdb_probe,
--
1.8.0
___
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[PATCH 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
From: Haijun.Zhang haijun.zh...@freescale.com
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
arch/powerpc/boot/dts/p1020rdb-pd.dtsi| 257 ++
arch/powerpc/boot/dts/p1020rdb-pd_32b.dts | 90 +++
2 files changed, 347 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
new file mode 100644
index 000..6e07fa7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
@@ -0,0 +1,257 @@
+/*
+ * P1020RDB-PD Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x03f0 0x0010;
+ label = NOR U-Boot Image;
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,p1020-fcm-nand,
+fsl,elbc-fcm-nand;
+ reg = 0x1 0x0 0x4;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = 0x0 0x0010;
+ label = NAND U-Boot Image
