Re: powerpc: Fix missing includes needed for chroma
Drop it now :) However, it may be nice to keep the A2 stuff until BGQ EOLs -jx On Wed, Nov 20, 2013 at 8:40 PM, Michael Neuling mi...@neuling.org wrote: chroma_defconfig is horribly broken currently, so add a bunch of #includes to fix it. Signed-off-by: Michael Neuling mi...@neuling.org --- So when are we dropping arch/powerpc/platforms/wsp? diff --git a/arch/powerpc/platforms/wsp/chroma.c b/arch/powerpc/platforms/wsp/chroma.c index 8ef53bc..aaa46b3 100644 --- a/arch/powerpc/platforms/wsp/chroma.c +++ b/arch/powerpc/platforms/wsp/chroma.c @@ -15,6 +15,7 @@ #include linux/of.h #include linux/smp.h #include linux/time.h +#include linux/of_fdt.h #include asm/machdep.h #include asm/udbg.h diff --git a/arch/powerpc/platforms/wsp/h8.c b/arch/powerpc/platforms/wsp/h8.c index d18e6cc..a3c87f3 100644 --- a/arch/powerpc/platforms/wsp/h8.c +++ b/arch/powerpc/platforms/wsp/h8.c @@ -10,6 +10,7 @@ #include linux/kernel.h #include linux/of.h #include linux/io.h +#include linux/of_address.h #include wsp.h diff --git a/arch/powerpc/platforms/wsp/ics.c b/arch/powerpc/platforms/wsp/ics.c index 2d3b1dd..3b782ce 100644 --- a/arch/powerpc/platforms/wsp/ics.c +++ b/arch/powerpc/platforms/wsp/ics.c @@ -18,6 +18,8 @@ #include linux/smp.h #include linux/spinlock.h #include linux/types.h +#include linux/of_irq.h +#include linux/of_address.h #include asm/io.h #include asm/irq.h diff --git a/arch/powerpc/platforms/wsp/opb_pic.c b/arch/powerpc/platforms/wsp/opb_pic.c index cb565bf..3f67298 100644 --- a/arch/powerpc/platforms/wsp/opb_pic.c +++ b/arch/powerpc/platforms/wsp/opb_pic.c @@ -15,6 +15,8 @@ #include linux/of.h #include linux/slab.h #include linux/time.h +#include linux/of_address.h +#include linux/of_irq.h #include asm/reg_a2.h #include asm/irq.h diff --git a/arch/powerpc/platforms/wsp/psr2.c b/arch/powerpc/platforms/wsp/psr2.c index 508ec82..a87b414 100644 --- a/arch/powerpc/platforms/wsp/psr2.c +++ b/arch/powerpc/platforms/wsp/psr2.c @@ -15,6 +15,7 @@ #include linux/of.h #include linux/smp.h #include linux/time.h +#include linux/of_fdt.h #include asm/machdep.h #include asm/udbg.h diff --git a/arch/powerpc/platforms/wsp/scom_wsp.c b/arch/powerpc/platforms/wsp/scom_wsp.c index 8928507..6538b4d 100644 --- a/arch/powerpc/platforms/wsp/scom_wsp.c +++ b/arch/powerpc/platforms/wsp/scom_wsp.c @@ -14,6 +14,7 @@ #include linux/of.h #include linux/spinlock.h #include linux/types.h +#include linux/of_address.h #include asm/cputhreads.h #include asm/reg_a2.h diff --git a/arch/powerpc/platforms/wsp/wsp.c b/arch/powerpc/platforms/wsp/wsp.c index ddb6efe..58cd1f0 100644 --- a/arch/powerpc/platforms/wsp/wsp.c +++ b/arch/powerpc/platforms/wsp/wsp.c @@ -13,6 +13,7 @@ #include linux/smp.h #include linux/delay.h #include linux/time.h +#include linux/of_address.h #include asm/scom.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Dec 18, 2012, at 10:31 AM, Peter Bergner berg...@vnet.ibm.com wrote:
On Tue, 2012-12-18 at 07:28 -0600, Jimi Xenidis wrote:
On Dec 17, 2012, at 6:26 PM, Peter Bergner berg...@vnet.ibm.com wrote:
Jimi, are you using an old binutils from before my patch that
changed the operand order for these types of instructions?
http://sourceware.org/ml/binutils/2009-02/msg00044.html
Actually, this confused me as well, that embedded has the same instruction
encoding but different mnemonic.
The mnemonic is the same (ie, dcbtst), and yes, the encoding is the same.
All that is different is the accepted operand ordering...and yes, it is
very unfortunate the operand ordering is different between embedded and
server. :(
I was under the impression that the assembler made no instruction decisions
based on CPU. So your only hint would be that '0b' prefix.
Does AS even see that?
GAS definitely makes decisions based on CPU (ie, -mcpu option). Below is
the GAS code used in recognizing the dcbtst instruction. This shows that
the server operand ordering is enabled for POWER4 and later cpus while
the embedded operand ordering is enabled for pre POWER4 cpus (yes, not
exactly a server versus embedded trigger, but that's we agreed on to
mitigate breaking any old asm code out there).
{dcbtst,X(31,246), X_MASK, POWER4,PPCNONE,{RA0,
RB, CT}},
{dcbtst,X(31,246), X_MASK, PPC|PPCVLE, POWER4,{CT,
RA0, RB}},
GAS doesn't look at how the operands are written to try and guess what
operand ordering you are attempting to use. Rather, it knows what ordering
it expects and the values had better match that ordering.
I agree, but that means it is impossible for the same .S file can be compiled
but -mcpu=e500mc and -mcpu=powerpc?
So either these files have to be Book3S versus Book3E --or-- we use a CPP macro
to get them right.
FWIW, I prefer the latter which allows more code reuse.
-jx
Peter
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Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Dec 17, 2012, at 5:33 AM, Anton Blanchard an...@samba.org wrote: Hi Jimi, I know this is a little late, but shouldn't these power7 specific thingies be in obj-$(CONFIG_PPC_BOOK3S_64). The reason I ask is that my compiler pukes on dcbtst and as I deal with that I wanted to point this out. I guess we could do that. I think it is the right idea since it is unclear that your optimizations would actually help an embedded system where most of these cache prefetches are NOPs and only wait decode/dispatch cycles. It's a bit strange your assembler is complaining about the dcbtst instructions since we wrap them with power4: Not really, the binutils is a little old (RHEL 6.2), unfortunately it _is_ the toolchain most people are using at the moment. It will take me a while to get everyone using newer ones since most are scientists using the packages they get. My suggestion was really for correctness, My current patches for BG/Q introduce a macro replacement. -jx .machine push .machine power4 dcbtr0,r4,0b01000 dcbtr0,r7,0b01010 dcbtst r0,r9,0b01000 dcbtst r0,r10,0b01010 eieio dcbtr0,r8,0b01010 /* GO */ .machine pop Anton ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On Dec 17, 2012, at 6:26 PM, Peter Bergner berg...@vnet.ibm.com wrote: On Mon, 2012-12-17 at 22:33 +1100, Anton Blanchard wrote: Hi Jimi, I know this is a little late, but shouldn't these power7 specific thingies be in obj-$(CONFIG_PPC_BOOK3S_64). The reason I ask is that my compiler pukes on dcbtst and as I deal with that I wanted to point this out. I guess we could do that. It's a bit strange your assembler is complaining about the dcbtst instructions since we wrap them with power4: .machine push .machine power4 dcbtr0,r4,0b01000 dcbtr0,r7,0b01010 dcbtst r0,r9,0b01000 dcbtst r0,r10,0b01010 eieio dcbtr0,r8,0b01010 /* GO */ .machine pop Jimi, are you using an old binutils from before my patch that changed the operand order for these types of instructions? http://sourceware.org/ml/binutils/2009-02/msg00044.html Actually, this confused me as well, that embedded has the same instruction encoding but different mnemonic. I was under the impression that the assembler made no instruction decisions based on CPU. So your only hint would be that '0b' prefix. Does AS even see that? If not, then without a _normalizing_ macro, I think will need that obj-$(CONFIG_PPC_BOOK3S_64) and .S files with the two can never be shared. -jx Peter ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 7, 2012, at 8:31 AM, Andrew Tauferner atau...@us.ibm.com wrote: Jimi, Do you actually want this upstream? I assume no. I needed to get these long-term patches out there for the BGQ community for test. To which BGQ community are you referring? This work is being done by IBM Research (me) and made possible by the US-DOE via: https://sites.google.com/site/foxxstack/project-updates What is the motivation for this work? Maintain a modern kernel that has a reasonable set of patches that, with the much appreciated feedback from the Linux community, _could_ go upstream. I would very much like to get a version of these upstream. I expect only the QPX, kexec, and (maybe) the DCR changes to cause any controversy, but I've been wrong before. Hehe. Ben had a variety of issues with the BG/Q firmware when he gave me some feedback a few years ago. Yup, I think I have addressed these issues. I'll be making those patches soon and hope to get a lot of feedback from these patches. What was the starting point for this work? On what is it based? https://repo.anl-external.org/viewvc/bgq-driver/V1R1M2/?sortdir=down -jx -jx Mikey Here is a are the summary logs: $ git log --reverse linux-stable/linux-3.4.y.. commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2 Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 09:26:00 2012 -0600 powerpc: Fix cputable #ifdef where CONFIG_PPC_A2 is used for CONFIG_PPC_BOOK3E_64 Signed-off-by: Jimi Xenidis ji...@pobox.com commit ea51920d7035c8d23801d6de46261e7d0a537dfd Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 08:58:27 2012 -0600 powerpc/book3e: Remove config for PPC_A2_DD2 since there is no reference to it This must have been leftover from early DD1 days which is not present in any current kernel code. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 08151401a5db4ff0d441a1b7bf8ad92bd92b14c5 Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:38:01 2012 -0600 powerpc/dcr: Some native DCR fixes The following fixes have been made: - dcr_read/write_native() must use the indexed version of the m[ft]dcrx since the non-indexed version only allows a 10-bit numerical space, but the C interface allows a full 32-bits. - C bindings for m[ft]dcrx, and the table versions, should use unsigned long so that they are 64/32 bit neutral. - The table versions (__m[ft]cdr) should obtain the table address with LOAD_REG_ADDR(), this will also make it 64/32bit neutral. Signed-off-by: Jimi Xenidis ji...@pobox.com commit c8320a5daaceed03992d763302020834ea8e17dd Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:12:00 2012 -0600 powerpc/dcr: Add 64-bit DCR access methods. This patch adds the ability to make 64-bit Device Control Register (DCR) accesses. Signed-off-by: Jimi Xenidis ji...@pobox.com commit a763b3f8453b3bd83d7dded8c6644939863af430 Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 12:49:24 2012 -0500 powerpc/boot: Add a spin_threads hook to platform_ops It is useful for the boot program to arrange for all secondary cpus and threads to enter the kernel in a kexec fashion. This hook makes it possible. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 391e43393380b514d4d02a42d059619542c7597b Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 13:01:23 2012 -0500 powerpc/kexec: Add kexec hold support for Book3e processors This patch add two items: 1) Book3e requires that GPR4 survive the hold process, so we make sure that happens. 2) Book3e has no real mode, and the hold code exploits this. Since these processors ares always translated, we arrange for the kexeced threads to enter the hold code using the normal kernel linear mapping. Signed-off-by: Jimi Xenidis ji...@pobox.com commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:41:25 2012 -0500 powerpc: Remove unecessary VSX symbols The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its presence causes build issues with more complex configurations. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 4e817bb42ec8e3d3689877528dd97c4286a870eb Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:10:52 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the rfdi instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 2071aa58b2f3b33d97c94e3a127f7c5d4ffaeb34 Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:14:22 2012 -0600 Blue Gene/Q wicked optimizing
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 10, 2012, at 3:32 PM, Jimi Xenidis ji...@pobox.com wrote: On Dec 7, 2012, at 8:31 AM, Andrew Tauferner atau...@us.ibm.com wrote: Jimi, Do you actually want this upstream? I assume no. I needed to get these long-term patches out there for the BGQ community for test. To which BGQ community are you referring? This work is being done by IBM Research (me) and made possible by the US-DOE via: https://sites.google.com/site/foxxstack/project-updates What is the motivation for this work? Maintain a modern kernel that has a reasonable set of patches that, with the much appreciated feedback from the Linux community, _could_ go upstream. I would very much like to get a version of these upstream. I expect only the QPX, kexec, and (maybe) the DCR changes to cause any controversy, but I've been wrong before. Hehe. Ben had a variety of issues with the BG/Q firmware when he gave me some feedback a few years ago. Yup, I think I have addressed these issues. I'll be making those patches soon and hope to get a lot of feedback from these patches. What was the starting point for this work? On what is it based? https://repo.anl-external.org/viewvc/bgq-driver/V1R1M2/?sortdir=down I should add that these patches have been heavily modified to meet requirements and suggestions of BenH and others. -jx -jx -jx Mikey Here is a are the summary logs: $ git log --reverse linux-stable/linux-3.4.y.. commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2 Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 09:26:00 2012 -0600 powerpc: Fix cputable #ifdef where CONFIG_PPC_A2 is used for CONFIG_PPC_BOOK3E_64 Signed-off-by: Jimi Xenidis ji...@pobox.com commit ea51920d7035c8d23801d6de46261e7d0a537dfd Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 08:58:27 2012 -0600 powerpc/book3e: Remove config for PPC_A2_DD2 since there is no reference to it This must have been leftover from early DD1 days which is not present in any current kernel code. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 08151401a5db4ff0d441a1b7bf8ad92bd92b14c5 Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:38:01 2012 -0600 powerpc/dcr: Some native DCR fixes The following fixes have been made: - dcr_read/write_native() must use the indexed version of the m[ft]dcrx since the non-indexed version only allows a 10-bit numerical space, but the C interface allows a full 32-bits. - C bindings for m[ft]dcrx, and the table versions, should use unsigned long so that they are 64/32 bit neutral. - The table versions (__m[ft]cdr) should obtain the table address with LOAD_REG_ADDR(), this will also make it 64/32bit neutral. Signed-off-by: Jimi Xenidis ji...@pobox.com commit c8320a5daaceed03992d763302020834ea8e17dd Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:12:00 2012 -0600 powerpc/dcr: Add 64-bit DCR access methods. This patch adds the ability to make 64-bit Device Control Register (DCR) accesses. Signed-off-by: Jimi Xenidis ji...@pobox.com commit a763b3f8453b3bd83d7dded8c6644939863af430 Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 12:49:24 2012 -0500 powerpc/boot: Add a spin_threads hook to platform_ops It is useful for the boot program to arrange for all secondary cpus and threads to enter the kernel in a kexec fashion. This hook makes it possible. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 391e43393380b514d4d02a42d059619542c7597b Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 13:01:23 2012 -0500 powerpc/kexec: Add kexec hold support for Book3e processors This patch add two items: 1) Book3e requires that GPR4 survive the hold process, so we make sure that happens. 2) Book3e has no real mode, and the hold code exploits this. Since these processors ares always translated, we arrange for the kexeced threads to enter the hold code using the normal kernel linear mapping. Signed-off-by: Jimi Xenidis ji...@pobox.com commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:41:25 2012 -0500 powerpc: Remove unecessary VSX symbols The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its presence causes build issues with more complex configurations. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 4e817bb42ec8e3d3689877528dd97c4286a870eb Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:10:52 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the rfdi instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 2071aa58b2f3b33d97c94e3a127f7c5d4ffaeb34 Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:14:22 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the mfdcrx instruction yet
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 9, 2012, at 6:47 PM, Michael Neuling mi...@neuling.org wrote: Jimi Xenidis ji...@pobox.com wrote: On Dec 7, 2012, at 7:38 AM, Jimi Xenidis ji...@pobox.com wrote: On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote: commit 279c0615917b959a652e81f4ad0d886e2d426d85 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:43:22 2012 -0500 powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX) This enables kernel support for the QPX extention and is intended for processors that support it, usually an IBM Blue Gene processor. Turning it on does not effect other processors but it does add code and will quadruple the per thread save and restore area for the FPU (hense the name). If you have enabled VSX it will only double the space. Signed-off-by: Jimi Xenidis ji...@pobox.com snip +BEGIN_FTR_SECTION\ +SAVE_32VSRS(n,c,base);\ +END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ +BEGIN_FTR_SECTION\ +SAVE_32QRS(n,c,base);\ +END_FTR_SECTION_IFSET(CPU_FTR_QPX); I don't think we want to do this. We are going to end up with 64 NOPS here somewhere. Excellent point, NOPs are cheap on most processors but not A2 and a lot of embedded, I can wrap some branches with the FTR instead. Do you have a concern on the code size? Thought about it a bit and came up with this solution for arch/powerpc/kernel/fpu.S. This should address the following issues - MSR_VSX vs MSR_VEC - Big chunks of NOPs in the code path - Less FTR space fixups at boot time. - IMNHSO easier to read especially when disassembled Indeed, I think it looks better. I was going to mention that it was already pretty complex to read, so a rewrite like this was probably needed. So thanks!! That being said, there is a pretty complex testing matrix of CONFIG_VSX/VMX/FPU/QPX/SMP/64/32 CPU_FTR/VSX/FPU/QPX/VMX so I'd need to look/test more carefully to make sure all of these are covered. Also, transactional memory (see http://lists.ozlabs.org/pipermail/linuxppc-dev/2012-November/102216.html) will change this code. You should rebase on top of that if you really want it considered for upstream. Is this in a git tree anywhere? perhaps BenH's next branch? -jx Mikey I did consider using the LR and BLR, but the !CONFIG_SMP case only adds one more special block and uses a different register set. Also if this is agreeable I would like us to consider removing the *_32FPVSRS* macros entirely and put the FTR tests in the actual code. This would allow us to use #ifdefs and reduce the amount of code that actually gets compiled. Thoughts? diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index e0ada05..5964067 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -25,30 +25,81 @@ #include asm/asm-offsets.h #include asm/ptrace.h -#ifdef CONFIG_VSX -#define __REST_32FPVSRS(n,c,base)\ -BEGIN_FTR_SECTION\ -b2f;\ -END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ -REST_32FPRS(n,base);\ -b3f;\ -2:REST_32VSRS(n,c,base);\ -3: - -#define __SAVE_32FPVSRS(n,c,base)\ -BEGIN_FTR_SECTION\ -b2f;\ -END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ -SAVE_32FPRS(n,base);\ -b3f;\ -2:SAVE_32VSRS(n,c,base);\ -3: -#else -#define __REST_32FPVSRS(n,b,base)REST_32FPRS(n, base) -#define __SAVE_32FPVSRS(n,b,base)SAVE_32FPRS(n, base) -#endif -#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) -#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) + +/* + * Restore subroutines, R4 is scratch and R5 is base + */ +vsx_restore: +REST_32VSRS(0, __REG_R4, __REG_R5) +b after_restore +qpx_restore: +REST_32QRS(0, __REG_R4, __REG_R5) +b after_restore +fpu_restore: +REST_32FPRS(0, __REG_R5) +b after_restore + +#define REST_32FPVSRS(n, c, base)\ +BEGIN_FTR_SECTION\ +b vsx_restore;\ +END_FTR_SECTION_IFSET(CPU_FTR_VSX)\ +BEGIN_FTR_SECTION\ +b qpx_restore;\ +END_FTR_SECTION_IFSET(CPU_FTR_QPX)\ +b fpu_restore;\ +after_restore: + +/* + * Save subroutines, R4 is scratch and R3 is base + */ +vsx_save: +SAVE_32VSRS(0, __REG_R4, __REG_R3) +b after_save +qpx_save: +SAVE_32QRS(0, __REG_R4, __REG_R3) +b after_save +fpu_save: +SAVE_32FPRS(0, __REG_R3) +b after_save + +#define SAVE_32FPVSRS(n, c
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 7, 2012, at 7:38 AM, Jimi Xenidis ji...@pobox.com wrote: On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote: commit 279c0615917b959a652e81f4ad0d886e2d426d85 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:43:22 2012 -0500 powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX) This enables kernel support for the QPX extention and is intended for processors that support it, usually an IBM Blue Gene processor. Turning it on does not effect other processors but it does add code and will quadruple the per thread save and restore area for the FPU (hense the name). If you have enabled VSX it will only double the space. Signed-off-by: Jimi Xenidis ji...@pobox.com snip +BEGIN_FTR_SECTION \ +SAVE_32VSRS(n,c,base); \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ +BEGIN_FTR_SECTION \ +SAVE_32QRS(n,c,base); \ +END_FTR_SECTION_IFSET(CPU_FTR_QPX); I don't think we want to do this. We are going to end up with 64 NOPS here somewhere. Excellent point, NOPs are cheap on most processors but not A2 and a lot of embedded, I can wrap some branches with the FTR instead. Do you have a concern on the code size? Thought about it a bit and came up with this solution for arch/powerpc/kernel/fpu.S. This should address the following issues - MSR_VSX vs MSR_VEC - Big chunks of NOPs in the code path - Less FTR space fixups at boot time. - IMNHSO easier to read especially when disassembled I did consider using the LR and BLR, but the !CONFIG_SMP case only adds one more special block and uses a different register set. Also if this is agreeable I would like us to consider removing the *_32FPVSRS* macros entirely and put the FTR tests in the actual code. This would allow us to use #ifdefs and reduce the amount of code that actually gets compiled. Thoughts? diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index e0ada05..5964067 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -25,30 +25,81 @@ #include asm/asm-offsets.h #include asm/ptrace.h -#ifdef CONFIG_VSX -#define __REST_32FPVSRS(n,c,base) \ -BEGIN_FTR_SECTION \ - b 2f; \ -END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ - REST_32FPRS(n,base);\ - b 3f; \ -2: REST_32VSRS(n,c,base); \ -3: - -#define __SAVE_32FPVSRS(n,c,base) \ -BEGIN_FTR_SECTION \ - b 2f; \ -END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ - SAVE_32FPRS(n,base);\ - b 3f; \ -2: SAVE_32VSRS(n,c,base); \ -3: -#else -#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) -#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) -#endif -#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) -#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) + +/* + * Restore subroutines, R4 is scratch and R5 is base + */ +vsx_restore: + REST_32VSRS(0, __REG_R4, __REG_R5) + b after_restore +qpx_restore: + REST_32QRS(0, __REG_R4, __REG_R5) + b after_restore +fpu_restore: + REST_32FPRS(0, __REG_R5) + b after_restore + +#define REST_32FPVSRS(n, c, base) \ +BEGIN_FTR_SECTION \ + b vsx_restore; \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX) \ +BEGIN_FTR_SECTION \ + b qpx_restore; \ +END_FTR_SECTION_IFSET(CPU_FTR_QPX) \ + b fpu_restore; \ +after_restore: + +/* + * Save subroutines, R4 is scratch and R3 is base + */ +vsx_save: + SAVE_32VSRS(0, __REG_R4, __REG_R3) + b after_save +qpx_save: + SAVE_32QRS(0, __REG_R4, __REG_R3) + b after_save +fpu_save: + SAVE_32FPRS(0, __REG_R3) + b after_save + +#define SAVE_32FPVSRS(n, c, base) \ +BEGIN_FTR_SECTION \ + b vsx_save; \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX) \ +BEGIN_FTR_SECTION \ + b qpx_save; \ +END_FTR_SECTION_IFSET
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 6, 2012, at 11:41 PM, Michael Neuling mi...@neuling.org wrote: commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:41:25 2012 -0500 powerpc: Remove unecessary VSX symbols The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its presence causes build issues with more complex configurations. Signed-off-by: Jimi Xenidis ji...@pobox.com Can you explain what these complex configurations are? In an earlier email we discussed the possibility that there was the possibility/desire that a single binary could support either FPU, VSX and the new QPX. However, if a CONFIG_VSX is not defined then THREAD_VSR0 does not get defined even though there might be some code that refers to it. Since it is an alias for the same piece of storage I was hoping to solve my config issue and be simplify the code. -jx Mikey ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 6, 2012, at 11:54 PM, Michael Neuling mi...@neuling.org wrote: commit 279c0615917b959a652e81f4ad0d886e2d426d85 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:43:22 2012 -0500 powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX) This enables kernel support for the QPX extention and is intended for processors that support it, usually an IBM Blue Gene processor. Turning it on does not effect other processors but it does add code and will quadruple the per thread save and restore area for the FPU (hense the name). If you have enabled VSX it will only double the space. Signed-off-by: Jimi Xenidis ji...@pobox.com Can you give a diagram of how the QPX registers are layed out. +#if defined(CONFIG_PPC_QPX) +#define TS_FPRWIDTH 4 +#elif defined(CONFIG_VSX) Are they 256 bits wide? Yes, this is why we nicknamed it the Quad Hummer :) - 4-wide double precision FPU SIMD - 2-wide complex SIMD - 4R/2W register file (32x256 bits per thread) - 32B (256 bits) datapath to/from L1 cache +#define QVLFDXA(QRT,RA,RB) \ + .long (0x7c00048f | ((QRT) 21) | ((RA) 16) | ((RB) 11)) Put this in ppc-opcode.h. +#if defined(CONFIG_VSX) || defined(CONFIG_PPC_QPX) + /* they are the same MSR bit */ OMG! Ooops, you are correct, this was in the original patch. I'll double check the work book, but it should be the architected VEC/SPV bit which is really for VMX. I'll track it down. +BEGIN_FTR_SECTION\ + SAVE_32VSRS(n,c,base); \ +END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ +BEGIN_FTR_SECTION\ + SAVE_32QRS(n,c,base); \ +END_FTR_SECTION_IFSET(CPU_FTR_QPX); I don't think we want to do this. We are going to end up with 64 NOPS here somewhere. Excellent point, NOPs are cheap on most processors but not A2 and a lot of embedded, I can wrap some branches with the FTR instead. Do you have a concern on the code size? I'd like to see this patch broken into different parts. I'm not sure how _this_ patch: https://github.com/jimix/linux-bgq/commit/279c0615917b959a652e81f4ad0d886e2d426d85 could be broken up, please advise. Also, have you boot tested this change on a VSX enabled box? I can try, I may bug you for help. Is there a commonly test (or apps) I should run? -jx Mikey ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] Add IBM Blue Gene/Q Platform
On Dec 6, 2012, at 11:56 PM, Michael Neuling mi...@neuling.org wrote: Jimi Xenidis ji...@pobox.com wrote: Rather than flood the mailing list with the patches, I've arranged for a git repo to hold the changesets. You can find the repo here: https://github.com/jimix/linux-bgq They are against GregKH's linux-stable.git long-term 3.4.y (y=22) branch. The first 9 (6e58088f..) effect common code and the rest are BGQ specific. Do you actually want this upstream? I assume no. I needed to get these long-term patches out there for the BGQ community for test. I would very much like to get a version of these upstream. I expect only the QPX, kexec, and (maybe) the DCR changes to cause any controversy, but I've been wrong before. I'll be making those patches soon and hope to get a lot of feedback from these patches. -jx Mikey Here is a are the summary logs: $ git log --reverse linux-stable/linux-3.4.y.. commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2 Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 09:26:00 2012 -0600 powerpc: Fix cputable #ifdef where CONFIG_PPC_A2 is used for CONFIG_PPC_BOOK3E_64 Signed-off-by: Jimi Xenidis ji...@pobox.com commit ea51920d7035c8d23801d6de46261e7d0a537dfd Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 08:58:27 2012 -0600 powerpc/book3e: Remove config for PPC_A2_DD2 since there is no reference to it This must have been leftover from early DD1 days which is not present in any current kernel code. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 08151401a5db4ff0d441a1b7bf8ad92bd92b14c5 Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:38:01 2012 -0600 powerpc/dcr: Some native DCR fixes The following fixes have been made: - dcr_read/write_native() must use the indexed version of the m[ft]dcrx since the non-indexed version only allows a 10-bit numerical space, but the C interface allows a full 32-bits. - C bindings for m[ft]dcrx, and the table versions, should use unsigned long so that they are 64/32 bit neutral. - The table versions (__m[ft]cdr) should obtain the table address with LOAD_REG_ADDR(), this will also make it 64/32bit neutral. Signed-off-by: Jimi Xenidis ji...@pobox.com commit c8320a5daaceed03992d763302020834ea8e17dd Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:12:00 2012 -0600 powerpc/dcr: Add 64-bit DCR access methods. This patch adds the ability to make 64-bit Device Control Register (DCR) accesses. Signed-off-by: Jimi Xenidis ji...@pobox.com commit a763b3f8453b3bd83d7dded8c6644939863af430 Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 12:49:24 2012 -0500 powerpc/boot: Add a spin_threads hook to platform_ops It is useful for the boot program to arrange for all secondary cpus and threads to enter the kernel in a kexec fashion. This hook makes it possible. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 391e43393380b514d4d02a42d059619542c7597b Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 13:01:23 2012 -0500 powerpc/kexec: Add kexec hold support for Book3e processors This patch add two items: 1) Book3e requires that GPR4 survive the hold process, so we make sure that happens. 2) Book3e has no real mode, and the hold code exploits this. Since these processors ares always translated, we arrange for the kexeced threads to enter the hold code using the normal kernel linear mapping. Signed-off-by: Jimi Xenidis ji...@pobox.com commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:41:25 2012 -0500 powerpc: Remove unecessary VSX symbols The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its presence causes build issues with more complex configurations. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 4e817bb42ec8e3d3689877528dd97c4286a870eb Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:10:52 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the rfdi instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 2071aa58b2f3b33d97c94e3a127f7c5d4ffaeb34 Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:14:22 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the mfdcrx instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 6e58088fabedbb2d724637b539ba180c03ed8b68 Author: Jimi Xenidis ji...@pobox.com Date: Wed Oct 31 16:33:21 2012 -0500 powerpc/book3e: IBM Blue Gene/Q Boot This patch specifically deals with the initial program load environment so that a boot image (dtbImage.bgq) can be loaded by the BGQ management tools. The boot code is a little odd because it has to deal with the following issues: - Linux boot image wrappers are 32-bit
Re: [PATCH] powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
On May 31, 2012, at 1:22 AM, Anton Blanchard an...@samba.org wrote: Implement a POWER7 optimised memcpy using VMX and enhanced prefetch instructions. snip Index: linux-build/arch/powerpc/lib/Makefile === --- linux-build.orig/arch/powerpc/lib/Makefile2012-05-30 15:27:30.0 +1000 +++ linux-build/arch/powerpc/lib/Makefile 2012-05-31 09:12:27.574372864 +1000 @@ -17,7 +17,8 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \ memcpy_64.o usercopy_64.o mem_64.o string.o \ checksum_wrappers_64.o hweight_64.o \ -copyuser_power7.o string_64.o copypage_power7.o +copyuser_power7.o string_64.o copypage_power7.o \ +memcpy_power7.o Hi, I know this is a little late, but shouldn't these power7 specific thingies be in obj-$(CONFIG_PPC_BOOK3S_64). The reason I ask is that my compiler pukes on dcbtst and as I deal with that I wanted to point this out. -jx obj-$(CONFIG_XMON)+= sstep.o ldstfp.o obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o Index: linux-build/arch/powerpc/lib/memcpy_64.S === --- linux-build.orig/arch/powerpc/lib/memcpy_64.S 2012-05-30 09:39:59.0 +1000 +++ linux-build/arch/powerpc/lib/memcpy_64.S 2012-05-31 09:12:00.093876936 +1000 @@ -11,7 +11,11 @@ .align 7 _GLOBAL(memcpy) +BEGIN_FTR_SECTION std r3,48(r1) /* save destination pointer for return value */ +FTR_SECTION_ELSE + b memcpy_power7 +ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY) PPC_MTOCRF(0x01,r5) cmpldi cr1,r5,16 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry Index: linux-build/arch/powerpc/lib/memcpy_power7.S === --- /dev/null 1970-01-01 00:00:00.0 + +++ linux-build/arch/powerpc/lib/memcpy_power7.S 2012-05-31 15:28:03.495781127 +1000 @@ -0,0 +1,650 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) IBM Corporation, 2012 + * + * Author: Anton Blanchard an...@au.ibm.com + */ +#include asm/ppc_asm.h + +#define STACKFRAMESIZE 256 +#define STK_REG(i) (112 + ((i)-14)*8) + +_GLOBAL(memcpy_power7) +#ifdef CONFIG_ALTIVEC + cmpldi r5,16 + cmpldi cr1,r5,4096 + + std r3,48(r1) + + blt .Lshort_copy + bgt cr1,.Lvmx_copy +#else + cmpldi r5,16 + + std r3,48(r1) + + blt .Lshort_copy +#endif + +.Lnonvmx_copy: + /* Get the source 8B aligned */ + neg r6,r4 + mtocrf 0x01,r6 + clrldi r6,r6,(64-3) + + bf cr7*4+3,1f + lbz r0,0(r4) + addir4,r4,1 + stb r0,0(r3) + addir3,r3,1 + +1: bf cr7*4+2,2f + lhz r0,0(r4) + addir4,r4,2 + sth r0,0(r3) + addir3,r3,2 + +2: bf cr7*4+1,3f + lwz r0,0(r4) + addir4,r4,4 + stw r0,0(r3) + addir3,r3,4 + +3: sub r5,r5,r6 + cmpldi r5,128 + blt 5f + + mflrr0 + stdur1,-STACKFRAMESIZE(r1) + std r14,STK_REG(r14)(r1) + std r15,STK_REG(r15)(r1) + std r16,STK_REG(r16)(r1) + std r17,STK_REG(r17)(r1) + std r18,STK_REG(r18)(r1) + std r19,STK_REG(r19)(r1) + std r20,STK_REG(r20)(r1) + std r21,STK_REG(r21)(r1) + std r22,STK_REG(r22)(r1) + std r0,STACKFRAMESIZE+16(r1) + + srdir6,r5,7 + mtctr r6 + + /* Now do cacheline (128B) sized loads and stores. */ + .align 5 +4: + ld r0,0(r4) + ld r6,8(r4) + ld r7,16(r4) + ld r8,24(r4) + ld r9,32(r4) + ld r10,40(r4) + ld r11,48(r4) + ld r12,56(r4) + ld r14,64(r4) + ld r15,72(r4) + ld r16,80(r4) + ld r17,88(r4) + ld r18,96(r4) + ld r19,104(r4) + ld r20,112(r4) + ld
[RFC] Add IBM Blue Gene/Q Platform
Rather than flood the mailing list with the patches, I've arranged for a git repo to hold the changesets. You can find the repo here: https://github.com/jimix/linux-bgq They are against GregKH's linux-stable.git long-term 3.4.y (y=22) branch. The first 9 (6e58088f..) effect common code and the rest are BGQ specific. Here is a are the summary logs: $ git log --reverse linux-stable/linux-3.4.y.. commit 5a8edb2bdd914597693eed299119ff4c2e6d31f2 Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 09:26:00 2012 -0600 powerpc: Fix cputable #ifdef where CONFIG_PPC_A2 is used for CONFIG_PPC_BOOK3E_64 Signed-off-by: Jimi Xenidis ji...@pobox.com commit ea51920d7035c8d23801d6de46261e7d0a537dfd Author: Jimi Xenidis ji...@pobox.com Date: Fri Nov 9 08:58:27 2012 -0600 powerpc/book3e: Remove config for PPC_A2_DD2 since there is no reference to it This must have been leftover from early DD1 days which is not present in any current kernel code. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 08151401a5db4ff0d441a1b7bf8ad92bd92b14c5 Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:38:01 2012 -0600 powerpc/dcr: Some native DCR fixes The following fixes have been made: - dcr_read/write_native() must use the indexed version of the m[ft]dcrx since the non-indexed version only allows a 10-bit numerical space, but the C interface allows a full 32-bits. - C bindings for m[ft]dcrx, and the table versions, should use unsigned long so that they are 64/32 bit neutral. - The table versions (__m[ft]cdr) should obtain the table address with LOAD_REG_ADDR(), this will also make it 64/32bit neutral. Signed-off-by: Jimi Xenidis ji...@pobox.com commit c8320a5daaceed03992d763302020834ea8e17dd Author: Jimi Xenidis ji...@pobox.com Date: Mon Nov 5 09:12:00 2012 -0600 powerpc/dcr: Add 64-bit DCR access methods. This patch adds the ability to make 64-bit Device Control Register (DCR) accesses. Signed-off-by: Jimi Xenidis ji...@pobox.com commit a763b3f8453b3bd83d7dded8c6644939863af430 Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 12:49:24 2012 -0500 powerpc/boot: Add a spin_threads hook to platform_ops It is useful for the boot program to arrange for all secondary cpus and threads to enter the kernel in a kexec fashion. This hook makes it possible. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 391e43393380b514d4d02a42d059619542c7597b Author: Jimi Xenidis ji...@pobox.com Date: Thu Nov 29 13:01:23 2012 -0500 powerpc/kexec: Add kexec hold support for Book3e processors This patch add two items: 1) Book3e requires that GPR4 survive the hold process, so we make sure that happens. 2) Book3e has no real mode, and the hold code exploits this. Since these processors ares always translated, we arrange for the kexeced threads to enter the hold code using the normal kernel linear mapping. Signed-off-by: Jimi Xenidis ji...@pobox.com commit f6e3c1f706cb6922349d639a74ff6c50acc8b9f8 Author: Jimi Xenidis ji...@pobox.com Date: Wed Dec 5 13:41:25 2012 -0500 powerpc: Remove unecessary VSX symbols The symbol THREAD_VSR0 is defined to be the same as THREAD_FPR0. Its presence causes build issues with more complex configurations. Signed-off-by: Jimi Xenidis ji...@pobox.com commit 4e817bb42ec8e3d3689877528dd97c4286a870eb Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:10:52 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the rfdi instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 2071aa58b2f3b33d97c94e3a127f7c5d4ffaeb34 Author: Jimi Xenidis ji...@pobox.com Date: Tue Nov 20 10:14:22 2012 -0600 Blue Gene/Q wicked optimizing compiler does not know the mfdcrx instruction yet Signed-off-by: Jimi Xenidis ji...@pobox.com commit 6e58088fabedbb2d724637b539ba180c03ed8b68 Author: Jimi Xenidis ji...@pobox.com Date: Wed Oct 31 16:33:21 2012 -0500 powerpc/book3e: IBM Blue Gene/Q Boot This patch specifically deals with the initial program load environment so that a boot image (dtbImage.bgq) can be loaded by the BGQ management tools. The boot code is a little odd because it has to deal with the following issues: - Linux boot image wrappers are 32-bit programs - BGQ Tools only load 64bit ELF programs - BGQ Firmware information is typically loaded at an address 4G - BGQ FW information contains 64-bit ABI function pointers (which are actually function descriptors) to access firmware methods - BGQ FW methods must be called in 64-bit mode Includes code contributed from: Andrew Tauferner atau...@us.ibm.com Todd Inglett tingl...@us.ibm.com Eric Van Hensbergen eri...@gmail.com Signed-off-by: Jimi Xenidis ji...@pobox.com commit
Re: Hijacking CPU_FTR_VSX for BGQ QPX
Sorry for the pause, lots of other things getting done... questions below. On Nov 9, 2012, at 10:33 PM, Michael Neuling mi...@neuling.org wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote: The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and restore the QPX registers. There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by the FPSCR and MSR[FP] I was thinking that I could hijack the VSX, since there is no plan to add it to embedded yet. I could be explicit or create an alieas fo the same bit, but the basic effect (after increasing the save area size) would be something like the diff below. Thoughts? Don't. Use a different bit, we can always split the mask again if needed, move more bits to mmu_features etc... Ok -#ifdef CONFIG_VSX +#if defined (CONFIG_VSX) defined(CONFIG_BGQ) +# error This code depends on CONFIG_VSX and CONFIG_BGQ being exclusive +#elif defined (CONFIG_VSX) +# define _REST_32VSRS(n,c,base) REST_32VSRS(n,c,base) +# define _SAVE_32VSRS(n,c,base) SAVE_32VSRS(n,c,base) +#elif defined(CONFIG_BGQ) Make a CONFIG_PPC_QPX or something like that specifically for the QPX stuff that you can then select from CONFIG_PPC_BGQ (don't do just CONFIG_BGQ). ack And don't just hijack stuff like that, it should be a runtime option, so add a new set etc... it should be possible to build a kernel that boots on a BGQ or a hypothetical BookE chip with VSX. ack Yeah both bluegene and VSX are designed for HPC, so it's not completely crazy that someone would put them together. Not sure that is possible, since they both include FPU state, which is why hijacking the the FPU routines is so delicious. -jx Also, we need to fix the CPU FTR issue. With PPR (Haren's stuff) and POWER8 we are going to blow CPU FTRs pretty soon anyway. This just adds to that. Mikey +# define _REST_32VSRS(n,c,base) REST_32QRS(n,c,base) +# define _SAVE_32VSRS(n,c,base) SAVE_32QRS(n,c,base) +#endif + +#if defined (CONFIG_VSX) || defined(CONFIG_BGQ) #define REST_32FPVSRS(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ REST_32FPRS(n,base);\ b 3f; \ -2: REST_32VSRS(n,c,base); \ +2: _REST_32VSRS(n,c,base); \ 3: #define SAVE_32FPVSRS(n,c,base) \ @@ -41,7 +51,7 @@ BEGIN_FTR_SECTION \ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ SAVE_32FPRS(n,base);\ b 3f; \ -2: SAVE_32VSRS(n,c,base); \ +2: _SAVE_32VSRS(n,c,base); \ 3: #else #define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC PATCH] powerpc/kexec: Add kexec hold support for Book3e processors
Motivation: IBM Blue Gene/Q comes with some very strange firmware that I'm trying to get out of using in the kernel. So instead I spin all the threads in the boot wrapper (using the firmware) and have them enter the kexec stub, pre-translated at the virtual linear address, never touching firmware again. This works strategy works wonderfully, but I need the following patch in the kexec stub. I believe it should not effect Book3S and Book3E does not appear to be here yet so I'd love to get any criticisms up front. This patch adds two items: 1) Book3e requires that GPR4 survive the hold process, so we make sure that happens. 2) Book3e has no real mode, and the hold code exploits this. Since these processors ares always translated, we arrange for the kexeced threads to enter the hold code using the normal kernel linear mapping. Signed-off-by: Jimi Xenidis ji...@pobox.com --- arch/powerpc/kernel/head_64.S | 19 ++- 1 files changed, 18 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 58bddee..1b00e95 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -122,6 +122,8 @@ __secondary_hold: #endif /* Grab our physical cpu number */ mr r24,r3 + /* stash r4 for book3e */ + mr r25,r4 /* Tell the master cpu we're here */ /* Relocation is off we are located at an address less */ @@ -129,16 +131,31 @@ __secondary_hold: std r24,__secondary_hold_acknowledge-_stext(0) sync + li r26,0 +#ifdef CONFIG_PPC_BOOK3E + tovirt(r26,r26) +#endif /* All secondary cpus wait here until told to start. */ -100: ld r4,__secondary_hold_spinloop-_stext(0) +100: ld r4,__secondary_hold_spinloop-_stext(r26) cmpdi 0,r4,0 beq 100b #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) +#ifdef CONFIG_PPC_BOOK3E + tovirt(r4,r4) +#endif ld r4,0(r4)/* deref function descriptor */ mtctr r4 mr r3,r24 + /* +* it may be the case that other platforms have r4 right to +* begin with, this gives us some safety in case it is not +*/ +#ifdef CONFIG_PPC_BOOK3E + mr r4,r25 +#else li r4,0 +#endif /* Make sure that patched code is visible */ isync bctr -- 1.7.1 freakazoid:bgq ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
hoo boy, interrupt Handling on BGQ
So interrupts need to go to FW before Linux, please let not talk about how silly that is. Lets talk about something far more silly... In order to get to the Linux exception handlers, we have to tell FW where the interrupt page is, and then it _copies_ it. IFAICT, this means that each vectors on the copied page must: 1) construct an 64-bit absolute address to a per vector stub 2) leap at the (with bctr or blr) 3) restore CTR or LR and anything else that (1) messed up 4) normal branch to the actual vector This is what I'll be working on, but I'd love to hear any other ideas. -jx ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Hijacking CPU_FTR_VSX for BGQ QPX
The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and restore the QPX registers. There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by the FPSCR and MSR[FP] I was thinking that I could hijack the VSX, since there is no plan to add it to embedded yet. I could be explicit or create an alieas fo the same bit, but the basic effect (after increasing the save area size) would be something like the diff below. Thoughts? -jx diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index de36955..adb08af 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -25,14 +25,24 @@ #include asm/asm-offsets.h #include asm/ptrace.h -#ifdef CONFIG_VSX +#if defined (CONFIG_VSX) defined(CONFIG_BGQ) +# error This code depends on CONFIG_VSX and CONFIG_BGQ being exclusive +#elif defined (CONFIG_VSX) +# define _REST_32VSRS(n,c,base) REST_32VSRS(n,c,base) +# define _SAVE_32VSRS(n,c,base) SAVE_32VSRS(n,c,base) +#elif defined(CONFIG_BGQ) +# define _REST_32VSRS(n,c,base) REST_32QRS(n,c,base) +# define _SAVE_32VSRS(n,c,base) SAVE_32QRS(n,c,base) +#endif + +#if defined (CONFIG_VSX) || defined(CONFIG_BGQ) #define REST_32FPVSRS(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ REST_32FPRS(n,base);\ b 3f; \ -2: REST_32VSRS(n,c,base); \ +2: _REST_32VSRS(n,c,base); \ 3: #define SAVE_32FPVSRS(n,c,base) \ @@ -41,7 +51,7 @@ BEGIN_FTR_SECTION \ END_FTR_SECTION_IFSET(CPU_FTR_VSX);\ SAVE_32FPRS(n,base);\ b 3f; \ -2: SAVE_32VSRS(n,c,base); \ +2: _SAVE_32VSRS(n,c,base); \ 3: #else #define REST_32FPVSRS(n,b,base)REST_32FPRS(n, base) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: RFC: book3e: DCR MMIO for IBM Blue Gene/Q
On Nov 4, 2012, at 9:23 PM, Jimi Xenidis wrote:
On Nov 4, 2012, at 5:51 PM, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Sun, 2012-11-04 at 10:32 -0600, Jimi Xenidis wrote:
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple
of questions:
1) anyone have a good devtree binding for this?
Not really, I think the cell stuff was the last we looked at this.
I'm thinking:
bgq {
#address-cells = 2;
#size-cells = 2;
...
dcr {
reg = 0x3ff 0xe000 0x0 0x0800;
compatible = ibm,bgq-dcr;
dcr-controller;
dcr-access-method = mmio;
dcr-mmio-stride = ??;
};
};
I'm not sure what stride I will use since I have yet to figure out the DCR
numbering in play at the moment, which will be painful.
Also, some clarity to the following would be nice:
/* Stride is not properly defined yet, default to 0x10 for Axon */
p = of_get_property(dp, dcr-mmio-stride, NULL);
stride = (p == NULL) ? 0x10 : *p;
/* XXX FIXME: Which property name is to use of the 2 following ? */
p = of_get_property(dp, dcr-mmio-range, NULL);
if (p == NULL)
p = of_get_property(dp, dcr-mmio-space, NULL);
if (p == NULL)
goto done;
Not sure what SLOF did back then. dcr-mmio-range sounds better to me.
I guess my reg property is not useful to the code?
Right, unless the DCR bridge has some registers of its own. It's also
handy to have as a standard way of representing the memory used by the
DCR bridge, tho that does mean duplication... but then it allows you to
have a nice unit address.
umm, was there a conclusion here? :-)
-jx
Is there a preference over dcr-mmio-range/space or in the absence of these
to we should use reg?
2) I need 64 bit reads and writes
My intention is to have dcr_{read,write}_generic_{mmio,native} take an
unsigned long for value all the way down.
For the native case, this would make is similar to mtspr and mfspr.
For the MMIO case, the selected in/out size would be based on #ifdef
__powerpc64__
As long as it doesn't break Axon...
So Axon, being 64-bit, would break with the changes proposed, since it is
64-bit bit and assumes 32bit accessors.
I'll simply add 64bit accessors for now.
-jx
Cheers,
Ben.
Thoughts?
-jx
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RFC: book3e: DCR MMIO for IBM Blue Gene/Q
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple of
questions:
1) anyone have a good devtree binding for this?
I'm thinking:
bgq {
#address-cells = 2;
#size-cells = 2;
...
dcr {
reg = 0x3ff 0xe000 0x0 0x0800;
compatible = ibm,bgq-dcr;
dcr-controller;
dcr-access-method = mmio;
dcr-mmio-stride = ??;
};
};
I'm not sure what stride I will use since I have yet to figure out the DCR
numbering in play at the moment, which will be painful.
Also, some clarity to the following would be nice:
/* Stride is not properly defined yet, default to 0x10 for Axon */
p = of_get_property(dp, dcr-mmio-stride, NULL);
stride = (p == NULL) ? 0x10 : *p;
/* XXX FIXME: Which property name is to use of the 2 following ? */
p = of_get_property(dp, dcr-mmio-range, NULL);
if (p == NULL)
p = of_get_property(dp, dcr-mmio-space, NULL);
if (p == NULL)
goto done;
I guess my reg property is not useful to the code?
Is there a preference over dcr-mmio-range/space or in the absence of these to
we should use reg?
2) I need 64 bit reads and writes
My intention is to have dcr_{read,write}_generic_{mmio,native} take an unsigned
long for value all the way down.
For the native case, this would make is similar to mtspr and mfspr.
For the MMIO case, the selected in/out size would be based on #ifdef
__powerpc64__
Thoughts?
-jx
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Re: RFC: book3e: DCR MMIO for IBM Blue Gene/Q
On Nov 4, 2012, at 5:51 PM, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Sun, 2012-11-04 at 10:32 -0600, Jimi Xenidis wrote:
I want to use the stuff in arch/platform/sysdev/dcr.c and I have a couple of
questions:
1) anyone have a good devtree binding for this?
Not really, I think the cell stuff was the last we looked at this.
I'm thinking:
bgq {
#address-cells = 2;
#size-cells = 2;
...
dcr {
reg = 0x3ff 0xe000 0x0 0x0800;
compatible = ibm,bgq-dcr;
dcr-controller;
dcr-access-method = mmio;
dcr-mmio-stride = ??;
};
};
I'm not sure what stride I will use since I have yet to figure out the DCR
numbering in play at the moment, which will be painful.
Also, some clarity to the following would be nice:
/* Stride is not properly defined yet, default to 0x10 for Axon */
p = of_get_property(dp, dcr-mmio-stride, NULL);
stride = (p == NULL) ? 0x10 : *p;
/* XXX FIXME: Which property name is to use of the 2 following ? */
p = of_get_property(dp, dcr-mmio-range, NULL);
if (p == NULL)
p = of_get_property(dp, dcr-mmio-space, NULL);
if (p == NULL)
goto done;
Not sure what SLOF did back then. dcr-mmio-range sounds better to me.
I guess my reg property is not useful to the code?
Right, unless the DCR bridge has some registers of its own. It's also
handy to have as a standard way of representing the memory used by the
DCR bridge, tho that does mean duplication... but then it allows you to
have a nice unit address.
umm, was there a conclusion here? :-)
-jx
Is there a preference over dcr-mmio-range/space or in the absence of these
to we should use reg?
2) I need 64 bit reads and writes
My intention is to have dcr_{read,write}_generic_{mmio,native} take an
unsigned long for value all the way down.
For the native case, this would make is similar to mtspr and mfspr.
For the MMIO case, the selected in/out size would be based on #ifdef
__powerpc64__
As long as it doesn't break Axon...
Cheers,
Ben.
Thoughts?
-jx
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[PATCH] [PATCH v2] powerpc: icswx: fix race condition where threads do not get their ACOP register updated in time.
There is a race where a thread causes a coprocessor type to be valid
in its own ACOP _and_ in the current context, but it does not
propagate to the ACOP register of other threads in time for them to
use it. The original code tries to solve this by sending an IPI to
all threads on the system, which is heavy handed, but unfortunately
still provides a window where the icswx is issued by other threads and
the ACOP is not up to date.
This patch detects that the ACOP DSI fault was a false positive and
syncs the ACOP and causes the icswx to be replayed.
Signed-off-by: Jimi Xenidis ji...@pobox.com
Cc: Anton Blanchard an...@samba.org
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
---
Re: benh
- fix typo in logic where I used and not
- remove pr_debug
---
arch/powerpc/mm/icswx.c | 23 +--
arch/powerpc/mm/icswx.h |6 ++
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git arch/powerpc/mm/icswx.c arch/powerpc/mm/icswx.c
index 5d9a59e..8cdbd86 100644
--- arch/powerpc/mm/icswx.c
+++ arch/powerpc/mm/icswx.c
@@ -163,7 +163,7 @@ EXPORT_SYMBOL_GPL(drop_cop);
static int acop_use_cop(int ct)
{
- /* todo */
+ /* There is no alternate policy, yet */
return -1;
}
@@ -227,11 +227,30 @@ int acop_handle_fault(struct pt_regs *regs, unsigned long
address,
ct = (ccw 16) 0x3f;
}
+ /*
+* We could be here because another thread has enabled acop
+* but the ACOP register has yet to be updated.
+*
+* This should have been taken care of by the IPI to sync all
+* the threads (see smp_call_function(sync_cop, mm, 1)), but
+* that could take forever if there are a significant amount
+* of threads.
+*
+* Given the number of threads on some of these systems,
+* perhaps this is the best way to sync ACOP rather than whack
+* every thread with an IPI.
+*/
+ if ((acop_copro_type_bit(ct) current-active_mm-context.acop) != 0) {
+ sync_cop(current-active_mm);
+ return 0;
+ }
+
+ /* check for alternate policy */
if (!acop_use_cop(ct))
return 0;
/* at this point the CT is unknown to the system */
- pr_warn(%s[%d]: Coprocessor %d is unavailable,
+ pr_warn(%s[%d]: Coprocessor %d is unavailable\n,
current-comm, current-pid, ct);
/* get inst if we don't already have it */
diff --git arch/powerpc/mm/icswx.h arch/powerpc/mm/icswx.h
index 42176bd..6dedc08 100644
--- arch/powerpc/mm/icswx.h
+++ arch/powerpc/mm/icswx.h
@@ -59,4 +59,10 @@ extern void free_cop_pid(int free_pid);
extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
+
+static inline u64 acop_copro_type_bit(unsigned int type)
+{
+ return 1ULL (63 - type);
+}
+
#endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
--
1.7.0.4
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Re: [PATCH] powerpc: icswx: fix race condition where threads do not get their ACOP register updated in time.
On Feb 26, 2012, at 5:47 PM, Benjamin Herrenschmidt wrote:
+/*
+ * We could be here because another thread has enabled acop
+ * but the ACOP register has yet to be updated.
+ *
+ * This should have been taken care of by the IPI to sync all
+ * the threads (see smp_call_function(sync_cop, mm, 1)), but
+ * that could take forever if there are a significant amount
+ * of threads.
+ *
+ * Given the number of threads on some of these systems,
+ * perhaps this is the best way to sync ACOP rather than whack
+ * every thread with an IPI.
+ */
This is actually pretty standard stuff... If it was me I would make it
all lazy and avoid the IPI completely but it doesn't necessarily hurt
that much.
I'm happy to get rid of the IPI completely if Anton (or someone else) agrees to
test on his end.
If not, do you want me to reduce the comment?
In any case the recovery is indeed needed and you should
probably also remove the pr_debug, it's really just spam.
ack
+if (acop_copro_type_bit(ct) current-active_mm-context.acop) {
Shouldn't that be ? In fact, gcc would even warn so either make
it acop_check_copro(acop, ct) or do a (x y) != 0
Ach!! nice catch!
-jx
Cheers,
Ben.
+pr_debug(%s[%d]: Spurrious ACOP Fault, CT: %d, bit: 0x%llx
+SPR: 0x%lx, mm-acop: 0x%lx\n,
+current-comm, current-pid,
+ct, acop_copro_type_bit(ct), mfspr(SPRN_ACOP),
+current-active_mm-context.acop);
+
+sync_cop(current-active_mm);
+return 0;
+}
+
+/* check for alternate policy */
if (!acop_use_cop(ct))
return 0;
/* at this point the CT is unknown to the system */
-pr_warn(%s[%d]: Coprocessor %d is unavailable,
+pr_warn(%s[%d]: Coprocessor %d is unavailable\n,
current-comm, current-pid, ct);
/* get inst if we don't already have it */
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
index 42176bd..6dedc08 100644
--- a/arch/powerpc/mm/icswx.h
+++ b/arch/powerpc/mm/icswx.h
@@ -59,4 +59,10 @@ extern void free_cop_pid(int free_pid);
extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
+
+static inline u64 acop_copro_type_bit(unsigned int type)
+{
+return 1ULL (63 - type);
+}
+
#endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
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[PATCH] powerpc: icswx: fix race condition where threads do not get their ACOP register updated in time.
There is a race where a thread causes a coprocessor type to be valid
in its own ACOP _and_ in the current context, but it does not
propagate to the ACOP register of other threads in time for them to
use it. The original code tries to solve this by sending an IPI to
all threads on the system, which is heavy handed, but unfortunately
still provides a window where the icswx is issued by other threads and
the ACOP is not up to date.
This patch detects that the ACOP DSI fault was a false positive and
syncs the ACOP and causes the icswx to be replayed.
Signed-off-by: Jimi Xenidis ji...@pobox.com
Cc: Anton Blanchard an...@samba.org
---
arch/powerpc/mm/icswx.c | 29 +++--
arch/powerpc/mm/icswx.h |6 ++
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 5d9a59e..4db5b36 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -163,7 +163,7 @@ EXPORT_SYMBOL_GPL(drop_cop);
static int acop_use_cop(int ct)
{
- /* todo */
+ /* There is no alternate policy, yet */
return -1;
}
@@ -227,11 +227,36 @@ int acop_handle_fault(struct pt_regs *regs, unsigned long
address,
ct = (ccw 16) 0x3f;
}
+ /*
+* We could be here because another thread has enabled acop
+* but the ACOP register has yet to be updated.
+*
+* This should have been taken care of by the IPI to sync all
+* the threads (see smp_call_function(sync_cop, mm, 1)), but
+* that could take forever if there are a significant amount
+* of threads.
+*
+* Given the number of threads on some of these systems,
+* perhaps this is the best way to sync ACOP rather than whack
+* every thread with an IPI.
+*/
+ if (acop_copro_type_bit(ct) current-active_mm-context.acop) {
+ pr_debug(%s[%d]: Spurrious ACOP Fault, CT: %d, bit: 0x%llx
+ SPR: 0x%lx, mm-acop: 0x%lx\n,
+ current-comm, current-pid,
+ ct, acop_copro_type_bit(ct), mfspr(SPRN_ACOP),
+ current-active_mm-context.acop);
+
+ sync_cop(current-active_mm);
+ return 0;
+ }
+
+ /* check for alternate policy */
if (!acop_use_cop(ct))
return 0;
/* at this point the CT is unknown to the system */
- pr_warn(%s[%d]: Coprocessor %d is unavailable,
+ pr_warn(%s[%d]: Coprocessor %d is unavailable\n,
current-comm, current-pid, ct);
/* get inst if we don't already have it */
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
index 42176bd..6dedc08 100644
--- a/arch/powerpc/mm/icswx.h
+++ b/arch/powerpc/mm/icswx.h
@@ -59,4 +59,10 @@ extern void free_cop_pid(int free_pid);
extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
+
+static inline u64 acop_copro_type_bit(unsigned int type)
+{
+ return 1ULL (63 - type);
+}
+
#endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
--
1.7.0.4
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Re: [PATCH] powerpc/of: add OF_DYNAMIC for chroma
On Feb 19, 2012, at 4:48 PM, Michael Neuling wrote: linux next-20120217 compiling ppc64e_defconfig fails with: arch/powerpc/platforms/wsp/h8.c: In function 'wsp_h8_getaddr': arch/powerpc/platforms/wsp/h8.c:116: error: implicit declaration of function 'of_detach_node' The below fixes this by selecting the new OF_DYNAMIC when PPC_CHROMA. Signed-off-by: Michael Neuling mi...@neuling.org Acked-by: Jimi Xenidis ji...@pobox.com diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig index 57d22a2..79d2225 100644 --- a/arch/powerpc/platforms/wsp/Kconfig +++ b/arch/powerpc/platforms/wsp/Kconfig @@ -25,6 +25,7 @@ config PPC_CHROMA bool PowerEN PCIe Chroma Card select EPAPR_BOOT select PPC_WSP + select OF_DYNAMIC default y endmenu ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [1/4] powerpc: Revert show_regs() define for readability
On Oct 31, 2011, at 9:18 AM, Kumar Gala wrote: On Oct 28, 2011, at 2:40 PM, Jimi Xenidis wrote: On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote: We had an existing ifdef for 4xx BOOKE processors that got changed to CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do with CONFIG_PPC_ADV_DEBUG_REGS. The define really should be: #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) and not #ifdef CONFIG_PPC_ADV_DEBUG_REGS Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/kernel/process.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8f53954..a1b5981 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -657,7 +657,7 @@ void show_regs(struct pt_regs * regs) if ((regs-trap != 0xc00) cpu_has_feature(CPU_FTR_CFAR)) printk(CFAR: REG\n, regs-orig_gpr3); if (trap == 0x300 || trap == 0x600) -#ifdef CONFIG_PPC_ADV_DEBUG_REGS +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) printk(DEAR: REG, ESR: REG\n, regs-dar, regs-dsisr); I'll be needing || defined(CONFIG_PPC_BOOK3E) added to this please. -jx Under what platform is CONFIG_PPC_BOOK3E set and CONFIG_BOOKE is not? this was a grep typo on my part. sorry. -jx - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [4/4] powerpc/booke: Re-organize debug code
On Oct 31, 2011, at 9:21 AM, Kumar Gala wrote:
On Oct 28, 2011, at 2:37 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code for
!CONFIG_PPC_ADV_DEBUG_REGS and removed some CONFIG_PPC_ADV_DEBUG_REGS
code in set_dabr that would never get built.
* Move do_send_trap into traps.c as its only used there
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/system.h |5 +--
arch/powerpc/kernel/process.c | 97
+---
arch/powerpc/kernel/traps.c | 17 +++
3 files changed, 53 insertions(+), 66 deletions(-)
diff --git a/arch/powerpc/include/asm/system.h
b/arch/powerpc/include/asm/system.h
index e30a13d..1dc5d9c 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -111,11 +111,8 @@ static inline int debugger_dabr_match(struct pt_regs
*regs) { return 0; }
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
extern int set_dabr(unsigned long dabr);
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-extern void do_send_trap(struct pt_regs *regs, unsigned long address,
-unsigned long error_code, int signal_code, int brkpt);
-#else
This part of the patch breaks xmon.c
Naively I simply wrapped the xmon call:
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f08836a..b5911b2 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -738,8 +738,10 @@ static void insert_bpts(void)
static void insert_cpu_bpts(void)
{
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
if (dabr.enabled)
set_dabr(dabr.address | (dabr.enabled 7));
+#endif
if (iabr cpu_has_feature(CPU_FTR_IABR))
mtspr(SPRN_IABR, iabr-address
| (iabr-enabled (BP_IABR|BP_IABR_TE)));
@@ -767,7 +769,9 @@ static void remove_bpts(void)
static void remove_cpu_bpts(void)
{
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
set_dabr(0);
+#endif
if (cpu_has_feature(CPU_FTR_IABR))
mtspr(SPRN_IABR, 0);
}
Shouldn't all of these functions be #ifndef'd out as we don't support
cpu_bpts on book-e parts in xmon code today?
Well I guess this is one for benh, because I would have expected xmon to test
and call ppc_md.dabr.
Actually, should everyone be doing that?
-jx
-JX
extern void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
#endif
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 269a309..989e574 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -251,50 +251,6 @@ void discard_lazy_cpu_state(void)
#endif /* CONFIG_SMP */
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-void do_send_trap(struct pt_regs *regs, unsigned long address,
- unsigned long error_code, int signal_code, int breakpt)
-{
- siginfo_t info;
-
- if (notify_die(DIE_DABR_MATCH, dabr_match, regs, error_code,
- 11, SIGSEGV) == NOTIFY_STOP)
- return;
-
- /* Deliver the signal to userspace */
- info.si_signo = SIGTRAP;
- info.si_errno = breakpt;/* breakpoint or watchpoint id */
- info.si_code = signal_code;
- info.si_addr = (void __user *)address;
- force_sig_info(SIGTRAP, info, current);
-}
-#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
-void do_dabr(struct pt_regs *regs, unsigned long address,
- unsigned long error_code)
-{
- siginfo_t info;
-
- if (notify_die(DIE_DABR_MATCH, dabr_match, regs, error_code,
- 11, SIGSEGV) == NOTIFY_STOP)
- return;
-
- if (debugger_dabr_match(regs))
- return;
-
- /* Clear the DABR */
- set_dabr(0);
-
- /* Deliver the signal to userspace */
- info.si_signo = SIGTRAP;
- info.si_errno = 0;
- info.si_code = TRAP_HWBKPT;
- info.si_addr = (void __user *)address;
- force_sig_info(SIGTRAP, info, current);
-}
-#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
-
-static DEFINE_PER_CPU(unsigned long, current_dabr);
-
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
/*
* Set the debug registers back to their default safe values.
*/
@@ -357,16 +313,7 @@ static void switch_booke_debug_regs(struct
thread_struct *new_thread)
prime_debug_regs(new_thread);
}
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
-#ifndef CONFIG_HAVE_HW_BREAKPOINT
-static void set_debug_reg_defaults(struct thread_struct *thread)
-{
- if (thread-dabr) {
- thread-dabr = 0;
- set_dabr(0);
- }
-}
-#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
-#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
+static DEFINE_PER_CPU(unsigned long, current_dabr);
int set_dabr(unsigned long dabr)
{
@@ -376,19 +323,45 @@ int
Re: [4/4] powerpc/booke: Re-organize debug code
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code for
!CONFIG_PPC_ADV_DEBUG_REGS and removed some CONFIG_PPC_ADV_DEBUG_REGS
code in set_dabr that would never get built.
* Move do_send_trap into traps.c as its only used there
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/system.h |5 +--
arch/powerpc/kernel/process.c | 97 +---
arch/powerpc/kernel/traps.c | 17 +++
3 files changed, 53 insertions(+), 66 deletions(-)
diff --git a/arch/powerpc/include/asm/system.h
b/arch/powerpc/include/asm/system.h
index e30a13d..1dc5d9c 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -111,11 +111,8 @@ static inline int debugger_dabr_match(struct pt_regs
*regs) { return 0; }
static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
#endif
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
extern int set_dabr(unsigned long dabr);
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-extern void do_send_trap(struct pt_regs *regs, unsigned long address,
- unsigned long error_code, int signal_code, int brkpt);
-#else
This part of the patch breaks xmon.c
Naively I simply wrapped the xmon call:
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index f08836a..b5911b2 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -738,8 +738,10 @@ static void insert_bpts(void)
static void insert_cpu_bpts(void)
{
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
if (dabr.enabled)
set_dabr(dabr.address | (dabr.enabled 7));
+#endif
if (iabr cpu_has_feature(CPU_FTR_IABR))
mtspr(SPRN_IABR, iabr-address
| (iabr-enabled (BP_IABR|BP_IABR_TE)));
@@ -767,7 +769,9 @@ static void remove_bpts(void)
static void remove_cpu_bpts(void)
{
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
set_dabr(0);
+#endif
if (cpu_has_feature(CPU_FTR_IABR))
mtspr(SPRN_IABR, 0);
}
-JX
extern void do_dabr(struct pt_regs *regs, unsigned long address,
unsigned long error_code);
#endif
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 269a309..989e574 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -251,50 +251,6 @@ void discard_lazy_cpu_state(void)
#endif /* CONFIG_SMP */
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-void do_send_trap(struct pt_regs *regs, unsigned long address,
- unsigned long error_code, int signal_code, int breakpt)
-{
- siginfo_t info;
-
- if (notify_die(DIE_DABR_MATCH, dabr_match, regs, error_code,
- 11, SIGSEGV) == NOTIFY_STOP)
- return;
-
- /* Deliver the signal to userspace */
- info.si_signo = SIGTRAP;
- info.si_errno = breakpt;/* breakpoint or watchpoint id */
- info.si_code = signal_code;
- info.si_addr = (void __user *)address;
- force_sig_info(SIGTRAP, info, current);
-}
-#else/* !CONFIG_PPC_ADV_DEBUG_REGS */
-void do_dabr(struct pt_regs *regs, unsigned long address,
- unsigned long error_code)
-{
- siginfo_t info;
-
- if (notify_die(DIE_DABR_MATCH, dabr_match, regs, error_code,
- 11, SIGSEGV) == NOTIFY_STOP)
- return;
-
- if (debugger_dabr_match(regs))
- return;
-
- /* Clear the DABR */
- set_dabr(0);
-
- /* Deliver the signal to userspace */
- info.si_signo = SIGTRAP;
- info.si_errno = 0;
- info.si_code = TRAP_HWBKPT;
- info.si_addr = (void __user *)address;
- force_sig_info(SIGTRAP, info, current);
-}
-#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
-
-static DEFINE_PER_CPU(unsigned long, current_dabr);
-
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
/*
* Set the debug registers back to their default safe values.
*/
@@ -357,16 +313,7 @@ static void switch_booke_debug_regs(struct thread_struct
*new_thread)
prime_debug_regs(new_thread);
}
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
-#ifndef CONFIG_HAVE_HW_BREAKPOINT
-static void set_debug_reg_defaults(struct thread_struct *thread)
-{
- if (thread-dabr) {
- thread-dabr = 0;
- set_dabr(0);
- }
-}
-#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
-#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
+static DEFINE_PER_CPU(unsigned long, current_dabr);
int set_dabr(unsigned long dabr)
{
@@ -376,19 +323,45 @@ int set_dabr(unsigned long dabr)
return ppc_md.set_dabr(dabr);
/* XXX should we have a CPU_FTR_HAS_DABR ? */
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
- mtspr(SPRN_DAC1, dabr);
-#ifdef CONFIG_PPC_47x
- isync();
-#endif
-#elif defined(CONFIG_PPC_BOOK3S)
mtspr(SPRN_DABR, dabr);
Re: [1/4] powerpc: Revert show_regs() define for readability
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote: We had an existing ifdef for 4xx BOOKE processors that got changed to CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do with CONFIG_PPC_ADV_DEBUG_REGS. The define really should be: #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) and not #ifdef CONFIG_PPC_ADV_DEBUG_REGS Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/kernel/process.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index 8f53954..a1b5981 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -657,7 +657,7 @@ void show_regs(struct pt_regs * regs) if ((regs-trap != 0xc00) cpu_has_feature(CPU_FTR_CFAR)) printk(CFAR: REG\n, regs-orig_gpr3); if (trap == 0x300 || trap == 0x600) -#ifdef CONFIG_PPC_ADV_DEBUG_REGS +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) printk(DEAR: REG, ESR: REG\n, regs-dar, regs-dsisr); I'll be needing || defined(CONFIG_PPC_BOOK3E) added to this please. -jx #else printk(DAR: REG, DSISR: %08lx\n, regs-dar, regs-dsisr); ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RFC: ESR_I/DLK processing
arch/powerpc/kernel/head_fsl_booke.S has the following code:
/* Data Storage Interrupt */
START_EXCEPTION(DataStorage)
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
stw r5,_ESR(r11)
mfspr r4,SPRN_DEAR/* Grab the DEAR, save it, pass arg2 */
andis. r10,r5,(ESR_ILK|ESR_DLK)@h
bne 1f
EXC_XFER_EE_LITE(0x0300, handle_page_fault)
1:
addir3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x0300, CacheLockingException)
I need something similar for A2 (and all book3e) and was wondering, why this
isn't just:
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 88abe70..8451822 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -159,6 +159,14 @@ int __kprobes do_page_fault(struct pt_regs *regs,
unsigned long address,
}
#endif
+#ifdef CONFIG_PPC_BOOK3E
+ if (error_code (ESR_DLK|ESR_ILK)) {
+ /* detect that this is a privileged op and SIGILL */
+ _exception(SIGILL, regs, ILL_PRVOPC, regs-nip);
+ return 0;
+ }
+#endif
+
if (notify_page_fault(regs))
return 0;
Its not like this need to be fast or anything.
I'd be happy to submit a patch that adds to fault.c and removed the I/DLK
processing from head_fsl_booke.S
Thoughts?
-jx
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Re: [PATCH v2] powerpc: book3e: WSP: Add Chroma as a new WSP/PowerEN platform.
On Tue Oct 4 05:02:41 EST 2011, Scott Wood wrote: Looking at your comments below, will the following be acceptable On 09/29/2011 09:27 PM, Jimi Xenidis wrote: diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig index ea2811c..a3eef8e 100644 --- a/arch/powerpc/platforms/wsp/Kconfig +++ b/arch/powerpc/platforms/wsp/Kconfig @@ -1,6 +1,7 @@ config PPC_WSP bool select PPC_A2 + select GENERIC_TBSYNC select PPC_ICSWX select PPC_SCOM select PPC_XICS @@ -8,14 +9,20 @@ config PPC_WSP select PCI select PPC_IO_WORKAROUNDS if PCI select PPC_INDIRECT_PIO if PCI + select PPC_WSP_COPRO default n menu WSP platform selection depends on PPC_BOOK3E_64 add SMP config PPC_PSR2 - bool PSR-2 platform - select GENERIC_TBSYNC + bool PowerEN System Reference Platform 2 + select EPAPR_BOOT + select PPC_WSP + default y Make these default n Will that address everything? -jx + +config PPC_CHROMA + bool PowerEN PCIe Chroma Card select EPAPR_BOOT select PPC_WSP default y This is an existing problem with PSR2, but please don't hide default y in a menu (at least make it a menuconfig). As is, it's not obvious from looking at the toplevel platforms menu that these platforms are enabled at all. Further, PPC_WSP doesn't build on non-SMP (undefined references to boot_cpuid and get_hard_smp_processor_id in ics.c), but the platforms that select it don't depend on SMP. this I can solve with -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3] powerpc: book3e: WSP: Add Chroma as a new WSP/PowerEN platform.
This patch add the Chroma platform to WSP/PowerEN, which is a PCIe card (a defconfig is included). The card includes an H8 service processor that is used to manage the card. The H8 is connected over the second serial UART on the PowerEN chip so this patch includes a simple 16550 driver to enable communication, mostly for power off and rebooting. This patch also includes a, WSP specific, halt method that will shut of all A2 cores but still leave power on at the chip level. This is desirable, especially if you wish to interrogate the chip with a hardware probe after the halt. Signed-off-by: Jimi Xenidis ji...@pobox.com --- Re: ga...@kernel.crashing.org use make savedefconfig ARGH!: apparently make savedefconfig does not clean up the INITRAMFS_SOURCE --- arch/powerpc/configs/chroma_defconfig | 307 + arch/powerpc/platforms/wsp/Kconfig| 11 +- arch/powerpc/platforms/wsp/Makefile |8 +- arch/powerpc/platforms/wsp/chroma.c | 56 ++ arch/powerpc/platforms/wsp/h8.c | 134 ++ arch/powerpc/platforms/wsp/psr2.c | 56 ++- arch/powerpc/platforms/wsp/wsp.c | 115 arch/powerpc/platforms/wsp/wsp.h | 16 ++- 8 files changed, 651 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/configs/chroma_defconfig create mode 100644 arch/powerpc/platforms/wsp/chroma.c create mode 100644 arch/powerpc/platforms/wsp/h8.c create mode 100644 arch/powerpc/platforms/wsp/wsp.c diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig new file mode 100644 index 000..acf7fb2 --- /dev/null +++ b/arch/powerpc/configs/chroma_defconfig @@ -0,0 +1,307 @@ +CONFIG_PPC64=y +CONFIG_PPC_BOOK3E_64=y +# CONFIG_VIRT_CPU_ACCOUNTING is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=256 +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_MEM_RES_CTLR=y +CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_SCOM_DEBUGFS=y +CONFIG_PPC_A2_DD2=y +CONFIG_KVM_GUEST=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HZ_100=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=y +CONFIG_NUMA=y +# CONFIG_MIGRATION is not set +CONFIG_PPC_64K_PAGES=y +CONFIG_SCHED_SMT=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE= +# CONFIG_SECCOMP is not set +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m
[PATCH] [PATCH v3] powerpc: Fix xmon for systems without MSR[RI]
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Restricted it to Book3e
Fix typo, its supposed to be CONFIG_PPC_BOOK3E
---
arch/powerpc/xmon/xmon.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..e88e7f5 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
static inline int unrecoverable_excp(struct pt_regs *regs)
{
-#ifdef CONFIG_4xx
- /* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_PPC_BOOK3E)
+ /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
return 0;
#else
return ((regs-msr MSR_RI) == 0);
--
1.7.0.4
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[PATCH 1/3 v3] powerpc: Split ICSWX ACOP and PID processing
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: b...@kernel.crashing.org
rebase
--in-reply-to=1317279773.29415.181.camel@pasglop
---
arch/powerpc/mm/Makefile |2 +
arch/powerpc/mm/icswx.c| 160 ++
arch/powerpc/mm/icswx.h| 39 +++
arch/powerpc/mm/icswx_pid.c| 87 ++
arch/powerpc/mm/mmu_context_hash64.c | 195 +---
arch/powerpc/platforms/Kconfig.cputype |8 ++
6 files changed, 297 insertions(+), 194 deletions(-)
create mode 100644 arch/powerpc/mm/icswx.c
create mode 100644 arch/powerpc/mm/icswx.h
create mode 100644 arch/powerpc/mm/icswx_pid.c
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 991ee81..3787b61 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
tlb_hash$(CONFIG_WORD_SIZE).o \
mmu_context_hash$(CONFIG_WORD_SIZE).o
+obj-$(CONFIG_PPC_ICSWX)+= icswx.o
+obj-$(CONFIG_PPC_ICSWX_PID)+= icswx_pid.o
obj-$(CONFIG_40x) += 40x_mmu.o
obj-$(CONFIG_44x) += 44x_mmu.o
obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 000..a98850f
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,160 @@
+/*
+ * ICSWX and ACOP Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. an...@samba.org
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include linux/sched.h
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/types.h
+#include linux/mm.h
+#include linux/spinlock.h
+#include linux/module.h
+#include icswx.h
+
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has no
+ * address, and the processor does not perform an MMU access to
+ * authenticate the transaction. The command portion of the PowerBus
+ * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
+ * Process ID (PID), which the coprocessor compares to the authorized
+ * LPID and PID held in the coprocessor, to determine if the process
+ * is authorized to generate the transaction. The data of the COP_REQ
+ * transaction is 128-byte or less in size and is placed in cacheable
+ * memory on a 128-byte cache line boundary.
+ *
+ * The task to use a coprocessor should use use_cop() to mark the use
+ * of the Coprocessor Type (CT) and context switching. On a server
+ * class processor, the PID register is used only for coprocessor
+ * management + * and so a coprocessor PID is allocated before
+ * executing icswx + * instruction. Drop_cop() is used to free the
+ * coprocessor PID.
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+
+void switch_cop(struct mm_struct *next)
+{
+#ifdef CONFIG_ICSWX_PID
+ mtspr(SPRN_PID, next-context.cop_pid);
+#endif
+ mtspr(SPRN_ACOP, next-context.acop);
+}
+
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise.
+ * The returned PID will be fed to the coprocessor to determine if an
+ * icswx transaction
[PATCH 2/3 v3] powerpc: book3e: Add ICSWX/ACOP support to Book3e cores like A2
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix white space *embarrassed*
Re: b...@kernel.crashing.org
rebase
---
arch/powerpc/include/asm/cputable.h|2 +-
arch/powerpc/include/asm/mmu-book3e.h |4
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/cpu_setup_a2.S | 10 --
arch/powerpc/platforms/Kconfig.cputype |2 +-
arch/powerpc/platforms/wsp/Kconfig |1 +
6 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index e30442c..7044233 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_COMPATIBLE(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/mmu-book3e.h
index 0260ea5..50210b9 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -214,6 +214,10 @@ typedef struct {
unsigned intid;
unsigned intactive;
unsigned long vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+ struct spinlock *cop_lockp; /* guard cop related stuff */
+ unsigned long acop; /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
u64 high_slices_psize; /* 4 bits per slice for now */
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39..e927049 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
+#endif
+
/* Bit definitions for CCR1. */
#defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity
checking */
#defineCCR1_TCS0x0080 /* Timer Clock Select */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S
b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818fe..ebc62f4 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
* core local but doing it always won't hurt
*/
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
/* Make sure ACOP starts out as zero */
li r3,0
mtspr SPRN_ACOP,r3
+ /* Skip the following if we are in Guest mode */
+ mfmsr r3
+ andis. r0,r3,MSR_GS@h
+ bne _icswx_skip_guest
+
/* Enable icswx instruction */
mfspr r3,SPRN_A2_CCR2
ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
/* Unmask all CTs in HACOP */
li r3,-1
mtspr SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
/* Enable doorbell */
mfspr r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index 4868d1f..f71f5e0 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -236,7 +236,7 @@ config VSX
config PPC_ICSWX
bool Support for PowerPC icswx coprocessor instruction
- depends on POWER4
+ depends on POWER4 || PPC_A2
default n
---help---
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index f4fb837..ea2811c 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,6 +1,7 @@
config PPC_WSP
bool
select PPC_A2
+ select PPC_ICSWX
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
--
1.7.0.4
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[PATCH 3/3 v3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application. If the application used
the record form (icswx.) then the architected reject is emulated.
If the application did not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
- Fix Kconfig/CONFIG mismatch
- Removed union/bitfields and inspect the bits directly
Re: b...@kernel.crashing.org
rebase
---
arch/powerpc/mm/fault.c| 17 +
arch/powerpc/mm/icswx.c| 113
arch/powerpc/mm/icswx.h| 23 +++
arch/powerpc/platforms/Kconfig.cputype | 13 -
4 files changed, 165 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c9..2f0d1b0 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -44,6 +44,8 @@
#include asm/siginfo.h
#include mm/mmu_decl.h
+#include icswx.h
+
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
{
@@ -143,6 +145,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned
long address,
is_write = error_code ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+ /*
+* we need to do this early because this data storage
+* interrupt does not update the DAR/DEAR so we don't want to
+* look at it
+*/
+ if (error_code ICSWX_DSI_UCT) {
+ int ret;
+
+ ret = acop_handle_fault(regs, address, error_code);
+ if (ret)
+ return ret;
+ }
+#endif
+
if (notify_page_fault(regs))
return 0;
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index a98850f..5d9a59e 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -17,6 +17,8 @@
#include linux/mm.h
#include linux/spinlock.h
#include linux/module.h
+#include linux/uaccess.h
+
#include icswx.h
/*
@@ -158,3 +160,114 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
spin_unlock(mm-page_table_lock);
}
EXPORT_SYMBOL_GPL(drop_cop);
+
+static int acop_use_cop(int ct)
+{
+ /* todo */
+ return -1;
+}
+
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+ u32 inst;
+ u32 __user *p;
+
+ p = (u32 __user *)regs-nip;
+ if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+ return 0;
+
+ if (__get_user(inst, p))
+ return 0;
+
+ return inst;
+}
+
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ * processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code)
+{
+ int ct;
+ u32 inst = 0;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+ pr_info(No coprocessors available);
+ _exception(SIGILL, regs, ILL_ILLOPN, address);
+ }
+
+ if (!user_mode(regs)) {
+ /* this could happen if the HV denies the
+* kernel access, for now we just die */
+ die(ICSWX from kernel failed, regs, SIGSEGV);
+ }
+
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct 0) {
+ /* we have to peek at the instruction word to figure out CT */
+ u32 ccw;
+ u32 rs;
+
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+
+ rs = (inst (31 - 10)) 0x1f;
+ ccw = regs-gpr[rs];
+ ct = (ccw 16) 0x3f;
+ }
+
+ if (!acop_use_cop(ct))
+ return 0;
+
+ /* at this point the CT is unknown to the system */
+ pr_warn(%s[%d]: Coprocessor %d is unavailable,
+ current-comm, current-pid, ct);
+
+ /* get inst if we don't already have it */
+ if (inst == 0) {
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+ }
+
+ /* Check if the instruction is the record form */
+ if (inst 1) {
+ /*
+* the instruction is record form so we can reject
+* using CR0
+*/
+ regs-ccr = ~(0xful 28);
+ regs-ccr |= ICSWX_RC_NOT_FOUND 28;
+
+ /* Move on to the next
[PATCH] powerpc: xmon: Fix the 'u' command
The 'u' command will print the TLB on book3e parts and the SLB on Book3s parts, but the help system doesn't say that correctly. Signed-off-by: Jimi Xenidis ji...@pobox.com --- arch/powerpc/xmon/xmon.c | 14 +- 1 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 13f82f8..ad6ada8 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -228,13 +228,11 @@ Commands:\n\ tprint backtrace\n\ xexit monitor and recover\n\ Xexit monitor and dont recover\n -#ifdef CONFIG_PPC64 +#if defined(CONFIG_PPC64) !defined(CONFIG_PPC_BOOK3E) u dump segment table or SLB\n -#endif -#ifdef CONFIG_PPC_STD_MMU_32 +#elif defined(CONFIG_PPC_STD_MMU_32) u dump segment registers\n -#endif -#ifdef CONFIG_44x +#elif defined(CONFIG_44x) || defined(CONFIG_PPC_BOOK3E) u dump TLB\n #endif ? help\n @@ -885,13 +883,11 @@ cmds(struct pt_regs *excp) case 'u': dump_segments(); break; -#endif -#ifdef CONFIG_4xx +#elif defined(CONFIG_4xx) case 'u': dump_tlb_44x(); break; -#endif -#ifdef CONFIG_PPC_BOOK3E +#elif defined(CONFIG_PPC_BOOK3E) case 'u': dump_tlb_book3e(); break; -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: xmon: Fix #if typo for systems without MSR[RI]
Sorry, there was a typo in the #if
signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/xmon/xmon.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 13f82f8..e88e7f5 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,7 +340,7 @@ int cpus_are_in_xmon(void)
static inline int unrecoverable_excp(struct pt_regs *regs)
{
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
+#if defined(CONFIG_4xx) || defined(CONFIG_PPC_BOOK3E)
/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
return 0;
#else
--
1.7.0.4
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Re: [PATCH] powerpc: book3e: WSP: Add Chroma as an new WSP/PowerEN platform.
On Sep 29, 2011, at 6:52 PM, Kumar Gala ga...@kernel.crashing.org wrote: On Sep 29, 2011, at 4:55 PM, Jimi Xenidis wrote: arch/powerpc/configs/chroma_defconfig | 1817 + Seems kind big, you probably need a 'make savedefconfig' ;) wow had no idea that evan existed, will do. -jx - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc: book3e: WSP: Add Chroma as a new WSP/PowerEN platform.
This patch add the Chroma platform to WSP/PowerEN, which is a PCIe card (a defconfig is included). The card includes an H8 service processor that is used to manage the card. The H8 is connected over the second serial UART on the PowerEN chip so this patch includes a simple 16550 driver to enable communication, mostly for power off and rebooting. This patch also includes a, WSP specific, halt method that will shut of all A2 cores but still leave power on at the chip level. This is desirable, especially if you wish to interrogate the chip with a hardware probe after the halt. Signed-off-by: Jimi Xenidis ji...@pobox.com --- Re: ga...@kernel.crashing.org use make savedefconfig --- arch/powerpc/configs/chroma_defconfig | 307 + arch/powerpc/platforms/wsp/Kconfig| 11 +- arch/powerpc/platforms/wsp/Makefile |8 +- arch/powerpc/platforms/wsp/chroma.c | 56 ++ arch/powerpc/platforms/wsp/h8.c | 134 ++ arch/powerpc/platforms/wsp/psr2.c | 56 ++- arch/powerpc/platforms/wsp/wsp.c | 115 arch/powerpc/platforms/wsp/wsp.h | 16 ++- 8 files changed, 651 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/configs/chroma_defconfig create mode 100644 arch/powerpc/platforms/wsp/chroma.c create mode 100644 arch/powerpc/platforms/wsp/h8.c create mode 100644 arch/powerpc/platforms/wsp/wsp.c diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig new file mode 100644 index 000..ce9e28f --- /dev/null +++ b/arch/powerpc/configs/chroma_defconfig @@ -0,0 +1,307 @@ +CONFIG_PPC64=y +CONFIG_PPC_BOOK3E_64=y +# CONFIG_VIRT_CPU_ACCOUNTING is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=256 +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_MEM_RES_CTLR=y +CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE=/home/jimix/work/linux/prism/ramdisks/rng.cpio.gz +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_INITRAMFS_COMPRESSION_GZIP=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_SCOM_DEBUGFS=y +CONFIG_PPC_A2_DD2=y +CONFIG_KVM_GUEST=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_HZ_100=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=y +CONFIG_NUMA=y +# CONFIG_MIGRATION is not set +CONFIG_PPC_64K_PAGES=y +CONFIG_SCHED_SMT=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE= +# CONFIG_SECCOMP is not set +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEASPM is not set +CONFIG_PCI_MSI=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m
[PATCH v2] powerpc: Fix xmon for systems without MSR[RI]
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Restricted it to Book3e
---
arch/powerpc/xmon/xmon.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..13f82f8 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
static inline int unrecoverable_excp(struct pt_regs *regs)
{
-#ifdef CONFIG_4xx
- /* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
+ /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
return 0;
#else
return ((regs-msr MSR_RI) == 0);
--
1.7.0.4
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[PATCH 1/3 v2] powerpc: Split ICSWX ACOP and PID processing
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix typo in arch/powerpc/mm/Makefile
Re: an...@samba.org
merge in: powerpc: Fix deadlock in icswx code
---
arch/powerpc/mm/Makefile |2 +
arch/powerpc/mm/icswx.c| 162 ++
arch/powerpc/mm/icswx.h| 34 ++
arch/powerpc/mm/icswx_pid.c| 87 ++
arch/powerpc/mm/mmu_context_hash64.c | 195
arch/powerpc/platforms/Kconfig.cputype | 10 ++-
6 files changed, 294 insertions(+), 196 deletions(-)
create mode 100644 arch/powerpc/mm/icswx.c
create mode 100644 arch/powerpc/mm/icswx.h
create mode 100644 arch/powerpc/mm/icswx_pid.c
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index bdca46e..fb7976f 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
tlb_hash$(CONFIG_WORD_SIZE).o \
mmu_context_hash$(CONFIG_WORD_SIZE).o
+obj-$(CONFIG_PPC_ICSWX)+= icswx.o
+obj-$(CONFIG_PPC_ICSWX_PID)+= icswx_pid.o
obj-$(CONFIG_40x) += 40x_mmu.o
obj-$(CONFIG_44x) += 44x_mmu.o
obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 000..2f1dd29
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,162 @@
+/*
+ * ICSWX and ACOP Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. an...@samba.org
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include linux/sched.h
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/types.h
+#include linux/mm.h
+#include linux/spinlock.h
+#include linux/module.h
+#include icswx.h
+
+
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has no
+ * address, and the processor does not perform an MMU access to
+ * authenticate the transaction. The command portion of the PowerBus
+ * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
+ * Process ID (PID), which the coprocessor compares to the authorized
+ * LPID and PID held in the coprocessor, to determine if the process
+ * is authorized to generate the transaction. The data of the COP_REQ
+ * transaction is cache block or less, typically 64 or 128 bytes in
+ * size, and is placed in cacheable memory on a 128-byte boundary
+ * _always_.
+ *
+ * The task to use a coprocessor should use use_cop() mark the use of
+ * the coprocessor type (CT) and context swithing. On a server
+ * processor the PID register is used only for coprocessor management
+ * and so a coprocessor PID is allocated before executing icswx
+ * instruction. Drop_cop() is used to free the resources created by
+ * use_cop().
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+
+void switch_cop(struct mm_struct *next)
+{
+#ifdef CONFIG_ICSWX_PID
+ mtspr(SPRN_PID, next-context.cop_pid);
+#endif
+ mtspr(SPRN_ACOP, next-context.acop);
+}
+
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise
[PATCH 2/3 v2] powerpc: book3e: Add ICSWX/ACOP support to Book3e cores like A2
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
Fix white space *embarrassed*
---
arch/powerpc/include/asm/cputable.h |2 +-
arch/powerpc/include/asm/mmu-book3e.h |4
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/cpu_setup_a2.S| 10 --
arch/powerpc/platforms/wsp/Kconfig|1 +
5 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index e30442c..7044233 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_COMPATIBLE(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/mmu-book3e.h
index 3ea0f9a..6554608 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -212,6 +212,10 @@ typedef struct {
unsigned intid;
unsigned intactive;
unsigned long vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+ struct spinlock *cop_lockp; /* guard cop related stuff */
+ unsigned long acop; /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
} mm_context_t;
/* Page size definitions, common between 32 and 64-bit
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39..e927049 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
+#endif
+
/* Bit definitions for CCR1. */
#defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity
checking */
#defineCCR1_TCS0x0080 /* Timer Clock Select */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S
b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818fe..ebc62f4 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
* core local but doing it always won't hurt
*/
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
/* Make sure ACOP starts out as zero */
li r3,0
mtspr SPRN_ACOP,r3
+ /* Skip the following if we are in Guest mode */
+ mfmsr r3
+ andis. r0,r3,MSR_GS@h
+ bne _icswx_skip_guest
+
/* Enable icswx instruction */
mfspr r3,SPRN_A2_CCR2
ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
/* Unmask all CTs in HACOP */
li r3,-1
mtspr SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
/* Enable doorbell */
mfspr r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index d051581..3540293 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,6 +1,7 @@
config PPC_WSP
bool
select PPC_A2
+ select PPC_ICSWX
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
--
1.7.0.4
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[PATCH 3/3 v2] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application. If the application used
the record form (icswx.) then the architected reject is emulated.
If the application did not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Re: ga...@kernel.crashing.org
- Fix Kconfig/CONFIG mismatch
- Removed union/bitfields and inspect the bits directly
---
arch/powerpc/mm/fault.c| 16 +
arch/powerpc/mm/icswx.c| 113
arch/powerpc/mm/icswx.h| 24 +++
arch/powerpc/platforms/Kconfig.cputype | 13 -
4 files changed, 165 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c9..88abe70 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -43,6 +43,7 @@
#include asm/tlbflush.h
#include asm/siginfo.h
#include mm/mmu_decl.h
+#include mm/icswx.h
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
@@ -143,6 +144,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned
long address,
is_write = error_code ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+ /*
+* we need to do this early because this data storage
+* interrupt does not update the DAR/DEAR so we don't want to
+* look at it
+*/
+ if (error_code ICSWX_DSI_UCT) {
+ int ret;
+
+ ret = acop_handle_fault(regs, address, error_code);
+ if (ret)
+ return ret;
+ }
+#endif
+
if (notify_page_fault(regs))
return 0;
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 2f1dd29..c8626cc 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -17,6 +17,8 @@
#include linux/mm.h
#include linux/spinlock.h
#include linux/module.h
+#include linux/uaccess.h
+
#include icswx.h
@@ -160,3 +162,114 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
spin_unlock(mm-page_table_lock);
}
EXPORT_SYMBOL_GPL(drop_cop);
+
+static int acop_use_cop(int ct)
+{
+ /* todo */
+ return -1;
+}
+
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+ u32 inst;
+ u32 __user *p;
+
+ p = (u32 __user *)regs-nip;
+ if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+ return 0;
+
+ if (__get_user(inst, p))
+ return 0;
+
+ return inst;
+}
+
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ * processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code)
+{
+ int ct;
+ u32 inst = 0;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+ pr_info(No coprocessors available);
+ _exception(SIGILL, regs, ILL_ILLOPN, address);
+ }
+
+ if (!user_mode(regs)) {
+ /* this could happen if the HV denies the
+* kernel access, for now we just die */
+ die(ICSWX from kernel failed, regs, SIGSEGV);
+ }
+
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct 0) {
+ /* we have to peek at the instruction word to figure out CT */
+ u32 ccw;
+ u32 rs;
+
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+
+ rs = (inst (31 - 10)) 0x1f;
+ ccw = regs-gpr[rs];
+ ct = (ccw 16) 0x3f;
+ }
+
+ if (!acop_use_cop(ct))
+ return 0;
+
+ /* at this point the CT is unknown to the system */
+ pr_warn(%s[%d]: Coprocessor %d is unavailable,
+ current-comm, current-pid, ct);
+
+ /* get inst if we don't already have it */
+ if (inst == 0) {
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+ }
+
+ /* Check if the instruction is the record form */
+ if (inst 1) {
+ /*
+* the instruction is record form so we can reject
+* using CR0
+*/
+ regs-ccr = ~(0xful 28);
+ regs-ccr |= ICSWX_RC_NOT_FOUND 28;
+
+ /* Move on to the next instruction
Re: [PATCH v2] powerpc: Fix xmon for systems without MSR[RI]
On Sep 23, 2011, at 11:32 AM, Scott Wood wrote:
On 09/23/2011 10:01 AM, Jimi Xenidis wrote:
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
Restricted it to Book3e
---
arch/powerpc/xmon/xmon.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..13f82f8 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
static inline int unrecoverable_excp(struct pt_regs *regs)
{
-#ifdef CONFIG_4xx
-/* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
+/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
return 0;
#else
return ((regs-msr MSR_RI) == 0);
How is CONFIG_BOOK3E better than CONFIG_BOOKE? Both e500mc (has RI) and
e500v2 (doesn't have RI) will select both symbols. Sounds like it
should be a cputable flag.
Ben was not in favor of wasting a cpu feature bit on this.
I figured that since Book3e ISA does not support an RI bit than I would leave
that too the those who extend it. :)
Any other ideas are welcome.
-JX
-Scott
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Re: [PATCH] powerpc: Fix deadlock in icswx code
On Sep 14, 2011, at 2:43 PM, Anton Blanchard wrote:
Hi Anton,
It would really help me a lot if you could review and maybe merge this with my
earlier patch that splits this file.
http://patchwork.ozlabs.org/patch/109103/
All it does is split.. I promise.
You don't have to take the other stuff.. yet :)
-JX
The icswx code introduced an A-B B-A deadlock:
CPU0CPU1
lock(anon_vma-mutex);
lock(mm-mmap_sem);
lock(anon_vma-mutex);
lock(mm-mmap_sem);
Instead of using the mmap_sem to keep mm_users constant, take the
page table spinlock.
Signed-off-by: Anton Blanchard an...@samba.org
Cc: sta...@kernel.org
---
diff --git a/arch/powerpc/mm/mmu_context_hash64.c
b/arch/powerpc/mm/mmu_context_hash64.c
index 3bafc3d..4ff587e 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -136,8 +136,8 @@ int use_cop(unsigned long acop, struct mm_struct *mm)
if (!mm || !acop)
return -EINVAL;
- /* We need to make sure mm_users doesn't change */
- down_read(mm-mmap_sem);
+ /* The page_table_lock ensures mm_users won't change under us */
+ spin_lock(mm-page_table_lock);
spin_lock(mm-context.cop_lockp);
if (mm-context.cop_pid == COP_PID_NONE) {
@@ -164,7 +164,7 @@ int use_cop(unsigned long acop, struct mm_struct *mm)
out:
spin_unlock(mm-context.cop_lockp);
- up_read(mm-mmap_sem);
+ spin_unlock(mm-page_table_lock);
return ret;
}
@@ -185,8 +185,8 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
if (WARN_ON_ONCE(!mm))
return;
- /* We need to make sure mm_users doesn't change */
- down_read(mm-mmap_sem);
+ /* The page_table_lock ensures mm_users won't change under us */
+ spin_lock(mm-page_table_lock);
spin_lock(mm-context.cop_lockp);
mm-context.acop = ~acop;
@@ -213,7 +213,7 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
}
spin_unlock(mm-context.cop_lockp);
- up_read(mm-mmap_sem);
+ spin_unlock(mm-page_table_lock);
}
EXPORT_SYMBOL_GPL(drop_cop);
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Re: [PATCH] powerpc: Fix xmon for systems without MSR[RI]
On Aug 30, 2011, at 1:08 PM, Scott Wood wrote: On 08/30/2011 01:11 AM, Benjamin Herrenschmidt wrote: On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote: From: David Gibson d...@au1.ibm.com Based on patch by David Gibson d...@au1.ibm.com xmon has a longstanding bug on systems which are SMP-capable but lack the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary CPUs will not properly keep quiet, but will print stuff, thereby garbling the primary xmon's output. This patch fixes it, by ignoring the RI bit if the processor does not support it. There's already a version of this for 4xx upstream, which we'll need to extend to other RI-lacking CPUs at some point. For now this adds BookE processors to the mix. Don't freescale one have RI ? e500mc does. hmm, according to the ISA, MSR[RI] is only defined for Book3s and is not defined for Book3e Should we scope it to just book3e? -jx e500v2 doesn't -- if a machine check happens while MSR[ME]=0, it causes a checkstop. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
union/struct representations for MAS Registers
I have some and use them in some code, they represent ISA 2.06 MAVN=1 (version
2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32 _val;
struct {
u32 v:1;
u32 iprot:1;
u32 tid:14;
u32 _reserved_1:2;
u32 ind:1;
u32 ts:1;
u32 tsize:4;
u32 _reserved_2:8;
};
};
-jx
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Re: union/struct representations for MAS Registers
On Aug 10, 2011, at 12:25 PM, Kumar Gala wrote:
On Aug 10, 2011, at 12:21 PM, Jimi Xenidis wrote:
I have some and use them in some code, they represent ISA 2.06 MAVN=1
(version 2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32 _val;
struct {
u32 v:1;
u32 iprot:1;
u32 tid:14;
u32 _reserved_1:2;
u32 ind:1;
u32 ts:1;
u32 tsize:4;
u32 _reserved_2:8;
};
};
Uugh, we really have avoided unions for such things and it would be nice to
keep it that way.
I like nice, I'll convert
-JX
- k
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Re: union/struct representations for MAS Registers
On Aug 10, 2011, at 12:25 PM, David Laight wrote:
I have some and use them in some code, they represent ISA
2.06 MAVN=1 (version 2)
Can I keep them?
if so, should I put them somewhere useful to others?
Examples:
union mas1 {
u32 _val;
struct {
u32 v:1;
u32 iprot:1;
u32 tid:14;
u32 _reserved_1:2;
u32 ind:1;
u32 ts:1;
u32 tsize:4;
u32 _reserved_2:8;
};
};
Bitfields are rather non-portable, the compiler has a lot of choice
about how to align the bits in memory.
I'm ok with the masking stuff.
However, I'm actually surprised this is true given the maturity of our ABIs.
-JX
Their use to map anything physical is doomed to portabilily issues.
David
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Re: [PATCH 3/3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
On Aug 9, 2011, at 12:26 AM, Kumar Gala wrote:
On Aug 8, 2011, at 5:26 PM, Jimi Xenidis wrote:
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application. If the application used
the record form (icswx.) then the architected reject is emulated.
If the application did not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/mm/fault.c| 16 +
arch/powerpc/mm/icswx.c| 114
arch/powerpc/mm/icswx.h| 34 ++
arch/powerpc/platforms/Kconfig.cputype | 11 +++
4 files changed, 175 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c9..88abe70 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -43,6 +43,7 @@
#include asm/tlbflush.h
#include asm/siginfo.h
#include mm/mmu_decl.h
+#include mm/icswx.h
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
@@ -143,6 +144,21 @@ int __kprobes do_page_fault(struct pt_regs *regs,
unsigned long address,
is_write = error_code ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+/*
+ * we need to do this early because this data storage
+ * interrupt does not update the DAR/DEAR so we don't want to
+ * look at it
+ */
+if (error_code ICSWX_DSI_UCT) {
+int ret;
+
+ret = acop_handle_fault(regs, address, error_code);
+if (ret)
+return ret;
+}
+#endif
+
if (notify_page_fault(regs))
return 0;
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 667330e..fbf71b4 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -17,6 +17,9 @@
#include linux/mm.h
#include linux/spinlock.h
#include linux/module.h
+
+#include asm/uaccess.h
+
#include icswx.h
@@ -161,3 +164,114 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
up_read(mm-mmap_sem);
}
EXPORT_SYMBOL_GPL(drop_cop);
+
+static int acop_use_cop(int ct)
+{
+/* todo */
+return -1;
+}
+
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+u32 inst;
+u32 __user *p;
+
+p = (u32 __user *)regs-nip;
+if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+return 0;
+
+if (__get_user(inst, p))
+return 0;
+
+return inst;
+}
+
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ * processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code)
+{
+int ct;
+u32 inst = 0;
+
+if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+pr_info(No coprocessors available);
+_exception(SIGILL, regs, ILL_ILLOPN, address);
+}
+
+if (!user_mode(regs)) {
+/* this could happen if the HV denies the
+ * kernel access, for now we just die */
+die(ICSWX from kernel failed, regs, SIGSEGV);
+}
+
+/* Some implementations leave us a hint for the CT */
+ct = ICSWX_GET_CT_HINT(error_code);
+if (ct 0) {
+/* we have to peek at the instruction work to figure out CT */
+union cop_ccw ccw;
don't use a union, we don't do this for any other place we decode
instructions (just use shift/mask). Utilize ppc-opcode.h
ack, union begone. I'll just do the single shift below to get the CT since its
the only spot I need it.
+u32 rs;
+
+inst = acop_get_inst(regs);
+if (inst == 0)
+return -1;
+
+rs = (inst (31 - 10)) 0x1f;
+ccw._val = regs-gpr[rs];
+ct = ccw.ct;
+}
+
+if (!acop_use_cop(ct))
+return 0;
+
+/* at this point the CT is unknown to the system */
+pr_warn(%s[%d]: Coprocessor %d is unavailable,
+current-comm, current-pid, ct);
+
+/* get inst if we don't already have it */
+if (inst == 0) {
+inst = acop_get_inst(regs);
+if (inst == 0)
+return -1;
+}
+
+/* Check if the instruction is the record form */
+if (inst 1) {
+/*
+ * the instruction is record form so we can reject
+ * using CR0
+ */
+regs
Re: [PATCH 3/3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
On Aug 9, 2011, at 10:15 AM, Benjamin Herrenschmidt wrote:
On Tue, 2011-08-09 at 00:26 -0500, Kumar Gala wrote:
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct 0) {
+ /* we have to peek at the instruction work to figure out CT */
+ union cop_ccw ccw;
don't use a union, we don't do this for any other place we decode
instructions (just use shift/mask). Utilize ppc-opcode.h
Except that the union here is -not- the instruction, but the content of
the RS register :-)
I agree, especially for when we need the kernel to build the struct/union.
However, that is a later patch (working on it now and if there are no
objections) so I'll add it then.
-JX
Cheers,
Ben.
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[PATCH] powerpc: Fix xmon for systems without MSR[RI]
From: David Gibson d...@au1.ibm.com
Based on patch by David Gibson d...@au1.ibm.com
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.
There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
BookE processors to the mix.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/xmon/xmon.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..fdb2f7e 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
static inline int unrecoverable_excp(struct pt_regs *regs)
{
-#ifdef CONFIG_4xx
- /* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+ /* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
return 0;
#else
return ((regs-msr MSR_RI) == 0);
--
1.7.0.4
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[PATCH] powerpc: wsp: Fix Wire Speed Processor platform configs
Some config selections were applied to the platform (reference board) when they actuall apply to the chip. Signed-off-by: Jimi Xenidis ji...@pobox.com --- arch/powerpc/platforms/wsp/Kconfig |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig index c3c48eb..d051581 100644 --- a/arch/powerpc/platforms/wsp/Kconfig +++ b/arch/powerpc/platforms/wsp/Kconfig @@ -1,5 +1,9 @@ config PPC_WSP bool + select PPC_A2 + select PPC_SCOM + select PPC_XICS + select PPC_ICP_NATIVE default n menu WSP platform selection @@ -7,13 +11,9 @@ menu WSP platform selection config PPC_PSR2 bool PSR-2 platform - select PPC_A2 select GENERIC_TBSYNC - select PPC_SCOM select EPAPR_BOOT select PPC_WSP - select PPC_XICS - select PPC_ICP_NATIVE default y endmenu -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
powerpc: Get icswx to work on both Book3s and Book3e platforms
The following patches deal with the fact that Book3e parts already have a PID register that is managed by the system. Currently an ICSWX not in the ACOP will get rejected as specified by both architectures. -JX ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3] powerpc: Split ICSWX ACOP and PID processing
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/mm/Makefile |4 +-
arch/powerpc/mm/icswx.c| 163 ++
arch/powerpc/mm/icswx.h| 34 ++
arch/powerpc/mm/icswx_pid.c| 87 ++
arch/powerpc/mm/mmu_context_hash64.c | 195
arch/powerpc/platforms/Kconfig.cputype | 10 ++-
6 files changed, 296 insertions(+), 197 deletions(-)
create mode 100644 arch/powerpc/mm/icswx.c
create mode 100644 arch/powerpc/mm/icswx.h
create mode 100644 arch/powerpc/mm/icswx_pid.c
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index bdca46e..ba51190 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,7 +21,9 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
tlb_hash$(CONFIG_WORD_SIZE).o \
mmu_context_hash$(CONFIG_WORD_SIZE).o
-obj-$(CONFIG_40x) += 40x_mmu.o
+obj-$(CONFIG_PPC_ICSWX)+= icswx.o
+obj-$(CONFIG_PPC_ICSWX_PID)+= icswx_pid.o
+obj-$(CONFIG_40x) += 40x_mmu.o?
obj-$(CONFIG_44x) += 44x_mmu.o
obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 000..667330e
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,163 @@
+/*
+ * ICSWX and ACOP Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. an...@samba.org
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include linux/sched.h
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/types.h
+#include linux/mm.h
+#include linux/spinlock.h
+#include linux/module.h
+#include icswx.h
+
+
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has no
+ * address, and the processor does not perform an MMU access to
+ * authenticate the transaction. The command portion of the PowerBus
+ * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
+ * Process ID (PID), which the coprocessor compares to the authorized
+ * LPID and PID held in the coprocessor, to determine if the process
+ * is authorized to generate the transaction. The data of the COP_REQ
+ * transaction is cache block or less, typically 64 or 128 bytes in
+ * size, and is placed in cacheable memory on a 128-byte boundary
+ * _always_.
+ *
+ * The task to use a coprocessor should use use_cop() mark the use of
+ * the coprocessor type (CT) and context swithing. On a server
+ * processor the PID register is used only for coprocessor management
+ * and so a coprocessor PID is allocated before executing icswx
+ * instruction. Drop_cop() is used to free the resources created by
+ * use_cop().
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+
+void switch_cop(struct mm_struct *next)
+{
+#ifdef CONFIG_ICSWX_PID
+ mtspr(SPRN_PID, next-context.cop_pid);
+#endif
+ mtspr(SPRN_ACOP, next-context.acop);
+}
+
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise.
+ * The returned PID will be fed to the coprocessor to determine
[PATCH 2/3] powerpc: book3e: Add ICSWX/ACOP support to Book3e cores like A2
ICSWX is also used by the A2 processor to access coprocessors,
although not all chips that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/include/asm/cputable.h |2 +-
arch/powerpc/include/asm/mmu-book3e.h |4
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/cpu_setup_a2.S| 10 --
arch/powerpc/platforms/wsp/Kconfig|1 +
5 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index e30442c..7044233 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_COMPATIBLE(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/mmu-book3e.h
index 3ea0f9a..06d7f91 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -212,6 +212,10 @@ typedef struct {
unsigned intid;
unsigned intactive;
unsigned long vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+ struct spinlock *cop_lockp; /* guard acop and cop_pid */
+ unsigned long acop; /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
} mm_context_t;
/* Page size definitions, common between 32 and 64-bit
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39..e927049 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
+#endif
+
/* Bit definitions for CCR1. */
#defineCCR1_DPC0x0100 /* Disable L1 I-Cache/D-Cache parity
checking */
#defineCCR1_TCS0x0080 /* Timer Clock Select */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S
b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818fe..ebc62f4 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
* core local but doing it always won't hurt
*/
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
/* Make sure ACOP starts out as zero */
li r3,0
mtspr SPRN_ACOP,r3
+ /* Skip the following if we are in Guest mode */
+ mfmsr r3
+ andis. r0,r3,MSR_GS@h
+ bne _icswx_skip_guest
+
/* Enable icswx instruction */
mfspr r3,SPRN_A2_CCR2
ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
/* Unmask all CTs in HACOP */
li r3,-1
mtspr SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
/* Enable doorbell */
mfspr r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index d051581..3540293 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,6 +1,7 @@
config PPC_WSP
bool
select PPC_A2
+ select PPC_ICSWX
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
--
1.7.0.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application. If the application used
the record form (icswx.) then the architected reject is emulated.
If the application did not used the record form (icswx) then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis ji...@pobox.com
---
arch/powerpc/mm/fault.c| 16 +
arch/powerpc/mm/icswx.c| 114
arch/powerpc/mm/icswx.h| 34 ++
arch/powerpc/platforms/Kconfig.cputype | 11 +++
4 files changed, 175 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c9..88abe70 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -43,6 +43,7 @@
#include asm/tlbflush.h
#include asm/siginfo.h
#include mm/mmu_decl.h
+#include mm/icswx.h
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
@@ -143,6 +144,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned
long address,
is_write = error_code ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+ /*
+* we need to do this early because this data storage
+* interrupt does not update the DAR/DEAR so we don't want to
+* look at it
+*/
+ if (error_code ICSWX_DSI_UCT) {
+ int ret;
+
+ ret = acop_handle_fault(regs, address, error_code);
+ if (ret)
+ return ret;
+ }
+#endif
+
if (notify_page_fault(regs))
return 0;
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 667330e..fbf71b4 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -17,6 +17,9 @@
#include linux/mm.h
#include linux/spinlock.h
#include linux/module.h
+
+#include asm/uaccess.h
+
#include icswx.h
@@ -161,3 +164,114 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
up_read(mm-mmap_sem);
}
EXPORT_SYMBOL_GPL(drop_cop);
+
+static int acop_use_cop(int ct)
+{
+ /* todo */
+ return -1;
+}
+
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+ u32 inst;
+ u32 __user *p;
+
+ p = (u32 __user *)regs-nip;
+ if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+ return 0;
+
+ if (__get_user(inst, p))
+ return 0;
+
+ return inst;
+}
+
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ * processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code)
+{
+ int ct;
+ u32 inst = 0;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+ pr_info(No coprocessors available);
+ _exception(SIGILL, regs, ILL_ILLOPN, address);
+ }
+
+ if (!user_mode(regs)) {
+ /* this could happen if the HV denies the
+* kernel access, for now we just die */
+ die(ICSWX from kernel failed, regs, SIGSEGV);
+ }
+
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct 0) {
+ /* we have to peek at the instruction work to figure out CT */
+ union cop_ccw ccw;
+ u32 rs;
+
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+
+ rs = (inst (31 - 10)) 0x1f;
+ ccw._val = regs-gpr[rs];
+ ct = ccw.ct;
+ }
+
+ if (!acop_use_cop(ct))
+ return 0;
+
+ /* at this point the CT is unknown to the system */
+ pr_warn(%s[%d]: Coprocessor %d is unavailable,
+ current-comm, current-pid, ct);
+
+ /* get inst if we don't already have it */
+ if (inst == 0) {
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+ }
+
+ /* Check if the instruction is the record form */
+ if (inst 1) {
+ /*
+* the instruction is record form so we can reject
+* using CR0
+*/
+ regs-ccr = ~(0xful 28);
+ regs-ccr |= ICSWX_RC_NOT_FOUND 28;
+
+ /* Move on to the next instruction */
+ regs-nip += 4;
+ } else {
+ /*
+* There is no architected mechanism to report a bad
powerpc: poweren: Add PCIe Root and MSI support the PowerEN
Based on patchs from: Benjamin Herrenschmidt b...@kernel.crashing.org Michael Ellerman mich...@ellerman.id.au I just brought them up to date -JX ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: poweren: pci: Add PCIe Root support to PowerEN
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Based on a patch by Benjamin Herrenschmidt b...@kernel.crashing.org
Modernized and slightly modified to not record erros into the nvram
log since we do not have that device driver just yet.
Jimi Xenidis ji...@pobox.com
---
arch/powerpc/platforms/wsp/Kconfig |3 +
arch/powerpc/platforms/wsp/Makefile |1 +
arch/powerpc/platforms/wsp/psr2.c|4 +
arch/powerpc/platforms/wsp/wsp.h |3 +
arch/powerpc/platforms/wsp/wsp_pci.c | 1133 ++
arch/powerpc/platforms/wsp/wsp_pci.h | 268
6 files changed, 1412 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/wsp/wsp_pci.c
create mode 100644 arch/powerpc/platforms/wsp/wsp_pci.h
diff --git a/arch/powerpc/platforms/wsp/Kconfig
b/arch/powerpc/platforms/wsp/Kconfig
index 3540293..ea2811c 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -5,6 +5,9 @@ config PPC_WSP
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
+ select PCI
+ select PPC_IO_WORKAROUNDS if PCI
+ select PPC_INDIRECT_PIO if PCI
default n
menu WSP platform selection
diff --git a/arch/powerpc/platforms/wsp/Makefile
b/arch/powerpc/platforms/wsp/Makefile
index 095be73..84519f8 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -4,3 +4,4 @@ obj-y += setup.o ics.o
obj-$(CONFIG_PPC_PSR2) += psr2.o opb_pic.o
obj-$(CONFIG_PPC_WSP) += scom_wsp.o
obj-$(CONFIG_SMP) += smp.o scom_smp.o
+obj-$(CONFIG_PCI) += wsp_pci.o
diff --git a/arch/powerpc/platforms/wsp/psr2.c
b/arch/powerpc/platforms/wsp/psr2.c
index 40f2891..166f2e4 100644
--- a/arch/powerpc/platforms/wsp/psr2.c
+++ b/arch/powerpc/platforms/wsp/psr2.c
@@ -63,6 +63,10 @@ static void __init psr2_setup_arch(void)
#ifdef CONFIG_SMP
a2_setup_smp();
#endif
+#ifdef CONFIG_PCI
+ wsp_setup_pci();
+#endif
+
}
static int __init psr2_probe(void)
diff --git a/arch/powerpc/platforms/wsp/wsp.h b/arch/powerpc/platforms/wsp/wsp.h
index 7c3e087..3347981 100644
--- a/arch/powerpc/platforms/wsp/wsp.h
+++ b/arch/powerpc/platforms/wsp/wsp.h
@@ -3,6 +3,9 @@
#include asm/wsp.h
+/* Devtree compatible strings for major devices */
+#define PCIE_COMPATIBLE ibm,wsp-pciex
+
extern void wsp_setup_pci(void);
extern void scom_init_wsp(void);
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c
b/arch/powerpc/platforms/wsp/wsp_pci.c
new file mode 100644
index 000..e0262cd
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -0,0 +1,1133 @@
+/*
+ * Copyright 2010 Ben Herrenschmidt, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define DEBUG
+
+#include linux/kernel.h
+#include linux/pci.h
+#include linux/delay.h
+#include linux/string.h
+#include linux/init.h
+#include linux/bootmem.h
+#include linux/irq.h
+#include linux/interrupt.h
+#include linux/debugfs.h
+
+#include asm/sections.h
+#include asm/io.h
+#include asm/prom.h
+#include asm/pci-bridge.h
+#include asm/machdep.h
+#include asm/ppc-pci.h
+#include asm/iommu.h
+#include asm/io-workarounds.h
+
+#include wsp.h
+#include wsp_pci.h
+#include msi.h
+
+
+/* Max number of TVTs for one table. Only 32-bit tables can use
+ * multiple TVTs and so the max currently supported is thus 8
+ * since only 2G of DMA space is supported
+ */
+#define MAX_TABLE_TVT_COUNT8
+
+struct wsp_dma_table {
+ struct list_headlink;
+ struct iommu_table table;
+ struct wsp_phb *phb;
+ struct page *tces[MAX_TABLE_TVT_COUNT];
+};
+
+/* We support DMA regions from 0...2G in 32bit space (no support for
+ * 64-bit DMA just yet). Each device gets a separate TCE table (TVT
+ * entry) with validation enabled (though not supported by SimiCS
+ * just yet).
+ *
+ * To simplify things, we divide this 2G space into N regions based
+ * on the constant below which could be turned into a tunable eventually
+ *
+ * We then assign dynamically those regions to devices as they show up.
+ *
+ * We use a bitmap as an allocator for these.
+ *
+ * Tables are allocated/created dynamically as devices are discovered,
+ * multiple TVT entries are used if needed
+ *
+ * When 64-bit DMA support is added we should simply use a separate set
+ * of larger regions (the HW supports 64 TVT entries). We can
+ * additionally create a bypass region in 64-bit space for performances
+ * though that would have a cost in term of security.
+ *
+ * If you set NUM_DMA32_REGIONS to 1, then a single table is shared
+ * for all devices and bus/dev/fn validation is disabled
+ *
+ * Note that a DMA32 region cannot be smaller than
[PATCH 2/2] powerpc: poweren: pci-msi: Add MSI support for PCI on PowerEN
From: Michael Ellerman mich...@ellerman.id.au
Based on a patch by Michael Ellerman mich...@ellerman.id.au
Patch was simply forward ported upstream.
Jimi Xenidis ji...@pobox.com
---
arch/powerpc/platforms/wsp/Makefile |1 +
arch/powerpc/platforms/wsp/ics.c| 48
arch/powerpc/platforms/wsp/ics.h|5 ++
arch/powerpc/platforms/wsp/msi.c| 102 +++
arch/powerpc/platforms/wsp/msi.h| 19 +++
5 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/wsp/msi.c
create mode 100644 arch/powerpc/platforms/wsp/msi.h
diff --git a/arch/powerpc/platforms/wsp/Makefile
b/arch/powerpc/platforms/wsp/Makefile
index 84519f8..a1486b4 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PPC_PSR2) += psr2.o opb_pic.o
obj-$(CONFIG_PPC_WSP) += scom_wsp.o
obj-$(CONFIG_SMP) += smp.o scom_smp.o
obj-$(CONFIG_PCI) += wsp_pci.o
+obj-$(CONFIG_PCI_MSI) += msi.o
\ No newline at end of file
diff --git a/arch/powerpc/platforms/wsp/ics.c b/arch/powerpc/platforms/wsp/ics.c
index e53bd9e..5768743 100644
--- a/arch/powerpc/platforms/wsp/ics.c
+++ b/arch/powerpc/platforms/wsp/ics.c
@@ -710,3 +710,51 @@ void __init wsp_init_irq(void)
/* We need to patch our irq chip's EOI to point to the right ICP */
wsp_irq_chip.irq_eoi = icp_ops-eoi;
}
+
+#ifdef CONFIG_PCI_MSI
+static void wsp_ics_msi_unmask_irq(struct irq_data *d)
+{
+ wsp_chip_unmask_irq(d);
+ unmask_msi_irq(d);
+}
+
+static unsigned int wsp_ics_msi_startup(struct irq_data *d)
+{
+ wsp_ics_msi_unmask_irq(d);
+ return 0;
+}
+
+static void wsp_ics_msi_mask_irq(struct irq_data *d)
+{
+ mask_msi_irq(d);
+ wsp_chip_mask_irq(d);
+}
+
+/*
+ * we do it this way because we reassinge default EOI handling in
+ * irq_init() above
+ */
+static void wsp_ics_eoi(struct irq_data *data)
+{
+ wsp_irq_chip.irq_eoi(data);
+}
+
+static struct irq_chip wsp_ics_msi = {
+ .name = WSP ICS MSI,
+ .irq_startup = wsp_ics_msi_startup,
+ .irq_mask = wsp_ics_msi_mask_irq,
+ .irq_unmask = wsp_ics_msi_unmask_irq,
+ .irq_eoi = wsp_ics_eoi,
+ .irq_set_affinity = wsp_chip_set_affinity
+};
+
+void wsp_ics_set_msi_chip(unsigned int irq)
+{
+ irq_set_chip(irq, wsp_ics_msi);
+}
+
+void wsp_ics_set_std_chip(unsigned int irq)
+{
+ irq_set_chip(irq, wsp_irq_chip);
+}
+#endif /* CONFIG_PCI_MSI */
diff --git a/arch/powerpc/platforms/wsp/ics.h b/arch/powerpc/platforms/wsp/ics.h
index e34d531..07b644e 100644
--- a/arch/powerpc/platforms/wsp/ics.h
+++ b/arch/powerpc/platforms/wsp/ics.h
@@ -17,4 +17,9 @@ extern void wsp_init_irq(void);
extern int wsp_ics_alloc_irq(struct device_node *dn, int num);
extern void wsp_ics_free_irq(struct device_node *dn, unsigned int irq);
+#ifdef CONFIG_PCI_MSI
+extern void wsp_ics_set_msi_chip(unsigned int irq);
+extern void wsp_ics_set_std_chip(unsigned int irq);
+#endif /* CONFIG_PCI_MSI */
+
#endif /* __ICS_H */
diff --git a/arch/powerpc/platforms/wsp/msi.c b/arch/powerpc/platforms/wsp/msi.c
new file mode 100644
index 000..380882f
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/msi.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2011 Michael Ellerman, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/pci.h
+#include linux/msi.h
+#include linux/irq.h
+#include linux/interrupt.h
+
+#include msi.h
+#include ics.h
+#include wsp_pci.h
+
+/* Magic addresses for 32 64-bit MSIs with hardcoded MVE 0 */
+#define MSI_ADDR_320xul
+#define MSI_ADDR_640x1000ul
+
+int wsp_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+ struct pci_controller *phb;
+ struct msi_desc *entry;
+ struct msi_msg msg;
+ unsigned int virq;
+ int hwirq;
+
+ phb = pci_bus_to_host(dev-bus);
+ if (!phb)
+ return -ENOENT;
+
+ entry = list_first_entry(dev-msi_list, struct msi_desc, list);
+ if (entry-msi_attrib.is_64) {
+ msg.address_lo = 0;
+ msg.address_hi = MSI_ADDR_64 32;
+ } else {
+ msg.address_lo = MSI_ADDR_32;
+ msg.address_hi = 0;
+ }
+
+ list_for_each_entry(entry, dev-msi_list, list) {
+ hwirq = wsp_ics_alloc_irq(phb-dn, 1);
+ if (hwirq 0) {
+ dev_warn(dev-dev, wsp_msi: hwirq alloc failed!\n);
+ return hwirq;
+ }
+
+ virq = irq_create_mapping(NULL, hwirq);
+ if (virq == NO_IRQ) {
+ dev_warn(dev-dev, wsp_msi
Re: [PATCH v2 0/12] Hypervisor-mode KVM on POWER7
On May 31, 2011, at 8:50 AM, Alexander Graf wrote: On 31.05.2011, at 14:35, Paul Mackerras wrote: On Tue, May 31, 2011 at 12:40:31PM +0200, Alexander Graf wrote: Thinking about the testability of this a bit more ... how much effort would it be to get this code running on a 970MP with SLOF? There should only be a few POWER7 specific pieces, right? Do you have a 970MP that has a usable hypervisor mode, i.e. not an Apple machine? The 970s in Apple machines have the HV hard-wired to 1, which means they do have a hypervisor mode but it isn't any use. If you do have such a machine, then we would have to look at some details like the instruction sequence for the partition switch, and make sure we don't try to use SMT4 mode. Also, I believe we will have to flush the TLB on partition switches, since Power processors prior to POWER7 didn't tag the TLB entries with the partition ID. So it should be quite feasible if you have a non-Apple machine. I will check whether the 970MP machines that Terrasoft were distributing would be suitable. We have one of them in the lab. That's the one I was thinking of and yes, I have one available. That way I could test 99% of your code, you don't have to release hardware, and everyone's happy :). Be aware that on 970s (off the top of my head): - did not have the LPCR architected so you'll have to access individual HID registers. - old style RMOR is supported, not VRMA - no MEDiated interrupt -jx Alex -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: dtc: Add python source code output
On Nov 10, 2008, at 10:11 AM, Milton Miller wrote: On 2008-11-07 at 02:31:40, David Gibson wrote: On Thu, Nov 06, 2008 at 06:55:44PM +1100, Michael Ellerman wrote: This commit adds an output format, which produces python code. When run, the python produces a data structure that can then be inspected in order to do various things. ... I'm not sure if this is generally useful (or sane) but it was for me so I thought I'd post it. Hrm, well the idea of langauge source output seems reasonable. But the actual data structure emitted, and the method of construction in Python both seem a bit odd to me. I have a dts that I want to use to configure a simulator, and this seemed like the nicest way to get there. dtc spits out the pythonised device tree, and then I have a 10 line python script that does the configuring. [snip] These branches also result in the value having different Python types depending on the context. That's not necessarily a bad thing, but since which Python type is chosen depends on a heuristic only, it certainly needs some care. You certainly need to be certain that you can always deduce the exact, byte-for-byte correct version of the property value from whatever you put into the Python data structure. + +out: + fprintf(f, n.properties.append(p)\n); So, emitting Python procedural code to build up the data structure, rather than a great big Python literal that the Python parser will just turn into the right thing seems a bit of a roundabout way of doing this. I would think so too. I haven't looked at the output, only at Davids comments. If the data structure is ambiguous, then I do think more thought is needed. There is value in the DTC (optionally) emitting a python library and then having the DTC result use it. It would allow for python to easily, at runtime, be able to modify the contents and not have to inline-edit, emit, compile a DTS. BTW: it would also be nice if the python library to dump the dts (or even dtb) Have you considered just parsing the flat tree binary? Either creating a python binding to libfdt or even just parsing the dtb directly? I have written perl code to parse a dtb and query it for nodes and properties, it wasn't too bad. I need to look at a bug report by another user and comment it, then I should seek the okays post it. It is currently read-only and iterative callback based (like the kernels early-scan-flat-tree stuff), but I have planned creating a tree for querying, editing, and re-flattening. Perl strings are counted length binary blobs, so property contents are interpreted with pack and unpack. The library has been used to search a dtb to build a list of cpu instances and memory blocks, and it has been used to query the properties of a known node in the tree. milton ___ devicetree-discuss mailing list [EMAIL PROTECTED] https://ozlabs.org/mailman/listinfo/devicetree-discuss ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 4/4] kvmppc: convert wrteei to wrtee as kvm guest optimization
On Aug 22, 2008, at 4:17 AM, Kumar Gala wrote: On Aug 22, 2008, at 3:08 AM, Christian Ehrhardt wrote: Scott Wood wrote: On Thu, Aug 21, 2008 at 09:21:39AM -0500, Kumar Gala wrote: Where is the other discussion? I'd like to understand what's going on here.. (especially since I added the wrtee[i] changes to kernel way back when). Presumably, they want to be able to replace wrtee with a store to a hypervisor/guest shared memory area, and there's no store-immediate instruction. -Scott Exactly Scott And for your question Kumar, in the last submission I was asked to split host and guest patches. So the host discussion lives on [EMAIL PROTECTED] as I mentioned (maybe a bit too hidden) in the [0/4] mail of this series. Maybe I'm missing something but it seems like just changing the code to wrtee isn't the best way to ensure you have enough space to put the set of instructions you guys want. Sorry, I have not really been following this, I assume you are replacing SPR accesses with load/stores that do not trap. I believe thats fine for reading any SPR, but not true for modifying some SPRs, particularly MSR. IMHO you must trap on any instruction that modifies the MSR. So you should prolly not rewrite mtmsr or wrtee* but let them trap. BTW: actually moving problem SPRs (like MSRs) to a read only page makes decoding far more efficient, but it does burn another TLB entry. -JX - k -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] Fix powerpc64 build if CONFIG_EPOLL=n
On Jul 27, 2008, at 10:23 AM, Stephen Rothwell wrote: Hi Jimi, On Sun, 27 Jul 2008 08:48:09 -0400 Jimi Xenidis [EMAIL PROTECTED] wrote: Declate compat_sys_epoll_pwait as a conditional syscall like the rest of the epoll interfaces. We could have put an #ifdef around the entry in include/asm-powerpc/ systbl.h, but IMHO this is ultimately correct patch. Already in Linus' tree - commit 5f17156fc55abac476d180e480bedb0f07f01b14 Fix build on COMPAT platforms when CONFIG_EPOLL is disabled Wow, missed by less than a week. Thanks for the pointer. -JX -- Cheers, Stephen Rothwell[EMAIL PROTECTED] http://www.canb.auug.org.au/~sfr/ ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] Fix powerpc64 build if CONFIG_EPOLL=n
Declate compat_sys_epoll_pwait as a conditional syscall like the rest of the epoll interfaces. We could have put an #ifdef around the entry in include/asm-powerpc/ systbl.h, but IMHO this is ultimately correct patch. Signed-off-by: Jimi Xenidis [EMAIL PROTECTED] --- diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index 5b9b467..0fea0ee 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -59,6 +59,7 @@ cond_syscall(sys_epoll_create); cond_syscall(sys_epoll_ctl); cond_syscall(sys_epoll_wait); cond_syscall(sys_epoll_pwait); +cond_syscall(compat_sys_epoll_pwait); cond_syscall(sys_semget); cond_syscall(sys_semop); cond_syscall(sys_semtimedop); ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [kvm-ppc-devel] [PATCH] [v2] Add idle wait support for 44x platforms
On Apr 4, 2008, at 3:06 AM, Jerone Young wrote:
# HG changeset patch
# User Jerone Young [EMAIL PROTECTED]
# Date 1207292108 18000
# Node ID afed3e5de82ab6c0ac8d6ceeb0292b6c41ece1ed
# Parent a5b2aebbc6ebd2439c655f1c047ed7e3c1991ec1
[v2] Add idle wait support for 44x platforms
This patch adds the ability for the CPU to go into wait state while
in cpu_idle loop. This helps virtulization solutions know when the
guest Linux kernel is in an idle state. There are two ways to do it.
1) Command line
idle=spin -- CPU will spin (this is the default)
idle=wait -- set CPU into wait state when idle
2) The device tree will be checked for the /hypervisor node
If this node is seen it will use wait for idle, so that
the hypervisor can know when guest Linux kernel it is in
an idle state.
This patch, unlike the last, isolates the code to 44x platforms.
Signed-off-by: Jerone Young [EMAIL PROTECTED]
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/
platforms/44x/Makefile
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -1,4 +1,4 @@ obj-$(CONFIG_44x) := misc_44x.o
-obj-$(CONFIG_44x) := misc_44x.o
+obj-$(CONFIG_44x) := misc_44x.o idle.o
obj-$(CONFIG_EBONY)+= ebony.o
obj-$(CONFIG_TAISHAN) += taishan.o
obj-$(CONFIG_BAMBOO) += bamboo.o
diff --git a/arch/powerpc/platforms/44x/idle.c b/arch/powerpc/
platforms/44x/idle.c
new file mode 100644
--- /dev/null
+++ b/arch/powerpc/platforms/44x/idle.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 IBM Corp.
+ *
+ * Derived from pasemi/idle.c
+ * by Olof Johansson [EMAIL PROTECTED]
+ *
+ * Added by: Jerone Young [EMAIL PROTECTED]
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA
+ *
+ */
+
+#include linux/of.h
+#include linux/kernel.h
+#include asm/machdep.h
+
+static int current_mode = 0;
Doesn't matter if the 0 is functionally redundant or pleasing to your
eye, it is the Linux way to leave out the = 0, so just do it
please.
+
+struct sleep_mode {
+ char *name;
+ void (*entry)(void);
+};
+
+static void ppc44x_idle(void)
Perhaps ppc44x_wait is more appropriate?
+{
+ unsigned long msr_save;
+
+ msr_save = mfmsr();
+ /* set wait state MSR */
+ mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE);
Did we decide to drop MSR_DE?
+ /* return to initial state */
+ mtmsr(msr_save);
It may be my paranoia but I'm pretty sure you need the isync() after
_both_ mtmsr()s
Certainly can't hurt.
+}
+
+static struct sleep_mode modes[] = {
+ { .name = spin, .entry = NULL },
+ { .name = wait, .entry = ppc44x_idle },
+};
+
+int __init ppc44x_idle_init(void)
+{
+ void *func = modes[current_mode].entry;
+ struct device_node *node;
+
+ node = of_find_node_by_path(/hypervisor);
+ if (node) {
+ /* if we find /hypervisor node is in device tree,
+ set idle mode to wait */
+ func = ppc44x_idle; /* wait */
+ of_node_put(node);
+ }
+
+ ppc_md.power_save = func;
+ return 0;
+}
+
+arch_initcall(ppc44x_idle_init);
IIRC, this would over-ride the idle_param() below, is that the
intended behavior?
+
+static int __init idle_param(char *p)
+{
+ int i;
+
+ for (i = 0; i sizeof(modes)/ARRAY_SIZE(modes); i++) {
It is supposed to be:
for (i = 0; i ARRAY_SIZE(modes); i++) {
What you have will actually eval to 0 and would have never checked
anything :)
+ if (!strcmp(modes[i].name, p)) {
+ current_mode = i;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+early_param(idle, idle_param);
--
---
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