Re: [PATCH 0/6] phase out CONFIG_VIRT_TO_BUS
On Mon, 6 Jun 2022 at 10:25, Greg Kroah-Hartman wrote: > > On Mon, Jun 06, 2022 at 10:41:03AM +0200, Arnd Bergmann wrote: > > From: Arnd Bergmann > > > > The virt_to_bus/bus_to_virt interface has been deprecated for > > decades. After Jakub Kicinski put a lot of work into cleaning out the > > network drivers using them, there are only a couple of other drivers > > left, which can all be removed or otherwise cleaned up, to remove the > > old interface for good. > > > > Any out of tree drivers using virt_to_bus() should be converted to > > using the dma-mapping interfaces, typically dma_alloc_coherent() > > or dma_map_single()). > > > > There are a few m68k and ppc32 specific drivers that keep using the > > interfaces, but these are all guarded with architecture-specific > > Kconfig dependencies, and are not actually broken. > > > > There are still a number of drivers that are using virt_to_phys() > > and phys_to_virt() in place of dma-mapping operations, and these > > are often broken, but they are out of scope for this series. > > I'll take patches 1 and 2 right now through my staging tree if that's > ok. > Hi, I'd love to say that I could fix this stuff up, however I've lacked access to suitable hardware for a long time now and don't foresee that changing any time soon... Martyn > thanks, > > greg k-h >
Re: ppc9a board support
Hi Chris, Support for the PPC9A is already in the Linux kernel, along with VME drivers. Martyn On 04/02/14 14:47, Chris Enrique wrote: hello, sorry if this message doesn't clearly hit the topic of this list but i would like to ask if anybody has information about bringing a linux-3.10 or later kernel to ge fanuc ppc9a powerpc board (existing bsp? vme drivers? etc.?) to prevent starting from scratch for this task. any ideas would be much appreciated. kind regards, chris ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev -- -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: device tree entry for tsi148
On 15/01/13 08:11, ternaryd wrote: Hi, I'm trying to install linux on an e500v2 board with the tsi148 VME-Bridge, but got stuck. Now it seems that I need to include information regarding this bridge into the .dts-file, but can't figure out how. Maybe somebody on this list could post the tsi148-specific part of a device tree, which I could use as a guide line? You don't need to include anything about the device it's self, but there will need to be an entry in the DTS for PCI. Which SOC are you using? Can you provide your boot log? Martyn -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: GE IMP3a
On 21/08/12 14:58, Kumar Gala wrote: On Aug 21, 2012, at 7:39 AM, Martyn Welch wrote: On 15/08/12 22:32, Kumar Gala wrote: Do you know why ge_imp3a.c has 0x9000 as the 'primary' PCIe bus on the board? Hi Kumar, Sorry, missed your mail. np. At a quick guess it's because that's the interface that is used for the on-board PCI devices. What PCI devices are on-board? Just SATA. Does the board have any PCIe-ISA bridges? No, though SERDES Port 1 is connected to a PCie-PCI non-transparent bridge to a PCI backplane. [ if you can generate an lspci dump, that might answer some of these questions ] Sorry, I don't have easy access to a board at the moment. Martyn -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: GE IMP3a
On 15/08/12 22:32, Kumar Gala wrote: Do you know why ge_imp3a.c has 0x9000 as the 'primary' PCIe bus on the board? Hi Kumar, Sorry, missed your mail. At a quick guess it's because that's the interface that is used for the on-board PCI devices. Martyn -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 4/4] powerpc: Board support for GE IMP3A
On 13/03/12 11:51, Linus Walleij wrote: On Mon, Mar 12, 2012 at 6:13 PM, Martyn Welch martyn.we...@ge.com wrote: Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020 processor. (...) +++ b/arch/powerpc/configs/ge_imp3a_defconfig @@ -0,0 +1,257 @@ +CONFIG_PPC_85xx=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_SPARSE_IRQ=y This habit of changing a lot of defconfig stuff in a patch dealing with other stuff is alien in the ARM world. Especially when changing a horde of stuff that has nothing to do with the patch subject. This is adding the defconfig, it's support for a new board: diff --git a/arch/powerpc/configs/ge_imp3a_defconfig b/arch/powerpc/configs/ge_imp3a_defconfig new file mode 100644 index 000..f8c51a4 --- /dev/null +++ b/arch/powerpc/configs/ge_imp3a_defconfig But I don't really know how PPC does these things so who am I to speak ... BTW: doesn't the make saveconfig reduce defconfigs on PPC? Paging Uwe on this. This is the output of make savedefconfig. Martyn -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V2 0/2] powerpc: Add support for GE IMP3A
These patches add support for the GE IMP3A. This board (based on a Freescale P2020) uses some support for FPGA logic common with the PPC9A and other 86xx based boards, so this support has been moved out of the 86xx directory. A config option (GE_FPGA) has been added to reduce churn on dependant drivers (such as the watchdog timer) when further boards are added. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 1/4] powerpc: Add GE FPGA config option
This patch adds the GE_FPGA configuration option. This is being carried out as ground work to allow the PIC and GPIO drivers to be move from the powerpc 86xx platform directory to more general locations to allow them to be used on non-86xx boards and to reduce churn when further boards using these drivers are added. Signed-off-by: Martyn Welch martyn.we...@ge.com --- v3: Broken out from patch moving PIC and GPIO drivers arch/powerpc/platforms/86xx/Kconfig |7 +++ arch/powerpc/platforms/86xx/Makefile |7 --- drivers/watchdog/Kconfig |2 +- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 8d6599d..abe2c4f 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -39,6 +39,7 @@ config GEF_PPC9A select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select GE_FPGA help This option enables support for the GE PPC9A. @@ -48,6 +49,7 @@ config GEF_SBC310 select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select GE_FPGA help This option enables support for the GE SBC310. @@ -57,10 +59,15 @@ config GEF_SBC610 select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select GE_FPGA select HAS_RAPIDIO help This option enables support for the GE SBC610. +config GE_FPGA + bool + default n + endif config MPC8641 diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile index 4b0d7b1..ac6a50f 100644 --- a/arch/powerpc/platforms/86xx/Makefile +++ b/arch/powerpc/platforms/86xx/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o obj-$(CONFIG_SBC8641D) += sbc8641d.o obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o -obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y) -obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y) -obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o gef_pic.o $(gef-gpio-y) +obj-$(CONFIG_GE_FPGA) += gef_pic.o $(gef-gpio-y) +obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o +obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o +obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 877b107..2955c3f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1039,7 +1039,7 @@ config LANTIQ_WDT config GEF_WDT tristate GE Watchdog Timer - depends on GEF_SBC610 || GEF_SBC310 || GEF_PPC9A + depends on GE_FPGA ---help--- Watchdog timer found in a number of GE single board computers. -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 2/4] gpio: Move GE GPIO driver to reside within GPIO subsystem
The GE GPIO driver provides basic support (set direction, read/write state) for the GPIO provided on some GE single board computers. This patch moves the driver from the 86xx specific platform directrory to the GPIO subsystem so that it can be used on non-86xx boards. Signed-off-by: Martyn Welch martyn.we...@ge.com --- v3: Split out from patch moving PIC and GPIO driver. Moving to gpio subsystem instead of sysdev. arch/powerpc/configs/86xx/gef_ppc9a_defconfig |1 + arch/powerpc/configs/86xx/gef_sbc310_defconfig |1 + arch/powerpc/configs/86xx/gef_sbc610_defconfig |2 ++ arch/powerpc/platforms/86xx/Makefile |3 +-- drivers/gpio/Kconfig | 11 +++ drivers/gpio/Makefile |1 + .../86xx/gef_gpio.c = drivers/gpio/gpio-ge.c |2 +- 7 files changed, 18 insertions(+), 3 deletions(-) rename arch/powerpc/platforms/86xx/gef_gpio.c = drivers/gpio/gpio-ge.c (98%) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index d41857a..da731c2 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -131,6 +131,7 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GE_FPGA=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM92=y CONFIG_WATCHDOG=y diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig index 38303ec..2149360 100644 --- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig @@ -132,6 +132,7 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GE_FPGA=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM92=y CONFIG_WATCHDOG=y diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 9853397..af2e8e1 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -183,6 +183,8 @@ CONFIG_NVRAM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GE_FPGA=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM92=y CONFIG_WATCHDOG=y diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile index ac6a50f..1ee6ca8 100644 --- a/arch/powerpc/platforms/86xx/Makefile +++ b/arch/powerpc/platforms/86xx/Makefile @@ -7,8 +7,7 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o obj-$(CONFIG_SBC8641D) += sbc8641d.o obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o -gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o -obj-$(CONFIG_GE_FPGA) += gef_pic.o $(gef-gpio-y) +obj-$(CONFIG_GE_FPGA) += gef_pic.o obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d0c4118..0409cf3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -190,6 +190,17 @@ config GPIO_VX855 additional drivers must be enabled in order to use the functionality of the device. +config GPIO_GE_FPGA + bool GE FPGA based GPIO + depends on GE_FPGA + help + Support for common GPIO functionality provided on some GE Single Board + Computers. + + This driver provides basic support (configure as input or output, read + and write pin state) for GPIO implemented in a number of GE single + board computers. + comment I2C GPIO expanders: config GPIO_MAX7300 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fa10df6..9a8fb54 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o +obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o obj-$(CONFIG_GPIO_JANZ_TTL)+= gpio-janz-ttl.o obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/drivers/gpio/gpio-ge.c similarity index 98% rename from arch/powerpc/platforms/86xx/gef_gpio.c rename to drivers/gpio/gpio-ge.c index 2a70336..f8e6289 100644 --- a/arch/powerpc/platforms/86xx/gef_gpio.c +++ b/drivers/gpio/gpio-ge.c @@ -14,7 +14,7 @@ * * Configuration of output modes (totem-pole/open-drain) * Interrupt configuration - interrupts are always generated the FPGA relies on - * the I/O interrupt controllers mask to stop them propergating + * the I/O interrupt controllers mask to stop them propergating */ #include linux/kernel.h -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev
[PATCH v3 3/4] powerpc: Move GE PIC drivers
Move the GE PIC drivers to allow these to be used by non-86xx boards.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Move GPIO and PIC drivers to sysdev/ge/ rather than platforms/.
v3: Now just PIC driver. GPIO driver going to drivers/gpio.
arch/powerpc/platforms/86xx/Kconfig|4
arch/powerpc/platforms/86xx/Makefile |1 -
arch/powerpc/platforms/86xx/gef_ppc9a.c|2 +-
arch/powerpc/platforms/86xx/gef_sbc310.c |2 +-
arch/powerpc/platforms/86xx/gef_sbc610.c |2 +-
arch/powerpc/sysdev/Kconfig|4
arch/powerpc/sysdev/Makefile |2 ++
arch/powerpc/sysdev/ge/Makefile|1 +
.../86xx/gef_pic.c = sysdev/ge/ge_pic.c} |2 +-
.../86xx/gef_pic.h = sysdev/ge/ge_pic.h} |0
10 files changed, 11 insertions(+), 9 deletions(-)
create mode 100644 arch/powerpc/sysdev/ge/Makefile
rename arch/powerpc/{platforms/86xx/gef_pic.c = sysdev/ge/ge_pic.c} (99%)
rename arch/powerpc/{platforms/86xx/gef_pic.h = sysdev/ge/ge_pic.h} (100%)
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index abe2c4f..7a6279e 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -64,10 +64,6 @@ config GEF_SBC610
help
This option enables support for the GE SBC610.
-config GE_FPGA
- bool
- default n
-
endif
config MPC8641
diff --git a/arch/powerpc/platforms/86xx/Makefile
b/arch/powerpc/platforms/86xx/Makefile
index 1ee6ca8..ede815d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
-obj-$(CONFIG_GE_FPGA) += gef_pic.o
obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c
b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 60ce07e..ed58b6c 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c
b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 3ecee25..710db69 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c
b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 5090d60..4a13d2f 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7b4df37..a84fecf 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -29,3 +29,7 @@ config SCOM_DEBUGFS
bool Expose SCOM controllers via debugfs
depends on PPC_SCOM
default n
+
+config GE_FPGA
+ bool
+ default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5e37b47..f80ff9f 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -65,3 +65,5 @@ obj-$(CONFIG_PPC_SCOM)+= scom.o
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
obj-$(CONFIG_PPC_XICS) += xics/
+
+obj-$(CONFIG_GE_FPGA) += ge/
diff --git a/arch/powerpc/sysdev/ge/Makefile b/arch/powerpc/sysdev/ge/Makefile
new file mode 100644
index 000..8731ffc
--- /dev/null
+++ b/arch/powerpc/sysdev/ge/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_GE_FPGA) += ge_pic.o
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c
b/arch/powerpc/sysdev/ge/ge_pic.c
similarity index 99%
rename from arch/powerpc/platforms/86xx/gef_pic.c
rename to arch/powerpc/sysdev/ge/ge_pic.c
index 94594e5..002a562 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/sysdev/ge/ge_pic.c
@@ -22,7 +22,7 @@
#include asm/prom.h
#include asm/irq.h
-#include gef_pic.h
+#include ge_pic.h
#define DEBUG
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h
b/arch/powerpc/sysdev/ge/ge_pic.h
similarity index 100%
rename from arch/powerpc/platforms/86xx/gef_pic.h
rename to arch/powerpc/sysdev/ge/ge_pic.h
--
1.7.0.4
___
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[PATCH v3 4/4] powerpc: Board support for GE IMP3A
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
processor.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Rebase patch onto powerpc/next, taking work by Kyle Moffett into
account.
v3: Correct detection of interrupt controller.
arch/powerpc/boot/dts/ge_imp3a.dts | 255 ++
arch/powerpc/configs/ge_imp3a_defconfig | 257 +++
arch/powerpc/platforms/85xx/Kconfig | 15 ++
arch/powerpc/platforms/85xx/Makefile|1 +
arch/powerpc/platforms/85xx/ge_imp3a.c | 246 +
drivers/gpio/gpio-ge.c | 28
6 files changed, 802 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/ge_imp3a.dts
create mode 100644 arch/powerpc/configs/ge_imp3a_defconfig
create mode 100644 arch/powerpc/platforms/85xx/ge_imp3a.c
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts
b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 000..fefae41
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,255 @@
+/*
+ * GE IMP3A Device Tree Source
+ *
+ * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ fsl/p2020si-pre.dtsi
+
+/ {
+ model = GE_IMP3A;
+ compatible = ge,imp3a;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@fef05000 {
+ reg = 0 0xfef05000 0 0x1000;
+
+ ranges = 0x0 0x0 0x0 0xff00 0x0100
+ 0x1 0x0 0x0 0xe000 0x0800
+ 0x2 0x0 0x0 0xe800 0x0800
+ 0x3 0x0 0x0 0xfc10 0x0002
+ 0x4 0x0 0x0 0xfc00 0x8000
+ 0x5 0x0 0x0 0xfc008000 0x8000
+ 0x6 0x0 0x0 0xfee0 0x0004
+ 0x7 0x0 0x0 0xfee8 0x0004;
+
+ /* nor@0,0 is a mirror of part of the memory in nor@1,0
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ nor@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = user;
+ reg = 0x0 0x780;
+ };
+
+ partition@780 {
+ label = firmware;
+ reg = 0x780 0x80;
+ read-only;
+ };
+ };
+
+ nvram@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
+ fpga@4,0 {
+ compatible = ge,imp3a-fpga-regs;
+ reg = 0x4 0x0 0x20;
+ };
+
+ gef_pic: pic@4,20 {
+ #interrupt-cells = 1;
+ interrupt-controller;
+ device_type = interrupt-controller;
+ compatible = ge,imp3a-fpga-pic, gef,fpga-pic-1.00;
+ reg = 0x4 0x20 0x20;
+ interrupts = 6 7 0 0;
+ };
+
+ gef_gpio: gpio@4,400 {
+ #gpio-cells = 2;
+ compatible = ge,imp3a-gpio;
+ reg = 0x4 0x400 0x24;
+ gpio-controller;
+ };
+
+ wdt@4,800 {
+ compatible = ge,imp3a-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
+ reg = 0x4 0x800 0x8;
+ interrupts = 10 4;
+ interrupt-parent = gef_pic;
+ };
+
+ /* Second watchdog available, driver currently
[PATCH V2 0/2] powerpc: Add support for GE IMP3A
These patches add support for the GE IMP3A. This board (based on a Freescale P2020) uses some support for FPGA logic common with the PPC9A and other 86xx based boards, so this support has been moved out of the 86xx directory. A config option (GE_FPGA) has been added to reduce churn on dependant drivers (such as the watchdog timer) when further boards are added. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V2 1/2] powerpc: Move GE GPIO and PIC drivers
Move the GE GPIO and PIC drivers to allow these to be used by non-86xx
boards.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Move GPIO and PIC drivers to sysdev/ge/ rather than platforms/.
arch/powerpc/platforms/86xx/Kconfig|3 +++
arch/powerpc/platforms/86xx/Makefile |7 +++
arch/powerpc/platforms/86xx/gef_ppc9a.c|2 +-
arch/powerpc/platforms/86xx/gef_sbc310.c |2 +-
arch/powerpc/platforms/86xx/gef_sbc610.c |2 +-
arch/powerpc/sysdev/Kconfig|7 +++
arch/powerpc/sysdev/Makefile |2 ++
arch/powerpc/sysdev/ge/Makefile|2 ++
.../86xx/gef_gpio.c = sysdev/ge/ge_gpio.c}|2 +-
.../86xx/gef_pic.c = sysdev/ge/ge_pic.c} |2 +-
.../86xx/gef_pic.h = sysdev/ge/ge_pic.h} |0
drivers/watchdog/Kconfig |2 +-
12 files changed, 23 insertions(+), 10 deletions(-)
create mode 100644 arch/powerpc/sysdev/ge/Makefile
rename arch/powerpc/{platforms/86xx/gef_gpio.c = sysdev/ge/ge_gpio.c} (98%)
rename arch/powerpc/{platforms/86xx/gef_pic.c = sysdev/ge/ge_pic.c} (99%)
rename arch/powerpc/{platforms/86xx/gef_pic.h = sysdev/ge/ge_pic.h} (100%)
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index 8d6599d..2015022 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -39,6 +39,7 @@ config GEF_PPC9A
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE PPC9A.
@@ -48,6 +49,7 @@ config GEF_SBC310
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE SBC310.
@@ -58,6 +60,7 @@ config GEF_SBC610
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAS_RAPIDIO
+ select GE_FPGA
help
This option enables support for the GE SBC610.
diff --git a/arch/powerpc/platforms/86xx/Makefile
b/arch/powerpc/platforms/86xx/Makefile
index 4b0d7b1..ede815d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
-gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
-obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o gef_pic.o $(gef-gpio-y)
+obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
+obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
+obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c
b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 60ce07e..ed58b6c 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c
b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 3ecee25..710db69 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c
b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 5090d60..4a13d2f 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -37,9 +37,9 @@
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
+#include sysdev/ge/ge_pic.h
#include mpc86xx.h
-#include gef_pic.h
#undef DEBUG
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7b4df37..cd0ef0b 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -29,3 +29,10 @@ config SCOM_DEBUGFS
bool Expose SCOM controllers via debugfs
depends on PPC_SCOM
default n
+
+config GE_FPGA
+ bool
+ default n
+ help
+ Support for common GPIO and interrupt routing functionality provided
+ on some GE Single Board Computers.
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5e37b47..f80ff9f 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -65,3 +65,5 @@ obj-$(CONFIG_PPC_SCOM)+= scom.o
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
obj-$(CONFIG_PPC_XICS) += xics/
+
+obj-$(CONFIG_GE_FPGA) += ge
[PATCH V2 2/2] powerpc: Board support for GE IMP3A
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
processor.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Rebase patch onto powerpc/next, taking work by Kyle Moffett into
account.
arch/powerpc/boot/dts/ge_imp3a.dts | 254 ++
arch/powerpc/configs/ge_imp3a_defconfig | 256 +++
arch/powerpc/platforms/85xx/Kconfig | 15 ++
arch/powerpc/platforms/85xx/Makefile|1 +
arch/powerpc/platforms/85xx/ge_imp3a.c | 246 +
arch/powerpc/sysdev/ge/ge_gpio.c| 28
6 files changed, 800 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/ge_imp3a.dts
create mode 100644 arch/powerpc/configs/ge_imp3a_defconfig
create mode 100644 arch/powerpc/platforms/85xx/ge_imp3a.c
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts
b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 000..f30fadb
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,254 @@
+/*
+ * GE IMP3A Device Tree Source
+ *
+ * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ fsl/p2020si-pre.dtsi
+
+/ {
+ model = GE_IMP3A;
+ compatible = ge,imp3a;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@fef05000 {
+ reg = 0 0xfef05000 0 0x1000;
+
+ ranges = 0x0 0x0 0x0 0xff00 0x0100
+ 0x1 0x0 0x0 0xe000 0x0800
+ 0x2 0x0 0x0 0xe800 0x0800
+ 0x3 0x0 0x0 0xfc10 0x0002
+ 0x4 0x0 0x0 0xfc00 0x8000
+ 0x5 0x0 0x0 0xfc008000 0x8000
+ 0x6 0x0 0x0 0xfee0 0x0004
+ 0x7 0x0 0x0 0xfee8 0x0004;
+
+ /* nor@0,0 is a mirror of part of the memory in nor@1,0
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ nor@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = user;
+ reg = 0x0 0x780;
+ };
+
+ partition@780 {
+ label = firmware;
+ reg = 0x780 0x80;
+ read-only;
+ };
+ };
+
+ nvram@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
+ fpga@4,0 {
+ compatible = ge,imp3a-fpga-regs;
+ reg = 0x4 0x0 0x20;
+ };
+
+ gef_pic: pic@4,20 {
+ #interrupt-cells = 1;
+ interrupt-controller;
+ compatible = ge,imp3a-fpga-pic, gef,fpga-pic-1.00;
+ reg = 0x4 0x20 0x20;
+ interrupts = 6 7 0 0;
+ };
+
+ gef_gpio: gpio@4,400 {
+ #gpio-cells = 2;
+ compatible = ge,imp3a-gpio;
+ reg = 0x4 0x400 0x24;
+ gpio-controller;
+ };
+
+ wdt@4,800 {
+ compatible = ge,imp3a-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
+ reg = 0x4 0x800 0x8;
+ interrupts = 10 4;
+ interrupt-parent = gef_pic;
+ };
+
+ /* Second watchdog available, driver currently supports one.
+ wdt@4,808 {
+ compatible = gef,imp3a-fpga-wdt, gef,fpga-wdt
Re: [PATCH 1/2] powerpc: Move GE GPIO and PIC drivers
On 26/02/12 23:37, Benjamin Herrenschmidt wrote: On Tue, 2012-02-07 at 11:28 +, Martyn Welch wrote: Move the GE GPIO and PIC drivers to allow these to be used by non-86xx boards. Hi, Sorry for the late review... No problem, thanks for the review! Signed-off-by: Martyn Welch martyn.we...@ge.com --- arch/powerpc/platforms/86xx/Kconfig |3 + arch/powerpc/platforms/86xx/Makefile |7 +- arch/powerpc/platforms/86xx/gef_gpio.c | 171 arch/powerpc/platforms/86xx/gef_pic.c| 252 -- arch/powerpc/platforms/86xx/gef_pic.h| 11 -- arch/powerpc/platforms/86xx/gef_ppc9a.c |3 +- arch/powerpc/platforms/86xx/gef_sbc310.c |3 +- arch/powerpc/platforms/86xx/gef_sbc610.c |3 +- arch/powerpc/platforms/Kconfig |7 + arch/powerpc/platforms/Makefile |3 + arch/powerpc/platforms/ge_gpio.c | 171 arch/powerpc/platforms/ge_pic.c | 252 ++ arch/powerpc/platforms/ge_pic.h | 11 ++ So I don't like having files showing up there. In fact, I want to move the only other one here, it's not the right place for it (fsl_uli1575.c). This patch (or one like it) has been around for a while now. Kumar wanted me to put them here rather than sysdev[1], but I'm easy either way. Please contemplate using arch/powerpc/sysdev instead. Maybe make a subdir in there (geip or something like that ?) I'd rather avoid geip (we seem to have a habit of renaming divisions), would ge be acceptable? Also, use git mv so that the file moves appear as such in the history, this will make review easier by clearly separating the move from actual changes to the files. Hmm, thought I'd done that. Will try again. Martyn [1] http://old.nabble.com/GE-GPIO-and-PIC-support.-td27212938.html -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.we...@ge.com | VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/2] powerpc: Add support for GE IMP3A
These patches add support for the GE IMP3A. This board (based on a Freescale P2020) uses some support for FPGA logic common with the PPC9A and other 86xx based boards, so this support has been moved out of the 86xx directory. A config option (GE_FPGA) has been added to reduce churn on dependant drivers (such as the watchdog timer) when further boards are added. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: Move GE GPIO and PIC drivers
Move the GE GPIO and PIC drivers to allow these to be used by non-86xx
boards.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
arch/powerpc/platforms/86xx/Kconfig |3 +
arch/powerpc/platforms/86xx/Makefile |7 +-
arch/powerpc/platforms/86xx/gef_gpio.c | 171
arch/powerpc/platforms/86xx/gef_pic.c| 252 --
arch/powerpc/platforms/86xx/gef_pic.h| 11 --
arch/powerpc/platforms/86xx/gef_ppc9a.c |3 +-
arch/powerpc/platforms/86xx/gef_sbc310.c |3 +-
arch/powerpc/platforms/86xx/gef_sbc610.c |3 +-
arch/powerpc/platforms/Kconfig |7 +
arch/powerpc/platforms/Makefile |3 +
arch/powerpc/platforms/ge_gpio.c | 171
arch/powerpc/platforms/ge_pic.c | 252 ++
arch/powerpc/platforms/ge_pic.h | 11 ++
drivers/watchdog/Kconfig |2 +-
14 files changed, 457 insertions(+), 442 deletions(-)
delete mode 100644 arch/powerpc/platforms/86xx/gef_gpio.c
delete mode 100644 arch/powerpc/platforms/86xx/gef_pic.c
delete mode 100644 arch/powerpc/platforms/86xx/gef_pic.h
create mode 100644 arch/powerpc/platforms/ge_gpio.c
create mode 100644 arch/powerpc/platforms/ge_pic.c
create mode 100644 arch/powerpc/platforms/ge_pic.h
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index 8d6599d..2015022 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -39,6 +39,7 @@ config GEF_PPC9A
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE PPC9A.
@@ -48,6 +49,7 @@ config GEF_SBC310
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE SBC310.
@@ -58,6 +60,7 @@ config GEF_SBC610
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAS_RAPIDIO
+ select GE_FPGA
help
This option enables support for the GE SBC610.
diff --git a/arch/powerpc/platforms/86xx/Makefile
b/arch/powerpc/platforms/86xx/Makefile
index 4b0d7b1..ede815d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
-gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
-obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o gef_pic.o $(gef-gpio-y)
+obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
+obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
+obj-$(CONFIG_GEF_PPC9A)+= gef_ppc9a.o
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c
b/arch/powerpc/platforms/86xx/gef_gpio.c
deleted file mode 100644
index 2a70336..000
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Driver for GE FPGA based GPIO
- *
- * Author: Martyn Welch martyn.we...@ge.com
- *
- * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed as is without any warranty of any
- * kind, whether express or implied.
- */
-
-/* TODO
- *
- * Configuration of output modes (totem-pole/open-drain)
- * Interrupt configuration - interrupts are always generated the FPGA relies on
- * the I/O interrupt controllers mask to stop them propergating
- */
-
-#include linux/kernel.h
-#include linux/compiler.h
-#include linux/init.h
-#include linux/io.h
-#include linux/of.h
-#include linux/of_device.h
-#include linux/of_platform.h
-#include linux/of_gpio.h
-#include linux/gpio.h
-#include linux/slab.h
-#include linux/module.h
-
-#define GEF_GPIO_DIRECT0x00
-#define GEF_GPIO_IN0x04
-#define GEF_GPIO_OUT 0x08
-#define GEF_GPIO_TRIG 0x0C
-#define GEF_GPIO_POLAR_A 0x10
-#define GEF_GPIO_POLAR_B 0x14
-#define GEF_GPIO_INT_STAT 0x18
-#define GEF_GPIO_OVERRUN 0x1C
-#define GEF_GPIO_MODE 0x20
-
-static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
-{
- unsigned int data;
-
- data = ioread32be(reg);
- /* value: 0=low; 1=high */
- if (value 0x1)
- data = data | (0x1 offset);
- else
- data = data ~(0x1 offset);
-
- iowrite32be(data, reg);
-}
-
-
-static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-{
- unsigned int data;
- struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
- data = ioread32be
[PATCH 2/2] powerpc: Board support for GE IMP3A
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
processor.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
arch/powerpc/boot/dts/ge_imp3a.dts | 254 ++
arch/powerpc/configs/ge_imp3a_defconfig | 256 ++
arch/powerpc/platforms/85xx/Kconfig | 12 ++
arch/powerpc/platforms/85xx/Makefile|1 +
arch/powerpc/platforms/85xx/ge_imp3a.c | 258 +++
arch/powerpc/platforms/ge_gpio.c| 28
6 files changed, 809 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/ge_imp3a.dts
create mode 100644 arch/powerpc/configs/ge_imp3a_defconfig
create mode 100644 arch/powerpc/platforms/85xx/ge_imp3a.c
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts
b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 000..f30fadb
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,254 @@
+/*
+ * GE IMP3A Device Tree Source
+ *
+ * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ fsl/p2020si-pre.dtsi
+
+/ {
+ model = GE_IMP3A;
+ compatible = ge,imp3a;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@fef05000 {
+ reg = 0 0xfef05000 0 0x1000;
+
+ ranges = 0x0 0x0 0x0 0xff00 0x0100
+ 0x1 0x0 0x0 0xe000 0x0800
+ 0x2 0x0 0x0 0xe800 0x0800
+ 0x3 0x0 0x0 0xfc10 0x0002
+ 0x4 0x0 0x0 0xfc00 0x8000
+ 0x5 0x0 0x0 0xfc008000 0x8000
+ 0x6 0x0 0x0 0xfee0 0x0004
+ 0x7 0x0 0x0 0xfee8 0x0004;
+
+ /* nor@0,0 is a mirror of part of the memory in nor@1,0
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ nor@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = ge,imp3a-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = user;
+ reg = 0x0 0x780;
+ };
+
+ partition@780 {
+ label = firmware;
+ reg = 0x780 0x80;
+ read-only;
+ };
+ };
+
+ nvram@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
+ fpga@4,0 {
+ compatible = ge,imp3a-fpga-regs;
+ reg = 0x4 0x0 0x20;
+ };
+
+ gef_pic: pic@4,20 {
+ #interrupt-cells = 1;
+ interrupt-controller;
+ compatible = ge,imp3a-fpga-pic, gef,fpga-pic-1.00;
+ reg = 0x4 0x20 0x20;
+ interrupts = 6 7 0 0;
+ };
+
+ gef_gpio: gpio@4,400 {
+ #gpio-cells = 2;
+ compatible = ge,imp3a-gpio;
+ reg = 0x4 0x400 0x24;
+ gpio-controller;
+ };
+
+ wdt@4,800 {
+ compatible = ge,imp3a-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
+ reg = 0x4 0x800 0x8;
+ interrupts = 10 4;
+ interrupt-parent = gef_pic;
+ };
+
+ /* Second watchdog available, driver currently supports one.
+ wdt@4,808 {
+ compatible = gef,imp3a-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
+ reg
Re: spi device from handle
On 12/01/12 16:02, Michael Remski wrote:
kernel 2.6.33
relevant section of dts has:
spi@7000 {
fpga0: fpga@0 {
#address-cells = 1;
#size-cells = 0;
compatible = fsl, espi-fpga;
reg = 0;
linux,modalias = spidev;
spi-max-frequency = 1572864;
};
}
I have another device driver that needs to talk to this fpga device, but for
the life of me I can't figure out the appropriate hooks to get there. The
device can be talked to from userland via /dev/spixyx.k, but how do I get to
the device from another driver?
Any little hints would be appreciated. Upgrading kernel is not an option
(sorry).
We have a FPGA that provides a number of different functions. Each function is
provided in a distinct register set. We have multiple entries in the DTS, one
for each piece of functionality. The drivers are then able to bind separately
against the required registers. So in the case of
arch/powerpc/boot/dts/gef_ppc9a.dts, fpga@4,0, wdt@4,2000, wdt@4,2010,
pic@4,4000 and gpio@7,14000 are all provided by the same FPGA and each has
it's own driver. However, I've just realised our FPGA is memory mapped and
looking at your DTS snippet yours isn't.
The only clean way I can think about doing it via spi would be to have a
driver that provides an in-kernel interface to access the functionality in the
FPGA (which binds to this entry in the DTS), then modify the driver providing
the user space access to use that and also use that interface for other
drivers needing access to the FPGA. Depending on the level of extrapolation
provided by the existing user space driver, this may be possible without
breaking anything in user space.
Martyn
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Re: [PATCH] powerpc/fsl: update compatiable on fsl 16550 uart nodes
On 08/12/11 06:45, Kumar Gala wrote:
The Freescale serial port's are pretty much a 16550, however there are
some FSL specific bugs and features. Add a fsl,ns16550 compatiable
string to allow code to handle those FSL specific issues.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
For what it's worth, for the gef_ppc9a, gef_sbc310 gef_sbc610:
Acked-by: Martyn Welch martyn.we...@ge.com
---
arch/powerpc/boot/dts/asp834x-redboot.dts|4 ++--
arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi |4 ++--
arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi |4 ++--
arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi |4 ++--
arch/powerpc/boot/dts/gef_ppc9a.dts |4 ++--
arch/powerpc/boot/dts/gef_sbc310.dts |4 ++--
arch/powerpc/boot/dts/gef_sbc610.dts |4 ++--
arch/powerpc/boot/dts/kmeter1.dts|2 +-
arch/powerpc/boot/dts/kuroboxHD.dts |4 ++--
arch/powerpc/boot/dts/kuroboxHG.dts |4 ++--
arch/powerpc/boot/dts/mpc8308_p1m.dts|4 ++--
arch/powerpc/boot/dts/mpc8308rdb.dts |4 ++--
arch/powerpc/boot/dts/mpc8313erdb.dts|4 ++--
arch/powerpc/boot/dts/mpc8315erdb.dts|4 ++--
arch/powerpc/boot/dts/mpc832x_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc832x_rdb.dts|4 ++--
arch/powerpc/boot/dts/mpc8349emitx.dts |4 ++--
arch/powerpc/boot/dts/mpc8349emitxgp.dts |4 ++--
arch/powerpc/boot/dts/mpc834x_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc836x_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc836x_rdk.dts|4 ++--
arch/powerpc/boot/dts/mpc8377_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc8377_rdb.dts|4 ++--
arch/powerpc/boot/dts/mpc8377_wlan.dts |4 ++--
arch/powerpc/boot/dts/mpc8378_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc8378_rdb.dts|4 ++--
arch/powerpc/boot/dts/mpc8379_mds.dts|4 ++--
arch/powerpc/boot/dts/mpc8379_rdb.dts|4 ++--
arch/powerpc/boot/dts/mpc8540ads.dts |4 ++--
arch/powerpc/boot/dts/mpc8541cds.dts |4 ++--
arch/powerpc/boot/dts/mpc8555cds.dts |4 ++--
arch/powerpc/boot/dts/mpc8610_hpcd.dts |4 ++--
arch/powerpc/boot/dts/mpc8641_hpcn.dts |4 ++--
arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts |4 ++--
arch/powerpc/boot/dts/sbc8349.dts|4 ++--
arch/powerpc/boot/dts/sbc8548.dts|4 ++--
arch/powerpc/boot/dts/sbc8641d.dts |4 ++--
arch/powerpc/boot/dts/socrates.dts |4 ++--
arch/powerpc/boot/dts/storcenter.dts |4 ++--
arch/powerpc/boot/dts/stxssa8555.dts |4 ++--
arch/powerpc/boot/dts/tqm8540.dts|4 ++--
arch/powerpc/boot/dts/tqm8541.dts|4 ++--
arch/powerpc/boot/dts/tqm8548-bigflash.dts |4 ++--
arch/powerpc/boot/dts/tqm8548.dts|4 ++--
arch/powerpc/boot/dts/tqm8555.dts|4 ++--
arch/powerpc/boot/dts/xcalibur1501.dts |4 ++--
arch/powerpc/boot/dts/xpedite5200.dts|4 ++--
arch/powerpc/boot/dts/xpedite5200_xmon.dts |4 ++--
arch/powerpc/boot/dts/xpedite5301.dts|4 ++--
arch/powerpc/boot/dts/xpedite5330.dts|4 ++--
arch/powerpc/boot/dts/xpedite5370.dts|4 ++--
51 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts
b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 261d10c..227290d 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -256,7 +256,7 @@
serial0: serial@4500 {
cell-index = 0;
device_type = serial;
- compatible = ns16550;
+ compatible = fsl,ns16550, ns16550;
reg = 0x4500 0x100;
clock-frequency = 4;
interrupts = 9 0x8;
@@ -266,7 +266,7 @@
serial1: serial@4600 {
cell-index = 1;
device_type = serial;
- compatible = ns16550;
+ compatible = fsl,ns16550, ns16550;
reg = 0x4600 0x100;
clock-frequency = 4;
interrupts = 10 0x8;
diff --git a/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
index 00fa1fd..5e268fd 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -35,7 +35,7 @@
serial0: serial@4500 {
cell-index = 0;
device_type = serial;
- compatible = ns16550;
+ compatible = fsl,ns16550, ns16550;
reg = 0x4500 0x100;
clock-frequency = 0;
interrupts = 42 2 0 0;
@@ -44,7 +44,7 @@ serial0: serial@4500
[PATCH] powerpc/86xx: Correct Gianfar support for GE boards
The GE DTBs were not updated when the Gianfar driver was converted to an
of_platform_driver in commit b31a1d8b41513b96e9c7ec2f68c5734cef0b26a4. Update
the DTBs, adding the required TBI entries.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 33 +
arch/powerpc/boot/dts/gef_sbc310.dts | 33 +
arch/powerpc/boot/dts/gef_sbc610.dts | 33 +
3 files changed, 87 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 83f4b79..2266bbb 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -269,14 +269,16 @@
enet0: ethernet@24000 {
#address-cells = 1;
#size-cells = 1;
+ cell-index = 0;
device_type = network;
- model = eTSEC;
+ model = TSEC;
compatible = gianfar;
reg = 0x24000 0x1000;
ranges = 0x0 0x24000 0x1000;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = 0x1d 0x2 0x1e 0x2 0x22 0x2;
+ interrupts = 29 2 30 2 34 2;
interrupt-parent = mpic;
+ tbi-handle = tbi0;
phy-handle = phy0;
phy-connection-type = gmii;
@@ -290,25 +292,48 @@
interrupt-parent = gef_pic;
interrupts = 0x9 0x4;
reg = 1;
+ device_type = ethernet-phy;
};
phy2: ethernet-phy@2 {
interrupt-parent = gef_pic;
interrupts = 0x8 0x4;
reg = 3;
+ device_type = ethernet-phy;
+ };
+ tbi0: tbi-phy@11 {
+ reg = 0x11;
+ device_type = tbi-phy;
};
};
};
enet1: ethernet@26000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ cell-index = 2;
device_type = network;
- model = eTSEC;
+ model = TSEC;
compatible = gianfar;
reg = 0x26000 0x1000;
+ ranges = 0x0 0x26000 0x1000;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = 0x1f 0x2 0x20 0x2 0x21 0x2;
+ interrupts = 31 2 32 2 33 2;
interrupt-parent = mpic;
+ tbi-handle = tbi2;
phy-handle = phy2;
phy-connection-type = gmii;
+
+ mdio@520 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,gianfar-tbi;
+ reg = 0x520 0x20;
+
+ tbi2: tbi-phy@11 {
+ reg = 0x11;
+ device_type = tbi-phy;
+ };
+ };
};
serial0: serial@4500 {
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index fc3a331..429e87d 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -267,14 +267,16 @@
enet0: ethernet@24000 {
#address-cells = 1;
#size-cells = 1;
+ cell-index = 0;
device_type = network;
- model = eTSEC;
+ model = TSEC;
compatible = gianfar;
reg = 0x24000 0x1000;
ranges = 0x0 0x24000 0x1000;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = 0x1d 0x2 0x1e 0x2 0x22 0x2;
+ interrupts = 29 2 30 2 34 2;
interrupt-parent = mpic;
+ tbi-handle = tbi0;
phy-handle = phy0;
phy-connection-type = gmii;
@@ -288,25 +290,48 @@
interrupt-parent = gef_pic;
interrupts = 0x9 0x4
Re: [PATCH] STAGING: Comedi: Build only on arches providing PAGE_KERNEL_NOCACHE
On 23/06/11 13:02, Ralf Baechle wrote:
On Thu, Jun 23, 2011 at 12:53:36PM +0100, Martyn Welch wrote:
On 23/06/11 12:45, Ralf Baechle wrote:
On architectures that don't define PAGE_KERNEL_NOCACHE, the Comedi driver
turns
into tragedy:
CC [M] drivers/staging/comedi/drivers.o
drivers/staging/comedi/drivers.c: In function ‘comedi_buf_alloc’:
drivers/staging/comedi/drivers.c:505:41: error: ‘PAGE_KERNEL_NOCACHE’
undeclared (first use in this function)
drivers/staging/comedi/drivers.c:505:41: note: each undeclared identifier
is rep orted only once for each function it appears in
make[3]: *** [drivers/staging/comedi/drivers.o] Error 1
Restrict the driver to only those architectures that define
PAGE_KERNEL_NOCACHE.
PAGE_KERNEL_NOCACHE is a kludge - some system architectures such as SGI IP27
are even uable to offer uncached operation - at least in the way an
unwitting
driver might assume. I haven't looked in details how the driver is using
the area vmaped with PAGE_KERNEL_NOCACHE but maybe doing it XFS-style using
cached memory and the flush_kernel_vmap_range / invalidate_kernel_vmap_range
APIs in conjunction with the DMA API is a practical alternative.
Signed-off-by: Ralf Baechle r...@linux-mips.org
drivers/staging/comedi/Kconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/staging/comedi/Kconfig b/drivers/staging/comedi/Kconfig
index 1502d80..bccdc12 100644
--- a/drivers/staging/comedi/Kconfig
+++ b/drivers/staging/comedi/Kconfig
@@ -2,6 +2,7 @@ config COMEDI
tristate Data acquisition support (comedi)
default N
depends on m
+ depends on BROKEN || FRV || M32R || MN10300 || SUPERH || TILE || X86
I'm sure I got comedi to compile on a 32-bit PPC board not that long ago. Has
something changed, or is this just not an exhaustive list?
(Adding the PPC folks to cc.)
A git grep -w PAGE_KERNEL_NOCACHE arch/powerpc/ doesn't find anything so
I don't think the driver will build there. I don't have a PPC toolchain
to verify that.
Ah, just found the tree looks like I had a little patch to make it seemingly
work, though it will make it not work for most other archs at a guess (it
may not even be right on PPC):
diff --git a/drivers/staging/comedi/drivers.c b/drivers/staging/comedi/drivers.c
index 44d6b62..263ad3d 100644
--- a/drivers/staging/comedi/drivers.c
+++ b/drivers/staging/comedi/drivers.c
@@ -505,7 +505,7 @@ int comedi_buf_alloc(struct comedi_device *dev, struct
comedi_subdevice *s,
}
if (i == n_pages) {
async-prealloc_buf =
- vmap(pages, n_pages, VM_MAP, PAGE_KERNEL_NOCACHE);
+ vmap(pages, n_pages, VM_MAP, PAGE_KERNEL_NC);
}
vfree(pages);
(Sorry for the wrapping)
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Re: GPIO MPC8315 board
On 22/06/11 09:56, Vasanth Ragavendran wrote:
Hi
I am using a MPC8315ERDB board. For this i've an external button which is
connected to GPIO pin 7 of the board. And if this button is pressed then
certain files have to be deleted. Browsing through the internet i found that
GPIO drivers have to be included into the kernel and hence i set a 'y' to
CONFIG_MPC8xxx_GPIO, CONFIG_GPIO_SYSFS and CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB
etc. And the dts file has be modified to include the following lines
gpio1: gpio-controller@c00 {
#gpio-cells = 2;
compatible = fsl,mpc8315-gpio, fsl,mpc8349-gpio;
reg = 0xc00 0x100;
interrupts = 74 0x8;
interrupt-parent = ipic;
gpio-controller; };
this is included under immr@e000.
further i included
erase-button@0 {
compatible = erase-button;
interrupts = 7 2;
interrupt-parent = gpio1;
};
am i right in including this? coz after compiling the kernel i get a folder
under /sys/class/gpio. I did an export using
echo 224 /sys/class/gpio/export.
224 was the number appearing in gpiochip224/base.
It created another folder gpio224.
However i'm not able to set the value in them nor the direction.
echo 1 /sys/class/gpio/gpio224/value
cat /sys/class/gpio/gpio224/value
returns a value of 0 only.
however the direction is in
cat /sys/class/gpio/gpio224/direction
in
echo out /sys/class/gpio/gpio224/direction
Martyn
Am i doing it correctly? How to check it programatically if the button is
pressed and take the corresponding action! Plz help!
My kernel version is 2.6.35.9.
Thanking you in advance.
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Re: known working sata_sil24.c setup on powerpc platforms?
On 06/04/11 18:00, Leon Woestenberg wrote: Hello, after investigating problems with sata_sil24.c on a freescale p2020 soc, I wonder if this driver works on powerpc at all? Does anyone know of a working setup of sata_sil24 on a big endian powerpc system? Yes, I think we even use it on a p2020 board, though I think our current kernel on that product is 2.6.34. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748 | Barbirolli Square, Manchester, E martyn.we...@ge.com | M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Getting the IRQ number (Was: Basic driver devel questions ?)
On 03/12/10 14:58, Guillaume Dargaud wrote: Why is there not a word about the functions platform_*_register in my various driver books ? LDD 3rd ed (O'Reilly), Writing LDD (Cooperstein) or LKD (Love)... Is it something specific to powerpc and the books are oriented x86 ? What's a good source, besides grepping the kernel to no end ? I have yet to find a Linux Device Driver book that isn't heavily skewed towards x86. Some of this stuff is either specific to powerpc or relevant a subset of non-x86 platforms. I think Google, the linuxppc-dev mailing list, related IRC channel and lxr.linux.no have been the sources I've mostly used learning about Linux on powerpc. -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc: reduce the size of the defconfigs
Uwe Kleine-König wrote: On Tue, Jul 13, 2010 at 05:09:45PM +1000, Stephen Rothwell wrote: This uses Uwe's script (modified by Olof Johansson to speed it up somewhat) to reduce the size of all the powerpc defconfigs. The resulting IMHO we should add the script to the source, too. And if it's only for me to see Olof's optimisation. :-) As the person who introduced the gef_* PPC defconfigs to the kernel (I understood this to be best practice), I'm happy to go along with whatever - as long as I can build a bootable kernel from the mainline kernel. I think I understand Linus' wish not to see all the defconfig churn (I get fed up diffing defconfigs, just to read through loads of additions and removals of undef'ed entires from just the few configs I'm interested in). I assume I'm not alone among those attempting to add board support to the mainline kernel in not being able to keep up with the LKML mailing list and therefore have missed most of this discussion (think I've managed to read some of it now). I would very much appreciate some documentation / guidance on how to use this script - preferably provided as a comment in the head of the script or/and some pointers in Documentation/. Martyn files have been verified to produce the same .config files by generating them before and after this patch and comparing the results. Signed-off-by: Stephen Rothwell s...@canb.auug.org.au --- 100 files changed, 51 insertions(+), 133815 deletions(-) Nice. Best regards Uwe -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] rtc: add support for DS3232 RTC
Zang Roy-R61911 wrote: -Original Message- From: Jean Delvare [mailto:kh...@linux-fr.org] Sent: Monday, July 05, 2010 15:23 PM To: Zang Roy-R61911 Cc: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Hu Mingkai-B21284; Srinivasan Srikanth-R9AABP Subject: Re: [PATCH] rtc: add support for DS3232 RTC Hi Roy, On Mon, 5 Jul 2010 14:45:26 +0800, Roy Zang wrote: This patch adds the driver for RTC chip DS3232 via I2C bus Signed-off-by: Mingkai Hu mingkai...@freescale.com Signed-off-by: Jingchang Lu b22...@freescale.com Signed-off-by: Srikanth Srinivasan srikanth.sriniva...@freescale.com Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- Tested on MPC8536DS and P4080DS board drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile |1 + drivers/rtc/rtc-ds3232.c | 466 ++ 3 files changed, 478 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/rtc-ds3232.c You're sending this patch to the wrong list. Please read MAINTAINERS again. Does linux-...@vger.kernel.org is the correct mail list? The rtc device is on the i2c bus. Roy I think the RTC mailing list is probably a little more appropriate... Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
CPM UART on MPC8270
Hi All,
I'm attempting to get an SCC port on an MPC8270 working with Linux. I'm
not overly familiar with the CPM and am having a bit of trouble.
Linux is booting natively on the 8270. I have access to the 8270 via a
set of PCI windows from a second core (includes one setup over the main
memory and one over the IMMR) and SMC1 is up and working with a console.
The SCCs seem to be detected correctly at boot:
f011a80.serial: ttyCPM0 at MMIO 0xc3014a80 (irq = 16) is a CPM UART
f011a00.serial: ttyCPM1 at MMIO 0xc3018a00 (irq = 40) is a CPM UART
f011a20.serial: ttyCPM2 at MMIO 0xc3020a20 (irq = 41) is a CPM UART
f011a40.serial: ttyCPM3 at MMIO 0xc3028a40 (irq = 42) is a CPM UART
With the DTS reading:
smc1: ser...@11a80 {
device_type = serial;
compatible = fsl,mpc8270-smc-uart,
fsl,cpm2-smc-uart;
reg = 0x11a80 0x20 0x87fc 2;
interrupts = 4 8;
interrupt-parent = PIC;
fsl,cpm-brg = 7;
fsl,cpm-command = 0x1d00;
};
scc1: ser...@11a00 {
device_type = serial;
compatible = fsl,mpc8270-scc-uart,
fsl,cpm2-scc-uart;
reg = 0x11a00 0x20 0x8000 0x100;
interrupts = 40 8;
interrupt-parent = PIC;
fsl,cpm-brg = 3;
fsl,cpm-command = 0x80;
};
scc2: ser...@11a20 {
device_type = serial;
compatible = fsl,mpc8270-scc-uart,
fsl,cpm2-scc-uart;
reg = 0x11a20 0x20 0x8100 0x100;
interrupts = 41 8;
interrupt-parent = PIC;
fsl,cpm-brg = 6;
fsl,cpm-command = 0x4a0;
};
scc3: ser...@11a40 {
device_type = serial;
compatible = fsl,mpc8270-scc-uart,
fsl,cpm2-scc-uart;
reg = 0x11a40 0x20 0x8200 0x100;
interrupts = 42 8;
interrupt-parent = PIC;
fsl,cpm-brg = 1;
fsl,cpm-command = 0x8c0;
};
I believe that I have the pins setup correctly and the BRGs connected
correctly in the setup_arch function.
At the moment I have SCC3 wired out. If I attempt to echo data out of
the SCC (echo Hello /dev/ttyCPM3) I get the prompt sits waiting.
Rebooting and turning on the debug yields the following output on the
console (but nothing out of the SCC port):
CPM uart[3]:startup
Interrupt attached
CPM uart[3]:set_termios
CPM uart[3]:start tx
CPM uart[3]:stop tx
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:stop rx
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:shutdown
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
CPM uart[3]:tx_empty: 0
...
It seemed to be waiting for ready bit of the Transmit Buffer Descriptor
to be cleared (which it never seems to be), prodding this bit through
the pci window did cause the process to continue, no data out but I did
get back to the prompt on the console.
I'm sure I'm just missing something really basic - can anyone enlighten me?
Martyn
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Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
Scott Wood wrote: On 06/02/2010 03:06 AM, Martyn Welch wrote: I think that's a more fundamental change to CPM early debug than I can handle right now. Is IMMRBASE on your board at some address that has a low likelihood of conflicting when treated as a kernel effective address? It's at 0x0f00, is seems ok, but then I'm not sure I fully understand kernel effective addresses. That overlaps userspace -- is the BAT cleared before userspace starts? To be honest, once I'd got the device booting past the early debug stage, I rebuilt the kernel without udbg in it... If you don't want to do the fixmap stuff, might want to at least just leave it at the current arbitrary effective address, which hasn't seemed to cause much trouble so far. Given that I've now switched udbg off in the kernel config, I really can't substantiate spending much more time on this. This patch was mainly to help others that maybe struggling to bring up Linux on a device with CPM serial. I'll try and get a revised patch out soon which keeps the current arbitrary effective address. Martyn But fixmap is the right way to do it. -Scott -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
Scott Wood wrote: On 06/01/2010 08:43 AM, Martyn Welch wrote: diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index e025e89..861cace 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -1194,12 +1194,13 @@ setup_disp_bat: #endif /* CONFIG_BOOTX_TEXT */ #ifdef CONFIG_PPC_EARLY_DEBUG_CPM +#define PPC_EARLY_DEBUG_CPM_ADDR ASM_CONST(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR) setup_cpm_bat: -lisr8, 0xf000 +lisr8, ppc_early_debug_cpm_a...@ha orir8, r8,0x002a mtsprSPRN_DBAT1L, r8 -lisr11, 0xf000 +lisr11, ppc_early_debug_cpm_a...@ha orir11, r11, (BL_1M 2) | 2 mtsprSPRN_DBAT1U, r11 Only the physical address should depend on where IMMR is. We should use fixmap instead of an arbitrary address for the effective address. There's a existing FIX_EARLY_DEBUG_BASE, but it's only 128 KiB so we'll have to either grow it, or map only a subset of IMMR. I think that's a more fundamental change to CPM early debug than I can handle right now. Is IMMRBASE on your board at some address that has a low likelihood of conflicting when treated as a kernel effective address? It's at 0x0f00, is seems ok, but then I'm not sure I fully understand kernel effective addresses. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3] powerpc: Add i8042 keyboard and mouse irq parsing
Benjamin Herrenschmidt wrote:
O
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..3d169bb 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
Is there a reasonable ifdef to use for the above or we don't care ?
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -567,6 +571,15 @@ int check_legacy_ioport(unsigned long base_port)
np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
if (np) {
parent = of_get_parent(np);
+
+of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
+if (!of_i8042_kbd_irq)
+of_i8042_kbd_irq = 1;
+
+of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
+if (!of_i8042_aux_irq)
+of_i8042_aux_irq = 12;
+
of_node_put(np);
np = parent;
break;
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..5d48bb6 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -27,6 +27,11 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+# define I8042_KBD_IRQ of_i8042_kbd_irq
+# define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
Now while that works, I do tend to dislike global variables like that.
_Maybe_ a better approach would be to have those #define resolve to
functions:
#define I8042_KBD_IRQ of_find_i8042_kbd_irq()
Or something like that ?
That means ending up having 2 functions which more/less reproduce the
loop to find the driver in the device-tree but that's a minor
inconvenience.
Now, maybe the variables are less bloat here. What do you think ? Which
way do you prefer ?
Personally, I'm happy either way. If you'd prefer I implement these as
functions, I can't quickly see why that wouldn't work. I thought using
variables would be the least disruptive.
I'm also happy to change it so that the irqs are specified in the kbd
and aux nodes (I agree it would make much more sense and was how the
first revision of this patch worked).
Either way, my preferred solution is that contained in this patch,
unless those with more experience agree otherwise... ;-)
Martyn
Cheers,
Ben.
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Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
Scott Wood wrote: On 05/28/2010 10:18 AM, Martyn Welch wrote: The CPM early debug console hardcodes the BAT to cover the IMMR at 0xf000. The IMMR (on the mpc8270 at the very least) can be set to a number of locations with bootstrap configuration, which are outside the hardcoded BAT configuration. This patch determines the correct location at which to configure a BAT during the boot process from the supplied PPC_EARLY_DEBUG_CPM_ADDR. Signed-off-by: Martyn Welchmartyn.we...@ge.com --- arch/powerpc/kernel/head_32.S|5 +++-- arch/powerpc/sysdev/cpm_common.c |4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index e025e89..861cace 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -1194,12 +1194,13 @@ setup_disp_bat: #endif /* CONFIG_BOOTX_TEXT */ #ifdef CONFIG_PPC_EARLY_DEBUG_CPM +#define PPC_EARLY_DEBUG_CPM_ADDR ASM_CONST(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR) setup_cpm_bat: -lisr8, 0xf000 +lisr8, ppc_early_debug_cpm_a...@ha orir8, r8,0x002a mtsprSPRN_DBAT1L, r8 -lisr11, 0xf000 +lisr11, ppc_early_debug_cpm_a...@ha orir11, r11, (BL_1M 2) | 2 mtsprSPRN_DBAT1U, r11 Only the physical address should depend on where IMMR is. We should use fixmap instead of an arbitrary address for the effective address. There's a existing FIX_EARLY_DEBUG_BASE, but it's only 128 KiB so we'll have to either grow it, or map only a subset of IMMR. I think that's a more fundamental change to CPM early debug than I can handle right now. Plus, CONFIG_PPC_EARLY_DEBUG_CPM_ADDR points to the TX descriptor, not to the beginning of IMMR, so you should mask off the lower 20 bits (the offset is probably less than 64K, and the BAT might just ignore the extra bits anyway, but why take chances?). I assume that an extra instruction andi r8, r8, 0xfff0 after each lis instruction would be what you are looking for? Martyn -Scott -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
Martyn Welch wrote: Scott Wood wrote: On 05/28/2010 10:18 AM, Martyn Welch wrote: The CPM early debug console hardcodes the BAT to cover the IMMR at 0xf000. The IMMR (on the mpc8270 at the very least) can be set to a number of locations with bootstrap configuration, which are outside the hardcoded BAT configuration. This patch determines the correct location at which to configure a BAT during the boot process from the supplied PPC_EARLY_DEBUG_CPM_ADDR. Signed-off-by: Martyn Welchmartyn.we...@ge.com --- arch/powerpc/kernel/head_32.S|5 +++-- arch/powerpc/sysdev/cpm_common.c |4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index e025e89..861cace 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -1194,12 +1194,13 @@ setup_disp_bat: #endif /* CONFIG_BOOTX_TEXT */ #ifdef CONFIG_PPC_EARLY_DEBUG_CPM +#define PPC_EARLY_DEBUG_CPM_ADDR ASM_CONST(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR) setup_cpm_bat: -lisr8, 0xf000 +lisr8, ppc_early_debug_cpm_a...@ha orir8, r8,0x002a mtsprSPRN_DBAT1L, r8 -lisr11, 0xf000 +lisr11, ppc_early_debug_cpm_a...@ha orir11, r11, (BL_1M 2) | 2 mtsprSPRN_DBAT1U, r11 Only the physical address should depend on where IMMR is. We should use fixmap instead of an arbitrary address for the effective address. There's a existing FIX_EARLY_DEBUG_BASE, but it's only 128 KiB so we'll have to either grow it, or map only a subset of IMMR. I think that's a more fundamental change to CPM early debug than I can handle right now. Plus, CONFIG_PPC_EARLY_DEBUG_CPM_ADDR points to the TX descriptor, not to the beginning of IMMR, so you should mask off the lower 20 bits (the offset is probably less than 64K, and the BAT might just ignore the extra bits anyway, but why take chances?). I assume that an extra instruction andi r8, r8, 0xfff0 after each lis instruction would be what you are looking for? andis even. Martyn Martyn -Scott -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
The CPM early debug console hardcodes the BAT to cover the IMMR at
0xf000. The IMMR (on the mpc8270 at the very least) can be set to a
number of locations with bootstrap configuration, which are outside the
hardcoded BAT configuration.
This patch determines the correct location at which to configure a BAT
during the boot process from the supplied PPC_EARLY_DEBUG_CPM_ADDR.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
arch/powerpc/kernel/head_32.S|5 +++--
arch/powerpc/sysdev/cpm_common.c |4 +++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index e025e89..861cace 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -1194,12 +1194,13 @@ setup_disp_bat:
#endif /* CONFIG_BOOTX_TEXT */
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
+#define PPC_EARLY_DEBUG_CPM_ADDR ASM_CONST(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR)
setup_cpm_bat:
- lis r8, 0xf000
+ lis r8, ppc_early_debug_cpm_a...@ha
ori r8, r8, 0x002a
mtspr SPRN_DBAT1L, r8
- lis r11, 0xf000
+ lis r11, ppc_early_debug_cpm_a...@ha
ori r11, r11, (BL_1M 2) | 2
mtspr SPRN_DBAT1U, r11
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 88b9812..984614f 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -57,7 +57,9 @@ void __init udbg_init_cpm(void)
{
if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
- setbat(1, 0xf000, 0xf000, 1024*1024, PAGE_KERNEL_NCG);
+#define EARLY_DEBUG_CPM_BAT (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR0xfff0)
+ setbat(1, EARLY_DEBUG_CPM_BAT, EARLY_DEBUG_CPM_BAT, 1024*1024,
+ PAGE_KERNEL_NCG);
#endif
udbg_putc = udbg_putc_cpm;
}
--
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Re: [PATCH v2] powerpc: Add i8042 keyboard and mouse irq parsing
Grant Likely wrote:
On Mon, May 24, 2010 at 10:25 AM, Martyn Welch martyn.we...@ge.com wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 49
++--
drivers/input/serio/i8042-io.h |8 ++
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..7f1bb99 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -558,13 +562,52 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL,
pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL,
pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np);
+ if (parent) {
+ /*
+* Attempt to parse DTS for keyboard irq,
+* fallback to standard.
+*/
+ of_i8042_kbd_irq =
irq_of_parse_and_map(parent,
+ 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_node_put(parent);
+ }
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np_aux);
+ if (parent) {
+ /*
+* Attempt to parse DTS for mouse (aux) irq,
+* fallback to standard.
+*/
+ of_i8042_aux_irq =
irq_of_parse_and_map(parent,
+ 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
+ of_node_put(parent);
+ }
+ }
+
This seems to be a lot more code that you need. The existing code
already obtains a pointer to the parent node for you. All you really
should need to add is the two calls to irq_of_parse_and_map() for
obtaining the kbd and aux irq numbers.
Your right - new patch on it's way.
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
Please fold these two extern definitions into the #elif
defined(CONFIG_PPC) block below.
Will do.
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special
*/
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQ of_i8042_kbd_irq
+#define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
Cheers,
g.
--
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GE
[PATCH v3] powerpc: Add i8042 keyboard and mouse irq parsing
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
v3: Code compacted as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 13 +
drivers/input/serio/i8042-io.h |5 +
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..3d169bb 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -567,6 +571,15 @@ int check_legacy_ioport(unsigned long base_port)
np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
if (np) {
parent = of_get_parent(np);
+
+ of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
of_node_put(np);
np = parent;
break;
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..5d48bb6 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -27,6 +27,11 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+# define I8042_KBD_IRQ of_i8042_kbd_irq
+# define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
--
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Re: mmio_nvram.c users ?
One day I'll manage to hit Reply or Reply All correctly... Benjamin Herrenschmidt wrote: Hi folks ! Anybody aware of anything other than Cell using that driver ? I'd like to make it a platform driver instead of having something that pokes at anything that has a device_type set to nvram (which is gross and bogus). But I need to know what platforms to fixup... We do on our boards, that would currently be the sbc310, sbc610 and ppc9a (all FSL 86xx based boards). I also have 2 other boards I'm currently working on that will also use that driver. Martyn Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc: Add i8042 keyboard and mouse irq parsing
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 49 ++--
drivers/input/serio/i8042-io.h |8 ++
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 48f0a00..7f1bb99 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -558,13 +562,52 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL, pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np);
+ if (parent) {
+ /*
+* Attempt to parse DTS for keyboard irq,
+* fallback to standard.
+*/
+ of_i8042_kbd_irq = irq_of_parse_and_map(parent,
+ 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_node_put(parent);
+ }
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+
+ /* Interrupt routing in parent node */
+ parent = of_get_parent(np_aux);
+ if (parent) {
+ /*
+* Attempt to parse DTS for mouse (aux) irq,
+* fallback to standard.
+*/
+ of_i8042_aux_irq = irq_of_parse_and_map(parent,
+ 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
+ of_node_put(parent);
+ }
+ }
+
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQ of_i8042_kbd_irq
+#define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748| Barbirolli Square, Manchester,
E martyn.we...@ge.com| M2 3AB VAT:GB 927559189
___
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[PATCH] powerpc: Add i8042 keyboard and mouse irq parsing
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts.
In addition the interrupts are provided in the dts, but in a way that is
not easily parsable using irq_of_parse_and_map().
This patch modifies the powerpc legacy IO code to attempt to parse the
device tree for this information, failing back to the hardcoded values if
it fails. For this to succeed the interrupts for the keyboard and mouse
ports need to be moved from the parent i8042 node to the individual port
nodes.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
To get irq_of_parse_and_map() to successfully parse the interrupts, I had
to do this to my device tree:
@@ -120,16 +120,17 @@
#address-cells = 1;
reg = 1 0x60 0x1
1 0x64 0x1;
- interrupts = 1 1 12 1;
interrupt-parent = lpc_pic;
keybo...@0 {
reg = 0x0;
+ interrupts = 1 1;
compatible = pnpPNP,303;
};
mo...@1 {
reg = 0x1;
+ interrupts = 12 1;
compatible = pnpPNP,f03;
};
};
I'm not sure how to parse for the correct interrupt if I don't do this. I
this is incorrect and someone could advise me on how the existing device
tree layout can be properly parsed, I'll happily modify this patch.
arch/powerpc/kernel/setup-common.c | 34 +++---
drivers/input/serio/i8042-io.h |8
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 03dd6a2..9c4dc4c 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -93,6 +93,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -555,13 +559,37 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL, pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /*
+* Attempt to parse DTS for keyboard irq, fallback to
+* standard.
+*/
+ of_i8042_kbd_irq = irq_of_parse_and_map(np, 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+ /*
+* Attempt to parse DTS for mouse (aux) irq, fallback to
+* standard.
+*/
+ of_i8042_aux_irq = irq_of_parse_and_map(np_aux, 0);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+ }
+
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQ of_i8042_kbd_irq
+#define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms
Re: [PATCH] powerpc: Add i8042 keyboard and mouse irq parsing
Martyn Welch wrote:
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts.
In addition the interrupts are provided in the dts, but in a way that is
not easily parsable using irq_of_parse_and_map().
This patch modifies the powerpc legacy IO code to attempt to parse the
device tree for this information, failing back to the hardcoded values if
it fails. For this to succeed the interrupts for the keyboard and mouse
ports need to be moved from the parent i8042 node to the individual port
nodes.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
To get irq_of_parse_and_map() to successfully parse the interrupts, I had
to do this to my device tree:
@@ -120,16 +120,17 @@
#address-cells = 1;
reg = 1 0x60 0x1
1 0x64 0x1;
- interrupts = 1 1 12 1;
interrupt-parent = lpc_pic;
keybo...@0 {
reg = 0x0;
+ interrupts = 1 1;
compatible = pnpPNP,303;
};
mo...@1 {
reg = 0x1;
+ interrupts = 12 1;
compatible = pnpPNP,f03;
};
};
I'm not sure how to parse for the correct interrupt if I don't do this. I
this is incorrect and someone could advise me on how the existing device
tree layout can be properly parsed, I'll happily modify this patch.
Grant, any suggestions? (sorry, forgot to CC you)
Martyn
arch/powerpc/kernel/setup-common.c | 34 +++---
drivers/input/serio/i8042-io.h |8
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 03dd6a2..9c4dc4c 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -93,6 +93,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -555,13 +559,37 @@ void probe_machine(void)
/* Match a class of boards, not a specific device configuration. */
int check_legacy_ioport(unsigned long base_port)
{
- struct device_node *parent, *np = NULL;
+ struct device_node *parent, *np = NULL, *np_aux = NULL;
int ret = -ENODEV;
switch(base_port) {
case I8042_DATA_REG:
- if (!(np = of_find_compatible_node(NULL, NULL, pnpPNP,303)))
- np = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ np = of_find_compatible_node(NULL, NULL, pnpPNP,303);
+ if (np) {
+ /*
+ * Attempt to parse DTS for keyboard irq, fallback to
+ * standard.
+ */
+ of_i8042_kbd_irq = irq_of_parse_and_map(np, 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+ }
+
+ np_aux = of_find_compatible_node(NULL, NULL, pnpPNP,f03);
+ if (np_aux) {
+ if (!np) {
+ of_node_put(np);
+ np = np_aux;
+ }
+ /*
+ * Attempt to parse DTS for mouse (aux) irq, fallback to
+ * standard.
+ */
+ of_i8042_aux_irq = irq_of_parse_and_map(np_aux, 0);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+ }
+
if (np) {
parent = of_get_parent(np);
of_node_put(np);
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..8fc8753 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -19,6 +19,11 @@
* IRQs.
*/
+#if defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+#endif
+
#ifdef __alpha__
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is
special */
@@ -27,6 +32,9 @@
#include asm/irq.h
#elif defined(CONFIG_SH_CAYMAN)
#include asm/irq.h
+#elif defined(CONFIG_PPC)
+#define I8042_KBD_IRQof_i8042_kbd_irq
+#define I8042_AUX_IRQof_i8042_aux_irq
#else
# define
[PATCH v2] Correct PowerPC Parport interrupt parsing.
Currently the parsing of the device tree in
arch/powerpc/include/asm/parport.h assumes that the interrupt provided in
the parallel port node is a valid virtual irq. The values for the
interrupts provided in the device tree should have meaning in the context
of the driver for the specific interrupt controller to which the interrupt
is connected and irq_of_parse_and_map() should be used to determine the
correct virtual irq.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Corrected irq_of_parse_and_map() index.
arch/powerpc/include/asm/parport.h | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/parport.h
b/arch/powerpc/include/asm/parport.h
index 94942d6..1ca1102 100644
--- a/arch/powerpc/include/asm/parport.h
+++ b/arch/powerpc/include/asm/parport.h
@@ -19,6 +19,8 @@ static int __devinit parport_pc_find_nonpci_ports (int
autoirq, int autodma)
u32 io1, io2;
int propsize;
int count = 0;
+ int virq;
+
for (np = NULL; (np = of_find_compatible_node(np,
parallel,
pnpPNP,400)) != NULL;) {
@@ -26,10 +28,13 @@ static int __devinit parport_pc_find_nonpci_ports (int
autoirq, int autodma)
if (!prop || propsize 6*sizeof(u32))
continue;
io1 = prop[1]; io2 = prop[2];
- prop = of_get_property(np, interrupts, NULL);
- if (!prop)
+
+ virq = irq_of_parse_and_map(np, 0);
+ if (virq == NO_IRQ)
continue;
- if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL, 0)
!= NULL)
+
+ if (parport_pc_probe_port(io1, io2, virq, autodma, NULL, 0)
+ != NULL)
count++;
}
return count;
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748| Barbirolli Square, Manchester,
E martyn.we...@ge.com| M2 3AB VAT:GB 927559189
___
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[PATCH] Correct PowerPC Parport interrupt parsing.
Currently the parsing of the device tree in
arch/powerpc/include/asm/parport.h assumes that the interrupt provided in
the parallel port node is a valid virtual irq. The values for the
interrupts provided in the device tree should have meaning in the context
of the driver for the specific interrupt controller to which the interrupt
is connected and irq_of_parse_and_map() should be used to determine the
correct virtual irq.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
I believe this is the correct way to discover interrupt numbering. I assume
this has worked in the past as the interrupt routing hasn't been as
interesting as the board I'm currently working on.
I also don't have any other targets I could test this on, can anyone tell
me if this will break support on existing devices?
arch/powerpc/include/asm/parport.h | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/parport.h
b/arch/powerpc/include/asm/parport.h
index 94942d6..aa3f7bc 100644
--- a/arch/powerpc/include/asm/parport.h
+++ b/arch/powerpc/include/asm/parport.h
@@ -19,6 +19,8 @@ static int __devinit parport_pc_find_nonpci_ports (int
autoirq, int autodma)
u32 io1, io2;
int propsize;
int count = 0;
+ int virq;
+
for (np = NULL; (np = of_find_compatible_node(np,
parallel,
pnpPNP,400)) != NULL;) {
@@ -26,10 +28,13 @@ static int __devinit parport_pc_find_nonpci_ports (int
autoirq, int autodma)
if (!prop || propsize 6*sizeof(u32))
continue;
io1 = prop[1]; io2 = prop[2];
- prop = of_get_property(np, interrupts, NULL);
- if (!prop)
+
+ virq = irq_of_parse_and_map(np, 1);
+ if (virq == NO_IRQ)
continue;
- if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL, 0)
!= NULL)
+
+ if (parport_pc_probe_port(io1, io2, virq, autodma, NULL, 0)
+ != NULL)
count++;
}
return count;
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748| Barbirolli Square, Manchester,
E martyn.we...@ge.com| M2 3AB VAT:GB 927559189
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Re: Gianfar driver failing on MPC8641D based board
Anton Vorontsov wrote: diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 8bd3c9f..cccb409 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -2021,7 +2021,6 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) } /* setup the TxBD length and buffer pointer for the first BD */ - tx_queue-tx_skbuff[tx_queue-skb_curtx] = skb; txbdp_start-bufPtr = dma_map_single(priv-ofdev-dev, skb-data, skb_headlen(skb), DMA_TO_DEVICE); @@ -2053,6 +2052,10 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) txbdp_start-lstatus = lstatus; + eieio(); /* force lstatus write before tx_skbuff */ + + tx_queue-tx_skbuff[tx_queue-skb_curtx] = skb; + /* Update the current skb pointer to the next entry we will use * (wrapping if necessary) */ tx_queue-skb_curtx = (tx_queue-skb_curtx + 1) I can confirm 10/10 successful boots on p2020ds and mpc8641_hpcn. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Renaming following split of GE Fanuc joint venture
This patch renames GE Fanuc boards following the split-up of the GE Fanuc joint venture. These boards are now made by GE Intelligent platorms. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/boot/dts/gef_ppc9a.dts |4 ++-- arch/powerpc/boot/dts/gef_sbc310.dts |4 ++-- arch/powerpc/boot/dts/gef_sbc610.dts |4 ++-- arch/powerpc/platforms/86xx/Kconfig | 12 ++-- arch/powerpc/platforms/86xx/gef_gpio.c | 10 +- arch/powerpc/platforms/86xx/gef_pic.c|6 +++--- arch/powerpc/platforms/86xx/gef_ppc9a.c | 12 ++-- arch/powerpc/platforms/86xx/gef_sbc310.c | 12 ++-- arch/powerpc/platforms/86xx/gef_sbc610.c | 12 ++-- 9 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index 977f260..83f4b79 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -1,7 +1,7 @@ /* - * GE Fanuc PPC9A Device Tree Source + * GE PPC9A Device Tree Source * - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts index 8e4efff..fc3a331 100644 --- a/arch/powerpc/boot/dts/gef_sbc310.dts +++ b/arch/powerpc/boot/dts/gef_sbc310.dts @@ -1,7 +1,7 @@ /* - * GE Fanuc SBC310 Device Tree Source + * GE SBC310 Device Tree Source * - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index bb70600..c0671cc 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -1,7 +1,7 @@ /* - * GE Fanuc SBC610 Device Tree Source + * GE SBC610 Device Tree Source * - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 2bbfd53..fbe9f36 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -33,32 +33,32 @@ config MPC8610_HPCD This option enables support for the MPC8610 HPCD board. config GEF_PPC9A - bool GE Fanuc PPC9A + bool GE PPC9A select DEFAULT_UIMAGE select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help - This option enables support for GE Fanuc's PPC9A. + This option enables support for the GE PPC9A. config GEF_SBC310 - bool GE Fanuc SBC310 + bool GE SBC310 select DEFAULT_UIMAGE select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB help - This option enables support for GE Fanuc's SBC310. + This option enables support for the GE SBC310. config GEF_SBC610 - bool GE Fanuc SBC610 + bool GE SBC610 select DEFAULT_UIMAGE select MMIO_NVRAM select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select HAS_RAPIDIO help - This option enables support for GE Fanuc's SBC610. + This option enables support for the GE SBC610. endif diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c index b2ea887..11f7b2b 100644 --- a/arch/powerpc/platforms/86xx/gef_gpio.c +++ b/arch/powerpc/platforms/86xx/gef_gpio.c @@ -1,9 +1,9 @@ /* - * Driver for GE Fanuc's FPGA based GPIO pins + * Driver for GE FPGA based GPIO * - * Author: Martyn Welch martyn.we...@gefanuc.com + * Author: Martyn Welch martyn.we...@ge.com * - * 2008 (c) GE Fanuc Intelligent Platforms Embedded Systems, Inc. + * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed as is without any warranty of any @@ -164,6 +164,6 @@ static int __init gef_gpio_init(void) }; arch_initcall(gef_gpio_init); -MODULE_DESCRIPTION(GE Fanuc I/O FPGA GPIO driver); -MODULE_AUTHOR(Martyn Welch martyn.we...@gefanuc.com); +MODULE_DESCRIPTION(GE I/O FPGA GPIO driver); +MODULE_AUTHOR(Martyn Welch martyn.we...@ge.com); MODULE_LICENSE(GPL); diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx
Re: Gianfar driver failing on MPC8641D based board
Anton Vorontsov wrote: On Thu, Feb 25, 2010 at 04:46:54PM +, Martyn Welch wrote: [...] nfs: server 192.168.0.1 not responding, still trying Further testing has shown that this isn't restricted to warm reboots, it happens from cold as well. In addition, the exact timing of the failure seems to vary, some boots have got further before failing. Unfortunately I don't have any 8641 boards near me, so I can't debug this myself. Though, I tested gianfar on MPC8568E-MDS with 2.6.33 kernel, and it seems to work just fine. I see you use SMP. Can you try to turn it off? If that will fix the issue, then it'll be a good data point. Meanwhile, I'll try SMP kernel on MPC8568 (UP), and let you know the results. Thanks I removed the second core from the dts file rather than truly disabling SMP in the kernel config. Doing this allowed the board to boot reliably. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Gianfar driver failing on MPC8641D based board
Anton Vorontsov wrote: On Thu, Feb 25, 2010 at 07:53:30PM -0500, Paul Gortmaker wrote: [...] I was able to reproduce it on an 8641D and bisected it down to this: --- commit a3bc1f11e9b867a4f49505ecac486a33af248b2e Author: Anton Vorontsov avoront...@ru.mvista.com Date: Tue Nov 10 14:11:10 2009 + gianfar: Revive SKB recycling Thanks for the bisect. I have a guess why tx hangs in SMP case. Could anyone try the patch down below? Yup, no problem. I'm afraid it doesn't resolve the problem for me. [...] ...which probably explains why you weren't seeing it on non-SMP. I'd imagine it would show up on any of the e500mc boards too. Yeah.. Pity, I don't have SMP boards anymore. I'll try to get one though. diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 8bd3c9f..3ff3bd0 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -2614,6 +2614,8 @@ static int gfar_poll(struct napi_struct *napi, int budget) tx_queue = priv-tx_queue[rx_queue-qindex]; tx_cleaned += gfar_clean_tx_ring(tx_queue); + if (!tx_cleaned !tx_queue-num_txbdfree) + tx_cleaned += 1; /* don't complete napi */ rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, budget_per_queue); rx_cleaned += rx_cleaned_per_queue; -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Gianfar driver failing on MPC8641D based board
Martyn Welch wrote: Paul Gortmaker wrote: On 10-02-26 09:35 AM, Anton Vorontsov wrote: On Fri, Feb 26, 2010 at 12:06:15PM +, Martyn Welch wrote: Anton Vorontsov wrote: On Thu, Feb 25, 2010 at 07:53:30PM -0500, Paul Gortmaker wrote: [...] I was able to reproduce it on an 8641D and bisected it down to this: --- commit a3bc1f11e9b867a4f49505ecac486a33af248b2e Author: Anton Vorontsovavoront...@ru.mvista.com Date: Tue Nov 10 14:11:10 2009 + gianfar: Revive SKB recycling Thanks for the bisect. I have a guess why tx hangs in SMP case. Could anyone try the patch down below? Yup, no problem. I'm afraid it doesn't resolve the problem for me. Hm.. I found a p2020 board and I was able to reproduce the issue. The patch down below fixed it completely for me... hm. Interesting. I just tested the patch on the sbc8641d, and it still has the issue with your patch applied. I'm using NFSroot just like Martyn was and it still appears bound up on that gianfar tx lock. I'll see if I can get a SysRq backtrace in case that will help you see how it manages to get there... I've got a p2020ds here as well, so I'll give NFSroot on that a try with your patch. Out of 10 boot attempts, 7 failed. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Gianfar driver failing on MPC8641D based board
Martyn Welch wrote: I have recently attempted to boot an 8641D based board from an NFS root. The boot process grinds to a halt not long after the first access of the NFS root and I receive multiple nfs: server 192.168.0.1 not responding, still trying messages. Wireshark suggests that there is no further traffic from this board at this point on. The NFS server seems to eventually try sending duplicate packets it's already sent, which results in nfs: server 192.168.0.1 OK messages, but the not responding messages resume with no further traffic from the board. I am able to boot to a ramdisk fine and the network seems to work - though I haven't really pushed the interface from it. I have attempted to git bisect, though I wasn't able to get much further than discovering the problem was introduced in the 2.6.33 merge window - at which point the gianfar network driver fails to compile (I have tried to git bisect skip many, many times to no avail). NFS booting fails for this board on todays linux-next, the master branch of Kumar's PPC tree and the head of the main tree. I have also been able to NFS boot from a random x86 based board that I have, using the head of the main tree and the linux-next tree. Copying the gianfar drivers from 2.6.32 into the head of the main tree restores the correct behaviour and I'm able to NFS boot. I have heard from others that the latest drivers work on 83xx and 85xx based boards, but it seems to be broken on at least the 8641D. I can see there has been a fair amount of work done on the gianfar driver, I assume that this is a bug introduced by the multiple queue support, but I'm way out of my depth on this. I have just compiled 2.6.33 for the Freescale MPC8641_HPCN demo board and am having still experiencing the problems outlined in my previous email, though I have noticed that I tend to be able to boot from cold, but my boot fails on reboot. Hitting the reset button doesn't help, I need to actually power the machine on and off again for it to work. As before, I'm way out of my depth in this, any one have any ideas? Below is a dump of the failed boot process: U-Boot 2009.01-00181-gc1b7c70 (Jan 30 2009 - 11:17:31) Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.0, (0x80900120) Clocks: CPU:1000 MHz, MPX: 400 MHz, DDR: 200 MHz, LBC: 25 MHz L2: Enabled Board: MPC8641HPCN, System ID: 0x10, System Version: 0x10, FPGA Version: 0x22 I2C: ready DRAM: DDR: 1 GB FLASH: 8 MB Invalid ID (ff ff ff ff) Scanning PCI bus 01 PCI-EXPRESS 1 on bus 00 - 02 PCI-EXPRESS 2 on bus 03 - 03 Video: No radeon video card found! In:serial Out: serial Err: serial SCSI: AHCI 0001. 32 slots 4 ports 3 Gbps 0xf impl IDE mode flags: ncq ilck pm led clo pmp pio slum part scanning bus for devices... Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 = tftp 400 hpcn/uImage-torvalds-linux-2.6 Speed: 1000, full duplex Using eTSEC1 device TFTP from server 192.168.0.1; our IP address is 192.168.0.30 Filename 'hpcn/uImage-torvalds-linux-2.6'. Load address: 0x400 Loading: # # ### done Bytes transferred = 2709050 (29563a hex) = tftp 500 hpcn/mpc8641_hpcn-torvalds-linux-2.6.dtb Speed: 1000, full duplex Using eTSEC1 device TFTP from server 192.168.0.1; our IP address is 192.168.0.30 Filename 'hpcn/mpc8641_hpcn-torvalds-linux-2.6.dtb'. Load address: 0x500 Loading: # done Bytes transferred = 11523 (2d03 hex) = setenv bootargs root=/dev/nfs rw nfsroot=192.168.0.1:/tftpboot/hpcn/root/ i = bootm 400 - 500 WARNING: adjusting available memory to 1000 ## Booting kernel from Legacy Image at 0400 ... Image Name: Linux-2.6.33-1-gbaac35c Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:2708986 Bytes = 2.6 MB Load Address: Entry Point: Verifying Checksum ... OK ## Flattened Device Tree blob at 0500 Booting using the fdt blob at 0x500 Uncompressing Kernel Image ... OK Loading Device Tree to 007fa000, end 007ffd02 ... OK Using MPC86xx HPCN machine description Total memory = 1024MB; using 2048kB for hash table (at cfe0) Linux version 2.6.33-1-gbaac35c (welc...@es-j7s4d2j) (gcc version 4.1.2) #20 CPU maps initialized for 1 thread per core bootconsole [udbg0] enabled setup_arch: bootmem mpc86xx_hpcn_setup_arch() Found FSL PCI host bridge at 0xffe08000. Firmware bus number: 0-2 PCI host bridge /p...@ffe08000 (primary) ranges: MEM 0x8000..0x9fff - 0x8000 IO 0xffc0..0xffc0 - 0x /p...@ffe08000: PCICSRBAR @ 0xfff0 Found FSL PCI host bridge at 0xffe09000. Firmware bus number: 0-0 PCI host bridge /p
Re: Gianfar driver failing on MPC8641D based board
Martyn Welch wrote: Martyn Welch wrote: I have recently attempted to boot an 8641D based board from an NFS root. The boot process grinds to a halt not long after the first access of the NFS root and I receive multiple nfs: server 192.168.0.1 not responding, still trying messages. Wireshark suggests that there is no further traffic from this board at this point on. The NFS server seems to eventually try sending duplicate packets it's already sent, which results in nfs: server 192.168.0.1 OK messages, but the not responding messages resume with no further traffic from the board. I am able to boot to a ramdisk fine and the network seems to work - though I haven't really pushed the interface from it. I have attempted to git bisect, though I wasn't able to get much further than discovering the problem was introduced in the 2.6.33 merge window - at which point the gianfar network driver fails to compile (I have tried to git bisect skip many, many times to no avail). NFS booting fails for this board on todays linux-next, the master branch of Kumar's PPC tree and the head of the main tree. I have also been able to NFS boot from a random x86 based board that I have, using the head of the main tree and the linux-next tree. Copying the gianfar drivers from 2.6.32 into the head of the main tree restores the correct behaviour and I'm able to NFS boot. I have heard from others that the latest drivers work on 83xx and 85xx based boards, but it seems to be broken on at least the 8641D. I can see there has been a fair amount of work done on the gianfar driver, I assume that this is a bug introduced by the multiple queue support, but I'm way out of my depth on this. I have just compiled 2.6.33 for the Freescale MPC8641_HPCN demo board and am having still experiencing the problems outlined in my previous email, though I have noticed that I tend to be able to boot from cold, but my boot fails on reboot. Hitting the reset button doesn't help, I need to actually power the machine on and off again for it to work. As before, I'm way out of my depth in this, any one have any ideas? Below is a dump of the failed boot process: U-Boot 2009.01-00181-gc1b7c70 (Jan 30 2009 - 11:17:31) Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.0, (0x80900120) Clocks: CPU:1000 MHz, MPX: 400 MHz, DDR: 200 MHz, LBC: 25 MHz L2: Enabled Board: MPC8641HPCN, System ID: 0x10, System Version: 0x10, FPGA Version: 0x22 I2C: ready DRAM: DDR: 1 GB FLASH: 8 MB Invalid ID (ff ff ff ff) Scanning PCI bus 01 PCI-EXPRESS 1 on bus 00 - 02 PCI-EXPRESS 2 on bus 03 - 03 Video: No radeon video card found! In:serial Out: serial Err: serial SCSI: AHCI 0001. 32 slots 4 ports 3 Gbps 0xf impl IDE mode flags: ncq ilck pm led clo pmp pio slum part scanning bus for devices... Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 = tftp 400 hpcn/uImage-torvalds-linux-2.6 Speed: 1000, full duplex Using eTSEC1 device TFTP from server 192.168.0.1; our IP address is 192.168.0.30 Filename 'hpcn/uImage-torvalds-linux-2.6'. Load address: 0x400 Loading: # # ### done Bytes transferred = 2709050 (29563a hex) = tftp 500 hpcn/mpc8641_hpcn-torvalds-linux-2.6.dtb Speed: 1000, full duplex Using eTSEC1 device TFTP from server 192.168.0.1; our IP address is 192.168.0.30 Filename 'hpcn/mpc8641_hpcn-torvalds-linux-2.6.dtb'. Load address: 0x500 Loading: # done Bytes transferred = 11523 (2d03 hex) = setenv bootargs root=/dev/nfs rw nfsroot=192.168.0.1:/tftpboot/hpcn/root/ i = bootm 400 - 500 WARNING: adjusting available memory to 1000 ## Booting kernel from Legacy Image at 0400 ... Image Name: Linux-2.6.33-1-gbaac35c Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:2708986 Bytes = 2.6 MB Load Address: Entry Point: Verifying Checksum ... OK ## Flattened Device Tree blob at 0500 Booting using the fdt blob at 0x500 Uncompressing Kernel Image ... OK Loading Device Tree to 007fa000, end 007ffd02 ... OK Using MPC86xx HPCN machine description Total memory = 1024MB; using 2048kB for hash table (at cfe0) Linux version 2.6.33-1-gbaac35c (welc...@es-j7s4d2j) (gcc version 4.1.2) #20 CPU maps initialized for 1 thread per core bootconsole [udbg0] enabled setup_arch: bootmem mpc86xx_hpcn_setup_arch() Found FSL PCI host bridge at 0xffe08000. Firmware bus number: 0-2 PCI host bridge /p...@ffe08000 (primary) ranges: MEM 0x8000..0x9fff - 0x8000 IO 0xffc0..0xffc0 - 0x /p...@ffe08000: PCICSRBAR
Gianfar driver failing on MPC8641D based board
I have recently attempted to boot an 8641D based board from an NFS root. The boot process grinds to a halt not long after the first access of the NFS root and I receive multiple nfs: server 192.168.0.1 not responding, still trying messages. Wireshark suggests that there is no further traffic from this board at this point on. The NFS server seems to eventually try sending duplicate packets it's already sent, which results in nfs: server 192.168.0.1 OK messages, but the not responding messages resume with no further traffic from the board. I am able to boot to a ramdisk fine and the network seems to work - though I haven't really pushed the interface from it. I have attempted to git bisect, though I wasn't able to get much further than discovering the problem was introduced in the 2.6.33 merge window - at which point the gianfar network driver fails to compile (I have tried to git bisect skip many, many times to no avail). NFS booting fails for this board on todays linux-next, the master branch of Kumar's PPC tree and the head of the main tree. I have also been able to NFS boot from a random x86 based board that I have, using the head of the main tree and the linux-next tree. Copying the gianfar drivers from 2.6.32 into the head of the main tree restores the correct behaviour and I'm able to NFS boot. I have heard from others that the latest drivers work on 83xx and 85xx based boards, but it seems to be broken on at least the 8641D. I can see there has been a fair amount of work done on the gianfar driver, I assume that this is a bug introduced by the multiple queue support, but I'm way out of my depth on this. I'm also off for the next week - so if I'm quiet, it'll be because of that. Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
GE GPIO and PIC support.
Hi, I'm currently adding support for a GE board based on the Freescale P2020. This board has a cascaded interrupt controller and GPIO which should be compatible with drivers currently provided for the MPC8641D based boards that are already in the kernel. At the moment the drivers (in gef_gpio.c and gef_pic.c) are in the arch/powerpc/platforms/86xx folder. As the p2020 is not 86xx, I guess I should move these drivers to a more central location. I'm currently not sure where would be best to move them to, I see arch/powerpc/sysdev and arch/powerpc/platforms as potential locations, where would be the most suitable? Martyn -- Martyn Welch (Principal Software Engineer) | Registered in England and GE Intelligent Platforms | Wales (3828642) at 100 T +44(0)127322748| Barbirolli Square, Manchester, E martyn.we...@ge.com| M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/8] Update to GE powerpc/86xx based boards.
The following series implements some minor fixes and updates to the GE SBC310, SBC610 and PPC9A -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/8] powerpc/86xx: Add MSI section to GE SBC310 DTS
Add the MSI section to the DTS file for the GE SBC310.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 820c2b3..8ea8d4a 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -338,6 +338,22 @@
device_type = open-pic;
};
+ m...@41600 {
+ compatible = fsl,mpc8641-msi, fsl,mpic-msi;
+ reg = 0x41600 0x80;
+ msi-available-ranges = 0 0x100;
+ interrupts =
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0;
+ interrupt-parent = mpic;
+ };
+
global-utilit...@e {
compatible = fsl,mpc8641-guts;
reg = 0xe 0x1000;
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189
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[PATCH 2/8] powerpc/86xx: Fix GE SBC310 XMC site support
From: Malcolm Crossley malcolm.crossl...@gefanuc.com
Correction to interrupt map mask for GE SBC310 XMC site and addition of
alias.
Signed-off-by: Malcolm Crossley malcolm.crossl...@gefanuc.com
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 8ea8d4a..8e4efff 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -32,6 +32,7 @@
serial0 = serial0;
serial1 = serial1;
pci0 = pci0;
+ pci1 = pci1;
};
cpus {
@@ -374,7 +375,7 @@
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 0x18 0x2;
- interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+ interrupt-map-mask = 0xff00 0x0 0x0 0x7;
interrupt-map =
0x 0x0 0x0 0x1 mpic 0x0 0x2
0x 0x0 0x0 0x2 mpic 0x1 0x2
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189
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[PATCH 3/8] powerpc/86xx: Add MSI section to GE SBC610 DTS
From: Malcolm Crossley malcolm.crossl...@gefanuc.com
Add the MSI section to the DTS file for the GE SBC610.
Signed-off-by: Malcolm Crossley malcolm.crossl...@gefanuc.com
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc610.dts | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
index 30911ad..78c336f 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -305,6 +305,22 @@
device_type = open-pic;
};
+ m...@41600 {
+ compatible = fsl,mpc8641-msi, fsl,mpic-msi;
+ reg = 0x41600 0x80;
+ msi-available-ranges = 0 0x100;
+ interrupts =
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0;
+ interrupt-parent = mpic;
+ };
+
global-utilit...@e {
compatible = fsl,mpc8641-guts;
reg = 0xe 0x1000;
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189
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[PATCH 4/8] powerpc: Basic flash support for GE SBC610
Support for the SBC610 VPX Single Board Computer from GE (PowerPC MPC8641D).
This patch adds basic support for the on-board flash.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc610.dts | 50
arch/powerpc/configs/86xx/gef_sbc610_defconfig | 23 +++
2 files changed, 56 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
index 78c336f..bb70600 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -75,14 +75,48 @@
interrupts = 19 2;
interrupt-parent = mpic;
- ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
- 1 0 0xe800 0x0800 // Paged Flash 0
- 2 0 0xe000 0x0800 // Paged Flash 1
- 3 0 0xfc10 0x0002 // NVRAM
- 4 0 0xfc00 0x8000 // FPGA
- 5 0 0xfc008000 0x8000 // AFIX FPGA
- 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
- 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = gef,sbc610-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = gef,sbc610-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = user;
+ reg = 0x0 0x780;
+ };
+ partit...@780 {
+ label = firmware;
+ reg = 0x780 0x80;
+ read-only;
+ };
+ };
nv...@3,0 {
device_type = nvram;
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index 1975d41..9284f04 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -623,7 +623,7 @@ CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set
#
@@ -643,13 +643,9 @@ CONFIG_MTD_BLOCK=y
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -660,7 +656,6 @@ CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
@@ -1682,7 +1677,17 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
[PATCH 5/8] powerpc/86xx: Switch on highmem support on GE SBC610
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_sbc610_defconfig |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 9284f04..4912602 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -234,7 +234,7 @@ CONFIG_MMIO_NVRAM=y # # Kernel options # -# CONFIG_HIGHMEM is not set +CONFIG_HIGHMEM=y CONFIG_TICK_ONESHOT=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y @@ -1832,6 +1832,7 @@ CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 6/8] powerpc/86xx: Add MSI section to GE PPC9A DTS
From: Malcolm Crossley malcolm.crossl...@gefanuc.com
Add the MSI section to the DTS file for the GE PPC9A.
Signed-off-by: Malcolm Crossley malcolm.crossl...@gefanuc.com
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
index c86114e..977f260 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -341,6 +341,22 @@
device_type = open-pic;
};
+ m...@41600 {
+ compatible = fsl,mpc8641-msi, fsl,mpic-msi;
+ reg = 0x41600 0x80;
+ msi-available-ranges = 0 0x100;
+ interrupts =
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0;
+ interrupt-parent = mpic;
+ };
+
global-utilit...@e {
compatible = fsl,mpc8641-guts;
reg = 0xe 0x1000;
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189
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[PATCH 7/8] powerpc/86xx: Enable VME driver on the GE PPC9A
Enable the VME driver (which is currently in staging) on the PPC9A Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 47 - 1 files changed, 46 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index 6cd2cd6..1a37b69 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -1499,7 +1499,52 @@ CONFIG_RTC_DRV_RX8581=y # # TI VLYNQ # -# CONFIG_STAGING is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_ET131X is not set +# CONFIG_ME4000 is not set +# CONFIG_MEILHAUS is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ALTERA_PCIE_CHDMA is not set +# CONFIG_INPUT_MIMIO is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_DST is not set +# CONFIG_POHMELFS is not set +# CONFIG_B3DFG is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_PLAN9AUTH is not set +# CONFIG_HECI is not set +# CONFIG_USB_CPC is not set + +# +# Qualcomm MSM Camera And Video +# + +# +# Camera Sensor Selection +# +# CONFIG_HYPERV_STORAGE is not set +# CONFIG_HYPERV_BLOCK is not set +# CONFIG_HYPERV_NET is not set +CONFIG_VME_BUS=y + +# +# VME Bridge Drivers +# +CONFIG_VME_TSI148=y + +# +# VME Device Drivers +# +# CONFIG_VME_USER is not set # # File systems -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 8/8] powerpc/86xx: Enable VME driver on the GE SBC610
Enable the VME driver (which is currently in staging) on the SBC610. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_sbc610_defconfig | 39 +++- 1 files changed, 38 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 4912602..37adfb6 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -1600,7 +1600,44 @@ CONFIG_RTC_DRV_RX8581=y # # TI VLYNQ # -# CONFIG_STAGING is not set +CONFIG_STAGING=y +# CONFIG_STAGING_EXCLUDE_BUILD is not set +# CONFIG_ET131X is not set +# CONFIG_ME4000 is not set +# CONFIG_MEILHAUS is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ALTERA_PCIE_CHDMA is not set +# CONFIG_INPUT_MIMIO is not set +# CONFIG_TRANZPORT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_DST is not set +# CONFIG_POHMELFS is not set +# CONFIG_B3DFG is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_PLAN9AUTH is not set +# CONFIG_HECI is not set +# CONFIG_VT6655 is not set +# CONFIG_USB_CPC is not set +# CONFIG_RDC_17F3101X is not set +CONFIG_VME_BUS=y + +# +# VME Bridge Drivers +# +# CONFIG_VME_CA91CX42 is not set +CONFIG_VME_TSI148=y + +# +# VME Device Drivers +# +# CONFIG_VME_USER is not set # # File systems -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Git tags
Hi Ben, Could you please pull the git tags from Linus' tree when you pull? It aids a little in quickly seeing how far a tree on kernel has moved forward, at the moment the last tag on your tree is v2.6.26-rc9 [1]. Martyn [1] http://git.kernel.org/gitweb.cgi?p=linux/kernel/git/benh/powerpc.git;a=summary -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] Mechanism to enable use Generic NVRAM driver for different size chips
Remove the reliance on a staticly defined NVRAM size, allowing platforms to
support NVRAMs with sizes differing from the standard. A fall back value is
provided for platforms not supporting this extension.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
Ben: Is this a suitable solution?
v2: rename nvram_size() to nvram_get_size(), thus avoiding the collision with
the global
variables in arch/powerpc/platforms/pseries/nvram.c and
arch/powerpc/platforms/chrp/nvram.c of the same name.
arch/powerpc/include/asm/nvram.h |3 +++
arch/powerpc/kernel/setup_32.c |8
drivers/char/generic_nvram.c | 27 ---
3 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index efde5ac..6c587ed 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -107,6 +107,9 @@ extern void pmac_xpram_write(int xpaddr, u8 data);
/* Synchronize NVRAM */
extern voidnvram_sync(void);
+/* Determine NVRAM size */
+extern ssize_t nvram_get_size(void);
+
/* Normal access to NVRAM */
extern unsigned char nvram_read_byte(int i);
extern void nvram_write_byte(unsigned char c, int i);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index e1e3059..53bcf3d 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -210,6 +210,14 @@ void nvram_write_byte(unsigned char val, int addr)
}
EXPORT_SYMBOL(nvram_write_byte);
+ssize_t nvram_get_size(void)
+{
+ if (ppc_md.nvram_size)
+ return ppc_md.nvram_size();
+ return -1;
+}
+EXPORT_SYMBOL(nvram_get_size);
+
void nvram_sync(void)
{
if (ppc_md.nvram_sync)
diff --git a/drivers/char/generic_nvram.c b/drivers/char/generic_nvram.c
index a00869c..ef31738 100644
--- a/drivers/char/generic_nvram.c
+++ b/drivers/char/generic_nvram.c
@@ -2,7 +2,7 @@
* Generic /dev/nvram driver for architectures providing some
* generic hooks, that is :
*
- * nvram_read_byte, nvram_write_byte, nvram_sync
+ * nvram_read_byte, nvram_write_byte, nvram_sync, nvram_get_size
*
* Note that an additional hook is supported for PowerMac only
* for getting the nvram partition informations
@@ -28,6 +28,8 @@
#define NVRAM_SIZE 8192
+static ssize_t nvram_len;
+
static loff_t nvram_llseek(struct file *file, loff_t offset, int origin)
{
lock_kernel();
@@ -36,7 +38,7 @@ static loff_t nvram_llseek(struct file *file, loff_t offset,
int origin)
offset += file-f_pos;
break;
case 2:
- offset += NVRAM_SIZE;
+ offset += nvram_len;
break;
}
if (offset 0) {
@@ -56,9 +58,9 @@ static ssize_t read_nvram(struct file *file, char __user *buf,
if (!access_ok(VERIFY_WRITE, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count)
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count)
if (__put_user(nvram_read_byte(i), p))
return -EFAULT;
*ppos = i;
@@ -74,9 +76,9 @@ static ssize_t write_nvram(struct file *file, const char
__user *buf,
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count) {
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count) {
if (__get_user(c, p))
return -EFAULT;
nvram_write_byte(c, i);
@@ -133,9 +135,20 @@ static struct miscdevice nvram_dev = {
int __init nvram_init(void)
{
+ int ret = 0;
+
printk(KERN_INFO Generic non-volatile memory driver v%s\n,
NVRAM_VERSION);
- return misc_register(nvram_dev);
+ ret = misc_register(nvram_dev);
+ if (ret != 0)
+ goto out;
+
+ nvram_len = nvram_get_size();
+ if (nvram_len 0)
+ nvram_len = NVRAM_SIZE;
+
+out:
+ return ret;
}
void __exit nvram_cleanup(void)
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[PATCH v2] powerpc/86xx: Update GE Fanuc sbc310 DTS
Update GE Fanuc DTS to match the alterations suggested during the merge of
the ppc9a DTS in commit 740d36ae6344f38c4da64c2ede765d7d2dd1f132
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
v2: Fixed run on message.
Kumar: I think the problem may be that this patch depends on a previous patch:
http://patchwork.ozlabs.org/patch/29335/
Martyn
arch/powerpc/boot/dts/gef_sbc310.dts | 29 +
1 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 7810ea9..2107d3c 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
/* fl...@0,0 is a mirror of part of the memory in fl...@1,0
fl...@0,0 {
- compatible = cfi-flash;
- reg = 0 0 0x0100;
+ compatible = gef,sbc310-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x0100;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = firmware;
- reg = 0x 0x0100;
+ reg = 0x0 0x0100;
read-only;
};
};
*/
fl...@1,0 {
- compatible = cfi-flash;
- reg = 1 0 0x800;
+ compatible = gef,sbc310-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = user;
- reg = 0x 0x0780;
+ reg = 0x0 0x780;
};
partit...@780 {
label = firmware;
- reg = 0x0780 0x0080;
+ reg = 0x780 0x80;
read-only;
};
};
@@ -121,18 +121,16 @@
};
w...@4,2000 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2000 0x8;
interrupts = 0x1a 0x4;
interrupt-parent = gef_pic;
};
/*
w...@4,2010 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2010 0x8;
interrupts = 0x1b 0x4;
interrupt-parent = gef_pic;
@@ -141,7 +139,7 @@
gef_pic: p...@4,4000 {
#interrupt-cells = 1;
interrupt-controller;
- compatible = gef,fpga-pic;
+ compatible = gef,sbc310-fpga-pic, gef,fpga-pic;
reg = 0x4 0x4000 0x20;
interrupts = 0x8
0x9;
@@ -161,7 +159,7 @@
#size-cells = 1;
#interrupt-cells = 2;
device_type = soc;
- compatible = simple-bus;
+ compatible = fsl,mpc8641-soc, simple-bus;
ranges = 0x0 0xfef0 0x0010;
bus-frequency = ;
@@ -412,5 +410,4 @@
0x0 0x0040;
};
};
-
};
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Re: next branch update
Benjamin Herrenschmidt wrote: So I opened powerpc-next, and pushed the pile that was in test (with an additional bug fix to one of my patches that was causing the crash at boot that mpe reported with hugetlbfs enabled). The pre-req patch for adding an argument to __pte_free_tlb() has already been merged upstream by Linus. Now is time for people who want things into 2.6.32 to be noisy about it. Hi Ben, I'd like to get the NVRAM patches into 2.6.32, I know you said to pester you in a week but your asking now :-) : http://patchwork.ozlabs.org/patch/29420/ http://patchwork.ozlabs.org/patch/29422/ http://patchwork.ozlabs.org/patch/29421/ http://patchwork.ozlabs.org/patch/29419/ http://patchwork.ozlabs.org/patch/29418/ There's also some updates to the boards I work on: http://patchwork.ozlabs.org/patch/29404/ http://patchwork.ozlabs.org/patch/29403/ http://patchwork.ozlabs.org/patch/29402/ http://patchwork.ozlabs.org/patch/29335/ http://patchwork.ozlabs.org/patch/29332/ Kumar: have you had a chance to look at these / are you happy with them? Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/5] Generic NVRAM support for large MMIO devices
Benjamin Herrenschmidt wrote: On Thu, 2009-07-02 at 17:12 +0100, Martyn Welch wrote: The following series allows the generic NVRAM driver to access MMIO based NVRAMs. In addition it enables support for NVRAMs of sizes differing from those found on PowerPC Macs (providing a safe fallback). Patches are also included to enable support for the NVRAM found on the GE Fanuc PPC9A, SBC310 and SBC610. If this patch series is unsuitable this late in the day for 2.6.31, please concider it for 2.6.32. No major issue with the series other than the change to the generic nvram code which needs to not break other architectures :-) Also, it will probably need to go through Andrew Morton, unless there's a maintainer for that driver, is there ? I'm not aware of a maintainer for the generic nvram driver. As mentioned in my other email, I'm fairly confident that this driver (/drivers/char/generic_nvram.c) is only used on PowerPC. I'm beginning to enter what is for me uncharted territory :-) How should I proceed? Are you happy to take the entire patch series, do I send the entire patch series to Andrew and LKML or just patch 2/5? Martyn Once you sort out that aspect of the patch series, I'm happy to take the rest in powerpc.git Cheers, Ben. -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/5] Mechanism to enable use Generic NVRAM driver for different size chips
Benjamin Herrenschmidt wrote:
On Thu, 2009-07-02 at 17:12 +0100, Martyn Welch wrote:
Remove the reliance on a staticly defined NVRAM size, allowing platforms to
support NVRAMs with sizes differing from the standard. A fall back value is
provided for platforms not supporting this extension.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
What about other archs that use this driver ? They would also need
that new nvram_size() ...
I'm fairly confident that this driver is solely used by the PowerPC
architecture. The config option being set in arch/powerpc/Kconfig[1].
Other than the obvious matches in drivers/char/Makefile[2] and powerpc
defconfigs, the only other places I can find the option being used are:
* As a requirement for CONFIG_NVRAM on the PowerPC platform in
drivers/char/Kconfig[3]
* In include/config/auto.conf and include/linux/autoconf.h. Are
these for generation of generic configs?
Martyn
[1]
http://git.kernel.org/gitweb.cgi?p=linux/kernel/git/benh/powerpc.git;a=blob;f=arch/powerpc/Kconfig#l145
[2]
http://git.kernel.org/gitweb.cgi?p=linux/kernel/git/benh/powerpc.git;a=blob;f=drivers/char/Makefile#l83
[3]
http://git.kernel.org/gitweb.cgi?p=linux/kernel/git/benh/powerpc.git;a=blob;f=drivers/char/Kconfig#l777
BTW. This patch touches non-arch code so should at least be CCed to lkml
Cheers,
Ben.
---
arch/powerpc/include/asm/nvram.h |3 +++
arch/powerpc/kernel/setup_32.c |8
drivers/char/generic_nvram.c | 27 ---
3 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index efde5ac..71df8b2 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -107,6 +107,9 @@ extern void pmac_xpram_write(int xpaddr, u8 data);
/* Synchronize NVRAM */
extern voidnvram_sync(void);
+/* Determine NVRAM size */
+extern ssize_t nvram_size(void);
+
/* Normal access to NVRAM */
extern unsigned char nvram_read_byte(int i);
extern void nvram_write_byte(unsigned char c, int i);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d15424..28f7570 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -208,6 +208,14 @@ void nvram_write_byte(unsigned char val, int addr)
}
EXPORT_SYMBOL(nvram_write_byte);
+ssize_t nvram_size(void)
+{
+ if (ppc_md.nvram_size)
+ return ppc_md.nvram_size();
+ return -1;
+}
+EXPORT_SYMBOL(nvram_size);
+
void nvram_sync(void)
{
if (ppc_md.nvram_sync)
diff --git a/drivers/char/generic_nvram.c b/drivers/char/generic_nvram.c
index a00869c..e5f71f3 100644
--- a/drivers/char/generic_nvram.c
+++ b/drivers/char/generic_nvram.c
@@ -2,7 +2,7 @@
* Generic /dev/nvram driver for architectures providing some
* generic hooks, that is :
*
- * nvram_read_byte, nvram_write_byte, nvram_sync
+ * nvram_read_byte, nvram_write_byte, nvram_sync, nvram_size
*
* Note that an additional hook is supported for PowerMac only
* for getting the nvram partition informations
@@ -28,6 +28,8 @@
#define NVRAM_SIZE 8192
+static ssize_t nvram_len;
+
static loff_t nvram_llseek(struct file *file, loff_t offset, int origin)
{
lock_kernel();
@@ -36,7 +38,7 @@ static loff_t nvram_llseek(struct file *file, loff_t offset,
int origin)
offset += file-f_pos;
break;
case 2:
- offset += NVRAM_SIZE;
+ offset += nvram_len;
break;
}
if (offset 0) {
@@ -56,9 +58,9 @@ static ssize_t read_nvram(struct file *file, char __user *buf,
if (!access_ok(VERIFY_WRITE, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count)
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count)
if (__put_user(nvram_read_byte(i), p))
return -EFAULT;
*ppos = i;
@@ -74,9 +76,9 @@ static ssize_t write_nvram(struct file *file, const char
__user *buf,
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count) {
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count) {
if (__get_user(c, p))
return -EFAULT;
nvram_write_byte(c, i);
@@ -133,9 +135,20 @@ static struct miscdevice nvram_dev = {
int __init nvram_init(void)
{
+ int ret = 0;
+
printk(KERN_INFO Generic non-volatile memory driver v%s\n,
NVRAM_VERSION);
- return misc_register(nvram_dev);
+ ret = misc_register(nvram_dev);
+ if (ret != 0)
+ goto out;
+
+ nvram_len = nvram_size
[PATCH] powerpc/86xx: Update GE Fanuc sbc310 DTS
Update GE Fanuc DTS to match the alterations suggested during the merge of the
ppc9a DTS in commit 740d36ae6344f38c4da64c2ede765d7d2dd1f132
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts | 29 +
1 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 7810ea9..2107d3c 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
/* fl...@0,0 is a mirror of part of the memory in fl...@1,0
fl...@0,0 {
- compatible = cfi-flash;
- reg = 0 0 0x0100;
+ compatible = gef,sbc310-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x0100;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = firmware;
- reg = 0x 0x0100;
+ reg = 0x0 0x0100;
read-only;
};
};
*/
fl...@1,0 {
- compatible = cfi-flash;
- reg = 1 0 0x800;
+ compatible = gef,sbc310-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
bank-width = 2;
device-width = 2;
#address-cells = 1;
#size-cells = 1;
partit...@0 {
label = user;
- reg = 0x 0x0780;
+ reg = 0x0 0x780;
};
partit...@780 {
label = firmware;
- reg = 0x0780 0x0080;
+ reg = 0x780 0x80;
read-only;
};
};
@@ -121,18 +121,16 @@
};
w...@4,2000 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2000 0x8;
interrupts = 0x1a 0x4;
interrupt-parent = gef_pic;
};
/*
w...@4,2010 {
- #interrupt-cells = 2;
- device_type = watchdog;
- compatible = gef,fpga-wdt;
+ compatible = gef,sbc310-fpga-wdt, gef,fpga-wdt-1.00,
+ gef,fpga-wdt;
reg = 0x4 0x2010 0x8;
interrupts = 0x1b 0x4;
interrupt-parent = gef_pic;
@@ -141,7 +139,7 @@
gef_pic: p...@4,4000 {
#interrupt-cells = 1;
interrupt-controller;
- compatible = gef,fpga-pic;
+ compatible = gef,sbc310-fpga-pic, gef,fpga-pic;
reg = 0x4 0x4000 0x20;
interrupts = 0x8
0x9;
@@ -161,7 +159,7 @@
#size-cells = 1;
#interrupt-cells = 2;
device_type = soc;
- compatible = simple-bus;
+ compatible = fsl,mpc8641-soc, simple-bus;
ranges = 0x0 0xfef0 0x0010;
bus-frequency = ;
@@ -412,5 +410,4 @@
0x0 0x0040;
};
};
-
};
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[PATCH] powerpc/86xx: Update defconfig for GE Fanuc's PPC9A
General update of defconfig including the following notable changes: - Enable GPIO access via sysfs on GE Fanuc's PPC9A. - Enable Highmem support. - Support for PCMCIA based daughter card. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 518 + 1 files changed, 196 insertions(+), 322 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index b6a23af..d8354d9 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -1,26 +1,28 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc3 -# Wed May 13 17:22:31 2009 +# Linux kernel version: 2.6.30 +# Thu Jul 2 13:55:24 2009 # # CONFIG_PPC64 is not set # # Processor support # -CONFIG_6xx=y +CONFIG_PPC_BOOK3S_32=y # CONFIG_PPC_85xx is not set # CONFIG_PPC_8xx is not set # CONFIG_40x is not set # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_BOOK3S=y +CONFIG_6xx=y CONFIG_PPC_FPU=y # CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y # CONFIG_PPC_MM_SLICES is not set +CONFIG_PPC_HAVE_PMU_SUPPORT=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y @@ -32,6 +34,7 @@ CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -41,7 +44,6 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_LOCKBREAK=y CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set @@ -56,11 +58,13 @@ CONFIG_PPC_UDBG_16550=y CONFIG_GENERIC_TBSYNC=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y +CONFIG_DTC=y CONFIG_DEFAULT_UIMAGE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config +CONFIG_CONSTRUCTORS=y # # General setup @@ -112,9 +116,7 @@ CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -127,8 +129,15 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -143,6 +152,10 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_USE_GENERIC_SMP_HELPERS=y + +# +# GCOV-based kernel profiling +# # CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y @@ -156,7 +169,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -216,7 +229,7 @@ CONFIG_MPIC=y # # Kernel options # -# CONFIG_HIGHMEM is not set +CONFIG_HIGHMEM=y CONFIG_TICK_ONESHOT=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y @@ -235,6 +248,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=m # CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y @@ -256,9 +270,9 @@ CONFIG_MIGRATION=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_PPC_4K_PAGES=y # CONFIG_PPC_16K_PAGES is not set # CONFIG_PPC_64K_PAGES is not set @@ -285,14 +299,32 @@ CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y CONFIG_PCIEPORTBUS=y CONFIG_PCIEAER=y +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set # CONFIG_PCI_LEGACY is not set -CONFIG_PCI_DEBUG=y # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set -# CONFIG_PCCARD is not set +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_IOCTL is not set +# CONFIG_CARDBUS is not set + +# +# PC-card bridges +# +CONFIG_YENTA=y +# CONFIG_YENTA_O2 is not set +# CONFIG_YENTA_RICOH is not set +CONFIG_YENTA_TI=y +# CONFIG_YENTA_TOSHIBA is not set +# CONFIG_PD6729 is not set +# CONFIG_I82092 is not set +CONFIG_PCCARD_NONSTATIC=y # CONFIG_HOTPLUG_PCI is not set # CONFIG_HAS_RAPIDIO is not set @@ -353,8 +385,8 @@ CONFIG_INET_XFRM_TUNNEL=m
[PATCH] powerpc/86xx: Update GE Fanuc sbc310 default configuration
General update of defconfig including the following notable changes: - Enable Highmem support. - Support for PCMCIA based daughter card. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_sbc310_defconfig | 213 +--- 1 files changed, 154 insertions(+), 59 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig index a66910e..f2362e5 100644 --- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig @@ -1,26 +1,28 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc3 -# Wed May 13 17:22:29 2009 +# Linux kernel version: 2.6.30 +# Thu Jul 2 14:10:12 2009 # # CONFIG_PPC64 is not set # # Processor support # -CONFIG_6xx=y +CONFIG_PPC_BOOK3S_32=y # CONFIG_PPC_85xx is not set # CONFIG_PPC_8xx is not set # CONFIG_40x is not set # CONFIG_44x is not set # CONFIG_E200 is not set CONFIG_PPC_BOOK3S=y +CONFIG_6xx=y CONFIG_PPC_FPU=y # CONFIG_PHYS_64BIT is not set CONFIG_ALTIVEC=y CONFIG_PPC_STD_MMU=y CONFIG_PPC_STD_MMU_32=y # CONFIG_PPC_MM_SLICES is not set +CONFIG_PPC_HAVE_PMU_SUPPORT=y CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PPC32=y @@ -32,6 +34,7 @@ CONFIG_GENERIC_TIME=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set CONFIG_IRQ_PER_CPU=y CONFIG_STACKTRACE_SUPPORT=y @@ -41,7 +44,6 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_LOCKBREAK=y CONFIG_ARCH_HAS_ILOG2_U32=y CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_GPIO=y # CONFIG_ARCH_NO_VIRT_TO_BUS is not set @@ -56,11 +58,13 @@ CONFIG_PPC_UDBG_16550=y CONFIG_GENERIC_TBSYNC=y CONFIG_AUDIT_ARCH=y CONFIG_GENERIC_BUG=y +CONFIG_DTC=y CONFIG_DEFAULT_UIMAGE=y # CONFIG_PPC_DCR_NATIVE is not set # CONFIG_PPC_DCR_MMIO is not set CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config +CONFIG_CONSTRUCTORS=y # # General setup @@ -91,7 +95,11 @@ CONFIG_CLASSIC_RCU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y @@ -109,7 +117,6 @@ CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -122,8 +129,15 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y +CONFIG_HAVE_PERF_COUNTERS=y + +# +# Performance Counters +# +# CONFIG_PERF_COUNTERS is not set CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -138,6 +152,10 @@ CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_USE_GENERIC_SMP_HELPERS=y + +# +# GCOV-based kernel profiling +# # CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y @@ -151,7 +169,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -168,7 +186,6 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED=cfq # CONFIG_FREEZER is not set -CONFIG_PPC_MSI_BITMAP=y # # Platform support @@ -212,7 +229,7 @@ CONFIG_MPIC=y # # Kernel options # -# CONFIG_HIGHMEM is not set +CONFIG_HIGHMEM=y CONFIG_TICK_ONESHOT=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y @@ -231,6 +248,7 @@ CONFIG_BINFMT_ELF=y # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y # CONFIG_IOMMU_HELPER is not set +# CONFIG_SWIOTLB is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_HAS_WALK_MEMORY=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y @@ -252,9 +270,9 @@ CONFIG_MIGRATION=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_PPC_4K_PAGES=y # CONFIG_PPC_16K_PAGES is not set # CONFIG_PPC_64K_PAGES is not set @@ -281,13 +299,32 @@ CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y CONFIG_PCIEPORTBUS=y CONFIG_PCIEAER=y +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y -CONFIG_PCI_MSI=y +# CONFIG_PCI_MSI is not set # CONFIG_PCI_LEGACY is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set -# CONFIG_PCCARD is not set +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y
[PATCH 0/5] Generic NVRAM support for large MMIO devices
The following series allows the generic NVRAM driver to access MMIO based NVRAMs. In addition it enables support for NVRAMs of sizes differing from those found on PowerPC Macs (providing a safe fallback). Patches are also included to enable support for the NVRAM found on the GE Fanuc PPC9A, SBC310 and SBC610. If this patch series is unsuitable this late in the day for 2.6.31, please concider it for 2.6.32. Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/5] Allow byte length reads from mmio NVRAM driver
Add a byte length read and write interface compatible with the nvram_generic
driver interface to the mmio driver.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/sysdev/mmio_nvram.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/mmio_nvram.c b/arch/powerpc/sysdev/mmio_nvram.c
index 7b49633..2073242 100644
--- a/arch/powerpc/sysdev/mmio_nvram.c
+++ b/arch/powerpc/sysdev/mmio_nvram.c
@@ -53,6 +53,23 @@ static ssize_t mmio_nvram_read(char *buf, size_t count,
loff_t *index)
return count;
}
+static unsigned char mmio_nvram_read_val(int addr)
+{
+ unsigned long flags;
+ unsigned char val;
+
+ if (addr = mmio_nvram_len)
+ return 0xff;
+
+ spin_lock_irqsave(mmio_nvram_lock, flags);
+
+ val = ioread8(mmio_nvram_start + addr);
+
+ spin_unlock_irqrestore(mmio_nvram_lock, flags);
+
+ return val;
+}
+
static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
{
unsigned long flags;
@@ -72,6 +89,19 @@ static ssize_t mmio_nvram_write(char *buf, size_t count,
loff_t *index)
return count;
}
+void mmio_nvram_write_val(int addr, unsigned char val)
+{
+ unsigned long flags;
+
+ if (addr mmio_nvram_len) {
+ spin_lock_irqsave(mmio_nvram_lock, flags);
+
+ iowrite8(val, mmio_nvram_start + addr);
+
+ spin_unlock_irqrestore(mmio_nvram_lock, flags);
+ }
+}
+
static ssize_t mmio_nvram_get_size(void)
{
return mmio_nvram_len;
@@ -114,6 +144,8 @@ int __init mmio_nvram_init(void)
printk(KERN_INFO mmio NVRAM, %luk at 0x%lx mapped to %p\n,
mmio_nvram_len 10, nvram_addr, mmio_nvram_start);
+ ppc_md.nvram_read_val = mmio_nvram_read_val;
+ ppc_md.nvram_write_val = mmio_nvram_write_val;
ppc_md.nvram_read = mmio_nvram_read;
ppc_md.nvram_write = mmio_nvram_write;
ppc_md.nvram_size = mmio_nvram_get_size;
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[PATCH 2/5] Mechanism to enable use Generic NVRAM driver for different size chips
Remove the reliance on a staticly defined NVRAM size, allowing platforms to
support NVRAMs with sizes differing from the standard. A fall back value is
provided for platforms not supporting this extension.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/include/asm/nvram.h |3 +++
arch/powerpc/kernel/setup_32.c |8
drivers/char/generic_nvram.c | 27 ---
3 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index efde5ac..71df8b2 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -107,6 +107,9 @@ extern void pmac_xpram_write(int xpaddr, u8 data);
/* Synchronize NVRAM */
extern voidnvram_sync(void);
+/* Determine NVRAM size */
+extern ssize_t nvram_size(void);
+
/* Normal access to NVRAM */
extern unsigned char nvram_read_byte(int i);
extern void nvram_write_byte(unsigned char c, int i);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1d15424..28f7570 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -208,6 +208,14 @@ void nvram_write_byte(unsigned char val, int addr)
}
EXPORT_SYMBOL(nvram_write_byte);
+ssize_t nvram_size(void)
+{
+ if (ppc_md.nvram_size)
+ return ppc_md.nvram_size();
+ return -1;
+}
+EXPORT_SYMBOL(nvram_size);
+
void nvram_sync(void)
{
if (ppc_md.nvram_sync)
diff --git a/drivers/char/generic_nvram.c b/drivers/char/generic_nvram.c
index a00869c..e5f71f3 100644
--- a/drivers/char/generic_nvram.c
+++ b/drivers/char/generic_nvram.c
@@ -2,7 +2,7 @@
* Generic /dev/nvram driver for architectures providing some
* generic hooks, that is :
*
- * nvram_read_byte, nvram_write_byte, nvram_sync
+ * nvram_read_byte, nvram_write_byte, nvram_sync, nvram_size
*
* Note that an additional hook is supported for PowerMac only
* for getting the nvram partition informations
@@ -28,6 +28,8 @@
#define NVRAM_SIZE 8192
+static ssize_t nvram_len;
+
static loff_t nvram_llseek(struct file *file, loff_t offset, int origin)
{
lock_kernel();
@@ -36,7 +38,7 @@ static loff_t nvram_llseek(struct file *file, loff_t offset,
int origin)
offset += file-f_pos;
break;
case 2:
- offset += NVRAM_SIZE;
+ offset += nvram_len;
break;
}
if (offset 0) {
@@ -56,9 +58,9 @@ static ssize_t read_nvram(struct file *file, char __user *buf,
if (!access_ok(VERIFY_WRITE, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count)
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count)
if (__put_user(nvram_read_byte(i), p))
return -EFAULT;
*ppos = i;
@@ -74,9 +76,9 @@ static ssize_t write_nvram(struct file *file, const char
__user *buf,
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
- if (*ppos = NVRAM_SIZE)
+ if (*ppos = nvram_len)
return 0;
- for (i = *ppos; count 0 i NVRAM_SIZE; ++i, ++p, --count) {
+ for (i = *ppos; count 0 i nvram_len; ++i, ++p, --count) {
if (__get_user(c, p))
return -EFAULT;
nvram_write_byte(c, i);
@@ -133,9 +135,20 @@ static struct miscdevice nvram_dev = {
int __init nvram_init(void)
{
+ int ret = 0;
+
printk(KERN_INFO Generic non-volatile memory driver v%s\n,
NVRAM_VERSION);
- return misc_register(nvram_dev);
+ ret = misc_register(nvram_dev);
+ if (ret != 0)
+ goto out;
+
+ nvram_len = nvram_size();
+ if (nvram_len 0)
+ nvram_len = NVRAM_SIZE;
+
+out:
+ return ret;
}
void __exit nvram_cleanup(void)
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[PATCH 5/5] powerpc/86xx: Support for NVRAM on GE Fanuc's PPC9A
Add support for NVRAM on GE Fanuc's PPC9A.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts |6 ++
arch/powerpc/configs/86xx/gef_ppc9a_defconfig |4 ++--
arch/powerpc/platforms/86xx/Kconfig |1 +
arch/powerpc/platforms/86xx/gef_ppc9a.c |5 +
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 910944e..c86114e 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -118,6 +118,12 @@
};
};
+ nv...@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
f...@4,0 {
compatible = gef,ppc9a-fpga-regs;
reg = 0x4 0x0 0x40;
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index d8354d9..e175abf 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30
-# Thu Jul 2 13:55:24 2009
+# Thu Jul 2 13:59:13 2009
#
# CONFIG_PPC64 is not set
@@ -214,7 +214,7 @@ CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index 6012022..2bbfd53 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -35,6 +35,7 @@ config MPC8610_HPCD
config GEF_PPC9A
bool GE Fanuc PPC9A
select DEFAULT_UIMAGE
+ select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c
b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 287f7bd..a792e5d 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -33,6 +33,7 @@
#include asm/udbg.h
#include asm/mpic.h
+#include asm/nvram.h
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
@@ -95,6 +96,10 @@ static void __init gef_ppc9a_setup_arch(void)
printk(KERN_WARNING Unable to map board registers\n);
of_node_put(regs);
}
+
+#if defined(CONFIG_MMIO_NVRAM)
+ mmio_nvram_init();
+#endif
}
/* Return the PCB revision */
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[PATCH 3/5] powerpc/86xx: Enable NVRAM on GE Fanuc's SBC610
This patch enables the NVRAM found on the GE Fanuc SBC610
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc610.dts |6 ++
arch/powerpc/configs/86xx/gef_sbc610_defconfig |4 ++--
arch/powerpc/platforms/86xx/Kconfig|1 +
arch/powerpc/platforms/86xx/gef_sbc610.c |5 +
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
index 35a6318..30911ad 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -84,6 +84,12 @@
6 0 0xfd00 0x0080 // IO FPGA (8-bit)
7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+ nv...@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
f...@4,0 {
compatible = gef,fpga-regs;
reg = 0x4 0x0 0x40;
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index c6a7fc8..b4a7c03 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -201,7 +201,7 @@ CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
@@ -1083,7 +1083,7 @@ CONFIG_UNIX98_PTYS=y
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_NVRAM is not set
+CONFIG_NVRAM=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index 9c7b64a..9d02dea 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -51,6 +51,7 @@ config GEF_SBC310
config GEF_SBC610
bool GE Fanuc SBC610
select DEFAULT_UIMAGE
+ select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAS_RAPIDIO
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c
b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 72b31a6..e10688a 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -33,6 +33,7 @@
#include asm/udbg.h
#include asm/mpic.h
+#include asm/nvram.h
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
@@ -95,6 +96,10 @@ static void __init gef_sbc610_setup_arch(void)
printk(KERN_WARNING Unable to map board registers\n);
of_node_put(regs);
}
+
+#if defined(CONFIG_MMIO_NVRAM)
+ mmio_nvram_init();
+#endif
}
/* Return the PCB revision */
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[PATCH 4/5] powerpc/86xx: Support for NVRAM on GE Fanuc's SBC310
Add support for NVRAM on GE Fanuc's SBC310.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts |6 ++
arch/powerpc/configs/86xx/gef_sbc310_defconfig |4 ++--
arch/powerpc/platforms/86xx/Kconfig|1 +
arch/powerpc/platforms/86xx/gef_sbc310.c |5 +
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 2107d3c..820c2b3 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -115,6 +115,12 @@
};
};
+ nv...@3,0 {
+ device_type = nvram;
+ compatible = simtek,stk14ca8;
+ reg = 0x3 0x0 0x2;
+ };
+
f...@4,0 {
compatible = gef,fpga-regs;
reg = 0x4 0x0 0x40;
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
index f2362e5..3d70f2a 100644
--- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30
-# Thu Jul 2 14:10:12 2009
+# Thu Jul 2 14:10:51 2009
#
# CONFIG_PPC64 is not set
@@ -214,7 +214,7 @@ CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
-# CONFIG_MMIO_NVRAM is not set
+CONFIG_MMIO_NVRAM=y
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
diff --git a/arch/powerpc/platforms/86xx/Kconfig
b/arch/powerpc/platforms/86xx/Kconfig
index 9d02dea..6012022 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -43,6 +43,7 @@ config GEF_PPC9A
config GEF_SBC310
bool GE Fanuc SBC310
select DEFAULT_UIMAGE
+ select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c
b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 90754e7..6a1a613 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -33,6 +33,7 @@
#include asm/udbg.h
#include asm/mpic.h
+#include asm/nvram.h
#include sysdev/fsl_pci.h
#include sysdev/fsl_soc.h
@@ -95,6 +96,10 @@ static void __init gef_sbc310_setup_arch(void)
printk(KERN_WARNING Unable to map board registers\n);
of_node_put(regs);
}
+
+#if defined(CONFIG_MMIO_NVRAM)
+ mmio_nvram_init();
+#endif
}
/* Return the PCB revision */
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[PATCH] powerpc/86xx: Correct reading of information presented in cpuinfo
/proc/cpuinfo should be showing the boards revision and the revision of the
FPGA fitted. The functions currently used to access this information as
incorrect.
Additionally the VME geographical address of the PPC9A and it's status as
system contoller are available in the board registers. Show these in cpuinfo.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/platforms/86xx/gef_ppc9a.c | 37 +--
1 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c
b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 2efa052..287f7bd 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -102,8 +102,8 @@ static unsigned int gef_ppc9a_get_pcb_rev(void)
{
unsigned int reg;
- reg = ioread32(ppc9a_regs);
- return (reg 8) 0xff;
+ reg = ioread32be(ppc9a_regs);
+ return (reg 16) 0xff;
}
/* Return the board (software) revision */
@@ -111,8 +111,8 @@ static unsigned int gef_ppc9a_get_board_rev(void)
{
unsigned int reg;
- reg = ioread32(ppc9a_regs);
- return (reg 16) 0xff;
+ reg = ioread32be(ppc9a_regs);
+ return (reg 8) 0xff;
}
/* Return the FPGA revision */
@@ -120,8 +120,26 @@ static unsigned int gef_ppc9a_get_fpga_rev(void)
{
unsigned int reg;
- reg = ioread32(ppc9a_regs);
- return (reg 24) 0xf;
+ reg = ioread32be(ppc9a_regs);
+ return reg 0xf;
+}
+
+/* Return VME Geographical Address */
+static unsigned int gef_ppc9a_get_vme_geo_addr(void)
+{
+ unsigned int reg;
+
+ reg = ioread32be(ppc9a_regs + 0x4);
+ return reg 0x1f;
+}
+
+/* Return VME System Controller Status */
+static unsigned int gef_ppc9a_get_vme_is_syscon(void)
+{
+ unsigned int reg;
+
+ reg = ioread32be(ppc9a_regs + 0x4);
+ return (reg 9) 0x1;
}
static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
@@ -131,10 +149,15 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
seq_printf(m, Vendor\t\t: GE Fanuc Intelligent Platforms\n);
seq_printf(m, Revision\t: %u%c\n, gef_ppc9a_get_pcb_rev(),
- ('A' + gef_ppc9a_get_board_rev() - 1));
+ ('A' + gef_ppc9a_get_board_rev()));
seq_printf(m, FPGA Revision\t: %u\n, gef_ppc9a_get_fpga_rev());
seq_printf(m, SVR\t\t: 0x%x\n, svid);
+
+ seq_printf(m, VME geo. addr\t: %u\n, gef_ppc9a_get_vme_geo_addr());
+
+ seq_printf(m, VME syscon\t: %s\n,
+ gef_ppc9a_get_vme_is_syscon() ? yes : no);
}
static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
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[PATCH] powerpc/86xx: Enable XMC site on GE Fanuc SBC310
This patch enables the XMC (PCIe daughter card) site on the SBC310.
STG enter the description for the patch above.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts | 37 ++
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts
b/arch/powerpc/boot/dts/gef_sbc310.dts
index 0f4c9ec..7810ea9 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -376,4 +376,41 @@
0x0 0x0040;
};
};
+
+ pci1: p...@fef09000 {
+ compatible = fsl,mpc8641-pcie;
+ device_type = pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ reg = 0xfef09000 0x1000;
+ bus-range = 0x0 0xff;
+ ranges = 0x0200 0x0 0xc000 0xc000 0x0 0x2000
+ 0x0100 0x0 0x 0xfe40 0x0 0x0040;
+ clock-frequency = ;
+ interrupt-parent = mpic;
+ interrupts = 0x19 0x2;
+ interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+ interrupt-map =
+ 0x 0x0 0x0 0x1 mpic 0x4 0x2
+ 0x 0x0 0x0 0x2 mpic 0x5 0x2
+ 0x 0x0 0x0 0x3 mpic 0x6 0x2
+ 0x 0x0 0x0 0x4 mpic 0x7 0x2
+ ;
+
+ p...@0 {
+ reg = 0 0 0 0 0;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ ranges = 0x0200 0x0 0xc000
+ 0x0200 0x0 0xc000
+ 0x0 0x2000
+
+ 0x0100 0x0 0x
+ 0x0100 0x0 0x
+ 0x0 0x0040;
+ };
+ };
+
};
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[PATCH] powerpc/86xx: Add I2C device mappings in DTS for SBC610
Mappings for temperature sensors (adt7461 and lm92) are missing from the
SBC610's DTS file.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc610.dts | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
index 6898d7e..85d1416 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -153,6 +153,16 @@
interrupt-parent = mpic;
dfsrr;
+ hw...@48 {
+ compatible = national,lm92;
+ reg = 0x48;
+ };
+
+ hw...@4c {
+ compatible = adi,adt7461;
+ reg = 0x4c;
+ };
+
r...@51 {
compatible = epson,rx8581;
reg = 0x0051;
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Re: [PATCH 2/2] powerpc/86xx: Add new LAW MCM device tree nodes for all 86xx systems
Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/boot/dts/gef_ppc9a.dts| 13 + arch/powerpc/boot/dts/gef_sbc310.dts | 13 + arch/powerpc/boot/dts/gef_sbc610.dts | 13 + arch/powerpc/boot/dts/mpc8610_hpcd.dts | 13 + arch/powerpc/boot/dts/mpc8641_hpcn.dts | 13 + arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts | 13 + arch/powerpc/boot/dts/sbc8641d.dts | 13 + 7 files changed, 91 insertions(+), 0 deletions(-) Am I right in thinking that this patch doesn't (as yet) enable any added functionality, or have I missed something? I assume this is destined for next (as it relies on Becky's powerpc/86xx: Add 36-bit device tree for mpc8641hpcn), assuming this, fwiw, seems good to me. Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 927559189 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] powerpc/86xx: clean up smp init code
Kumar Gala wrote: On Apr 23, 2009, at 7:54 AM, Martyn Welch wrote: Kumar Gala wrote: Removed the need for asm/mpc86xx.h as it was only used in mpc86xx_smp.c and just moved the defines it cared about into there. Also fixed up the ioremap to only map the one 4k page we need access to and to iounmap when we are done. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/include/asm/mpc86xx.h | 33 arch/powerpc/platforms/86xx/gef_ppc9a.c|1 - arch/powerpc/platforms/86xx/gef_sbc310.c |1 - arch/powerpc/platforms/86xx/gef_sbc610.c |1 - arch/powerpc/platforms/86xx/mpc8610_hpcd.c |1 - arch/powerpc/platforms/86xx/mpc86xx_hpcn.c |1 - arch/powerpc/platforms/86xx/mpc86xx_smp.c |8 ++- arch/powerpc/platforms/86xx/sbc8641d.c |1 - 8 files changed, 7 insertions(+), 40 deletions(-) delete mode 100644 arch/powerpc/include/asm/mpc86xx.h I assume this patch relies on one of the other patches posted? Just applying this patch to my development tree (based on your main branch) resulted in the following on a PPC9A: mpic: requesting IPIs ... __ioremap(): phys addr 0x0 is RAM lr c041e5c8 Unable to handle kernel paging request for data at address 0x0010 Faulting instruction address: 0xc041e5cc Oops: Kernel access of bad area, sig: 11 [#1] PREEMPT SMP NR_CPUS=2 GE Fanuc PPC9A Modules linked in: NIP: c041e5cc LR: c041e5c8 CTR: c0013d90 REGS: ef841ea0 TRAP: 0300 Not tainted (2.6.30-rc3-00016-gabae74f) MSR: 1032 ME,IR,DR CR: 2422 XER: DAR: 0010, DSISR: 4000 TASK = ef83f980[1] 'swapper' THREAD: ef84 CPU: 0 GPR00: c041e5c8 ef841f50 ef83f980 1032 c048 4000 GPR08: c0441a4c ef84 c044 2242 dfff 0ff50d00 0001 GPR16: c044 c048 c048 c0468000 c044 c0442838 GPR24: 0002 c048 c048 7d5043a6 9032 0004 0001 c350 NIP [c041e5cc] smp_86xx_kick_cpu+0x70/0x11c LR [c041e5c8] smp_86xx_kick_cpu+0x6c/0x11c Call Trace: [ef841f50] [c041e5c8] smp_86xx_kick_cpu+0x6c/0x11c (unreliable) [ef841f70] [c0435010] __cpu_up+0xa4/0x1b0 [ef841f90] [c04355ec] cpu_up+0x104/0x1cc [ef841fd0] [c0412368] kernel_init+0x1d8/0x1f0 [ef841ff0] [c0012cb8] kernel_thread+0x4c/0x68 Instruction dump: 3c80c000 61290100 38a1 7d234b78 38843464 8369 4bbfa7f9 4bbfcb21 38801000 38631000 4bbf91ad 7c0004ac 81230010 0c09 4c00012c 3801 ---[ end trace 31fd0ba7d8756001 ]--- Kernel panic - not syncing: Attempted to kill init! Rebooting in 180 seconds.. I'm not able to reproduce this failure. It seems like either ioremap is returning 0 or you are getting 0 from get_immrbase().. either way I don't see how my change would cause what you are seeing on your board. I've just built the kernel with no local patches in case they were causing the problem and adding this patch causes the above problem. Are you running w/CONFIG_PHYS_64BIT=y? I am using the config in the kernel (arch/powerpc/configs/68xx/gef_ppc9a_defconfig) as is, ditto for the DTS. CONFIG_PHYS_64BIT is not set. However, looking into it a bit further 'device_type = soc;' is missing from the DTS file, so I assume get_immrbase() is returning -1. That might explain some other weird errors I recently noticed that I haven't managed to find the time to track down yet... Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] powerpc/86xx: Add device_type entry to soc for ppc9a
The 'device_type = soc;' line *is* needed in the DTS for get_immrbase() to return the correct address. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/boot/dts/gef_ppc9a.dts |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts index d47ad07..53a7a62 100644 --- a/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -161,6 +161,7 @@ #address-cells = 1; #size-cells = 1; #interrupt-cells = 2; + device_type = soc; compatible = fsl,mpc8641-soc, simple-bus; ranges = 0x0 0xfef0 0x0010; reg = 0xfef0 0x10;// CCSRBAR 1M ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] powerpc/86xx: clean up smp init code
Kumar Gala wrote: Removed the need for asm/mpc86xx.h as it was only used in mpc86xx_smp.c and just moved the defines it cared about into there. Also fixed up the ioremap to only map the one 4k page we need access to and to iounmap when we are done. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/include/asm/mpc86xx.h | 33 arch/powerpc/platforms/86xx/gef_ppc9a.c|1 - arch/powerpc/platforms/86xx/gef_sbc310.c |1 - arch/powerpc/platforms/86xx/gef_sbc610.c |1 - arch/powerpc/platforms/86xx/mpc8610_hpcd.c |1 - arch/powerpc/platforms/86xx/mpc86xx_hpcn.c |1 - arch/powerpc/platforms/86xx/mpc86xx_smp.c |8 ++- arch/powerpc/platforms/86xx/sbc8641d.c |1 - 8 files changed, 7 insertions(+), 40 deletions(-) delete mode 100644 arch/powerpc/include/asm/mpc86xx.h I assume this patch relies on one of the other patches posted? Just applying this patch to my development tree (based on your main branch) resulted in the following on a PPC9A: mpic: requesting IPIs ... __ioremap(): phys addr 0x0 is RAM lr c041e5c8 Unable to handle kernel paging request for data at address 0x0010 Faulting instruction address: 0xc041e5cc Oops: Kernel access of bad area, sig: 11 [#1] PREEMPT SMP NR_CPUS=2 GE Fanuc PPC9A Modules linked in: NIP: c041e5cc LR: c041e5c8 CTR: c0013d90 REGS: ef841ea0 TRAP: 0300 Not tainted (2.6.30-rc3-00016-gabae74f) MSR: 1032 ME,IR,DR CR: 2422 XER: DAR: 0010, DSISR: 4000 TASK = ef83f980[1] 'swapper' THREAD: ef84 CPU: 0 GPR00: c041e5c8 ef841f50 ef83f980 1032 c048 4000 GPR08: c0441a4c ef84 c044 2242 dfff 0ff50d00 0001 GPR16: c044 c048 c048 c0468000 c044 c0442838 GPR24: 0002 c048 c048 7d5043a6 9032 0004 0001 c350 NIP [c041e5cc] smp_86xx_kick_cpu+0x70/0x11c LR [c041e5c8] smp_86xx_kick_cpu+0x6c/0x11c Call Trace: [ef841f50] [c041e5c8] smp_86xx_kick_cpu+0x6c/0x11c (unreliable) [ef841f70] [c0435010] __cpu_up+0xa4/0x1b0 [ef841f90] [c04355ec] cpu_up+0x104/0x1cc [ef841fd0] [c0412368] kernel_init+0x1d8/0x1f0 [ef841ff0] [c0012cb8] kernel_thread+0x4c/0x68 Instruction dump: 3c80c000 61290100 38a1 7d234b78 38843464 8369 4bbfa7f9 4bbfcb21 38801000 38631000 4bbf91ad 7c0004ac 81230010 0c09 4c00012c 3801 ---[ end trace 31fd0ba7d8756001 ]--- Kernel panic - not syncing: Attempted to kill init! Rebooting in 180 seconds.. Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 4/4] powerpc/86xx: Move gianfar mdio nodes under the ethernet nodes
Anton Vorontsov wrote: Currently it doesn't matter where the mdio nodes are placed, but with power management support (i.e. when sleep = properties will take effect), mdio nodes placement will become important: mdio controller is a part of the ethernet block, so the mdio nodes should be placed correctly. Otherwise we may wrongly assume that MDIO controllers are available during sleep. Suggested-by: Scott Wood scottw...@freescale.com Suggested-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com --- arch/powerpc/boot/dts/gef_ppc9a.dts| 39 --- arch/powerpc/boot/dts/gef_sbc310.dts | 39 --- arch/powerpc/boot/dts/gef_sbc610.dts | 39 --- arch/powerpc/boot/dts/mpc8641_hpcn.dts | 157 +++- arch/powerpc/boot/dts/sbc8641d.dts | 156 +++- arch/powerpc/platforms/86xx/gef_ppc9a.c|1 + arch/powerpc/platforms/86xx/gef_sbc310.c |1 + arch/powerpc/platforms/86xx/gef_sbc610.c |1 + arch/powerpc/platforms/86xx/mpc8610_hpcd.c |1 + arch/powerpc/platforms/86xx/mpc86xx_hpcn.c |1 + arch/powerpc/platforms/86xx/sbc8641d.c |1 + 11 files changed, 237 insertions(+), 199 deletions(-) Tested on ppc9a. Other GE Fanuc boards look sane. Tested-by: Martyn Welch martyn.we...@gefanuc.com Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v4 2/2] powerpc/86xx: Default configuration for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 1889 + 1 files changed, 1889 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig new file mode 100644 index 000..df2c163 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Fri Mar 13 15:36:11 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set
[PATCH v4 0/2] powerpc/86xx: Board support for GE Fanuc PPC9A
The following series implements basic support for the GE Fanuc PPC9A, a 6U single board computer, based on the Freescale MPC8641D. This series provides: - The ability to boot the board with a serial console. - Ethernet support. - Sata and USB. - Support for one of the 2 available watchdog timers. - Support for the onboard temperature sensors - Support for the onboard RTC v2: Corrections to DTS as suggested by David Gibson v3: Further DTS corrections as suggested by David Gibson v4: Removed superfluous space in flash compatible field as spotted by David Gibson Note: I have left the original wtd compatible tag in as well, so as to avoid having to make more changes to the wdt code for this patch (as this will require the DTS files for the other boards to also be changed). I have changed the reference in the board file WRT the PIC, so the legacy value is not needed here. Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v4 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 364 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 598 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..dbc2a1d
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,364 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = gef,ppc9a-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = gef,ppc9a-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1
[PATCH v3 0/2] powerpc/86xx: Board support for GE Fanuc PPC9A
The following series implements basic support for the GE Fanuc PPC9A, a 6U single board computer, based on the Freescale MPC8641D. This series provides: - The ability to boot the board with a serial console. - Ethernet support. - Sata and USB. - Support for one of the 2 available watchdog timers. - Support for the onboard temperature sensors - Support for the onboard RTC v2: Corrections to DTS as suggested by David Gibson v3: Further DTS corrections as suggested by David Gibson Note: I have left the original wtd compatible tag in as well, so as to avoid having to make more changes to the wdt code for this patch (as this will require the DTS files for the other boards to also be changed). I have changed the reference in the board file WRT the PIC, so the legacy value is not needed here. Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v3 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 364 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 598 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..dac7f8b
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,364 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = gef,ppc9a-firmware-mirror, cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = gef, ppc9a-paged-flash, cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1
[PATCH v3 2/2] powerpc/86xx: Default configuration for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 1889 + 1 files changed, 1889 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig new file mode 100644 index 000..df2c163 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Fri Mar 13 15:36:11 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set
Re: [PATCH v2 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
David Gibson wrote:
On Mon, Mar 16, 2009 at 10:32:18AM +, Martyn Welch wrote:
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Uh.. sorry. Should have noticed these little nitpicks the first time
around.
No problem, just a few queries.
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080;// IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
It would be nice to have the actual type of flash chips here, although
it's not essential.
Flash is a little tricky, it's paged. We haven't found a good way of dealing
with this yet and as a result we currently just support the first page, which
may not even match one full chip width. This is especially so for fl...@0,0,
which is mirrored via an FPGA, the exact region depends on some jumper settings
and is access is definitely read only via this region (this region is commented
out in the DTS and really there for completeness as we don't expect to ever use
it or enable it from Linux and is only there to all the firmware to boot). We
are currently using Spansion s29gl01gp parts, which have some tricky mechanisms
for sector protection (given that the parts are paged). As a result, providing
the specific chip won't be much use, if a specific driver is written for
spansion flash the spansion specific mechanisms are unlikely to work.
If you still want the specific chip, how about this:
compatible = spansion, s29gl01gp, cfi-flash;
[snip]
+ f...@4,0 {
+ compatible = gef,fpga-regs;
I don't imagine this is the only set of FPGA based control regs GE
Fanuc will ever make, so this should be more precise. Including the
board type here is probably the way to go.
OK.
compatible = gef,fpga-regs-ppc9a;
+ reg = 0x4 0x0 0x40;
+ };
+
+ w...@4,2000 {
+ compatible = gef,fpga-wdt;
And likewise here.
We only have one core that is used on all our sites current and planned boards
(as far as I know). How about (idea borrowed from virtex440-ml507.dts):
compatible = gef,fpga-wdt-1.00;
+ reg = 0x4 0x2000 0x8;
+ interrupts = 0x1a 0x4;
+ interrupt-parent = gef_pic;
+ };
+ /* Second watchdog available, driver currently supports one.
+ w...@4,2010 {
+ compatible = gef,fpga-wdt;
+ reg = 0x4 0x2010 0x8;
+ interrupts = 0x1b 0x4;
+ interrupt-parent = gef_pic;
+ };
+ */
+ gef_pic: p...@4,4000 {
+ #interrupt-cells = 1;
+ interrupt-controller;
+ compatible = gef,fpga-pic;
And possibly here, although in this case I imagine several boards
might have compatible FPGA PICs.
Yes, the same design is used on all the new boards I know about. As with the
watchdog, boards in the future may have different designs. Would this be
acceptable?:
compatible = gef,fpga-pic-1.00;
+ i2c1: i...@3000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl-i2c;
This should list include a compatible string specific to the
particular SoC model before the general name.
The documentation seems to suggest to use fsl-i2c. Should it be like this?:
compatible = fsl,mpc8641d-i2c, fsl-i2c;
Martyn
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476
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[PATCH 0/2 v2] powerpc/86xx: Board support for GE Fanuc PPC9A
The following series implements basic support for the GE Fanuc PPC9A, a 6U single board computer, based on the Freescale MPC8641D. This series provides: - The ability to boot the board with a serial console. - Ethernet support. - Sata and USB. - Support for one of the 2 available watchdog timers. - Support for the onboard temperature sensors - Support for the onboard RTC v2: Corrections to DTS as suggested by David Gibson Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
v2: Corrections to DTS (soc compatible, remove device_type) as suggesed by
David Gibson.
arch/powerpc/boot/dts/gef_ppc9a.dts | 362 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 596 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..055f0b7
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,362 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2
[PATCH v2 2/2] powerpc/86xx: Default configuration for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 1889 + 1 files changed, 1889 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig new file mode 100644 index 000..df2c163 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Fri Mar 13 15:36:11 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set
[PATCH] powerpc/86xx: Run sbc310 USB fixup code only on the appropriate platform.
Patch to limit NEC fixup to SBC310, following similar patch to SBC610 by Tony
Breeds: 368a12117dd8abf6eaefa37c21ac313b517128b9
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
Hi Kumar,
The sbc310 patches have been added to your next tree. This patch is
needed to stop the same problem occuring as occured with the sbc610.
arch/powerpc/platforms/86xx/gef_sbc310.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c
b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 0f20172..ba3ce43 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -153,6 +153,10 @@ static void __init gef_sbc310_nec_fixup(struct pci_dev
*pdev)
{
unsigned int val;
+ /* Do not do the fixup on other platforms! */
+ if (!machine_is(gef_sbc310))
+ return;
+
printk(KERN_INFO Running NEC uPD720101 Fixup\n);
/* Ensure only ports 1 2 are enabled */
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[PATCH 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts | 363 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 597 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..3be1c43
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,363 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1
[PATCH 0/2] powerpc/86xx: Board support for GE Fanuc PPC9A
The following series implements basic support for the GE Fanuc PPC9A, a 6U single board computer, based on the Freescale MPC8641D. This series provides: - The ability to boot the board with a serial console. - Ethernet support. - Sata and USB. - Support for one of the 2 available watchdog timers. - Support for the onboard temperature sensors - Support for the onboard RTC Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 2/2] powerpc/86xx: Default configuration for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 1889 + 1 files changed, 1889 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig new file mode 100644 index 000..df2c163 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Fri Mar 13 15:36:11 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set
[PATCH] powerpc/86xx: Correct local bus registers in GE Fanuc SBC610 dts file
The registers for the local bus are incorrectly set to 0xf8005000 rather than there actual location of 0xfef05000. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/boot/dts/gef_sbc610.dts |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts index c3978b5..34570bd 100644 --- a/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/arch/powerpc/boot/dts/gef_sbc610.dts @@ -71,7 +71,7 @@ #address-cells = 2; #size-cells = 1; compatible = fsl,mpc8641-localbus, simple-bus; - reg = 0xf8005000 0x1000; + reg = 0xfef05000 0x1000; interrupts = 19 2; interrupt-parent = mpic; ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] powerpc/mm: Fix _PAGE_COHERENT support on classic ppc32 HW
Kumar Gala wrote: The following commit: commit 64b3d0e8122b422e879b23d42f9e0e8efbbf9744 Author: Benjamin Herrenschmidt b...@kernel.crashing.org Date: Thu Dec 18 19:13:51 2008 + powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED broke setting of the _PAGE_COHERENT bit in the PPC HW PTE. Since we now actually set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing it out before we propogate it to the PPC HW PTE. Reported-by: Martyn Welch martyn.we...@gefanuc.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/mm/hash_low_32.S |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S index 67850ec..14af8ce 100644 --- a/arch/powerpc/mm/hash_low_32.S +++ b/arch/powerpc/mm/hash_low_32.S @@ -320,7 +320,7 @@ _GLOBAL(create_hpte) and r8,r8,r0/* writable if _RW _DIRTY */ rlwimi r5,r5,32-1,30,30/* _PAGE_USER - PP msb */ rlwimi r5,r5,32-2,31,31/* _PAGE_USER - PP lsb */ - ori r8,r8,0xe14 /* clear out reserved bits and M */ + ori r8,r8,0xe04 /* clear out reserved bits */ andcr8,r5,r8/* PP = user? (rwdirty? 2: 3): 0 */ BEGIN_FTR_SECTION rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ This does indeed resolve the problem I was having. Sorry for not replying sooner - bad weather here in the UK unexpectedly extended a planned holiday. Thank you for resolving this issue, Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Booting 2.6.29-rc3 on mpc8661d_hpcn failing
On Wed, 2009-02-04 at 11:47 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2009-02-03 at 15:50 +, Martyn Welch wrote:
The primary CPU is spinning in smp_generic_give_timebase() waiting for
!tbsync-ack. The secondary CPU has made it into
smp_generic_take_timebase() and has apparently (according to some
printk's I put in there) set tbsync-ack=1. After that I don't get
any printk's, I guess that the one I have put in the !
tbsync-handshake while loop is making it to the print buffer, but
with both processors spinning it's not getting to the serial console.
At a guess, given that commit 64b3d0e8122b422e879b23d42f9e0e8efbbf9744
seems to be the point that it stopped working correctly, that tbsync
is now somehow becoming cached?
Maybe we are missing the M bit in the mapping ?
Let's see... the kernel mapping is done via BATs on those guys (ie, e600
is a hash table based processor right ? some kind of 74xx). The code
that sets them up is in
arch/powerpc/mm/ppc_mmu_32.c
In mmu_mapin_ram() we call setbat() multiple times. The last argument is
the flags which is set to _PAGE_RAM. That should contain
_PAGE_COHERENT when CONFIG_SMP is set unless I screwed up. IE. _PAGE_RAM
is _PAGE_KERNEL | _PAGE_HWEXEC. _PAGE_KERNEL is _PAGE_BASE plus things,
and _PAGE_BASE should contains _PAGE_COHERENT if CONFIG_SMP or
CONFIG_PPC_STD_MMU are set and they should both be in your case.
setbat() itself will clear _PAGE_COHERENT under some circumstances
however. Either if the flags contain _PAGE_NO_CACHE, which should not be
the case here, or if the CPU feature bit CPU_FTR_NEED_COHERENT is -not-
set. I think that could be the cause of the problem.
CPU_FTR_NEED_COHERENT is set as part of CPU_FTR_COMMON if CONFIG_SMP
is set (among other things). So it -should- be set for you. since
CPU_FTR_COMMON should be OR'ed with all CPU table entries.
So I'm a bit at a loss here... unless something else went wrong.
Please let me know what you find out.
Cheers,
Ben.
I think it is indeed something else. I added the patch below which
resulted in the following lines in the kernel messages:
Set BAT 2 for 0x1000 from phys:0x0 at virt:0xc000
Page coherency set
Set BAT 3 for 0x1000 from phys:0x1000 at virt:0xd000
Page coherency set
...
tbsync structure allocated at 0xef818360 for 0x48
tbsync happens to live at 0xc0515110
running happens to live at 0xc0515114
This suggests to me that whilst *tbsync and running are located within
RAM mapped by the BATs, the memory allocated for the tbsync structure is
not and is mapped via page tables. I guess this structure is then only
mapped correctly for the first core.
Martyn
--
diff --git a/arch/powerpc/kernel/smp-tbsync.c b/arch/powerpc/kernel/smp-tbsync.c
index a5e5452..fdeda20 100644
--- a/arch/powerpc/kernel/smp-tbsync.c
+++ b/arch/powerpc/kernel/smp-tbsync.c
@@ -117,6 +117,10 @@ void __devinit smp_generic_give_timebase(void)
/* if this fails then this kernel won't work anyway... */
tbsync = kzalloc( sizeof(*tbsync), GFP_KERNEL );
+ printk(tbsync structure allocated at 0x%p for 0x%x\n, tbsync,
+ sizeof(*tbsync));
+ printk(tbsync happens to live at 0x%p\n, tbsync);
+ printk(running happens to live at 0x%p\n, running);
mb();
running = 1;
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index fe65c40..2035cd6 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -123,6 +123,9 @@ void __init setbat(int index, unsigned long virt, phys_addr_
int wimgxpp;
struct ppc_bat *bat = BATS[index];
+ printk(Set BAT %d for 0x%x from phys:0x%lx at virt:0x%lx\n, index,
+ size, phys, virt);
+
if ((flags _PAGE_NO_CACHE) ||
(cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
flags = ~_PAGE_COHERENT;
@@ -134,6 +137,11 @@ void __init setbat(int index, unsigned long virt, phys_addr
wimgxpp = flags (_PAGE_WRITETHRU | _PAGE_NO_CACHE
| _PAGE_COHERENT | _PAGE_GUARDED);
wimgxpp |= (flags _PAGE_RW)? BPP_RW: BPP_RX;
+ if (wimgxpp _PAGE_COHERENT) {
+ printk(Page coherency set\n);
+ } else {
+ printk(Page coherency cleared\n);
+ }
bat[1].batu = virt | (bl 2) | 2; /* Vs=1, Vp=0 */
bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
#ifndef CONFIG_KGDB /* want user access for breakpoints */
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd,|Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476
___
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