[PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property
Re-organize the SPI partitions and use the same SPI flash memory
map for most of the platforms which have 16MB SPI flash mounted.
1. Extend the U-Boot partition to 1MB
The image for booting from SPI is larger than 512KB, while
the size of U-Boot partition is 512KB on some boards, so
enlarge it to 1MB in order to contain the whole U-Boot image.
2. Reserve space for U-Boot environment variables
The environment variables are stored at offset 0x10, so
if other image was put at this address, it'll be overlapped
when saving the environment variables.
3. Reserve space for FMAN ucode
The FMAN ucode is required on DPAA platform and is stored at
offset 0x11, this address should not be used to store any
other images.
4. Extend the kernel partition to 5MB
Here is diagram for the SPI flash memory map:
0x00 |-|
| U-Boot |
| (1MB) |
0x10 |-|
| Env(64KB) |
0x11 |-|
| ucode |
0x18 |-|
| DTB |
| (512KB) |
0x20 |-|
| kernel |
| (5MB) |
0x70 |-|
| file system |
| (9MB) |
0x100 |-|
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based on 'next' branch on git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
arch/powerpc/boot/dts/bsc9131rdb.dtsi | 35 -
arch/powerpc/boot/dts/c293pcie.dts | 35 -
arch/powerpc/boot/dts/mpc8536ds.dtsi | 12 +-
arch/powerpc/boot/dts/p1010rdb.dtsi| 40 --
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 24 +---
arch/powerpc/boot/dts/p1020rdb-pd.dts | 34 -
arch/powerpc/boot/dts/p1020rdb.dtsi| 23 ---
arch/powerpc/boot/dts/p1021mds.dts | 17 +++
arch/powerpc/boot/dts/p1021rdb-pc.dtsi | 32 +--
arch/powerpc/boot/dts/p1022ds.dtsi | 21 +-
arch/powerpc/boot/dts/p1023rds.dts | 10 ++---
arch/powerpc/boot/dts/p1024rdb.dtsi| 40 --
arch/powerpc/boot/dts/p1025rdb.dtsi| 23 +--
arch/powerpc/boot/dts/p2020rdb-pc.dtsi | 40 --
arch/powerpc/boot/dts/p2020rdb.dts | 38 ++--
arch/powerpc/boot/dts/p2041rdb.dts | 12 +-
arch/powerpc/boot/dts/p3041ds.dts | 12 +-
arch/powerpc/boot/dts/p4080ds.dts | 12 +-
arch/powerpc/boot/dts/p5020ds.dts | 12 +-
arch/powerpc/boot/dts/p5040ds.dts | 13 ++-
20 files changed, 180 insertions(+), 305 deletions(-)
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi
b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
index 9e6c013..8250593 100644
--- a/arch/powerpc/boot/dts/bsc9131rdb.dtsi
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
@@ -81,32 +81,25 @@
compatible = spansion,s25sl12801;
reg = 0;
spi-max-frequency = 5000;
-
- /* 512KB for u-boot Bootloader Image */
- partition@0 {
- reg = 0x0 0x0008;
- label = SPI Flash U-Boot Image;
+ partition@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
read-only;
};
-
- /* 512KB for DTB Image */
- partition@8 {
- reg = 0x0008 0x0008;
- label = SPI Flash DTB Image;
+ partition@dtb {
+ label = dtb;
+ reg = 0x0018 0x0008;
+ read-only;
};
-
- /* 4MB for Linux Kernel Image */
- partition@10 {
- reg = 0x0010 0x0040;
- label = SPI Flash Kernel Image;
+ partition@kernel {
+ label = kernel;
+ reg = 0x0020 0x0050;
+ read-only;
};
-
- /*11MB for RFS Image */
- partition@50 {
- reg = 0x0050 0x00B0;
- label = SPI Flash RFS Image;
+ partition@fs {
+ label = file system;
+ reg
[PATCH 1/4] powerpc/mpic_msgr: fix compile error when SMP disabled
In file included from arch/powerpc/sysdev/mpic_msgr.c:20:0:
~/arch/powerpc/include/asm/mpic_msgr.h: In function 'mpic_msgr_set_destination':
~/arch/powerpc/include/asm/mpic_msgr.h:117:2:
error: implicit declaration of function 'get_hard_smp_processor_id'
make[1]: *** [arch/powerpc/sysdev/mpic_msgr.o] Error 1
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/include/asm/mpic_msgr.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic_msgr.h
b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc..326d33c 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
#include linux/types.h
#include linux/spinlock.h
+#include asm/smp.h
struct mpic_msgr {
u32 __iomem *base;
--
1.7.5.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/4] powerpc/mpic_msgr: add lock for MPIC message global variable
Also fix issue of accessing invalid msgr pointer issue. The local
msgr pointer in fucntion mpic_msgr_get will be accessed before
getting a valid address which will cause kernel crash.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/sysdev/mpic_msgr.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 6e7fa38..dc1cfe3 100644
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -27,6 +27,7 @@
static struct mpic_msgr **mpic_msgrs;
static unsigned int mpic_msgr_count;
+static DEFINE_RAW_SPINLOCK(msgrs_lock);
static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
{
@@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
if (reg_num = mpic_msgr_count)
return ERR_PTR(-ENODEV);
- raw_spin_lock_irqsave(msgr-lock, flags);
- if (mpic_msgrs[reg_num]-in_use == MSGR_FREE) {
- msgr = mpic_msgrs[reg_num];
+ raw_spin_lock_irqsave(msgrs_lock, flags);
+ msgr = mpic_msgrs[reg_num];
+ if (msgr-in_use == MSGR_FREE)
msgr-in_use = MSGR_INUSE;
- }
- raw_spin_unlock_irqrestore(msgr-lock, flags);
+ raw_spin_unlock_irqrestore(msgrs_lock, flags);
return msgr;
}
--
1.7.5.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/4] powerpc/mpic_msgr: fix offset error when setting mer register
Signed-off-by: Mingkai Hu mingkai...@freescale.com --- arch/powerpc/sysdev/mpic_msgr.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c index dc1cfe3..483d8fa 100644 --- a/arch/powerpc/sysdev/mpic_msgr.c +++ b/arch/powerpc/sysdev/mpic_msgr.c @@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev) reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i; msgr-base = msgr_block_addr + i * MPIC_MSGR_STRIDE; - msgr-mer = msgr-base + MPIC_MSGR_MER_OFFSET; + msgr-mer = (u32 *)((u8 *)msgr-base + MPIC_MSGR_MER_OFFSET); msgr-in_use = MSGR_FREE; msgr-num = i; raw_spin_lock_init(msgr-lock); -- 1.7.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/4] powerpc/mpc85xx: add MPIC message dts node
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi | 43 +
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 10 +
2 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
new file mode 100644
index 000..1cf0b77
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+message@42400 {
+ compatible = fsl,mpic-v3.1-msgr;
+ reg = 0x42400 0x200;
+ interrupts =
+ 0xb4 2 0 0
+ 0xb5 2 0 0
+ 0xb6 2 0 0
+ 0xb7 2 0 0;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index fdedf7b..71c30eb 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -53,6 +53,16 @@ timer@41100 {
3 0 3 0;
};
+message@41400 {
+ compatible = fsl,mpic-v3.1-msgr;
+ reg = 0x41400 0x200;
+ interrupts =
+ 0xb0 2 0 0
+ 0xb1 2 0 0
+ 0xb2 2 0 0
+ 0xb3 2 0 0;
+};
+
msi@41600 {
compatible = fsl,mpic-msi;
reg = 0x41600 0x80;
--
1.7.5.1
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/85xx: Add p2040 RDB board support
P2040RDB Specification:
---
2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
128 Mbyte NOR flash single-chip memory
256 Kbit M24256 I2C EEPROM
16 Mbyte SPI memory
SD connector to interface with the SD memory card
dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
I2C1: Real time clock, Temperature sensor
I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
UART: supports two UARTs up to 115200 bps for console
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
PCIe:
- Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
- Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based on http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
arch/powerpc/boot/dts/p2040rdb.dts | 166 +++
arch/powerpc/boot/dts/p2040si.dtsi | 623 ++
arch/powerpc/configs/corenet32_smp_defconfig |1 +
arch/powerpc/platforms/85xx/Kconfig | 12 +
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc/platforms/85xx/p2040_rdb.c | 88
6 files changed, 891 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2040rdb.dts
create mode 100644 arch/powerpc/boot/dts/p2040si.dtsi
create mode 100644 arch/powerpc/platforms/85xx/p2040_rdb.c
diff --git a/arch/powerpc/boot/dts/p2040rdb.dts
b/arch/powerpc/boot/dts/p2040rdb.dts
new file mode 100644
index 000..7d84e39
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2040rdb.dts
@@ -0,0 +1,166 @@
+/*
+ * P2040RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ p2040si.dtsi
+
+/ {
+ model = fsl,P2040RDB;
+ compatible = fsl,P2040RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ memory {
+ device_type = memory;
+ };
+
+ soc: soc@ffe00 {
+ spi@11 {
+ flash@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000; /* input clock
*/
+ partition@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partition@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partition@dtb {
+ label = dtb
[PATCH 1/2] eSPI: change the read behavior of the SPIRF
The user must read N bytes of SPIRF (1 = N = 4) that do not exceed the
amount of data in the receive FIFO, so read the SPIRF byte by byte when
the data in receive FIFO is less than 4 bytes.
On Simics, when read N bytes that exceed the amout of data in receive
FIFO, we can't read the data out, that is we can't clear the rx FIFO,
then the CPU will loop on the espi rx interrupt.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
The patch 2/2 is againsted on this patch, so I resent this patch again
for convience which sent several weeks ago.
drivers/spi/spi_fsl_espi.c | 19 ---
1 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
index e3b4f64..ae78926 100644
--- a/drivers/spi/spi_fsl_espi.c
+++ b/drivers/spi/spi_fsl_espi.c
@@ -507,16 +507,29 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32
events)
/* We need handle RX first */
if (events SPIE_NE) {
- u32 rx_data;
+ u32 rx_data, tmp;
+ u8 rx_data_8;
/* Spin until RX is done */
while (SPIE_RXCNT(events) min(4, mspi-len)) {
cpu_relax();
events = mpc8xxx_spi_read_reg(reg_base-event);
}
- mspi-len -= 4;
- rx_data = mpc8xxx_spi_read_reg(reg_base-receive);
+ if (mspi-len = 4) {
+ rx_data = mpc8xxx_spi_read_reg(reg_base-receive);
+ } else {
+ tmp = mspi-len;
+ rx_data = 0;
+ while (tmp--) {
+ rx_data_8 = in_8((u8 *)reg_base-receive);
+ rx_data |= (rx_data_8 (tmp * 8));
+ }
+
+ rx_data = (4 - mspi-len) * 8;
+ }
+
+ mspi-len -= 4;
if (mspi-rx)
mspi-get_rx(rx_data, mspi);
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] eSPI: fix wrong setting of the address in the command buffer
Or else we cann't operate on the right address when the trans length
is greater than 65535.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/spi/spi_fsl_espi.c | 16 +---
1 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
index ae78926..a99e233 100644
--- a/drivers/spi/spi_fsl_espi.c
+++ b/drivers/spi/spi_fsl_espi.c
@@ -258,18 +258,18 @@ static int fsl_espi_bufs(struct spi_device *spi, struct
spi_transfer *t)
return mpc8xxx_spi-count;
}
-static void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
+static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
{
- if (cmd[1] cmd[2] cmd[3]) {
+ if (cmd) {
cmd[1] = (u8)(addr 16);
cmd[2] = (u8)(addr 8);
cmd[3] = (u8)(addr 0);
}
}
-static unsigned int fsl_espi_cmd2addr(u8 *cmd)
+static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
{
- if (cmd[1] cmd[2] cmd[3])
+ if (cmd)
return cmd[1] 16 | cmd[2] 8 | cmd[3] 0;
return 0;
@@ -395,9 +395,11 @@ static void fsl_espi_rw_trans(struct spi_message *m,
}
}
- addr = fsl_espi_cmd2addr(local_buf);
- addr += pos;
- fsl_espi_addr2cmd(addr, local_buf);
+ if (pos 0) {
+ addr = fsl_espi_cmd2addr(local_buf);
+ addr += pos;
+ fsl_espi_addr2cmd(addr, local_buf);
+ }
espi_trans-n_tx = n_tx;
espi_trans-n_rx = trans_len;
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] eSPI: change the read behavior of the SPIRF
The user must read N bytes of SPIRF (1 = N = 4) that do not exceed the
amount of data in the receive FIFO, so read the SPIRF byte by byte when
the data in receive FIFO is less than 4 bytes.
On Simics, when read N bytes that exceed the amout of data in receive
FIFO, we can't read the data out, that is we can't clear the rx FIFO,
then the CPU will loop on the espi rx interrupt.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/spi/spi_fsl_espi.c | 19 ---
1 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
index e3b4f64..ae78926 100644
--- a/drivers/spi/spi_fsl_espi.c
+++ b/drivers/spi/spi_fsl_espi.c
@@ -507,16 +507,29 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32
events)
/* We need handle RX first */
if (events SPIE_NE) {
- u32 rx_data;
+ u32 rx_data, tmp;
+ u8 rx_data_8;
/* Spin until RX is done */
while (SPIE_RXCNT(events) min(4, mspi-len)) {
cpu_relax();
events = mpc8xxx_spi_read_reg(reg_base-event);
}
- mspi-len -= 4;
- rx_data = mpc8xxx_spi_read_reg(reg_base-receive);
+ if (mspi-len = 4) {
+ rx_data = mpc8xxx_spi_read_reg(reg_base-receive);
+ } else {
+ tmp = mspi-len;
+ rx_data = 0;
+ while (tmp--) {
+ rx_data_8 = in_8((u8 *)reg_base-receive);
+ rx_data |= (rx_data_8 (tmp * 8));
+ }
+
+ rx_data = (4 - mspi-len) * 8;
+ }
+
+ mspi-len -= 4;
if (mspi-rx)
mspi-get_rx(rx_data, mspi);
--
1.7.0.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 4/5] powerpc/of: add eSPI controller dts bindings and DTS modification
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 ++-
arch/powerpc/boot/dts/mpc8536ds.dts| 52
arch/powerpc/boot/dts/p4080ds.dts | 11 ++---
3 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..777abd7 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -1,7 +1,9 @@
* SPI (Serial Peripheral Interface)
Required properties:
-- cell-index : SPI controller index.
+- cell-index : QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
- compatible : should be fsl,spi.
- mode : the SPI operation mode, it can be cpu or cpu-qe.
- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,mpc8536-espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb..a75c10e 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
};
};
+ s...@7000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x7000 0x1000;
+ interrupts = 59 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+
+ fl...@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000;
+ partit...@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partit...@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partit...@dtb {
+ label = dtb;
+ reg = 0x0060 0x0010;
+ read-only;
+ };
+ partit...@fs {
+ label = file system;
+ reg = 0x0070 0x0090;
+ };
+ };
+ fl...@1 {
+ compatible = spansion,s25sl12801;
+ reg = 1;
+ spi-max-frequency = 4000;
+ };
+ fl...@2 {
+ compatible = spansion,s25sl12801;
+ reg = 2;
+ spi-max-frequency = 4000;
+ };
+ fl...@3 {
+ compatible = spansion,s25sl12801;
+ reg = 3;
+ spi-max-frequency = 4000;
+ };
+ };
+
d...@21300 {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24..5b7fc29 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
};
s...@11
[PATCH v4 3/5] eSPI: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0x. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Added support to the transaction that the length is grater than 0x.
- Made some changes according to Anton's comments.
drivers/spi/Kconfig|9 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_espi.c | 748
drivers/spi/spi_fsl_lib.h |3 +
4 files changed, 761 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_fsl_espi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 79ad06f..f6888af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -195,6 +195,15 @@ config SPI_FSL_SPI
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
+config SPI_FSL_ESPI
+ tristate Freescale eSPI controller
+ depends on FSL_SOC
+ select SPI_FSL_LIB
+ help
+ This enables using the Freescale eSPI controllers in master mode.
+ From MPC8536, 85xx platform uses the controller, and all P10xx,
+ P20xx, P30xx,P40xx, P50xx uses this controller.
+
config SPI_OMAP_UWIRE
tristate OMAP1 MicroWire
depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7974c21..833d17e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
+obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
new file mode 100644
index 000..e3b4f64
--- /dev/null
+++ b/drivers/spi/spi_fsl_espi.c
@@ -0,0 +1,748 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/module.h
+#include linux/delay.h
+#include linux/irq.h
+#include linux/spi/spi.h
+#include linux/platform_device.h
+#include linux/fsl_devices.h
+#include linux/mm.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include linux/interrupt.h
+#include linux/err.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+/* eSPI Controller registers */
+struct fsl_espi_reg {
+ __be32 mode;/* 0x000 - eSPI mode register */
+ __be32 event; /* 0x004 - eSPI event register */
+ __be32 mask;/* 0x008 - eSPI mask register */
+ __be32 command; /* 0x00c - eSPI command register */
+ __be32 transmit;/* 0x010 - eSPI transmit FIFO access register*/
+ __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
+ u8 res[8]; /* 0x018 - 0x01c
[PATCH v4 2/5] spi/mpc8xxx: refactor the common code for SPI/eSPI controller
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
drivers/spi/Kconfig |5 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_lib.c | 237 +++
drivers/spi/spi_fsl_lib.h | 119 ++
drivers/spi/spi_fsl_spi.c | 552 +
5 files changed, 522 insertions(+), 392 deletions(-)
create mode 100644 drivers/spi/spi_fsl_lib.c
create mode 100644 drivers/spi/spi_fsl_lib.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6af34c6..79ad06f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -182,9 +182,14 @@ config SPI_MPC512x_PSC
This enables using the Freescale MPC5121 Programmable Serial
Controller in SPI master mode.
+config SPI_FSL_LIB
+ tristate
+ depends on FSL_SOC
+
config SPI_FSL_SPI
tristate Freescale SPI controller
depends on FSL_SOC
+ select SPI_FSL_LIB
help
This enables using the Freescale SPI controllers in master mode.
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 770817c..7974c21 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPI_PL022) += amba-pl022.o
obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
+obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_lib.c b/drivers/spi/spi_fsl_lib.c
new file mode 100644
index 000..5cd741f
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.c
@@ -0,0 +1,237 @@
+/*
+ * Freescale SPI/eSPI controller driver library.
+ *
+ * Maintainer: Kumar Gala
+ *
+ * Copyright (C) 2006 Polycom, Inc.
+ *
+ * CPM SPI and QE buffer descriptors mode support:
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Author: Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/kernel.h
+#include linux/interrupt.h
+#include linux/fsl_devices.h
+#include linux/dma-mapping.h
+#include linux/mm.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+#define MPC8XXX_SPI_RX_BUF(type) \
+void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
+{\
+ type *rx = mpc8xxx_spi-rx; \
+ *rx++ = (type)(data mpc8xxx_spi-rx_shift);\
+ mpc8xxx_spi-rx = rx; \
+}
+
+#define MPC8XXX_SPI_TX_BUF(type) \
+u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
+{ \
+ u32 data; \
+ const type *tx = mpc8xxx_spi-tx; \
+ if (!tx)\
+ return 0; \
+ data = *tx++ mpc8xxx_spi-tx_shift; \
+ mpc8xxx_spi-tx = tx; \
+ return data;\
+}
+
+MPC8XXX_SPI_RX_BUF(u8)
+MPC8XXX_SPI_RX_BUF(u16)
+MPC8XXX_SPI_RX_BUF(u32)
+MPC8XXX_SPI_TX_BUF(u8)
+MPC8XXX_SPI_TX_BUF(u16)
+MPC8XXX_SPI_TX_BUF(u32)
+
+struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
+{
+ return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
+}
+
+void mpc8xxx_spi_work(struct work_struct *work)
+{
+ struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
+ work);
+
+ spin_lock_irq(mpc8xxx_spi-lock);
+ while (!list_empty(mpc8xxx_spi-queue)) {
+ struct spi_message *m = container_of(mpc8xxx_spi-queue.next
[PATCH v4 5/5] mtd: m25p80: add support to parse the partitions by OF node
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Made changes according to Grant's comments.
drivers/mtd/devices/m25p80.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6f512b5..9d20738 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -924,6 +924,11 @@ static int __devinit m25p_probe(struct spi_device *spi)
nr_parts = data-nr_parts;
}
+ if (nr_parts = 0 spi-dev.of_node) {
+ nr_parts = of_mtd_parse_partitions(spi-dev,
+ spi-dev.of_node, parts);
+ }
+
if (nr_parts 0) {
for (i = 0; i nr_parts; i++) {
DEBUG(MTD_DEBUG_LEVEL2, partitions[%d] =
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v4 0/5] refactor spi_mpc8xxx.c and add eSPI controller support
This patchset refactor the file spi_mpc8xxx.c to abstract some common code as a lib used by the SPI/eSPI controller driver, move the SPI controller driver code to spi_fsl_spi.c, and add the eSPI controller support with spi_fsl_espi.c. v4 main change: - Update to the latest kernel base(Linux 2.6.36-rc7). - Add support to the transaction that the length is grater than 0x in the eSPI controller's driver. - Some changes according to Grant and Anton's comments. Tested on P4080DS and MPC8536DS board. [PATCH v4 1/5] spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.c [PATCH v4 2/5] spi/mpc8xxx: refactor the common code for SPI/eSPI controller [PATCH v4 3/5] eSPI: add eSPI controller support [PATCH v4 4/5] powerpc/of: add eSPI controller dts bindings and DTS modification [PATCH v4 5/5] mtd: m25p80: add support to parse the partitions by OF node Thanks, Mingkai ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 4/7] powerpc/of: add eSPI controller dts bindings and DTS modification
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v3:
- Add fsl,p4080-espi compatible property.
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 ++-
arch/powerpc/boot/dts/mpc8536ds.dts| 52
arch/powerpc/boot/dts/p4080ds.dts | 11 ++---
3 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..777abd7 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -1,7 +1,9 @@
* SPI (Serial Peripheral Interface)
Required properties:
-- cell-index : SPI controller index.
+- cell-index : QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
- compatible : should be fsl,spi.
- mode : the SPI operation mode, it can be cpu or cpu-qe.
- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,mpc8536-espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb..a75c10e 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
};
};
+ s...@7000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x7000 0x1000;
+ interrupts = 59 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+
+ fl...@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000;
+ partit...@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partit...@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partit...@dtb {
+ label = dtb;
+ reg = 0x0060 0x0010;
+ read-only;
+ };
+ partit...@fs {
+ label = file system;
+ reg = 0x0070 0x0090;
+ };
+ };
+ fl...@1 {
+ compatible = spansion,s25sl12801;
+ reg = 1;
+ spi-max-frequency = 4000;
+ };
+ fl...@2 {
+ compatible = spansion,s25sl12801;
+ reg = 2;
+ spi-max-frequency = 4000;
+ };
+ fl...@3 {
+ compatible = spansion,s25sl12801;
+ reg = 3;
+ spi-max-frequency = 4000;
+ };
+ };
+
d...@21300 {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24..5b7fc29 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
};
s...@11 {
- cell
[PATCH v3 5/7] mtd: m25p80: add support to parse the SPI flash's partitions
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v3:
- Move the SPI flash partition code to the probe function.
drivers/mtd/devices/m25p80.c | 39 +++
1 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6f512b5..47d53c7 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -772,7 +772,7 @@ static const struct spi_device_id *__devinit
jedec_probe(struct spi_device *spi)
static int __devinit m25p_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
- struct flash_platform_data *data;
+ struct flash_platform_data data, *pdata;
struct m25p *flash;
struct flash_info *info;
unsignedi;
@@ -782,13 +782,27 @@ static int __devinit m25p_probe(struct spi_device *spi)
* a chip ID, try the JEDEC id commands; they'll work for most
* newer chips, even if we don't recognize the particular chip.
*/
- data = spi-dev.platform_data;
- if (data data-type) {
+ pdata = spi-dev.platform_data;
+ if (!pdata spi-dev.of_node) {
+ int nr_parts;
+ struct mtd_partition *parts;
+ struct device_node *np = spi-dev.of_node;
+
+ nr_parts = of_mtd_parse_partitions(spi-dev, np, parts);
+ if (nr_parts) {
+ pdata = data;
+ memset(pdata, 0, sizeof(*pdata));
+ pdata-parts = parts;
+ pdata-nr_parts = nr_parts;
+ }
+ }
+
+ if (pdata pdata-type) {
const struct spi_device_id *plat_id;
for (i = 0; i ARRAY_SIZE(m25p_ids) - 1; i++) {
plat_id = m25p_ids[i];
- if (strcmp(data-type, plat_id-name))
+ if (strcmp(pdata-type, plat_id-name))
continue;
break;
}
@@ -796,7 +810,8 @@ static int __devinit m25p_probe(struct spi_device *spi)
if (i ARRAY_SIZE(m25p_ids) - 1)
id = plat_id;
else
- dev_warn(spi-dev, unrecognized id %s\n, data-type);
+ dev_warn(spi-dev, unrecognized id %s\n,
+ pdata-type);
}
info = (void *)id-driver_data;
@@ -847,8 +862,8 @@ static int __devinit m25p_probe(struct spi_device *spi)
write_sr(flash, 0);
}
- if (data data-name)
- flash-mtd.name = data-name;
+ if (pdata pdata-name)
+ flash-mtd.name = pdata-name;
else
flash-mtd.name = dev_name(spi-dev);
@@ -919,9 +934,9 @@ static int __devinit m25p_probe(struct spi_device *spi)
part_probes, parts, 0);
}
- if (nr_parts = 0 data data-parts) {
- parts = data-parts;
- nr_parts = data-nr_parts;
+ if (nr_parts = 0 pdata pdata-parts) {
+ parts = pdata-parts;
+ nr_parts = pdata-nr_parts;
}
if (nr_parts 0) {
@@ -937,9 +952,9 @@ static int __devinit m25p_probe(struct spi_device *spi)
flash-partitioned = 1;
return add_mtd_partitions(flash-mtd, parts, nr_parts);
}
- } else if (data data-nr_parts)
+ } else if (pdata pdata-nr_parts)
dev_warn(spi-dev, ignoring %d default partitions on %s\n,
- data-nr_parts, data-name);
+ pdata-nr_parts, pdata-name);
return add_mtd_device(flash-mtd) == 1 ? -ENODEV : 0;
}
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 2/7] spi/mpc8xxx: refactor the common code for SPI/eSPI controller
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v3:
- Update to the latest kernel base.
- Add a void *reg_base to compatible for SPI and eSPI register base.
drivers/spi/Kconfig |5 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_lib.c | 237 +++
drivers/spi/spi_fsl_lib.h | 119 ++
drivers/spi/spi_fsl_spi.c | 552 +
5 files changed, 522 insertions(+), 392 deletions(-)
create mode 100644 drivers/spi/spi_fsl_lib.c
create mode 100644 drivers/spi/spi_fsl_lib.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6af34c6..79ad06f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -182,9 +182,14 @@ config SPI_MPC512x_PSC
This enables using the Freescale MPC5121 Programmable Serial
Controller in SPI master mode.
+config SPI_FSL_LIB
+ tristate
+ depends on FSL_SOC
+
config SPI_FSL_SPI
tristate Freescale SPI controller
depends on FSL_SOC
+ select SPI_FSL_LIB
help
This enables using the Freescale SPI controllers in master mode.
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 770817c..7974c21 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPI_PL022) += amba-pl022.o
obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
+obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_lib.c b/drivers/spi/spi_fsl_lib.c
new file mode 100644
index 000..5cd741f
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.c
@@ -0,0 +1,237 @@
+/*
+ * Freescale SPI/eSPI controller driver library.
+ *
+ * Maintainer: Kumar Gala
+ *
+ * Copyright (C) 2006 Polycom, Inc.
+ *
+ * CPM SPI and QE buffer descriptors mode support:
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Author: Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/kernel.h
+#include linux/interrupt.h
+#include linux/fsl_devices.h
+#include linux/dma-mapping.h
+#include linux/mm.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+#define MPC8XXX_SPI_RX_BUF(type) \
+void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
+{\
+ type *rx = mpc8xxx_spi-rx; \
+ *rx++ = (type)(data mpc8xxx_spi-rx_shift);\
+ mpc8xxx_spi-rx = rx; \
+}
+
+#define MPC8XXX_SPI_TX_BUF(type) \
+u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
+{ \
+ u32 data; \
+ const type *tx = mpc8xxx_spi-tx; \
+ if (!tx)\
+ return 0; \
+ data = *tx++ mpc8xxx_spi-tx_shift; \
+ mpc8xxx_spi-tx = tx; \
+ return data;\
+}
+
+MPC8XXX_SPI_RX_BUF(u8)
+MPC8XXX_SPI_RX_BUF(u16)
+MPC8XXX_SPI_RX_BUF(u32)
+MPC8XXX_SPI_TX_BUF(u8)
+MPC8XXX_SPI_TX_BUF(u16)
+MPC8XXX_SPI_TX_BUF(u32)
+
+struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
+{
+ return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
+}
+
+void mpc8xxx_spi_work(struct work_struct *work)
+{
+ struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
+ work);
+
+ spin_lock_irq(mpc8xxx_spi-lock);
+ while (!list_empty(mpc8xxx_spi-queue)) {
+ struct spi_message *m
[PATCH v3 3/7] eSPI: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v3:
- Update to the latest kernel base.
drivers/spi/Kconfig|9 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_espi.c | 642
drivers/spi/spi_fsl_lib.h |1 +
4 files changed, 653 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_fsl_espi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 79ad06f..f6888af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -195,6 +195,15 @@ config SPI_FSL_SPI
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
+config SPI_FSL_ESPI
+ tristate Freescale eSPI controller
+ depends on FSL_SOC
+ select SPI_FSL_LIB
+ help
+ This enables using the Freescale eSPI controllers in master mode.
+ From MPC8536, 85xx platform uses the controller, and all P10xx,
+ P20xx, P30xx,P40xx, P50xx uses this controller.
+
config SPI_OMAP_UWIRE
tristate OMAP1 MicroWire
depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7974c21..833d17e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
+obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
new file mode 100644
index 000..be98148
--- /dev/null
+++ b/drivers/spi/spi_fsl_espi.c
@@ -0,0 +1,642 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/module.h
+#include linux/delay.h
+#include linux/irq.h
+#include linux/spi/spi.h
+#include linux/platform_device.h
+#include linux/fsl_devices.h
+#include linux/mm.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+#include linux/interrupt.h
+#include linux/err.h
+
+#include spi_fsl_lib.h
+
+/* eSPI Controller registers */
+struct fsl_espi_reg {
+ __be32 mode;/* 0x000 - eSPI mode register */
+ __be32 event; /* 0x004 - eSPI event register */
+ __be32 mask;/* 0x008 - eSPI mask register */
+ __be32 command; /* 0x00c - eSPI command register */
+ __be32 transmit;/* 0x010 - eSPI transmit FIFO access register*/
+ __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
+ u8 res[8]; /* 0x018 - 0x01c reserved */
+ __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
+};
+
+/* eSPI Controller mode register definitions */
+#define SPMODE_ENABLE (1 31)
+#define SPMODE_LOOP(1 30)
+#define SPMODE_TXTHR(x)((x) 8)
+#define SPMODE_RXTHR(x)((x) 0)
+
+/* eSPI Controller CS mode register definitions */
+#define CSMODE_CI_INACTIVEHIGH (1 31)
+#define
[PATCH v3 7/7] DTS: add fsl,spi-quirk-trans-len-limit property
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v3:
- Add spi-quirk-trans-len-limit property to the board's dts.
Documentation/powerpc/dts-bindings/fsl/spi.txt |3 +++
arch/powerpc/boot/dts/mpc8536ds.dts|1 +
arch/powerpc/boot/dts/p4080ds.dts |1 +
3 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 777abd7..e1cb84e 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -41,6 +41,9 @@ Required properties:
- interrupts : should contain eSPI interrupt, the device has one interrupt.
- fsl,espi-num-chipselects : the number of the chipselect signals.
+Optional properties:
+- fsl,spi-quirk-trans-len-limit : the max trans length is limited to 0x.
+
Example:
s...@11 {
#address-cells = 1;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index a75c10e..6911c76 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -116,6 +116,7 @@
interrupts = 59 0x2;
interrupt-parent = mpic;
fsl,espi-num-chipselects = 4;
+ fsl,spi-quirk-trans-len-limit;
fl...@0 {
#address-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 5b7fc29..060fc45 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -243,6 +243,7 @@
interrupts = 53 0x2;
interrupt-parent = mpic;
fsl,espi-num-chipselects = 4;
+ fsl,spi-quirk-trans-len-limit;
fl...@0 {
#address-cells = 1;
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 0/6] refactor spi_mpc8xxx.c and add eSPI controller support
In-Reply-To: This patchset refactor the file spi_mpc8xxx.c to abstract some common code as a lib used by the SPI/eSPI controller driver, move the SPI controller driver code to spi_fsl_spi.c, and add the eSPI controller support with spi_fsl_espi.c. Tested on P4080DS and MPC8536DS board based on latest Linux tree. [PATCH v2 1/6] spi/mpc8xxx: refactor the common code for SPI/eSPI controller [PATCH v2 2/6] eSPI: add eSPI controller support [PATCH v2 3/6] mtd: m25p80: add support to parse the SPI flash's partitions [PATCH v2 4/6] mtd: m25p80: add a read function to read page by page [PATCH v2 5/6] powerpc/of: add eSPI controller dts bindings [PATCH v2 6/6] DTS: add SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board Thanks, Mingkai ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 6/6] DTS: add SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Remove the whitespace inconsitencies
arch/powerpc/boot/dts/mpc8536ds.dts | 52 +++
arch/powerpc/boot/dts/p4080ds.dts | 11 +++-
2 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb..a75c10e 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
};
};
+ s...@7000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x7000 0x1000;
+ interrupts = 59 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+
+ fl...@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000;
+ partit...@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partit...@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partit...@dtb {
+ label = dtb;
+ reg = 0x0060 0x0010;
+ read-only;
+ };
+ partit...@fs {
+ label = file system;
+ reg = 0x0070 0x0090;
+ };
+ };
+ fl...@1 {
+ compatible = spansion,s25sl12801;
+ reg = 1;
+ spi-max-frequency = 4000;
+ };
+ fl...@2 {
+ compatible = spansion,s25sl12801;
+ reg = 2;
+ spi-max-frequency = 4000;
+ };
+ fl...@3 {
+ compatible = spansion,s25sl12801;
+ reg = 3;
+ spi-max-frequency = 4000;
+ };
+ };
+
d...@21300 {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 6b29eab..48437ad 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
};
s...@11 {
- cell-index = 0;
#address-cells = 1;
#size-cells = 0;
- compatible = fsl,espi;
+ compatible = fsl,mpc8536-espi;
reg = 0x11 0x1000;
interrupts = 53 0x2;
interrupt-parent = mpic;
- espi,num-ss-bits = 4;
- mode = cpu;
+ fsl,espi-num-chipselects = 4;
- fsl_m25...@0 {
+ fl...@0 {
#address-cells = 1;
#size-cells = 1;
- compatible = fsl,espi-flash;
+ compatible = spansion,s25sl12801;
reg = 0;
- linux,modalias = fsl_m25p80;
spi-max-frequency = 4000; /* input clock
*/
partit...@u-boot {
label = u-boot;
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 5/6] powerpc/of: add eSPI controller dts bindings
Also modifiy the document of cell-index in SPI controller.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Add cell-index clarification
- Add mpc8536 chip name to the compatible value
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..01543ca 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -1,7 +1,9 @@
* SPI (Serial Peripheral Interface)
Required properties:
-- cell-index : SPI controller index.
+- cell-index : QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
- compatible : should be fsl,spi.
- mode : the SPI operation mode, it can be cpu or cpu-qe.
- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,mpc8536-espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 2/6] eSPI: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Rename fsl_espi.c to spi_fsl_espi.c, also the config name
- Move register map definiton from spi_fsl_lib.c to spi_fsl_espi.c
- Break some funcions line in the arguments instead of the declaration
- Inconsistent whitespacing in the macro definition
- Init bits_per_word to 0 to eliminate the else clause
- Add brace for the else clause to match if clause
- Add chip name mpc8536 to the compatible value
- Drop the last entry's comma in the match table
- move module_init() immediately after the init fsl_espi_init() function
drivers/spi/Kconfig|9 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_espi.c | 633
drivers/spi/spi_fsl_lib.h |2 +
4 files changed, 645 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_fsl_espi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index cd7f13b..a379363 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -140,6 +140,15 @@ config SPI_FSL_SPI
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
+config SPI_FSL_ESPI
+ tristate Freescale eSPI controller
+ depends on FSL_SOC
+ select SPI_FSL_LIB
+ help
+ This enables using the Freescale eSPI controllers in master mode.
+ From MPC8536, 85xx platform uses the controller, and all P10xx,
+ P20xx, P40xx uses this controller.
+
config SPI_GPIO
tristate GPIO-based bitbanging SPI Master
depends on GENERIC_GPIO
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cf8d9be..dd86ba7 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
+obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
new file mode 100644
index 000..61987cf
--- /dev/null
+++ b/drivers/spi/spi_fsl_espi.c
@@ -0,0 +1,633 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/module.h
+#include linux/delay.h
+#include linux/irq.h
+#include linux/spi/spi.h
+#include linux/platform_device.h
+#include linux/fsl_devices.h
+#include linux/mm.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+#include linux/interrupt.h
+
+#include spi_fsl_lib.h
+
+/* eSPI Controller registers */
+struct fsl_espi_reg {
+ __be32 mode;/* 0x000 - eSPI mode register */
+ __be32 event; /* 0x004 - eSPI event register */
+ __be32 mask;/* 0x008 - eSPI mask register */
+ __be32 command; /* 0x00c - eSPI command register */
+ __be32 transmit;/* 0x010 - eSPI transmit FIFO access register*/
+ __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
+ u8 res[8
[PATCH v2 3/6] mtd: m25p80: add support to parse the SPI flash's partitions
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Move the flash partition function from of_spi.c to MTD driver
drivers/mtd/devices/m25p80.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 81e49a9..5f00075 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -752,6 +752,31 @@ static const struct spi_device_id *__devinit
jedec_probe(struct spi_device *spi)
return NULL;
}
+/*
+ * parse_flash_partition - Parse the flash partition on the SPI bus
+ * @spi: Pointer to spi_device device
+ */
+void parse_flash_partition(struct spi_device *spi)
+{
+ struct mtd_partition *parts;
+ struct flash_platform_data *pdata;
+ int nr_parts = 0;
+ struct device_node *np = spi-dev.of_node;
+
+ nr_parts = of_mtd_parse_partitions(spi-dev, np, parts);
+ if (!nr_parts)
+ return;
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return;
+
+ pdata-parts = parts;
+ pdata-nr_parts = nr_parts;
+ spi-dev.platform_data = pdata;
+
+ return;
+}
/*
* board specific setup should have ensured the SPI clock used here
@@ -771,6 +796,10 @@ static int __devinit m25p_probe(struct spi_device *spi)
* a chip ID, try the JEDEC id commands; they'll work for most
* newer chips, even if we don't recognize the particular chip.
*/
+
+ /* Parse the flash partition */
+ parse_flash_partition(spi);
+
data = spi-dev.platform_data;
if (data data-type) {
const struct spi_device_id *plat_id;
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 4/6] mtd: m25p80: add a read function to read page by page
For Freescale's eSPI controller, the max transaction length one time
is limitted by the SPCOM[TRANSLEN] field which is 0x. When used
mkfs.ext2 command to create ext2 filesystem on the flash, the read
length will exceed the max value of the SPCOM[TRANSLEN] field, so
change the read function to read page by page.
For other SPI flash driver, also needed to supply the read function
if used the eSPI controller.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Add SPI_MASTER_TRANS_LIMIT flag to indicate the master's trans length
limitation, so the MTD driver can select the correct transfer behaviour
at driver probe time
drivers/mtd/devices/m25p80.c | 78 ++
drivers/spi/spi_fsl_espi.c |1 +
include/linux/spi/spi.h |1 +
3 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 5f00075..30e4568 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -376,6 +376,81 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
}
/*
+ * Read an address range from the flash chip page by page.
+ * Some controller has transaction length limitation such as the
+ * Freescale's eSPI controller can only trasmit 0x bytes one
+ * time, so we have to read page by page if the len is more than
+ * the limitation.
+ */
+static int m25p80_page_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct m25p *flash = mtd_to_m25p(mtd);
+ struct spi_transfer t[2];
+ struct spi_message m;
+ u32 i, page_size = 0;
+
+ DEBUG(MTD_DEBUG_LEVEL2, %s: %s %s 0x%08x, len %zd\n,
+ dev_name(flash-spi-dev), __func__, from,
+ (u32)from, len);
+
+ /* sanity checks */
+ if (!len)
+ return 0;
+
+ if (from + len flash-mtd.size)
+ return -EINVAL;
+
+ spi_message_init(m);
+ memset(t, 0, (sizeof t));
+
+ /* NOTE:
+* OPCODE_FAST_READ (if available) is faster.
+* Should add 1 byte DUMMY_BYTE.
+*/
+ t[0].tx_buf = flash-command;
+ t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
+ spi_message_add_tail(t[0], m);
+
+ t[1].rx_buf = buf;
+ spi_message_add_tail(t[1], m);
+
+ /* Byte count starts at zero. */
+ if (retlen)
+ *retlen = 0;
+
+ mutex_lock(flash-lock);
+
+ /* Wait till previous write/erase is done. */
+ if (wait_till_ready(flash)) {
+ /* REVISIT status return?? */
+ mutex_unlock(flash-lock);
+ return 1;
+ }
+
+ /* Set up the write data buffer. */
+ flash-command[0] = OPCODE_READ;
+
+ for (i = page_size; i len; i += page_size) {
+ page_size = len - i;
+ if (page_size flash-page_size)
+ page_size = flash-page_size;
+ m25p_addr2cmd(flash, from + i, flash-command);
+ t[1].len = page_size;
+ t[1].rx_buf = buf + i;
+
+ spi_sync(flash-spi, m);
+
+ *retlen += m.actual_length - m25p_cmdsz(flash)
+ - FAST_READ_DUMMY_BYTE;
+ }
+
+ mutex_unlock(flash-lock);
+
+ return 0;
+}
+
+/*
* Write an address range to the flash chip. Data must be written in
* FLASH_PAGESIZE chunks. The address range may be any size provided
* it is within the physical boundaries.
@@ -877,6 +952,9 @@ static int __devinit m25p_probe(struct spi_device *spi)
flash-mtd.erase = m25p80_erase;
flash-mtd.read = m25p80_read;
+ if (spi-master-flags SPI_MASTER_TRANS_LIMIT)
+ flash-mtd.read = m25p80_page_read;
+
/* sst flash chips use AAI word program */
if (info-jedec_id 16 == 0xbf)
flash-mtd.write = sst_write;
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
index 61987cf..e15b7dc 100644
--- a/drivers/spi/spi_fsl_espi.c
+++ b/drivers/spi/spi_fsl_espi.c
@@ -470,6 +470,7 @@ static struct spi_master * __devinit fsl_espi_probe(struct
device *dev,
goto err_probe;
master-setup = fsl_espi_setup;
+ master-flags = SPI_MASTER_TRANS_LIMIT;
mpc8xxx_spi = spi_master_get_devdata(master);
mpc8xxx_spi-spi_do_one_msg = fsl_espi_do_one_msg;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index af56071..0729cbd 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -261,6 +261,7 @@ struct spi_master {
#define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
#define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */
#define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
+#define SPI_MASTER_TRANS_LIMIT BIT(3) /* have trans length limit */
/* Setup mode and clock, etc (spi
[PATCH 0/6] refactor spi_mpc8xxx.c and add eSPI controller support
This patchset refactor the file spi_mpc8xxx.c to abstract some common code as a lib used by the SPI/eSPI controller driver, move the SPI controller driver code to fsl_spi.c, and add the eSPI controller support with fsl_espi.c. Tested on P4080DS and MPC8536DS board based on latest Linux tree. [PATCH 1/6] spi/mpc8xxx: refactor the common code for SPI/eSPI controller [PATCH 2/6] eSPI: add eSPI controller support [PATCH 3/6] of/spi: add support to parse the SPI flash's partitions [PATCH 4/6] mtd: m25p80: change the read function to read page by page [PATCH 5/6] powerpc/of: add eSPI controller dts bindings [PATCH 6/6] DTS: add SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board Thanks, Mingkai ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/6] mtd: m25p80: change the read function to read page by page
For Freescale's eSPI controller, the max transaction length one time
is limitted by the SPCOM[TRANSLEN] field which is 0x1. When used
mkfs.ext2 command to create ext2 filesystem on the flash, the read
length will exceed the max value of the SPCOM[TRANSLEN] field, so
change the read function to read page by page.
For other SPI flash driver, also needed to change the read function
if used the eSPI controller.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/mtd/devices/m25p80.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 81e49a9..6cbe6b1 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -317,6 +317,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
struct m25p *flash = mtd_to_m25p(mtd);
struct spi_transfer t[2];
struct spi_message m;
+ u32 i, page_size = 0;
DEBUG(MTD_DEBUG_LEVEL2, %s: %s %s 0x%08x, len %zd\n,
dev_name(flash-spi-dev), __func__, from,
@@ -341,7 +342,6 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
spi_message_add_tail(t[0], m);
t[1].rx_buf = buf;
- t[1].len = len;
spi_message_add_tail(t[1], m);
/* Byte count starts at zero. */
@@ -364,11 +364,21 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from,
size_t len,
/* Set up the write data buffer. */
flash-command[0] = OPCODE_READ;
- m25p_addr2cmd(flash, from, flash-command);
- spi_sync(flash-spi, m);
+ for (i = page_size; i len; i += page_size) {
+ page_size = len - i;
+ if (page_size flash-page_size)
+ page_size = flash-page_size;
- *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
+ m25p_addr2cmd(flash, from + i, flash-command);
+ t[1].len = page_size;
+ t[1].rx_buf = buf + i;
+
+ spi_sync(flash-spi, m);
+
+ *retlen += m.actual_length - m25p_cmdsz(flash)
+ - FAST_READ_DUMMY_BYTE;
+ }
mutex_unlock(flash-lock);
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 5/6] powerpc/of: add eSPI controller dts bindings
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Documentation/powerpc/dts-bindings/fsl/spi.txt | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..b360bf9 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -29,3 +29,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/6] of/spi: add support to parse the SPI flash's partitions
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/of/of_spi.c | 11 +++
drivers/spi/spi_mpc8xxx.c |1 +
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/of/of_spi.c b/drivers/of/of_spi.c
index 5fed7e3..284ca0e 100644
--- a/drivers/of/of_spi.c
+++ b/drivers/of/of_spi.c
@@ -10,6 +10,8 @@
#include linux/device.h
#include linux/spi/spi.h
#include linux/of_spi.h
+#include linux/spi/flash.h
+#include linux/mtd/partitions.h
/**
* of_register_spi_devices - Register child devices onto the SPI bus
@@ -26,6 +28,7 @@ void of_register_spi_devices(struct spi_master *master,
struct device_node *np)
const __be32 *prop;
int rc;
int len;
+ struct flash_platform_data *pdata;
for_each_child_of_node(np, nc) {
/* Alloc an spi_device */
@@ -81,6 +84,14 @@ void of_register_spi_devices(struct spi_master *master,
struct device_node *np)
of_node_get(nc);
spi-dev.of_node = nc;
+ /* Parse the mtd partitions */
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return;
+ pdata-nr_parts = of_mtd_parse_partitions(master-dev,
+ nc, pdata-parts);
+ spi-dev.platform_data = pdata;
+
/* Register the new device */
request_module(spi-modalias);
rc = spi_add_device(spi);
diff --git a/drivers/spi/spi_mpc8xxx.c b/drivers/spi/spi_mpc8xxx.c
index efed70e..0fadaeb 100644
--- a/drivers/spi/spi_mpc8xxx.c
+++ b/drivers/spi/spi_mpc8xxx.c
@@ -137,6 +137,7 @@ int mpc8xxx_spi_transfer(struct spi_device *spi,
void mpc8xxx_spi_cleanup(struct spi_device *spi)
{
+ kfree(spi-dev.platform_data);
kfree(spi-controller_state);
}
--
1.6.4
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/6] eSPI: add eSPI controller support
Add eSPI controller support based on the common code spi_mpc8xxx.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time, so all the transfers in the same message are needed to combine to one transfer. Signed-off-by: Mingkai Hu mingkai...@freescale.com --- drivers/spi/Kconfig |7 + drivers/spi/Makefile |1 + drivers/spi/fsl_espi.c| 562 + drivers/spi/spi_mpc8xxx.h | 12 + 4 files changed, 582 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/fsl_espi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cd564e2..c647a00 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -196,6 +196,13 @@ config SPI_FSL_SPI help This enables using the Freescale SPI controllers in master mode. +config SPI_FSL_ESPI + tristate Freescale eSPI controller + depends on FSL_SOC + select SPI_MPC8xxx + help + This enables using the Freescale eSPI controllers in master mode. + config SPI_OMAP_UWIRE tristate OMAP1 MicroWire depends on ARCH_OMAP1 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dca9fea..6af459b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o obj-$(CONFIG_SPI_FSL_SPI) += fsl_spi.o +obj-$(CONFIG_SPI_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c new file mode 100644 index 000..ac70c8c --- /dev/null +++ b/drivers/spi/fsl_espi.c @@ -0,0 +1,562 @@ +/* + * MPC8xxx eSPI controller driver. + * + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include linux/module.h +#include linux/delay.h +#include linux/irq.h +#include linux/spi/spi.h +#include linux/platform_device.h +#include linux/fsl_devices.h +#include linux/mm.h +#include linux/of.h +#include linux/of_platform.h +#include linux/of_spi.h +#include sysdev/fsl_soc.h + +#include spi_mpc8xxx.h + +/* eSPI Controller mode register definitions */ +#define SPMODE_ENABLE (1 31) +#define SPMODE_LOOP(1 30) +#define SPMODE_TXTHR(x)((x) 8) +#define SPMODE_RXTHR(x)((x) 0) + +/* eSPI Controller CS mode register definitions */ +#define CSMODE_CI_INACTIVEHIGH (1 31) +#define CSMODE_CP_BEGIN_EDGECLK(1 30) +#define CSMODE_REV (1 29) +#define CSMODE_DIV16 (1 28) +#define CSMODE_PM(x) ((x) 24) +#define CSMODE_POL_1 (1 20) +#define CSMODE_LEN(x) ((x) 16) +#define CSMODE_BEF(x) ((x) 12) +#define CSMODE_AFT(x) ((x) 8) +#define CSMODE_CG(x) ((x) 3) + +/* Default mode/csmode for eSPI controller */ +#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) +#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ + | CSMODE_AFT(0) | CSMODE_CG(1)) + +/* SPIE register values */ +#defineSPIE_NE 0x0200 /* Not empty */ +#defineSPIE_NF 0x0100 /* Not full */ + +/* SPIM register values */ +#defineSPIM_NE 0x0200 /* Not empty */ +#defineSPIM_NF 0x0100 /* Not full */ +#define SPIE_RXCNT(reg) ((reg 24) 0x3F) +#define SPIE_TXCNT(reg) ((reg 16) 0x3F) + +/* SPCOM register values */ +#define SPCOM_CS(x
