RE: [PATCH v7 2/6] soc/fsl/guts: Add definition for LX2160A
> -Original Message-
> From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
> On Behalf Of Vabhav Sharma
> Sent: Monday, October 29, 2018 2:28 PM
> To: sudeep.ho...@arm.com; o...@buserror.net; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> mturque...@baylibre.com; sb...@kernel.org; r...@rjwysocki.net;
> viresh.ku...@linaro.org; linux-...@vger.kernel.org; linux...@vger.kernel.org;
> linux-kernel-ow...@vger.kernel.org; catalin.mari...@arm.com;
> will.dea...@arm.com; gre...@linuxfoundation.org; a...@arndb.de;
> kstew...@linuxfoundation.org; yamada.masah...@socionext.com; Leo Li
> ; shawn...@kernel.org
> Cc: ulf.hans...@linaro.org; Udit Kumar ; Pankaj Bansal
> ; li...@armlinux.org.uk; adrian.hun...@intel.com;
> Varun Sethi ; Vabhav Sharma ;
> Yinbo Zhu
> Subject: [PATCH v7 2/6] soc/fsl/guts: Add definition for LX2160A
>
> Adding compatible string "lx2160a-dcfg" to initialize guts driver for lx2160
> and
> SoC die attribute definition for LX2160A
>
> Signed-off-by: Vabhav Sharma
> Signed-off-by: Yinbo Zhu
> Acked-by: Li Yang
> ---
> drivers/soc/fsl/guts.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c index
> 302e0c8..bcab1ee 100644
> --- a/drivers/soc/fsl/guts.c
> +++ b/drivers/soc/fsl/guts.c
> @@ -100,6 +100,11 @@ static const struct fsl_soc_die_attr fsl_soc_die[] = {
> .svr = 0x8700,
> .mask = 0xfff7,
> },
> + /* Die: LX2160A, SoC: LX2160A/LX2120A/LX2080A */
> + { .die = "LX2160A",
> + .svr = 0x8736,
Do all the threevariants " LX2160A/LX2120A/LX2080A" have same SVR?
> + .mask = 0xff3f,
> + },
> { },
> };
>
> @@ -222,6 +227,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
> { .compatible = "fsl,ls1088a-dcfg", },
> { .compatible = "fsl,ls1012a-dcfg", },
> { .compatible = "fsl,ls1046a-dcfg", },
> + { .compatible = "fsl,lx2160a-dcfg", },
> {}
> };
> MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
> --
> 2.7.4
>
>
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[PATCH 2/4] powerpc/device-tree: bindings for DSP cores/clusters for Freescale SOCs
From: poonam aggrwal <poonam.aggr...@freescale.com>
Device Tree Bindings for DSP CPU clusters and DSP CPUs for Freescale PowerPC
SOCs which have DSP CPUs in addition to PowerPC CPUs.
For example B4860 has 3 DSP clusters which have 2 SC3900 cores each.
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
This patch was sent earlier and some comments were received. Some have been
taken care; others we can further discuss. Apologize for not following up
on them in time.
.../devicetree/bindings/powerpc/fsl/dsp-cpus.txt | 78 ++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
b/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
new file mode 100644
index 000..6d901ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
@@ -0,0 +1,78 @@
+===
+Binding for DSP CPU clusters and DSP CPUs for Freescale SOCs which
+have DSP CPUs in addition to PowerPC cpus.
+Copyright 2013 Freescale Semiconductor Inc.
+
+Power Architecture CPUs in Freescale SOCs are represented in device trees as
+per the definition in ePAPR.
+
+Required properties for DSP CPU cluster:
+- compatible : should be "fsl,sc3900-cluster".
+- reg : should contain the cluster index
+
+Required properties for DSP CPU:
+- compatible : should be "fsl,sc3900".
+- reg : should contain index of DSP CPU within the DSP clsuter.
+- next-level-cache : should point to the phandle of the next-level L2 cache.
+
+Example for B4860:
+B4860 SOC of Freescale has 3 DSP clusters. Each DSP cluster has 2 DSP CPUs
each.
+The DSP CPUs are SC3900. There is a shared L2 cache per DSP cluster.
+ dsp-clusters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsp-cluster0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <0>;
+
+ dsp0: dsp@0 {
+ compatible = "fsl,sc3900";
+ reg = <0>;
+ next-level-cache = <_2>;
+ };
+ dsp1: dsp@1 {
+ compatible = "fsl,sc3900";
+ reg = <1>;
+ next-level-cache = <_2>;
+ };
+ };
+
+ dsp-cluster1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <1>;
+
+ dsp2: dsp@2 {
+ compatible = "fsl,sc3900";
+ reg = <2>;
+ next-level-cache = <_3>;
+ };
+ dsp3: dsp@3 {
+ compatible = "fsl,sc3900";
+ reg = <3>;
+ next-level-cache = <_3>;
+ };
+ };
+
+ dsp-cluster2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <2>;
+
+ dsp4: dsp@4 {
+ compatible = "fsl,sc3900";
+ reg = <4>;
+ next-level-cache = <_4>;
+ };
+ dsp5: dsp@5 {
+ compatible = "fsl,sc3900";
+ reg = <5>;
+ next-level-cache = <_4>;
+ };
+ };
+ };
--
1.9.1
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[PATCH 1/4]fsl/powerpc/b4860: Renamed the L2 caches
To make provision for more than one L2 caches in the system, change the name
from L2 to L2_1; same as in T4 platforms.
* Also remove the L2 entry from common file
"arch/powerpc/boot/dts/fsl/b4si-post.dtsi"
Keep them only in separate files for b4860 and b4420.
Signed-off-by: Shaveta Leekha <shav...@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4 +++-
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 4 ++--
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4 +++-
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 8
arch/powerpc/boot/dts/fsl/b4si-post.dtsi| 6 --
5 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 1ea8602..f996cce 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -89,7 +89,9 @@
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
};
- L2: l2-cache-controller@c2 {
+ L2_1: l2-cache-controller@c2 {
compatible = "fsl,b4420-l2-cache-controller";
+ reg = <0xc2 0x4>;
+ next-level-cache = <>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 338af7e..4257a77 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -65,14 +65,14 @@
device_type = "cpu";
reg = <0 1>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index d1e26a7..be91803 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -258,7 +258,9 @@
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
};
- L2: l2-cache-controller@c2 {
+ L2_1: l2-cache-controller@c2 {
compatible = "fsl,b4860-l2-cache-controller";
+ reg = <0xc2 0x4>;
+ next-level-cache = <>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 1948f73..6823caa 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -65,28 +65,28 @@
device_type = "cpu";
reg = <0 1>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
clocks = <>;
- next-level-cache = <>;
+ next-level-cache = <_1>;
fsl,portid-mapping = <0x8000>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 603910a..d45ff04 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -465,10 +465,4 @@
[PATCH 3/4]fsl/powerpc/b4860: Adds DSP cores/clusters and their L2 caches
B4860 has 3 DSP clusters, each cluster having 2 DSP cores (SC3900),
and every cluster has a shared L2 cache.
Signed-off-by: Shaveta Leekha <shav...@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 18 +
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 +
2 files changed, 77 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index be91803..f6c3b9b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -263,4 +263,22 @@
reg = <0xc2 0x4>;
next-level-cache = <>;
};
+
+ L2_2: l2-cache-controller@c6 {
+ compatible = "fsl,b4860-l2-cache-controller";
+ reg = <0xc6 0x1000>;
+ next-level-cache = <>;
+ };
+
+ L2_3: l2-cache-controller@ca {
+ compatible = "fsl,b4860-l2-cache-controller";
+ reg = <0xca 0x1000>;
+ next-level-cache = <>;
+ };
+
+ L2_4: l2-cache-controller@ce {
+ compatible = "fsl,b4860-l2-cache-controller";
+ reg = <0xce 0x1000>;
+ next-level-cache = <>;
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 6823caa..dbfb2a6 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -90,4 +90,63 @@
fsl,portid-mapping = <0x8000>;
};
};
+
+ dsp-clusters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsp-cluster0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <0>;
+
+ dsp0: dsp@0 {
+ compatible = "fsl,sc3900";
+ reg = <0>;
+ next-level-cache = <_2>;
+ };
+ dsp1: dsp@1 {
+ compatible = "fsl,sc3900";
+ reg = <1>;
+ next-level-cache = <_2>;
+ };
+ };
+
+ dsp-cluster1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <1>;
+
+ dsp2: dsp@2 {
+ compatible = "fsl,sc3900";
+ reg = <2>;
+ next-level-cache = <_3>;
+ };
+ dsp3: dsp@3 {
+ compatible = "fsl,sc3900";
+ reg = <3>;
+ next-level-cache = <_3>;
+ };
+ };
+
+ dsp-cluster2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <2>;
+
+ dsp4: dsp@4 {
+ compatible = "fsl,sc3900";
+ reg = <4>;
+ next-level-cache = <_4>;
+ };
+ dsp5: dsp@5 {
+ compatible = "fsl,sc3900";
+ reg = <5>;
+ next-level-cache = <_4>;
+ };
+ };
+ };
};
--
1.9.1
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[PATCH 4/4]fsl/powerpc/b4420: Adds DSP cores/clusters and their L2 caches
B4420 has 1 DSP cluster, having 2 DSP cores (SC3900), and a shared L2 cache.
Signed-off-by: Shaveta Leekha <shav...@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 6 ++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 23 +++
2 files changed, 29 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index f996cce..02fa374 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -94,4 +94,10 @@
reg = <0xc2 0x4>;
next-level-cache = <>;
};
+
+ L2_2: l2-cache-controller@c6 {
+ compatible = "fsl,b4420-l2-cache-controller";
+ reg = <0xc6 0x4>;
+ next-level-cache = <>;
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 4257a77..900086b 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -76,4 +76,27 @@
fsl,portid-mapping = <0x8000>;
};
};
+
+ dsp-clusters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsp-cluster0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,sc3900-cluster";
+ reg = <0>;
+
+ dsp0: dsp@0 {
+ compatible = "fsl,sc3900";
+ reg = <0>;
+ next-level-cache = <_2>;
+ };
+ dsp1: dsp@1 {
+ compatible = "fsl,sc3900";
+ reg = <1>;
+ next-level-cache = <_2>;
+ };
+ };
+ };
};
--
1.9.1
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[PATCH] fsl/powerpc/b4860: Removed LIODN register from sRIO node
In case of B4860 LIODN register for sRIO is not in GUTs block but in the sRIO
register space.
Signed-off-by: Varun Sethi <varun.se...@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com>
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 9ba904b..d1e26a7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -51,14 +51,12 @@
#address-cells = <2>;
#size-cells = <2>;
cell-index = <1>;
- fsl,liodn-reg = < 0x510>; /* RIO1LIODNR */
};
port2 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <2>;
- fsl,liodn-reg = < 0x514>; /* RIO2LIODNR */
};
};
--
1.9.1
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[PATCH] Device Tree bindings for DSP clusters and DSP CPUs
Binding for DSP CPU clusters and DSP CPUs for Freescale SOCs which
have DSP CPUs in addition to PowerPC CPUs. For example B4860.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/dsp-cpus.txt | 78
1 files changed, 78 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
b/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
new file mode 100644
index 000..da7f5d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dsp-cpus.txt
@@ -0,0 +1,78 @@
+===
+Binding for DSP CPU clusters and DSP CPUs for Freescale SOCs which
+have DSP CPUs in addition to PowerPC cpus.
+Copyright 2013 Freescale Semiconductor Inc.
+
+Power Architecture CPUs in Freescale SOCs are represented in device trees as
+per the definition in ePAPR.
+
+Required properties for DSP CPU cluster:
+- compatible : should be fsl,dsp-cluster or fsl,sc3900-cluster.
+- reg : should contain the cluster index
+
+Required properties for DSP CPU:
+- compatible : should be fsl,dsp or fsl,sc3900.
+- reg : should contain index of DSP CPU within the DSP clsuter.
+- next-level-cache : should point to the phandle of the next-level L2 cache.
+
+Example for B4860:
+B4860 SOC of Freescale has 3 DSP clusters. Each DSP cluster has 2 DSP CPUs
each.
+The DSP CPUs are SC3900. There is a shared L2 cache per DSP cluster.
+ dsp-clusters {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ dsp-cluster0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,sc3900-cluster;
+ reg = 0;
+
+ dsp0: dsp@0 {
+ compatible = fsl,sc3900;
+ reg = 0;
+ next-level-cache = L2_2;
+ };
+ dsp1: dsp@1 {
+ compatible = fsl,sc3900;
+ reg = 1;
+ next-level-cache = L2_2;
+ };
+ };
+
+ dsp-cluster1 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,sc3900-cluster;
+ reg = 1;
+
+ dsp2: dsp@2 {
+ compatible = fsl,sc3900;
+ reg = 2;
+ next-level-cache = L2_3;
+ };
+ dsp3: dsp@3 {
+ compatible = fsl,sc3900;
+ reg = 3;
+ next-level-cache = L2_3;
+ };
+ };
+
+ dsp-cluster2 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,sc3900-cluster;
+ reg = 2;
+
+ dsp4: dsp@4 {
+ compatible = fsl,sc3900;
+ reg = 4;
+ next-level-cache = L2_4;
+ };
+ dsp5: dsp@5 {
+ compatible = fsl,sc3900;
+ reg = 5;
+ next-level-cache = L2_4;
+ };
+ };
+ };
--
1.7.4.1
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[PATCH] Device Tree Bindings for Freescale TDM controller
From: Poonam Aggrwal poonam.aggr...@freescale.com
This TDM controller is available in various Freescale SOCs like MPC8315, P1020,
P1022, P1010.
Signed-off-by: Sandeep Singh sand...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
Documentation/devicetree/bindings/tdm/fsl-tdm.txt | 71 +
1 files changed, 71 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/tdm/fsl-tdm.txt
diff --git a/Documentation/devicetree/bindings/tdm/fsl-tdm.txt
b/Documentation/devicetree/bindings/tdm/fsl-tdm.txt
new file mode 100644
index 000..61431e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/tdm/fsl-tdm.txt
@@ -0,0 +1,71 @@
+=
+TDM Device Tree Binding
+Copyright (C) 2012 Freescale Semiconductor Inc.
+
+NOTE: The bindings described in this document are preliminary
+and subject to change.
+
+=
+TDM (Time Division Multiplexing)
+
+DESCRIPTION
+
+The TDM is full duplex serial port designed to allow various devices including
+digital signal processors (DSPs) to communicate with a variety of serial
devices
+including industry standard framers, codecs, other DSPs and microprocessors.
+
+The below properties describe the device tree bindings for Freescale TDM
+controller.
+This TDM controller is available on various Freescale Processors like
+MPC8313, P1020, P1022 and P1010.
+
+PROPERTIES
+
+ - compatible
+ Usage: required
+ Value type: string
+ Definition: Should contain fsl,mpc8315-tdm.
+ So mpc8313 will have compatible = fsl,mpc8315-tdm;
+ p1010 will have compatible fsl,p1010-tdm, fsl,mpc8315-tdm;
+
+ - reg
+ Usage: required
+ Value type: tdm-reg-offset tdm-reg-size dmac-reg-offset dmac-reg-size
+ Definition: A standard property. Specifies the physical address
+ offset and length of the TDM registers and TDM DMAC registers for
+ the device.
+
+ - clock-frequency
+ Usage: optional
+ Value type: u32
+ Definition: The frequency at which the TDM block is operating.
+
+ - interrupts
+ Usage: required
+ Value type: tdm-err-intr tdm-err-intr-type dmac-intr dmac-intr-type
+ Definition: This field defines two interrupt specifiers namely interrupt
+ number and interrupt type for TDM error and TDM DMAC.
+
+ - phy-handle
+ Usage: optional
+ Value type: phandle
+ Definition: Phandle of the line controller node or framer node eg. SLIC,
+ E1\T1 etc.
+
+ - fsl-max-time-slots
+ Usage: required
+ Value type: u32
+ Definition: Maximum number of 8-bit time slots in one TDM frame.
+ This is the maximum number which TDM hardware supports.
+
+EXAMPLE
+
+ tdm@16000 {
+ device_type = tdm;
+ compatible = fsl,p1010-tdm, fsl,mpc8315-tdm;
+ reg = 0x16000 0x200 0x2c000 0x2000;
+ clock-frequency = 0;
+ interrupts = 16 8 62 8;
+ phy-handle = zarlink1
+ fsl-max-time-slots = 128
+ };
--
1.5.6.5
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[PATCH][1/3][RFC] Adding documentation for TDM
From: Sandeep Singh sand...@freescale.com tdm-summary.txt contains general description about TDM. tdm-framework.txt contains specific description of TDM framework. Signed-off-by: Sandeep Singh sand...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- Added the documentation to so that reviwers get the context. Documentation/tdm/tdm-framework.txt | 257 +++ Documentation/tdm/tdm-summary.txt | 103 ++ 2 files changed, 360 insertions(+), 0 deletions(-) create mode 100644 Documentation/tdm/tdm-framework.txt create mode 100644 Documentation/tdm/tdm-summary.txt diff --git a/Documentation/tdm/tdm-framework.txt b/Documentation/tdm/tdm-framework.txt new file mode 100644 index 000..9f0ca36 --- /dev/null +++ b/Documentation/tdm/tdm-framework.txt @@ -0,0 +1,257 @@ +This document gives an overview of TDM framework and its interface with +low level drivers and upper level users/clients. + +Terminology: + +1. Adapter or TDM adapter: Refers to an instance of TDM controller/device on + the system. +2. TDM channel: The channel is the smallest entity on which all the TDM + read/write operations will occur. + Technically all channels map to a set of consecutive time slots on the + physical TDM frame. + The channels will be dynamically created and destroyed using + tdm_open_channel and tdm_close_channel. +3. TDM frame: Is a set of TDM channels which is transmitted sequentially over + time. The frame start is identified by a frame sync signal that is briefly + asserted at the beginning of each frame. + +X--TDM Frame 0-X--TDM Frame 1-X +||||||||||||||| +| 0 | 1 | 2 | 3 | 4 | ...| n | 0 | 1 | 2 | 3 | 4 | ...| n |... +||||||||||||||| + +ch 0 ch 0 + +4. TDM client: Application/driver which registers with TDM framework to use TDM + device. +5. TDM port: It can be seen as a virtual device exposed to a client. At a time + TDM port can work in one of the follwing configurations + full/fractional/E1/T1/raw. + +TDM modes + +A TDM device can operate in one of the following modes: +1. Single port full mode - Single user/no interleaving 2. Single port +channelised mode (raw, E1, T1)- many users using different + channels +3. Single port fractional mode - +4. Multi port mode - multiple users using different ports in different + configurations. + +All the above configurations differ in number of TDM client they +support, number of TDM channels and number of TDM ports. + +Currently we are supporting only single port channelised mode. Hence +all the explanations below refer to channelised mode of TDM. This +framework can be easily extended to support other modes. + +Single port Channelised Mode +== +In single port channelised mode there can be only one port and each +channel can have only one time slot.The number of active channels can +be less than the maximum supported channels/slots. + +X--TDM Frame 0-X--TDM Frame 1-X +||||||||||||||| +| 0 | 1 | 2 | 3 | 4 | ...| n | 0 | 1 | 2 | 3 | 4 | ...| n |... +||||||||||||||| +------ +ch0 ch1 ch0 ch1 +client0 client1 + +TDM Subsystem Overview + + + |---| + |user mode TDM clients | + |---| +|| +--- + tdm-dev.c || +|| +|| || + client register | kernel mode TDM clients| +|| || +|| || +|| || +|| client register +|| || +\/ \/ + __ + || + | client interface | + || + | TDM Subsystem Framework| + | (tdm-core.c) | + || + | -buffer handling | + | -interleaving/de
[PATCH][2/3][RFC] TDM Framework
From: Sandeep Singh sand...@freescale.com TDM Framework is an attempt to provide a platform independent layer which can offer a standard interface for TDM access to different client modules. Beneath, the framework layer can house different types of TDM drivers to handle various TDM devices, the hardware intricacies of the devices being completely taken care by TDM drivers. This framework layer will allow any type of TDM device to hook with it. For example Freescale controller as on MPC8315, UCC based TDM controller, or any other controller. The main functions of this Framework are: - provides interface to TDM clients to access TDM functionalities. - provides standard interface for TDM drivers to hook with the framework. - handles various data handling stuff and buffer management. In future this Framework will be extended to provide Interface for Line control devices also. For example SLIC, E1/T1 Framers etc. Limitations/Future Work --- 1. Presently the framework supports only Single Port channelised mode. 2. Also the configurability options are limited which will be extended later on. 3. Only kernel mode TDM clients are supported currently. Support for User mode clients will be added later. Signed-off-by: Sandeep Singh sand...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- A couple of todos' are left in the patch, we are working on it and will be addressed in the updated patch set. drivers/Kconfig |1 + drivers/Makefile|1 + drivers/tdm/Kconfig | 25 + drivers/tdm/tdm-core.c | 1146 +++ include/linux/mod_devicetable.h | 11 + include/linux/tdm.h | 347 6 files changed, 1531 insertions(+), 0 deletions(-) create mode 100644 drivers/tdm/Kconfig create mode 100644 drivers/tdm/tdm-core.c create mode 100644 include/linux/tdm.h diff --git a/drivers/Kconfig b/drivers/Kconfig index ad6c1eb..25f7f5b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -130,4 +130,5 @@ source drivers/virt/Kconfig source drivers/net/dpa/NetCommSw/Kconfig +source drivers/tdm/Kconfig endmenu diff --git a/drivers/Makefile b/drivers/Makefile index cd546eb..362b5ed 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_INFINIBAND)+= infiniband/ obj-$(CONFIG_SGI_SN) += sn/ obj-y += firmware/ obj-$(CONFIG_CRYPTO) += crypto/ +obj-$(CONFIG_TDM) += tdm/ obj-$(CONFIG_SUPERH) += sh/ obj-$(CONFIG_ARCH_SHMOBILE)+= sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET diff --git a/drivers/tdm/Kconfig b/drivers/tdm/Kconfig new file mode 100644 index 000..8db2b05 --- /dev/null +++ b/drivers/tdm/Kconfig @@ -0,0 +1,25 @@ +# +# TDM subsystem configuration +# + +menuconfig TDM + tristate TDM support + ---help--- + More information is contained in the directory file:Documentation/tdm/, + especially in the file called summary there. + If you want TDM support, you should say Y here and also to the + specific driver for your bus adapter(s) below. + + This TDM support can also be built as a module. If so, the module + will be called tdm-core. + +if TDM + +config TDM_DEBUG_CORE + bool TDM Core debugging messages + help + Say Y here if you want the TDM core to produce a bunch of debug + messages to the system log. Select this if you are having a + problem with TDM support and want to see more of what is going on. + +endif # TDM diff --git a/drivers/tdm/tdm-core.c b/drivers/tdm/tdm-core.c new file mode 100644 index 000..cdda260 --- /dev/null +++ b/drivers/tdm/tdm-core.c @@ -0,0 +1,1146 @@ +/* driver/tdm/tdm-core.c + * + * Copyright (C) 2012 Freescale Semiconductor, Inc, All rights reserved. + * + * TDM core is the interface between TDM clients and TDM devices. + * It is also intended to serve as an interface for line controld + * devices later on. + * + * Author:Hemant Agrawal hem...@freescale.com + * Rajesh Gumasta rajesh.guma...@freescale.com + * + * Modified by Sandeep Kr Singh sand...@freescale.com + * Poonam Aggarwal poonam.aggar...@freescale.com + * 1. Added framework based initialization of device. + * 2. All the init/run time configuration is now done by framework. + * 3. Added channel level operations. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should
[PATCH][3/3][RFC] TDM device Support driver for Freescale TDM controller
From: Sandeep Singh sand...@freescale.com Freescale TDM controller consists of a TDM module supporting 128 channels running at up to 50 Mbps with 8-bit and 16-bit word size. The TDM bus connects gluelessly to most T1/E1frames as well as to common buses such as the H.110, SCAS, and MVIP. The TDM also supports an I2S mode. The TDM module operates in independent or shared mode when receiving or transmitting data This controller is available on MPC8315, P1010, P1020 Freescale SOCs. The driver registers itself with the TDM Framework provides TDM functionality to the client modules. As of now the driver supports only channelised mode. Signed-off-by: Sandeep Singh sand...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com --- drivers/tdm/Kconfig |1 + drivers/tdm/Makefile | 10 + drivers/tdm/device/Kconfig | 15 + drivers/tdm/device/Makefile |9 + drivers/tdm/device/tdm_fsl.c | 892 ++ drivers/tdm/device/tdm_fsl.h | 456 + 6 files changed, 1383 insertions(+), 0 deletions(-) create mode 100644 drivers/tdm/Makefile create mode 100644 drivers/tdm/device/Kconfig create mode 100644 drivers/tdm/device/Makefile create mode 100644 drivers/tdm/device/tdm_fsl.c create mode 100644 drivers/tdm/device/tdm_fsl.h diff --git a/drivers/tdm/Kconfig b/drivers/tdm/Kconfig index 8db2b05..87d6929 100644 --- a/drivers/tdm/Kconfig +++ b/drivers/tdm/Kconfig @@ -22,4 +22,5 @@ config TDM_DEBUG_CORE messages to the system log. Select this if you are having a problem with TDM support and want to see more of what is going on. +source drivers/tdm/device/Kconfig endif # TDM diff --git a/drivers/tdm/Makefile b/drivers/tdm/Makefile new file mode 100644 index 000..fd2464b --- /dev/null +++ b/drivers/tdm/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the TDM core. +# + +obj-$(CONFIG_TDM) += tdm-core.o + +obj-y += device/ +ifeq ($(CONFIG_TDM_DEBUG_CORE),y) +EXTRA_CFLAGS += -DDEBUG +endif diff --git a/drivers/tdm/device/Kconfig b/drivers/tdm/device/Kconfig new file mode 100644 index 000..db5d741 --- /dev/null +++ b/drivers/tdm/device/Kconfig @@ -0,0 +1,15 @@ +# +# Sensor device configuration +# + +menu TDM Device support + +config TDM_FSL + tristate Driver for Freescale TDM controller + depends on FSL_SOC + ---help--- + This is a driver for Freescale TDM controller. The controller + is found in various Freescale SOCs viz MPC8315, P1020. The TDM driver + basically multiplexes and demultiplexes data from different channels. + The TDM can interface SLIC kind of devices. +endmenu diff --git a/drivers/tdm/device/Makefile b/drivers/tdm/device/Makefile new file mode 100644 index 000..e671a66 --- /dev/null +++ b/drivers/tdm/device/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the TDM bus drivers. +# + +obj-$(CONFIG_TDM_FSL) += tdm_fsl.o + +#ifeq ($(CONFIG_TDM_DEBUG_BUS),y) +#EXTRA_CFLAGS += -DDEBUG +#endif diff --git a/drivers/tdm/device/tdm_fsl.c b/drivers/tdm/device/tdm_fsl.c new file mode 100644 index 000..99ee4d7 --- /dev/null +++ b/drivers/tdm/device/tdm_fsl.c @@ -0,0 +1,892 @@ +/* + * drivers/tdm/tdm_fsl.c + * + * Copyright (C) 2007-2012 Freescale Semiconductor, Inc, All rights reserved. + * + * TDM driver for Freescale TDM controller. + * This driver can interface with SLIC device to run VOIP kind of + * applications. + * + * Author: P. V. Suresh p...@freescale.com + * Hemant Agrawal hem...@freescale.com + * Rajesh Gumasta rajesh.guma...@freescale.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + /* Note that this is a complete rewrite of P.V. Suresh's driver code. +But we have used so much of his original code and ideas that it seems +only fair to recognize him as co-author -- Rajesh Hemant */ + +#include linux/kernel.h +#include linux/module.h +#include linux/sched.h +#include linux/init.h +#include linux/platform_device.h +#include linux/slab.h +#include linux/of_platform.h +#include linux/io.h +#include linux/tdm.h +#include linux/interrupt.h +#include linux/irq.h +#include linux/dma-mapping.h +#include linux/spinlock.h +#include sysdev/fsl_soc.h + +#include tdm_fsl.h + +#define DRV_DESC Freescale TDM Driver
[PATCH] [NAND FSL eLBC] Modified the NAND FSL elbc driver code to correctly determine which chipselect is connected to NAND flash.
The current code that determines which bank/chipselect is used for a
given NAND instance only worked for 32-bit addresses and assumed
a 1:1 mapping. This breaks in 36-bit physical configs.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Acked-by: Scott Wood scottw...@freescale.com
---
Tested on P2020RDB and P1020RDB platforms.
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 09228c6..a9b0cfa 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -853,7 +853,7 @@ static int __devinit fsl_elbc_nand_probe(struct of_device
*dev,
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== (u32)res.start)
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
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[no subject]
Subject: [PATCH][v4] powerpc/85xx: Added P1020RDB Platform support.
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the later patches.
- changes above v3- minor change in a comment for localbus chipselects.
arch/powerpc/boot/dts/p1020rdb.dts| 477 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR (RO) U-Boot Image
[PATCH][v4] powerpc/85xx: Added P1020RDB Platform support.
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the later patches.
- changes above v3- minor change in a comment for localbus chipselects.
PLEASE ignore the earlier patch mail with no subject.
arch/powerpc/boot/dts/p1020rdb.dts| 477 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR (RO) U-Boot Image;
+ read
[PATCH][v2] powerpc/85xx: Create dts for each core in CAMP mode for P2020RDB
This patch creates the dts files for each core and splits the devices between
the two cores for P2020RDB.
core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.
MPIC is shared between two cores but each core will protect its
interrupts from other core by using protected-sources of mpic.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- Removed interrupt properties for serial ports to make them work in polling
mode.
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 363 +
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 184 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 10 +-
3 files changed, 556 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
new file mode 100644
index 000..0fe93d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -0,0 +1,363 @@
+/*
+ * P2020 RDB Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
+ * eth1, eth2, sdhc, crypto, global-util, pci0.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P2020;
+ compatible = fsl,P2020RDB, fsl,MPC85XXRDB-CAMP;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ ethernet1 = enet1;
+ ethernet2 = enet2;
+ serial0 = serial0;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p2...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ s...@ffe0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ device_type = soc;
+ compatible = fsl,p2020-immr, simple-bus;
+ ranges = 0x0 0x0 0xffe0 0x10;
+ bus-frequency = 0;// Filled out by uboot.
+
+ ecm-...@0 {
+ compatible = fsl,ecm-law;
+ reg = 0x0 0x1000;
+ fsl,num-laws = 12;
+ };
+
+ e...@1000 {
+ compatible = fsl,p2020-ecm, fsl,ecm;
+ reg = 0x1000 0x1000;
+ interrupts = 17 2;
+ interrupt-parent = mpic;
+ };
+
+ memory-control...@2000 {
+ compatible = fsl,p2020-memory-controller;
+ reg = 0x2000 0x1000;
+ interrupt-parent = mpic;
+ interrupts = 18 2;
+ };
+
+ i...@3000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 0;
+ compatible = fsl-i2c;
+ reg = 0x3000 0x100;
+ interrupts = 43 2;
+ interrupt-parent = mpic;
+ dfsrr;
+ r...@68 {
+ compatible = dallas,ds1339;
+ reg = 0x68;
+ };
+ };
+
+ i...@3100 {
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 1;
+ compatible = fsl-i2c;
+ reg = 0x3100 0x100;
+ interrupts = 43 2;
+ interrupt-parent = mpic;
+ dfsrr;
+ };
+
+ serial0: ser...@4500 {
+ cell-index = 0;
+ device_type = serial;
+ compatible = ns16550;
+ reg = 0x4500 0x100;
+ clock-frequency = 0;
+ };
+
+ s...@7000 {
+ cell-index = 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,espi
[PATCH][v1] powerpc/85xx: Create dts for each core in CAMP mode for P2020RDB
This patch creates the dts files for each core and splits the devices between
the two cores for P2020RDB.
core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.
MPIC is shared between two cores but each core will protect its
interrupts from other core by using protected-sources of mpic.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 365 +
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 186 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 10 +-
3 files changed, 560 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
new file mode 100644
index 000..ca072da
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -0,0 +1,365 @@
+/*
+ * P2020 RDB Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
+ * eth1, eth2, sdhc, crypto, global-util, pci0.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P2020;
+ compatible = fsl,P2020RDB, fsl,MPC85XXRDB-CAMP;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ ethernet1 = enet1;
+ ethernet2 = enet2;
+ serial0 = serial0;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p2...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ s...@ffe0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ device_type = soc;
+ compatible = fsl,p2020-immr, simple-bus;
+ ranges = 0x0 0x0 0xffe0 0x10;
+ bus-frequency = 0;// Filled out by uboot.
+
+ ecm-...@0 {
+ compatible = fsl,ecm-law;
+ reg = 0x0 0x1000;
+ fsl,num-laws = 12;
+ };
+
+ e...@1000 {
+ compatible = fsl,p2020-ecm, fsl,ecm;
+ reg = 0x1000 0x1000;
+ interrupts = 17 2;
+ interrupt-parent = mpic;
+ };
+
+ memory-control...@2000 {
+ compatible = fsl,p2020-memory-controller;
+ reg = 0x2000 0x1000;
+ interrupt-parent = mpic;
+ interrupts = 18 2;
+ };
+
+ i...@3000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 0;
+ compatible = fsl-i2c;
+ reg = 0x3000 0x100;
+ interrupts = 43 2;
+ interrupt-parent = mpic;
+ dfsrr;
+ r...@68 {
+ compatible = dallas,ds1339;
+ reg = 0x68;
+ };
+ };
+
+ i...@3100 {
+ #address-cells = 1;
+ #size-cells = 0;
+ cell-index = 1;
+ compatible = fsl-i2c;
+ reg = 0x3100 0x100;
+ interrupts = 43 2;
+ interrupt-parent = mpic;
+ dfsrr;
+ };
+
+ serial0: ser...@4500 {
+ cell-index = 0;
+ device_type = serial;
+ compatible = ns16550;
+ reg = 0x4500 0x100;
+ clock-frequency = 0;
+ interrupts = 42 2;
+ interrupt-parent = mpic;
+ };
+
+ s...@7000 {
+ cell-index = 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,espi
[PATCH][v3] powerpc/85xx: P1020RDB Support Added
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the later patches.
arch/powerpc/boot/dts/p1020rdb.dts| 477 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR (RO) U-Boot Image;
+ read-only;
+ };
+ };
+
+ n...@1,0 {
+ #address-cells = 1
[PATCH][v2] powerpc/85xx: P1020RDB Support Added
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch-next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the following patches.
- changes over v1- few changes in interrupt numbers.
arch/powerpc/boot/dts/p1020rdb.dts| 477 +
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 000..1e0e850
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P1020;
+ compatible = fsl,P1020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p1...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p1...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 16 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR (RO) U-Boot Image;
+ read-only;
+ };
+ };
+
+ n...@1,0
[PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
1) etSEC1
- RGMII
- connected to a 5 port Vitesse Switch(VSC7385)
- Switch is memory mapped through eLBC interface(CS#2)
- IRQ1
2) etSEC2
- SGMII
- connected to VSC8221
- IRQ2
3) etSEC3
- RGMII
- connected to VSC8641
- IRQ3
- 2 1X PCIe interfaces
- SD/MMC ,USB
- SPI EEPROM
- Serial I2C EEPROM
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
incorporated Felix feedback regarding the partition names.
fixed the vitesse switch ranges entry in device tree.
arch/powerpc/boot/dts/p2020rdb.dts| 586 +
arch/powerpc/configs/mpc85xx_defconfig|1 +
arch/powerpc/platforms/85xx/Kconfig |9 +
arch/powerpc/platforms/85xx/Makefile |3 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++
5 files changed, 739 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts
b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000..617029f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P2020;
+ compatible = fsl,P2020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ ethernet2 = enet2;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p2...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p2...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p2020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System
[v3][PATCH][powerpc/85xx] P2020RDB Platform Support Added
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
1) etSEC1
- RGMII
- connected to a 5 port Vitesse Switch(VSC7385)
- Switch is memory mapped through eLBC interface(CS#2)
- IRQ1
2) etSEC2
- SGMII
- connected to VSC8221
- IRQ2
3) etSEC3
- RGMII
- connected to VSC8641
- IRQ3
- 2 1X PCIe interfaces
- SD/MMC ,USB
- SPI EEPROM
- Serial I2C EEPROM
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Incorporated more feedback from Felix
arch/powerpc/boot/dts/p2020rdb.dts| 586 +
arch/powerpc/configs/mpc85xx_defconfig|1 +
arch/powerpc/platforms/85xx/Kconfig |9 +
arch/powerpc/platforms/85xx/Makefile |3 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++
5 files changed, 739 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts
b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000..da4cb0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P2020;
+ compatible = fsl,P2020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ ethernet2 = enet2;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p2...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p2...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p2020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partit...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partit...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ partit...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ partit...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ partit...@f0
[PATCH][powerpc/85xx] P2020RDB Platform Support Added
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
1) etSEC1
- RGMII
- connected to a 5 port Vitesse Switch(VSC7385)
- Switch is memory mapped through eLBC interface(CS#2)
- IRQ1
2) etSEC2
- SGMII
- connected to VSC8221
- IRQ2
3) etSEC3
- RGMII
- connected to VSC8641
- IRQ3
- 2 1X PCIe interfaces
- SD/MMC ,USB
- SPI EEPROM
- Serial I2C EEPROM
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
---
based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
arch/powerpc/boot/dts/p2020rdb.dts| 586 +
arch/powerpc/configs/mpc85xx_defconfig|1 +
arch/powerpc/platforms/85xx/Kconfig |9 +
arch/powerpc/platforms/85xx/Makefile |3 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++
5 files changed, 739 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts
b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000..d6d8131
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = fsl,P2020;
+ compatible = fsl,P2020RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ ethernet2 = enet2;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ pci1 = pci1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,p2...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ next-level-cache = L2;
+ };
+
+ PowerPC,p2...@1 {
+ device_type = cpu;
+ reg = 0x1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ local...@ffe05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p2020-elbc, fsl,elbc, simple-bus;
+ reg = 0 0xffe05000 0 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ /* NOR and NAND Flashes */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xffa0 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0800;
+
+ n...@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ vitesse-7385...@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR (RO) Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ d...@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR (RO) DTB Image;
+ read-only;
+ };
+
+ uim...@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR (RO) Linux Kernel Image;
+ read-only;
+ };
+
+ jf...@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR (RW) JFFS2 Root File System;
+ };
+
+ u-b...@f0 {
+ /* This location must not be altered
Re: [PATCH 2/3] arch/ : Platform changes for UCC TDM driver for MPC8323ERDB.Also includes related QE changes.
Thanx Tabi for your comments.
Sorry I was on leave for the last week, so could not reply in time.
Shall make the changes you suggested and repost the patch.
Regards
Poonam
On 12/11/07, Timur Tabi [EMAIL PROTECTED] wrote:
Poonam_Aggrwal-b10812 wrote:
+ qe = of_find_node_by_type(NULL, qe);
+ if (qe) {
+ unsigned int size;
+ prop = of_get_property
+ (qe, brg-frequency,
size);
+ of_node_put(qe);
+ of_node_put(brg);
+ return *prop;
+ }
Only very recent versions of U-Boot set the brg-frequency property, so you
need
to check for situations where *prop is 0. If it is, then you need to
take the
QE's bus-frequency property and divide it by two. See my ucc_uart driver
for an
example.
And PowerPC-specific patches should not be cross-posted to linux-kernel.
--
Timur Tabi
Linux kernel developer at Freescale
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