Re: [PATCH v4 0/3] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs)

[Prabhakar Kushwaha]

Hi Akashi,

On Fri, Nov 15, 2019 at 7:29 AM AKASHI Takahiro
 wrote:
>
> Bhupesh,
>
> On Fri, Nov 15, 2019 at 01:24:17AM +0530, Bhupesh Sharma wrote:
> > Hi Akashi,
> >
> > On Wed, Nov 13, 2019 at 12:11 PM AKASHI Takahiro
> >  wrote:
> > >
> > > Hi Bhupesh,
> > >
> > > Do you have a corresponding patch for userspace tools,
> > > including crash util and/or makedumpfile?
> > > Otherwise, we can't verify that a generated core file is
> > > correctly handled.
> >
> > Sure. I am still working on the crash-utility related changes, but you
> > can find the makedumpfile changes I posted a couple of days ago here
> > (see [0]) and the github link for the makedumpfile changes can be seen
> > via [1].
> >
> > I will post the crash-util changes shortly as well.
> > Thanks for having a look at the same.
>
> Thank you.
> I have tested my kdump patch with a hacked version of crash
> where VA_BITS_ACTUAL is calculated from tcr_el1_t1sz in vmcoreinfo.
>

I also did hack to calculate VA_BITS_ACTUAL is calculated from
tcr_el1_t1sz in vmcoreinfo. Now i am getting error same as mentioned
by you in other thread last month.
https://www.mail-archive.com/crash-utility@redhat.com/msg07385.html

how this error was overcome?

I am using
 - crashkernel: https://github.com/crash-utility/crash.git  commit:
babd7ae62d4e8fd6f93fd30b88040d9376522aa3
and
 - Linux: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
commit: af42d3466bdc8f39806b26f593604fdc54140bcb

--pk

Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects

[Prabhakar Kushwaha]

On 8/22/2014 11:21 PM, Scott Wood wrote:

On Fri, 2014-08-22 at 20:07 +0530, Prabhakar Kushwaha wrote:

Sorry Scott for late reply,

Please find my reply in-lined


On 8/21/2014 4:51 AM, Scott Wood wrote:

On Wed, 2014-08-20 at 09:05 +0530, Prabhakar Kushwaha wrote:

On 8/20/2014 5:38 AM, Scott Wood wrote:

On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote:

Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.

Signed-off-by: Aaron Sierra asie...@xes-inc.com
---
include/linux/fsl_ifc.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 84d60cb..62762ff 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -29,7 +29,7 @@
#include linux/of_platform.h
#include linux/interrupt.h

-#define FSL_IFC_BANK_COUNT 4

+#define FSL_IFC_BANK_COUNT 8

First please modify fsl_ifc_nand.c to limit itself to the number of
banks it dynamically determines are present based on the IFC version.



Number of available bank/chip select are defined by SoC and it is
independent of SoC.

Do you mean defined by the SoC and independent of the IFC version?

IFC v 1.0.0 supports 4 Chip Select.
IFC v 1.1.0 onwards, IFC supports 8 chip select.

But SoC finally defines number of chip select coming out of SoC. Like
LS1021A with IFC ver 1.4.0 have only 7 Chip Select.

What matters here is whether the registers are implemented, not whether
a chip select is pinned out -- so use the IFC version.


I checked with IFC IP team  There is no side-effect of reading CS-8  
register if only 7 CS exposed by SoC


IFC version can be used.

Regards,
Prabhakar


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Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects

[Prabhakar Kushwaha]

Sorry Scott for late reply,

Please find my reply in-lined


On 8/21/2014 4:51 AM, Scott Wood wrote:

On Wed, 2014-08-20 at 09:05 +0530, Prabhakar Kushwaha wrote:

On 8/20/2014 5:38 AM, Scott Wood wrote:

On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote:

Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.

Signed-off-by: Aaron Sierra asie...@xes-inc.com
---
   include/linux/fsl_ifc.h | 10 +-
   1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 84d60cb..62762ff 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -29,7 +29,7 @@
   #include linux/of_platform.h
   #include linux/interrupt.h
   
-#define FSL_IFC_BANK_COUNT 4

+#define FSL_IFC_BANK_COUNT 8

First please modify fsl_ifc_nand.c to limit itself to the number of
banks it dynamically determines are present based on the IFC version.



Number of available bank/chip select are defined by SoC and it is
independent of SoC.

Do you mean defined by the SoC and independent of the IFC version?


IFC v 1.0.0 supports 4 Chip Select.
IFC v 1.1.0 onwards, IFC supports 8 chip select.

But SoC finally defines number of chip select coming out of SoC. Like 
LS1021A with IFC ver 1.4.0 have only 7 Chip Select.



It should be fix in following way

Option 1:
u-boot:  fix device tree with number of available chip select. It may
require IFC binding change
Linux: Read device tree and determine the Chip Selects

If we do this then it will need to be an optional property that defaults
to the current assumption being made (4).


Yes, I agree with you.


In the future we really ought to check whether there are integration
parameters when coming up with the initial binding for a hardware
block...


True.



Option 2:
Make it static because any way IFC NAND driver polls to
FSL_IFC_BANK_COUNT to know NAND flash chip select. This patch is doing same.

I don't understand what you're saying here.  The driver does not know at
compile time how many there are.  What this patch does is assume it's OK
to access non-existent registers in the rare case that there's no match
in the registers that exist.


in case of P1010, If we run loop for 8 times,
 we are accessing reserved memory, that's why it may work. In Ideal 
scenario, we should not access the reserved memory.




Aaron tested this on P1010 and it seemed to work, though I'm not
generally fond of relying on such things.


yes, I agree.

 If I conclude  ==   We should go with option 1.  Am I correct?


Regards,
Prabhakar

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Re: [PATCH 1/2] fsl_ifc: Fix csor_ext position in fsl_ifc_regs

[Prabhakar Kushwaha]

On 8/16/2014 2:37 AM, Aaron Sierra wrote:

According to Freescale manuals, the IFC_CSORn_EXT register is located
immediately _after_ the bank's IFC_CSORn register.

This patch adjusts the csor_ext member of and reserved register arrays
immediately surrounding the csor_cs structure to provide proper access
to this register.

Signed-off-by: Aaron Sierra asie...@xes-inc.com
---



Thanks for fixing it.

Acked-by: Prabhakar Kushwaha prabha...@freescale.com

Thanks,
Prabhakar
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Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects

[Prabhakar Kushwaha]

On 8/20/2014 5:38 AM, Scott Wood wrote:

On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote:

Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.

Signed-off-by: Aaron Sierra asie...@xes-inc.com
---
  include/linux/fsl_ifc.h | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 84d60cb..62762ff 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -29,7 +29,7 @@
  #include linux/of_platform.h
  #include linux/interrupt.h
  
-#define FSL_IFC_BANK_COUNT 4

+#define FSL_IFC_BANK_COUNT 8

First please modify fsl_ifc_nand.c to limit itself to the number of
banks it dynamically determines are present based on the IFC version.




Number of available bank/chip select are defined by SoC and it is 
independent of SoC.

It should be fix in following way

Option 1:
u-boot:  fix device tree with number of available chip select. It may 
require IFC binding change

Linux: Read device tree and determine the Chip Selects

or

Option 2:
Make it static because any way IFC NAND driver polls to 
FSL_IFC_BANK_COUNT to know NAND flash chip select. This patch is doing same.


Regards,
Prabhakar


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[PATCH][v10] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 
 Changes for v6: Updated branch of creation 
 Changes for v7: Incororated Scott's commetns
- Create patch set
- remove whitespace
- Removed l2switch. It will be added later
 Changes for v8: Incorporated Scott's comments
- Added comment line in T1042si-post.dtsi
- removed extra lines
 Changes for v9:
- updated clock node as per new bindings
- removed extra line
- added dma node
 Changes for v10:
- update corenet compatible
- remove clock frequency from dts file
 - fix white space

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  430 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   37 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  104 +++
 3 files changed, 571 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..2cae320
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,430 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free

[PATCH][v10] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented.
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 Changes for v6: Updated depedencies
 Changes for v7: Incororated Scott's commetns
- Create patch set
 Changes for v8: Sending as it is
 Changes for v9:
- removed partitions
- updated FPGA node
- Fix PCIe range fields
 Changes for v10:
- Updated SPI flash compatible

 arch/powerpc/boot/dts/t1040qds.dts|   46 +++
 arch/powerpc/boot/dts/t1042qds.dts|   46 +++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  166 +
 arch/powerpc/platforms/85xx/Kconfig   |2 +-
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 5 files changed, 263 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING

Re: [1/2, v9] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

On 3/20/2014 4:03 AM, Scott Wood wrote:

On Sat, Jan 25, 2014 at 05:10:59PM +0530, Prabhakar Kushwaha wrote:

+   corenet-cf@18000 {
+   compatible = fsl,corenet-cf;
+   reg = 0x18000 0x1000;
+   interrupts = 16 2 1 31;
+   fsl,ccf-num-csdids = 32;
+   fsl,ccf-num-snoopids = 32;
+   };

I know this isn't a new problem, but this needs a binding -- and a
different compatible from p4080-era CCF.  AFAICT it's a completely
different programming model, and even the block version registers weren't
present in the original version.


No binding present for corenet-cf looks like new binding needs to be 
sent with possible compatabile.




+/include/ qoriq-mpic.dtsi
+
+   guts: global-utilities@e {
+   compatible = fsl,t1040-device-config, 
fsl,qoriq-device-config-2.0;
+   reg = 0xe 0xe00;
+   fsl,has-rstcr;
+   fsl,liodn-bits = 12;
+   };
+
+   clockgen: global-utilities@e1000 {
+   compatible = fsl,t1040-clockgen, fsl,qoriq-clockgen-2.0,
+  fixed-clock;
+   ranges = 0x0 0xe1000 0x1000;
+   clock-frequency = 1;

Why is clock-frequency hardcoded here rather than supplied by U-Boot?
Especially since this is an SoC file, not a board file.


Your are correct.
Means, clock-frequency should be added to clockgen in board device tree ??



+   reg = 0xe1000 0x1000;
+   clock-output-names = sysclk;
+   #address-cells = 1;
+   #size-cells = 1;

clock-output-names and fixed-clock doesn't belong on this node.


Yes, clock-output-names and fixed-clock should be present in sysclk node.





+
+   sysclk: sysclk {
+   #clock-cells = 0;
+   compatible = fsl,qoriq-sysclk-2.0;
+   clock-output-names = sysclk;
+   };
+
+
+   pll0: pll0@800 {
+   #clock-cells = 1;
+   reg = 0x800 4;
+   compatible = fsl,qoriq-core-pll-2.0;
+   clocks = clockgen;
+   clock-output-names = pll0, pll0-div2, pll0-div4;
+   };
+
+   pll1: pll1@820 {
+   #clock-cells = 1;
+   reg = 0x820 4;
+   compatible = fsl,qoriq-core-pll-2.0;
+   clocks = clockgen;
+   clock-output-names = pll1, pll1-div2, pll1-div4;
+   };

clocks should point to sysclk.


got it!!




+   display@18 {
+   compatible = fsl,t1040-diu, fsl,diu;
+   reg = 0x18 1000;
+   interrupts = 74 2 0 0;
+   };
+
+/include/ qoriq-sata2-0.dtsi
+sata@22 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+};
+/include/ qoriq-sata2-1.dtsi
+sata@221000 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+};
+/include/ qoriq-sec5.0-0.dtsi
+};

Whitespace



i did not find this whitespace :(


Regards,
Prabhakar



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Re: [PATCH v2] powerpc: select MEMORY for FSL_IFC to not break existing .config files

[Prabhakar Kushwaha]

On 2/20/2014 8:10 PM, Paul Gortmaker wrote:

On 14-02-20 01:05 AM, Prabhakar Kushwaha wrote:

On 2/20/2014 4:16 AM, Paul Gortmaker wrote:

commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc (driver/memory:Move
Freescale IFC driver to a common driver) introduces this build
regression into the mpc85xx_defconfig:

   drivers/built-in.o: In function `fsl_ifc_nand_remove':
   drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/built-in.o: In function `fsl_ifc_nand_probe':
   drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/built-in.o: In function `match_bank':
   drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to 
`convert_ifc_address'
   drivers/built-in.o: In function `fsl_ifc_nand_probe':
   drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to 
`fsl_ifc_ctrl_dev'
   drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to 
`fsl_ifc_ctrl_dev'
   make: *** [vmlinux] Error 1

This happens because there is nothing to descend us into the
drivers/memory directory in the mpc85xx_defconfig.  It wasn't
selecting CONFIG_MEMORY.  So we never built drivers/memory/fsl_ifc.o
and so we have nothing to link the above symbols against.

Since the goal of the original commit was to relocate the driver to
an arch independent location, it only makes sense to relocate the
Kconfig setting there as well.  But that alone won't fix the build
failure; for that we ensure whoever selects FSL_IFC also selects MEMORY.

Cc: Prabhakar Kushwaha prabha...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: Arnd Bergmann a...@arndb.de
Cc: David Woodhouse dw...@infradead.org
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---

[v2: fix the mislocated FSL_IFC as per Scott's comment.  It still
   probably makes sense to go in via Greg's char-misc/char-misc-next
   (vs. powerpc-next) since that is where the regression was introduced.]

   arch/powerpc/Kconfig | 4 
   drivers/memory/Kconfig   | 4 
   drivers/mtd/nand/Kconfig | 1 +
   3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 957bf344c0f5..b9fcecc706ab 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -736,10 +736,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
   
-config FSL_IFC

-   bool
-depends on FSL_SOC
-
   config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db365bc..a3640fe9852f 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,8 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
   
+config FSL_IFC

+   bool
+   depends on FSL_SOC
+
   endif
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 90ff447bf043..a4bee41ad5cb 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -428,6 +428,7 @@ config MTD_NAND_FSL_IFC
tristate NAND support for Freescale IFC controller
depends on MTD_NAND  FSL_SOC
select FSL_IFC
+   select MEMORY
help
  Various Freescale chips e.g P1010, include a NAND Flash machine
  with built-in hardware ECC capabilities.

Hi All,

I am not sure which version of patch is being picked here.

Latest version is v8 and it is a patch set and it do enable
CONFIG_MEMORY in powerpc/configs

It really doesn't matter what the latest version is, if the
maintainer has already taken an earlier version and merged it.
In that case one needs to work with the maintainer to determine
whether they want a new version, or a delta/fixup commit on the
old one.

I think, I got the reason of this issue.
I thought this patch will be picked by powerpc.git and updated version 
were sent on linuxppc-dev mail list after initial version review on both 
powerpc and linux-kernel mailing list. It should have sent on both the 
list always.   A learning for future :)


I am OK with the current patch and modification  because it  full fill 
my requirements.

I will sent separate patch to fix other things.



1.  driver/memory:Move Freescale IFC driver to a common driver
http://patchwork.ozlabs.org/patch/315531/

So, this has the Kconfig move part, but the one currently in
char-misc does not.  And it still needs the select.


2. powerpc/config: Enable memory driver
http://patchwork.ozlabs.org/patch/315532/

Updating the defconfigs is fine

Re: [PATCH v2] powerpc: select MEMORY for FSL_IFC to not break existing .config files

[Prabhakar Kushwaha]

On 2/20/2014 4:16 AM, Paul Gortmaker wrote:

commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc (driver/memory:Move
Freescale IFC driver to a common driver) introduces this build
regression into the mpc85xx_defconfig:

  drivers/built-in.o: In function `fsl_ifc_nand_remove':
  drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/built-in.o: In function `fsl_ifc_nand_probe':
  drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/built-in.o: In function `match_bank':
  drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to 
`convert_ifc_address'
  drivers/built-in.o: In function `fsl_ifc_nand_probe':
  drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to 
`fsl_ifc_ctrl_dev'
  drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to 
`fsl_ifc_ctrl_dev'
  make: *** [vmlinux] Error 1

This happens because there is nothing to descend us into the
drivers/memory directory in the mpc85xx_defconfig.  It wasn't
selecting CONFIG_MEMORY.  So we never built drivers/memory/fsl_ifc.o
and so we have nothing to link the above symbols against.

Since the goal of the original commit was to relocate the driver to
an arch independent location, it only makes sense to relocate the
Kconfig setting there as well.  But that alone won't fix the build
failure; for that we ensure whoever selects FSL_IFC also selects MEMORY.

Cc: Prabhakar Kushwaha prabha...@freescale.com
Cc: Scott Wood scottw...@freescale.com
Cc: Arnd Bergmann a...@arndb.de
Cc: David Woodhouse dw...@infradead.org
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---

[v2: fix the mislocated FSL_IFC as per Scott's comment.  It still
  probably makes sense to go in via Greg's char-misc/char-misc-next
  (vs. powerpc-next) since that is where the regression was introduced.]

  arch/powerpc/Kconfig | 4 
  drivers/memory/Kconfig   | 4 
  drivers/mtd/nand/Kconfig | 1 +
  3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 957bf344c0f5..b9fcecc706ab 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -736,10 +736,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
  
-config FSL_IFC

-   bool
-depends on FSL_SOC
-
  config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db365bc..a3640fe9852f 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,8 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
  
+config FSL_IFC

+   bool
+   depends on FSL_SOC
+
  endif
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 90ff447bf043..a4bee41ad5cb 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -428,6 +428,7 @@ config MTD_NAND_FSL_IFC
tristate NAND support for Freescale IFC controller
depends on MTD_NAND  FSL_SOC
select FSL_IFC
+   select MEMORY
help
  Various Freescale chips e.g P1010, include a NAND Flash machine
  with built-in hardware ECC capabilities.


Hi All,

I am not sure which version of patch is being picked here.

Latest version is v8 and it is a patch set and it do enable 
CONFIG_MEMORY in powerpc/configs


1.  driver/memory:Move Freescale IFC driver to a common driver
http://patchwork.ozlabs.org/patch/315531/

2. powerpc/config: Enable memory driver
http://patchwork.ozlabs.org/patch/315532/

Regards,
Prabhakar





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[PATCH 2/2][v8] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 changes for v5:
- Rebased to branch next of 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 Changes for v6: Sending as it is
 Changes for v7: Sending as it is
 Changes for v8: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..087d437 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508dd..25b03f8 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index 83d3550..cba638c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -216,6 +216,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4b68629..e315b8a 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -217,6 +217,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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[PATCH 1/2][v8] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

 Also remove module_platform_driver() and  instead call
 platform_driver_register() from subsys_initcall() to make sure this module
 has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Branch next

Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

Changes for v5: 
- Moved powerpc/Kconfig option to driver/memory

Changes for v6:
- Update Kconfig details

Changes for v7:
- Update Kconfig

Changes for v8:
- Update Kconfig help

 .../{powerpc = memory-controllers}/fsl/ifc.txt|0
 arch/powerpc/Kconfig   |4 
 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Kconfig |8 
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 8 files changed, 16 insertions(+), 8 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a5e5d2e..00edd29 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -734,10 +734,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
-config FSL_IFC
-   bool
-depends on FSL_SOC
-
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac90..afbcc37 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db..57721ed 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,12 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
 
+config FSL_IFC
+   bool Freescale Integrated Flash Controller
+   depends on FSL_SOC
+   help
+ This driver is for the Integrated Flash Controller(IFC) module
+ available in Freescale SoCs. This controller allows to handle
+ devices such as NOR, NAND, FPGA and ASIC etc.
+
 endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 969d923..f2bf25c 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index fbc885b..3d5d792 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -29,8 +29,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -298,7 +298,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver

[PATCH 1/2][v7] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

 Also remove module_platform_driver() and  instead call
 platform_driver_register() from subsys_initcall() to make sure this module
 has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Branch next

Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

Changes for v5: 
- Moved powerpc/Kconfig option to driver/memory

Changes for v6:
- Update Kconfig details

Changes for v7:
- Update Kconfig

 .../{powerpc = memory-controllers}/fsl/ifc.txt|0
 arch/powerpc/Kconfig   |4 
 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Kconfig |8 
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 8 files changed, 16 insertions(+), 8 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6ca5d5c..3f868f5 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -728,10 +728,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
-config FSL_IFC
-   bool
-depends on FSL_SOC
-
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac90..afbcc37 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db..3176866 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,12 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
 
+config FSL_IFC
+   bool Freescale Integrated Flash Controller
+   depends on FSL_SOC
+   help
+ This driver is for the Integrated Flash Controller Controller(IFC)
+ module available in Freescale SoCs. This controller allows to handle 
flash
+ devices such as NOR, NAND, FPGA and ASIC etc
+
 endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 969d923..f2bf25c 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index fbc885b..3d5d792 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -29,8 +29,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -298,7 +298,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver);
+}
+subsys_initcall(fsl_ifc_init

[PATCH 2/2][v7] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 changes for v5:
- Rebased to branch next of 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 Changes for v6: Sending as it is
 Changes for v7: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..087d437 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508dd..25b03f8 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index 83d3550..cba638c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -216,6 +216,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4b68629..e315b8a 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -217,6 +217,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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[PATCH 1/2][v9] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 
 Changes for v6: Updated branch of creation 
 Changes for v7: Incororated Scott's commetns
- Create patch set
- remove whitespace
- Removed l2switch. It will be added later
 Changes for v8: Incorporated Scott's comments
- Added comment line in T1042si-post.dtsi
- removed extra lines
 Changes for v9:
- updated clock node as per new bindings
- removed extra line
- added dma node

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  433 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   37 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  104 +++
 3 files changed, 574 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..fa1f32a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,433 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either

[PATCH 2/2][v9] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented.
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 Changes for v6: Updated depedencies
 Changes for v7: Incororated Scott's commetns
- Create patch set
 Changes for v8: Sending as it is
 Changes for v9:
- removed partitions
- updated FPGA node
- Fix PCIe range fields

 arch/powerpc/boot/dts/t1040qds.dts|   46 +++
 arch/powerpc/boot/dts/t1042qds.dts|   46 +++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  165 +
 arch/powerpc/platforms/85xx/Kconfig   |2 +-
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 5 files changed, 262 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

[PATCH 1/2][v6] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

 Also remove module_platform_driver() and  instead call
 platform_driver_register() from subsys_initcall() to make sure this module
 has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Branch next

Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

Changes for v5: 
- Moved powerpc/Kconfig option to driver/memory

Changes for v6:
- Update Kconfig details

 .../{powerpc = memory-controllers}/fsl/ifc.txt|0
 arch/powerpc/Kconfig   |4 
 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Kconfig |9 +
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 8 files changed, 17 insertions(+), 8 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index fa39517..91dc43c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -727,10 +727,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
-config FSL_IFC
-   bool
-depends on FSL_SOC
-
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac90..afbcc37 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db..555d26f 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,13 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
 
+config FSL_IFC
+   bool Freescale Integrated Flash Controller
+   default y
+depends on FSL_SOC
+   help
+ This driver is for the Integrated Flash Controller Controller(IFC) 
+ module available in Freescale SoCs. This controller allows to handle 
flash
+ devices such as NOR, NAND, FPGA and ASIC etc
+
 endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 969d923..f2bf25c 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index fbc885b..3d5d792 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -29,8 +29,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -298,7 +298,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver);
+}
+subsys_initcall(fsl_ifc_init);
 
 MODULE_LICENSE(GPL

[PATCH 2/2][v6] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 changes for v5:
- Rebased to branch next of 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 Changes for v6: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..087d437 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508dd..25b03f8 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index 83d3550..cba638c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -216,6 +216,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4b68629..e315b8a 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -217,6 +217,7 @@ CONFIG_RTC_DRV_CMOS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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[PATCH] powerpc/config: Remove unnecssary CONFIG_FSL_IFC

[Prabhakar Kushwaha]

CONFIG_FSL_IFC gets enabled by Kconfig dependancies.
So remove unnecssary define from the defconfigs

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 arch/powerpc/configs/corenet64_smp_defconfig |1 -
 arch/powerpc/configs/mpc85xx_defconfig   |1 -
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 25b03f8..188e117 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -26,7 +26,6 @@ CONFIG_CORENET_GENERIC=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
-CONFIG_FSL_IFC=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index cba638c..3c44a53 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -49,7 +49,6 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index e315b8a..dd55ed6 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -52,7 +52,6 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
-- 
1.7.9.5



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Re: [PATCH] powerpc/configs: Enbale Freescale IFC controller

[Prabhakar Kushwaha]

On 1/18/2014 12:19 AM, Scott Wood wrote:

On Fri, 2014-01-17 at 11:02 -0600, Kumar Gala wrote:

On Jan 17, 2014, at 12:09 AM, Prabhakar Kushwaha prabha...@freescale.com 
wrote:


Currently IFC NAND driver is enabled in corenet32smp_defconfig. But IFC
controller is not enabled

So, Enable IFC controller in corenet32smp_defconfig.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
branch master

arch/powerpc/configs/corenet32_smp_defconfig |1 +
1 file changed, 1 insertion(+)

Shouldn’t the NAND driver get the IFC controller enabled by Kconfig 
dependancies?

Yes (by select, not dependencies).

Prabhakar, was there an actual problem you saw before?  Did you run
savedefconfig after making this change?

CONFIG_FSL_IFC isn't even user-selectable (though it probably should be,
as how else would it get enabled in the absence of NAND for catching NOR
errors?).



Thanks Kumar and Scott for reviewing this patch.

Yes, it should be enabled by Kconfig dependency.   as we have
config FSL_IFC
bool
depends on FSL_SOC

The only reason I changed this code because i wanted all powerpc/configs 
to be similar as they have CONFIG_FSL_IFC enabled by default.


arch/powerpc/configs/mpc85xx_smp_defconfig:54:CONFIG_FSL_IFC=y
arch/powerpc/configs/corenet64_smp_defconfig:29:CONFIG_FSL_IFC=y
arch/powerpc/configs/mpc85xx_defconfig:51:CONFIG_FSL_IFC=y

So either I should add in corenet32smp_defconfig to make similar to others.
or
remove from all.

I chose first option.

Regards,
Prabhakar





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Re: [PATCH 1/2][v3] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

On 1/17/2014 10:38 PM, Kumar Gala wrote:

On Jan 15, 2014, at 11:42 PM, Prabhakar Kushwaha prabha...@freescale.com 
wrote:


Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.

Also remove module_platform_driver() and  instead call
platform_driver_register() from subsys_initcall() to make sure this module
has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

.../{powerpc = memory-controllers}/fsl/ifc.txt|0
arch/powerpc/sysdev/Makefile   |1 -
drivers/memory/Makefile|1 +
{arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
drivers/mtd/nand/fsl_ifc_nand.c|2 +-
.../include/asm = include/linux}/fsl_ifc.h|0
6 files changed, 8 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

The Kconfig option for FSL_IFC should move into drivers/memory/Kconfig


Thanks Kumar for taking time and review this patch.

You are correct. I was checking sysdev/Kconfig  but it is defined in 
powerpc/Kconfig

I missed it :)

Regards,
Prabhakar



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[PATCH 1/2][v5] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

 Also remove module_platform_driver() and  instead call
 platform_driver_register() from subsys_initcall() to make sure this module
 has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

Changes for v5: 
- Moved powerpc/Kconfig option to driver/memory


 .../{powerpc = memory-controllers}/fsl/ifc.txt|0
 arch/powerpc/Kconfig   |4 
 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Kconfig |4 
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 8 files changed, 12 insertions(+), 8 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b44b52c..83fb8b3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -725,10 +725,6 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
-config FSL_IFC
-   bool
-depends on FSL_SOC
-
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac90..afbcc37 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 29a11db..b33bb0e 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -50,4 +50,8 @@ config TEGRA30_MC
  analysis, especially for IOMMU/SMMU(System Memory Management
  Unit) module.
 
+config FSL_IFC
+   bool
+depends on FSL_SOC
+
 endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 969d923..f2bf25c 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index d7fc722..135a950 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -30,8 +30,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -299,7 +299,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver);
+}
+subsys_initcall(fsl_ifc_init);
 
 MODULE_LICENSE(GPL);
 MODULE_AUTHOR(Freescale Semiconductor);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 4335577..865b323 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -30,7 +30,7 @@
 #include linux/mtd/nand.h
 #include linux/mtd/partitions.h
 #include linux/mtd/nand_ecc.h
-#include asm/fsl_ifc.h
+#include linux/fsl_ifc.h
 
 #define FSL_IFC_V1_1_0 0x0101
 #define

[PATCH 1/2][4] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

  Also remove module_platform_driver() and  instead call
  platform_driver_register() from subsys_initcall() to make sure this module
  has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes for v2:
- Move fsl_ifc in driver/memory

Changes for v3:
- move device tree bindings to memory

Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

 .../{powerpc = memory-controllers}/fsl/ifc.txt|0
 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 6 files changed, 8 insertions(+), 4 deletions(-)
 rename Documentation/devicetree/bindings/{powerpc = 
memory-controllers}/fsl/ifc.txt (100%)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99464a7..ec69532 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 9cce5d7..b494e5b 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,5 +6,6 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index d7fc722..135a950 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -30,8 +30,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -299,7 +299,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver);
+}
+subsys_initcall(fsl_ifc_init);
 
 MODULE_LICENSE(GPL);
 MODULE_AUTHOR(Freescale Semiconductor);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index f1f7f12..43d1a92 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -29,7 +29,7 @@
 #include linux/mtd/nand.h
 #include linux/mtd/partitions.h
 #include linux/mtd/nand_ecc.h
-#include asm/fsl_ifc.h
+#include linux/fsl_ifc.h
 
 #define FSL_IFC_V1_1_0 0x0101
 #define ERR_BYTE   0xFF /* Value returned for read
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/include/linux/fsl_ifc.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_ifc.h
rename to include/linux/fsl_ifc.h
-- 
1.7.9.5



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[PATCH 2/2][v4] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Rebased to 
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git


 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 60027c2..b717e5d 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -144,6 +144,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 6c8b020..efbe5a3 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index 5a58882..e215d4d 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -210,6 +210,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 165e6b3..7bc167c 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -210,6 +210,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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[PATCH] powerpc/configs: Enbale Freescale IFC controller

[Prabhakar Kushwaha]

Currently IFC NAND driver is enabled in corenet32smp_defconfig. But IFC
controller is not enabled

So, Enable IFC controller in corenet32smp_defconfig.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
 branch master

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 087d437..9578cbe9 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -25,6 +25,7 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
 CONFIG_CORENET_GENERIC=y
 CONFIG_HIGHMEM=y
+CONFIG_FSL_IFC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_KEXEC=y
-- 
1.7.9.5



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[PATCH 2/2][v2] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 changes for v2: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..087d437 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508dd..25b03f8 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index d2e0fab..87aad6d 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -213,6 +213,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4cb7b59..d5d6915 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -214,6 +214,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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[PATCH 1/2][v2] driver/memory:Move Freescale IFC driver to a common driver

[Prabhakar Kushwaha]

Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.

Also remove module_platform_driver() and  instead call
platform_driver_register() from subsys_initcall() to make sure this module
has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Changes for v2:
- Move fsl_ifc in driver/memory

 arch/powerpc/sysdev/Makefile   |1 -
 drivers/memory/Makefile|1 +
 {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c  |8 ++--
 drivers/mtd/nand/fsl_ifc_nand.c|2 +-
 .../include/asm = include/linux}/fsl_ifc.h|0
 5 files changed, 8 insertions(+), 4 deletions(-)
 rename {arch/powerpc/sysdev = drivers/memory}/fsl_ifc.c (98%)
 rename {arch/powerpc/include/asm = include/linux}/fsl_ifc.h (100%)

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac90..afbcc37 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)  += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)  += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)  += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)  += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)  += fsl_85xx_l2ctlr.o 
fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)  += simple_gpio.o
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 969d923..f2bf25c 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
 obj-$(CONFIG_OF)   += of_memory.o
 endif
 obj-$(CONFIG_TI_EMIF)  += emif.o
+obj-$(CONFIG_FSL_IFC)  += fsl_ifc.o
 obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)   += tegra20-mc.o
 obj-$(CONFIG_TEGRA30_MC)   += tegra30-mc.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/drivers/memory/fsl_ifc.c
similarity index 98%
rename from arch/powerpc/sysdev/fsl_ifc.c
rename to drivers/memory/fsl_ifc.c
index d7fc722..135a950 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
@@ -30,8 +30,8 @@
 #include linux/of.h
 #include linux/of_device.h
 #include linux/platform_device.h
+#include linux/fsl_ifc.h
 #include asm/prom.h
-#include asm/fsl_ifc.h
 
 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
@@ -299,7 +299,11 @@ static struct platform_driver fsl_ifc_ctrl_driver = {
.remove  = fsl_ifc_ctrl_remove,
 };
 
-module_platform_driver(fsl_ifc_ctrl_driver);
+static int __init fsl_ifc_init(void)
+{
+   return platform_driver_register(fsl_ifc_ctrl_driver);
+}
+subsys_initcall(fsl_ifc_init);
 
 MODULE_LICENSE(GPL);
 MODULE_AUTHOR(Freescale Semiconductor);
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 4335577..865b323 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -30,7 +30,7 @@
 #include linux/mtd/nand.h
 #include linux/mtd/partitions.h
 #include linux/mtd/nand_ecc.h
-#include asm/fsl_ifc.h
+#include linux/fsl_ifc.h
 
 #define FSL_IFC_V1_1_0 0x0101
 #define ERR_BYTE   0xFF /* Value returned for read
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/include/linux/fsl_ifc.h
similarity index 100%
rename from arch/powerpc/include/asm/fsl_ifc.h
rename to include/linux/fsl_ifc.h
-- 
1.7.9.5



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[PATCH 2/2][v3] powerpc/config: Enable memory driver

[Prabhakar Kushwaha]

As Freescale IFC controller has been moved to driver to driver/memory.

So enable memory driver in powerpc config

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Changes for v2: Sending as it is
 Changes for v3: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 arch/powerpc/configs/mpc85xx_defconfig   |1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig   |1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794d..087d437 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_UIO=y
 CONFIG_STAGING=y
+CONFIG_MEMORY=y
 CONFIG_VIRT_DRIVERS=y
 CONFIG_FSL_HV_MANAGER=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508dd..25b03f8 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -129,6 +129,7 @@ CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_ISO9660_FS=m
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index d2e0fab..87aad6d 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -213,6 +213,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4cb7b59..d5d6915 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -214,6 +214,7 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
+CONFIG_MEMORY=y
 # CONFIG_NET_DMA is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-- 
1.7.9.5



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Re: [PATCH 1/2][v8] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

On 10/29/2013 6:41 AM, Scott Wood wrote:

On Mon, 2013-10-21 at 09:07 +0530, Prabhakar Kushwaha wrote:

Hi Ben,

This patch is present in upstream review list from a long time.
There are no review comments.

So, I request you to pick this patch-set for powerpc.git repository.
http://patchwork.ozlabs.org/patch/280207/
http://patchwork.ozlabs.org/patch/280208/

This revision has only been posted for about 2.5 weeks.


+   #address-cells = 1;
+   #size-cells = 1;
+   pll0: pll0@800 {
+   #clock-cells = 1;
+   reg = 0x800 4;
+   compatible = fsl,qoriq-core-pll-2.0;
+   clocks = clockgen;
+   clock-output-names = pll0, pll0-div2, pll0-div4;
+   };
+   pll1: pll1@820 {
+   #clock-cells = 1;
+   reg = 0x820 4;
+   compatible = fsl,qoriq-core-pll-2.0;
+   clocks = clockgen;
+   clock-output-names = pll1, pll1-div2, pll1-div4;
+   };
+   mux0: mux0@0 {
+   #clock-cells = 0;
+   reg = 0x0 4;
+   compatible = fsl,core-mux-clock;
+   clocks = pll0 0, pll0 1, pll0 2,
+pll1 0, pll1 1, pll1 2;
+   clock-names = pll0_0, pll0_1, pll0_2,
+   pll1_0, pll1_1, pll1_2;
+   clock-output-names = cmux0;
+   };

The clock bindings are still under discussion.


I think, I should wait for clock bindings discussion :(


+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -0,0 +1,106 @@
+/*
+ * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ e5500_power_isa.dtsi
+
+/ {
+   compatible = fsl,T104x;

No wildcards in compatibles.  If your response is that this will get
overwritten anyway, then why have compatible here at all?


I will take care of this


+   crypto = crypto;
+
+   };

No blank lines before a closing brace.




I will take care of this.

Thanks,
Prabhakar



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Re: [PATCH 1/2][v8] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

Hi Ben,

This patch is present in upstream review list from a long time.
There are no review comments.

So, I request you to pick this patch-set for powerpc.git repository.
http://patchwork.ozlabs.org/patch/280207/
http://patchwork.ozlabs.org/patch/280208/

Regards,
Prabhakar


On 10/03/2013 09:14 AM, Prabhakar Kushwaha wrote:

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

  - Four e5500 cores, each with a private 256 KB L2 cache
  - 256 KB shared L3 CoreNet platform cache (CPC)
  - Interconnect CoreNet platform
  - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
  - Data Path Acceleration Architecture (DPAA) incorporating acceleration
  for the following functions:
 -  Packet parsing, classification, and distribution
 -  Queue management for scheduling, packet sequencing, and congestion
management
 -  Cryptography Acceleration (SEC 5.0)
 - RegEx Pattern Matching Acceleration (PME 2.2)
 - IEEE Std 1588 support
 - Hardware buffer management for buffer allocation and deallocation
  - Ethernet interfaces
 - Integrated 8-port Gigabit Ethernet switch (T1040 only)
 - Four 1 Gbps Ethernet controllers
  - Two RGMII interfaces or one RGMII and one MII interfaces
  - High speed peripheral interfaces
- Four PCI Express 2.0 controllers running at up to 5 GHz
- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- Upto two QSGMII interface
- Upto six SGMII interface supporting 1000 Mbps
- One SGMII interface supporting upto 2500 Mbps
  - Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
-  eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
- TDM interface
  - Multicore programmable interrupt controller (PIC)
  - Two 8-channel DMA engines
  - Single source clocking implementation
  - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
  Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
  Branch merge

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
 - update clock device tree node as per
   http://patchwork.ozlabs.org/patch/274134/
 - removed DMA node, It will be added later as per
   http://patchwork.ozlabs.org/patch/271238/
 - Updated display compatible field
  
  Changes for v3: Incorporated Scott's comments

- Updated soc compatible field
- updated clock compatible field

  Changes for v4: Sending as it is
  Changes for v5: Sending as it is
  Changes for v6: Updated branch of creation
  Changes for v7: Incororated Scott's commetns
 - Create patch set
 - remove whitespace
 - Removed l2switch. It will be added later
  Changes for v8: Incorporated Scott's comments
 - Added comment line in T1042si-post.dtsi
 - removed extra lines

  arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  418 +++
  arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   37 +++
  arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  106 +++
  3 files changed, 561 insertions(+)
  create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
  create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
  create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..9bf1c30
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,418 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used

[PATCH 2/2][v8] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented.
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 Changes for v6: Updated depedencies
 Changes for v7: Incororated Scott's commetns
- Create patch set
 changes for v8: Sending as it is
 
 This patch depends upon followng patches in mentioned order
 1) powerpc/b4qds: enable coreint
   http://patchwork.ozlabs.org/patch/274390/

 2) powerpc/85xx: introduce corenet_generic machine
   http://patchwork.ozlabs.org/patch/278067/

 3) powerpc/85xx: rename the corenet_ds.c to corenet_generic.c
   http://patchwork.ozlabs.org/patch/278072/

 4) powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
   http://patchwork.ozlabs.org/patch/278073/


 arch/powerpc/boot/dts/t1040qds.dts|   46 ++
 arch/powerpc/boot/dts/t1042qds.dts|   46 ++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  192 +
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 4 files changed, 288 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE

[PATCH 1/2][v8] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 
 Changes for v6: Updated branch of creation 
 Changes for v7: Incororated Scott's commetns
- Create patch set
- remove whitespace
- Removed l2switch. It will be added later
 Changes for v8: Incorporated Scott's comments
- Added comment line in T1042si-post.dtsi
- removed extra lines

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  418 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   37 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  106 +++
 3 files changed, 561 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..9bf1c30
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,418 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED

[PATCH 1/2][v7] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 
 Changes for v6: Updated branch of creation 
 Changes for v7: Incororated Scott's commetns
- Create patch set
- remove whitespace
- Removed l2switch. It will be added later

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  418 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   35 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  109 +++
 3 files changed, 562 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..9bf1c30
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,418 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

[PATCH 2/2][v7] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented. 
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 Changes for v6: Updated depedencies
 Changes for v7: Incororated Scott's commetns
- Create patch set
 
 This patch depends upon followng patches in mentioned order
 1) powerpc/b4qds: enable coreint
   http://patchwork.ozlabs.org/patch/274390/

 2) powerpc/85xx: introduce corenet_generic machine
   http://patchwork.ozlabs.org/patch/278067/

 3) powerpc/85xx: rename the corenet_ds.c to corenet_generic.c
   http://patchwork.ozlabs.org/patch/278072/

 4) powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
   http://patchwork.ozlabs.org/patch/278073/


 arch/powerpc/boot/dts/t1040qds.dts|   46 ++
 arch/powerpc/boot/dts/t1042qds.dts|   46 ++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  192 +
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 4 files changed, 288 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT

Re: [PATCH 1/2][v7] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

On 10/01/2013 01:17 AM, Scott Wood wrote:

On Mon, 2013-09-30 at 12:24 +0530, Prabhakar Kushwaha wrote:

 - Removed l2switch. It will be added later

Why?


I am not aware of bindings required for l2switch as we are not working 
on the driver.
Earlier I thought of putting a place holder. but as you suggested to put 
bindings in documentation.

It will be good if it is put by actual driver owner.




+sata@22 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+};
+/include/ qoriq-sata2-1.dtsi
+sata@221000 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+};

Whitespace


do we have any scripts which check for whitespace as checkpatch never 
give any warning/error.

it is a very silly mistake which I am doing continuously :(


+/include/ qoriq-sec5.0-0.dtsi
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
new file mode 100644
index 000..f286a50
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -0,0 +1,35 @@
+/*
+ * T1042 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t1040si-post.dtsi

Should at least have a comment indicating that eventually this should
hold the l2 switch node.


yes. Ideally it should be.
but if I put a comment then I believe this patch will not be completed. 
it will think as a RFC.

as I believe putting of TODO is generally for RFC patches.


+   aliases {
+   ccsr = soc;
+   dcsr = dcsr;
+
+   serial0 = serial0;
+   serial1 = serial1;
+   serial2 = serial2;
+   serial3 = serial3;
+   pci0 = pci0;
+   pci1 = pci1;
+   pci2 = pci2;
+   pci3 = pci3;
+   usb0 = usb0;
+   usb1 = usb1;
+   sdhc = sdhc;
+
+   crypto = crypto;
+
+   };
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;

[snip]

+   L2_4: l2-cache {
+   next-level-cache = cpc;
+   };
+   };
+
+   };
+};

Don't leave a blank line before a closing brace.

my mistake. I will take care.

Thanks,
Prabhakar


___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH 1/2][v7] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

On 10/01/2013 01:17 AM, Scott Wood wrote:

On Mon, 2013-09-30 at 12:24 +0530, Prabhakar Kushwaha wrote:

 - Removed l2switch. It will be added later

Why?


I am not aware of bindings required for l2switch as we are not working 
on the driver.
Earlier I thought of putting a place holder. but as you suggested to put 
bindings in documentation.

it will require proper discussion this may delay the base patch acceptance.
so It will be good if it is put by actual driver owner.


+sata@22 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+};
+/include/ qoriq-sata2-1.dtsi
+sata@221000 {
+   fsl,iommu-parent = pamu0;
+   fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+};

Whitespace


do we have any scripts which check for whitespace as checkpatch never 
give any warning/error.

it is a very silly mistake which I am doing continuously :(


+/include/ qoriq-sec5.0-0.dtsi
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
new file mode 100644
index 000..f286a50
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -0,0 +1,35 @@
+/*
+ * T1042 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t1040si-post.dtsi

Should at least have a comment indicating that eventually this should
hold the l2 switch node.


yes. Ideally it should be.
but if i put a comment then I believe this patch will not be completed. 
it will think as a RFC.

as I believe putting of TODO is generally for RFC patches.

should I put comment without TODO?


+   aliases {
+   ccsr = soc;
+   dcsr = dcsr;
+
+   serial0 = serial0;
+   serial1 = serial1;
+   serial2 = serial2;
+   serial3 = serial3;
+   pci0 = pci0;
+   pci1 = pci1;
+   pci2 = pci2;
+   pci3 = pci3;
+   usb0 = usb0;
+   usb1 = usb1;
+   sdhc = sdhc;
+
+   crypto = crypto;
+
+   };
+
+   cpus {
+   #address-cells = 1;
+   #size-cells = 0;

[snip]

+   L2_4: l2-cache {
+   next-level-cache = cpc;
+   };
+   };
+
+   };
+};

Don't leave a blank line before a closing brace.



   


My mistake. I will take care.

thanks,
Prabhakar



___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH][v5] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented. 
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 
 This patch depends upon followng patches in mentioned order
 1) powerpc/b4qds: enable coreint
   http://patchwork.ozlabs.org/patch/274390/

 2) powerpc/85xx: introduce corenet_generic machine
   http://patchwork.ozlabs.org/patch/277341/

 3) powerpc/85xx: rename the corenet_ds.c to corenet_generic.c
   http://patchwork.ozlabs.org/patch/277342/

 4) powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
   http://patchwork.ozlabs.org/patch/277343/


 arch/powerpc/boot/dts/t1040qds.dts|   46 ++
 arch/powerpc/boot/dts/t1042qds.dts|   46 ++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  192 +
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 4 files changed, 288 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT

[PATCH][v5] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  423 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   41 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  109 +++
 3 files changed, 573 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..b16b528
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,423 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL

[PATCH][v6] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented. 
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description
 Changes for v5: Incorporated Scott's comments
- Ported on top of Kevin's patch
 Changes for v6: Updated depedencies
 
 This patch depends upon followng patches in mentioned order
 1) powerpc/b4qds: enable coreint
   http://patchwork.ozlabs.org/patch/274390/

 2) powerpc/85xx: introduce corenet_generic machine
   http://patchwork.ozlabs.org/patch/278067/

 3) powerpc/85xx: rename the corenet_ds.c to corenet_generic.c
   http://patchwork.ozlabs.org/patch/278072/

 4) powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
   http://patchwork.ozlabs.org/patch/278073/


 arch/powerpc/boot/dts/t1040qds.dts|   46 ++
 arch/powerpc/boot/dts/t1042qds.dts|   46 ++
 arch/powerpc/boot/dts/t104xqds.dtsi   |  192 +
 arch/powerpc/platforms/85xx/corenet_generic.c |4 +
 4 files changed, 288 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING

[PATCH][v6] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch merge

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 
 Changes for v5: Sending as it is 
 Changes for v6: Updated branch of creation 

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  423 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   41 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  109 +++
 3 files changed, 573 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..b16b528
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,423 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor

[PATCH] dts/c293pcie: Add range field for IFC NAND

[Prabhakar Kushwaha]

C290PCIe has NAND flash present on IFC Chip Select(CS) 1.

So Add ranges field for NAND flash on CS1.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 branch next

 arch/powerpc/boot/dts/c293pcie.dts |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/boot/dts/c293pcie.dts 
b/arch/powerpc/boot/dts/c293pcie.dts
index 1238bda..6681cc2 100644
--- a/arch/powerpc/boot/dts/c293pcie.dts
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -45,6 +45,7 @@
ifc: ifc@fffe1e000 {
reg = 0xf 0xffe1e000 0 0x2000;
ranges = 0x0 0x0 0xf 0xec00 0x0400
+ 0x1 0x0 0xf 0xff80 0x0001
  0x2 0x0 0xf 0xffdf 0x0001;
 
};
-- 
1.7.9.5



___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH][v4] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 Changes for v4: Sending as it is 

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  423 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   41 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  109 +++
 3 files changed, 573 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..b16b528
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,423 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

[PATCH 1/2][v4] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

Add T104xQDS support in Kconfig and Makefile. Also create device tree.
Following features are currently not implmented. 
  - SerDes: Aurora
  - IFC: GASIC, Promjet
  - QIXIS
  - Ethernet
  - DIU
  - power supplies management
  - ProfiBus

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 
 Changes for v3: Sending as it is
 Changes for v4: Updated description

 arch/powerpc/boot/dts/t1040qds.dts  |   46 
 arch/powerpc/boot/dts/t1042qds.dts  |   46 
 arch/powerpc/boot/dts/t104xqds.dtsi |  192 +++
 arch/powerpc/platforms/85xx/Kconfig |   20 
 arch/powerpc/platforms/85xx/Makefile|1 +
 arch/powerpc/platforms/85xx/t104x_qds.c |  118 +++
 6 files changed, 423 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/t104x_qds.c

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t104xsi-pre.dtsi
+/include

[PATCH 2/2][v4] powerpc/configs: Enable T1040QDS by default in corenet

[Prabhakar Kushwaha]

T1040 supports both 32  64 bit kernel.
so enable T1040QDS by default in the config files.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is
 Changes for v3: Sending as it is
 Changes for v4: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 3dfab4c..19d1d31 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -28,6 +28,7 @@ CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index fa94fb3..d23ee10 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -24,6 +24,7 @@ CONFIG_MAC_PARTITION=y
 CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
-- 
1.7.9.5



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Re: [PATCH 1/2][v3] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

On 09/20/2013 08:38 AM, Timur Tabi wrote:

Kushwaha Prabhakar-B32579 wrote:
My primary object is to put base patch in Linux. once it done other 
things can be enabled one by one.


Any features which are not enabled must be specified in the patch 
description.  The patch says that the board supports DIU, but the code 
doesn't, so that's misleading.



Also, I am not familiar with DIU driver:(.


I can help you with the DIU driver.

shall I remove the DIU node, and  while adding support of DIU, all 
modification will be sent.


I think it should be okay to leave the DIU node.  I think the kernel 
will crash if you try to enable a DIU console (video= on the kernel 
command line), but I think it's okay to ignore that for the moment.




Got it.
I think patch set is OK for now. No need to send v4.

DIU support will be added later.

Regards,
Prabhakar




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[PATCH][v3] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

Changes for v2: Incorporated Scott's comments
- Update t1040si-post.dtsi
- update clock device tree node as per
  http://patchwork.ozlabs.org/patch/274134/
- removed DMA node, It will be added later as per
  http://patchwork.ozlabs.org/patch/271238/
- Updated display compatible field
 
 Changes for v3: Incorporated Scott's comments
   - Updated soc compatible field
   - updated clock compatible field

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  423 +++
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |   41 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  109 +++
 3 files changed, 573 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..b16b528
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,423 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING

[PATCH 2/2][v3] powerpc/configs: Enable T1040QDS by default in corenet

[Prabhakar Kushwaha]

T1040 supports both 32  64 bit kernel.
so enable T1040QDS by default in the config files.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is
 Changes for v3: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 3dfab4c..19d1d31 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -28,6 +28,7 @@ CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index fa94fb3..d23ee10 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -24,6 +24,7 @@ CONFIG_MAC_PARTITION=y
 CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
-- 
1.7.9.5



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[PATCH][v2] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

 Add T104xQDS support in Kconfig and Makefile. Also create device tree.

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Incorporated Scott's comments
- Created t104xqds.dtsi, both t1040qds  t1042qds include it
- Updated get_irq 

 arch/powerpc/boot/dts/t1040qds.dts  |   46 
 arch/powerpc/boot/dts/t1042qds.dts  |   46 
 arch/powerpc/boot/dts/t104xqds.dtsi |  192 +++
 arch/powerpc/platforms/85xx/Kconfig |   20 
 arch/powerpc/platforms/85xx/Makefile|1 +
 arch/powerpc/platforms/85xx/t104x_qds.c |  118 +++
 6 files changed, 423 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/boot/dts/t104xqds.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/t104x_qds.c

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..973c29c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t104xsi-pre.dtsi
+/include/ t104xqds.dtsi
+
+/ {
+   model = fsl,T1040QDS;
+   compatible = fsl,T1040QDS;
+   #address-cells = 2;
+   #size-cells = 2;
+   interrupt-parent = mpic;
+};
+
+/include/ fsl/t1040si-post.dtsi
diff --git a/arch/powerpc/boot/dts

[PATCH][v2] powerpc/configs: Enable T1040QDS by default in corenet

[Prabhakar Kushwaha]

T1040 supports both 32  64 bit kernel.
so enable T1040QDS by default in the config files.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
 Branch next

 Changes for v2: Sending as it is

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 3dfab4c..19d1d31 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -28,6 +28,7 @@ CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index fa94fb3..d23ee10 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -24,6 +24,7 @@ CONFIG_MAC_PARTITION=y
 CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
-- 
1.7.9.5



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[PATCH] powerpc/mpc85xx:Add initial device tree support of T104x

[Prabhakar Kushwaha]

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking  telecommunications.

T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.

The T1040/T1042 SoC includes the following function and features:

 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
-  Packet parsing, classification, and distribution
-  Queue management for scheduling, packet sequencing, and congestion
management
-  Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
 - Two RGMII interfaces or one RGMII and one MII interfaces
 - High speed peripheral interfaces
   - Four PCI Express 2.0 controllers running at up to 5 GHz
   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
   - Upto two QSGMII interface
   - Upto six SGMII interface supporting 1000 Mbps
   - One SGMII interface supporting upto 2500 Mbps
 - Additional peripheral interfaces
   - Two USB 2.0 controllers with integrated PHY
   - SD/eSDHC/eMMC
   -  eSPI controller
   - Four I2C controllers
   - Four UARTs
   - Four GPIO controllers
   - Integrated flash controller (IFC)
   - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
   - TDM interface
 - Multicore programmable interrupt controller (PIC)
 - Two 8-channel DMA engines
 - Single source clocking implementation
 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

TODO: Add noded for ethernet

 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  116 
 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi |  430 +++
 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi  |  111 +++
 3 files changed, 657 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000..6ef27fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,116 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t1042si-post.dtsi
+
+pci0

[PATCH 1/2] powerpc/fsl-booke: Add initial T104x_QDS board support

[Prabhakar Kushwaha]

 Add support for T104x board in board file t104x_qds.c, It is common for
 both T1040 and T1042 as they share same QDS board.

 T1040QDS board Overview
 ---
 - SERDES Connections, 8 lanes supporting:
  — PCI Express: supporting Gen 1 and Gen 2;
  — SGMII
  — QSGMII
  — SATA 2.0
  — Aurora debug with dedicated connectors (T1040 only)
 - DDR Controller
 - Supports rates of up to 1600 MHz data-rate
 - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
 -IFC/Local Bus
 - NAND flash: 8-bit, async, up to 2GB.
 - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
 - GASIC: Simple (minimal) target within Qixis FPGA
 - PromJET rapid memory download support
 - Ethernet
 - Two on-board RGMII 10/100/1G ethernet ports.
 - PHY #0 remains powered up during deep-sleep (T1040 only)
 - QIXIS System Logic FPGA
 - Clocks
 - System and DDR clock (SYSCLK, “DDRCLK”)
 - SERDES clocks
 - Power Supplies
 - Video
 - DIU supports video at up to 1280x1024x32bpp
 - USB
 - Supports two USB 2.0 ports with integrated PHYs
 — Two type A ports with 5V@1.5A per port.
 — Second port can be converted to OTG mini-AB
 - SDHC
 - SDHC port connects directly to an adapter card slot, featuring:
 - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
 — Supporting eMMC memory devices
 - SPI
-  On-board support of 3 different devices and sizes
 - Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports

 Add T104xQDS support in Kconfig and Makefile. Also create device tree.

Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

TODO: Add noded for ethernet and board stuff

 arch/powerpc/boot/dts/t1040qds.dts  |  201 +++
 arch/powerpc/boot/dts/t1042qds.dts  |  201 +++
 arch/powerpc/platforms/85xx/Kconfig |   20 +++
 arch/powerpc/platforms/85xx/Makefile|1 +
 arch/powerpc/platforms/85xx/t104x_qds.c |  102 
 5 files changed, 525 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/t1040qds.dts
 create mode 100644 arch/powerpc/boot/dts/t1042qds.dts
 create mode 100644 arch/powerpc/platforms/85xx/t104x_qds.c

diff --git a/arch/powerpc/boot/dts/t1040qds.dts 
b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000..cea5632
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,201 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t104xsi-pre.dtsi
+
+/ {
+   model = fsl,T1040QDS;
+   compatible = fsl,T1040QDS;
+   #address-cells = 2;
+   #size-cells = 2;
+   interrupt-parent = mpic;
+
+   aliases {
+/* TODO */
+   };
+
+   ifc: localbus@ffe124000 {
+   reg = 0xf 0xfe124000 0 0x2000;
+   ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf

[PATCH 2/2] powerpc/configs: Enable T1040QDS by default in corenet

[Prabhakar Kushwaha]

T1040 supports both 32  64 bit kernel.
so enable T1040QDS by default in the config files.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git

 arch/powerpc/configs/corenet32_smp_defconfig |1 +
 arch/powerpc/configs/corenet64_smp_defconfig |1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/powerpc/configs/corenet32_smp_defconfig 
b/arch/powerpc/configs/corenet32_smp_defconfig
index 60027c2..6e71494 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -28,6 +28,7 @@ CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 6c8b020..6bfb82b 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -24,6 +24,7 @@ CONFIG_MAC_PARTITION=y
 CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T104x_QDS=y
 CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
-- 
1.7.9.5



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[PATCH] powerpc: add CONFIG(s) require for using flash controller

[Prabhakar Kushwaha]

Add CONFIG(s) required for NAND and NOR flash controller usage.
It defines MTD, Jffs2 and UBIFS file system required for controllers.

It also enables IFC controller

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
 branch next

 arch/powerpc/configs/corenet64_smp_defconfig |   35 +-
 arch/powerpc/configs/mpc85xx_defconfig   |   31 +++
 arch/powerpc/configs/mpc85xx_smp_defconfig   |   31 +++
 3 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig 
b/arch/powerpc/configs/corenet64_smp_defconfig
index 36a5c41..1c6eb66 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -26,6 +26,7 @@ CONFIG_P5040_DS=y
 CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
+CONFIG_FSL_IFC=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -58,16 +59,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -122,7 +140,16 @@ CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
@@ -130,6 +157,12 @@ CONFIG_NFSD=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
 CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig 
b/arch/powerpc/configs/mpc85xx_defconfig
index e12146f..37812b4 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -47,6 +47,7 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -78,18 +79,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_FTL=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
@@ -207,6 +223,15 @@ CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
@@ -225,6 +250,12 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig 
b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 8d00ea5b..7fc3e6f 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -50,6 +50,7 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -81,18 +82,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y

[PATCH] driver/mtd/IFC:Wait tWB time, poll R/B before command execution

[Prabhakar Kushwaha]

IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.

NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Hemant Nautiyal hemant.nauti...@freescale.com
---
 Based upon git://git.infradead.org/linux-mtd.git branch master

 drivers/mtd/nand/fsl_ifc_nand.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8f0dd13..7e5b17c 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -382,7 +382,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned 
int command,
timing = IFC_FIR_OP_RBCD;
 
out_be32(ifc-ifc_nand.nand_fir0,
-   (IFC_FIR_OP_CMD0  IFC_NAND_FIR0_OP0_SHIFT) |
+   (IFC_FIR_OP_CW0  IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA   IFC_NAND_FIR0_OP1_SHIFT) |
(timing  IFC_NAND_FIR0_OP2_SHIFT));
out_be32(ifc-ifc_nand.nand_fcr0,
@@ -785,7 +785,7 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 
/* READID */
out_be32(ifc-ifc_nand.nand_fir0,
-   (IFC_FIR_OP_CMD0  IFC_NAND_FIR0_OP0_SHIFT) |
+   (IFC_FIR_OP_CW0  IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA   IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RB  IFC_NAND_FIR0_OP2_SHIFT));
out_be32(ifc-ifc_nand.nand_fcr0,
-- 
1.7.9.5



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Re: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any write

[Prabhakar Kushwaha]

On 09/13/2012 06:23 PM, Kumar Gala wrote:

On Sep 13, 2012, at 3:54 AM, Prabhakar Kushwaha wrote:


IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. byte select is not supported. Hence Read Modify Write is
implemented in IFC for any system side write into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.

Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use READID
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.infradead.org/linux-mtd.git branch master
The compilation of this patch depends upon following patch.
http://patchwork.ozlabs.org/patch/177893/
This patch is currently applied on 
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
branch next and status is Awaiting Upstream


drivers/mtd/nand/fsl_ifc_nand.c |   56 ++-
1 file changed, 55 insertions(+), 1 deletion(-)

If MTD maintainers ack, I'm happy to pull this in via PPC tree.


Hi  Artem,

Can you please ACK this patch so that it can be pulled via PPC tree.

Regards,
Prabhakar



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[PATCH] powerpc/mpc85xx:Update interrupt handling for IFC controller

[Prabhakar Kushwaha]

IFC may have one or two interrupts.  If two interrupt specifiers are present,
the first is the common interrupt (CM_EVTER_STAT), and the second is the NAND
interrupt (NAND_EVTER_STAT).
If there is only one, that interrupt reports both types of event.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
branch next 

 arch/powerpc/sysdev/fsl_ifc.c |   20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
index b31f19f..097cc9d2 100644
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -244,12 +244,6 @@ static int __devinit fsl_ifc_ctrl_probe(struct 
platform_device *dev)
/* get the nand machine irq */
fsl_ifc_ctrl_dev-nand_irq =
irq_of_parse_and_map(dev-dev.of_node, 1);
-   if (fsl_ifc_ctrl_dev-nand_irq == NO_IRQ) {
-   dev_err(dev-dev, failed to get irq resource 
-   for NAND Machine\n);
-   ret = -ENODEV;
-   goto err;
-   }
 
fsl_ifc_ctrl_dev-dev = dev-dev;
 
@@ -267,12 +261,14 @@ static int __devinit fsl_ifc_ctrl_probe(struct 
platform_device *dev)
goto err_irq;
}
 
-   ret = request_irq(fsl_ifc_ctrl_dev-nand_irq, fsl_ifc_nand_irq, 0,
- fsl-ifc-nand, fsl_ifc_ctrl_dev);
-   if (ret != 0) {
-   dev_err(dev-dev, failed to install irq (%d)\n,
-   fsl_ifc_ctrl_dev-nand_irq);
-   goto err_nandirq;
+   if (fsl_ifc_ctrl_dev-nand_irq) {
+   ret = request_irq(fsl_ifc_ctrl_dev-nand_irq, fsl_ifc_nand_irq,
+   0, fsl-ifc-nand, fsl_ifc_ctrl_dev);
+   if (ret != 0) {
+   dev_err(dev-dev, failed to install irq (%d)\n,
+   fsl_ifc_ctrl_dev-nand_irq);
+   goto err_nandirq;
+   }
}
 
return 0;
-- 
1.7.9.5



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[PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any write

[Prabhakar Kushwaha]

IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. byte select is not supported. Hence Read Modify Write is
implemented in IFC for any system side write into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.

Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use READID
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.infradead.org/linux-mtd.git branch master
 The compilation of this patch depends upon following patch.
 http://patchwork.ozlabs.org/patch/177893/
 This patch is currently applied on 
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
 branch next and status is Awaiting Upstream


 drivers/mtd/nand/fsl_ifc_nand.c |   56 ++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 1f71b54..3d15b92 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -31,6 +31,7 @@
 #include linux/mtd/nand_ecc.h
 #include asm/fsl_ifc.h
 
+#define FSL_IFC_V1_1_0 0x0101
 #define ERR_BYTE   0xFF /* Value returned for read
bytes when read failed  */
 #define IFC_TIMEOUT_MSECS  500  /* Maximum number of mSecs to wait
@@ -775,13 +776,62 @@ static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
return 0;
 }
 
+static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
+{
+   struct fsl_ifc_ctrl *ctrl = priv-ctrl;
+   struct fsl_ifc_regs __iomem *ifc = ctrl-regs;
+   uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
+   uint32_t cs = priv-bank;
+
+   /* Save CSOR and CSOR_ext */
+   csor = in_be32(ifc-csor_cs[cs].csor);
+   csor_ext = in_be32(ifc-csor_cs[cs].csor_ext);
+
+   /* chage PageSize 8K and SpareSize 1K*/
+   csor_8k = (csor  ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
+   out_be32(ifc-csor_cs[cs].csor, csor_8k);
+   out_be32(ifc-csor_cs[cs].csor_ext, 0x400);
+
+   /* READID */
+   out_be32(ifc-ifc_nand.nand_fir0,
+   (IFC_FIR_OP_CMD0  IFC_NAND_FIR0_OP0_SHIFT) |
+   (IFC_FIR_OP_UA   IFC_NAND_FIR0_OP1_SHIFT) |
+   (IFC_FIR_OP_RB  IFC_NAND_FIR0_OP2_SHIFT));
+   out_be32(ifc-ifc_nand.nand_fcr0,
+   NAND_CMD_READID  IFC_NAND_FCR0_CMD0_SHIFT);
+   out_be32(ifc-ifc_nand.row3, 0x0);
+
+   out_be32(ifc-ifc_nand.nand_fbcr, 0x0);
+
+   /* Program ROW0/COL0 */
+   out_be32(ifc-ifc_nand.row0, 0x0);
+   out_be32(ifc-ifc_nand.col0, 0x0);
+
+   /* set the chip select for NAND Transaction */
+   out_be32(ifc-ifc_nand.nand_csel, cs  IFC_NAND_CSEL_SHIFT);
+
+   /* start read seq */
+   out_be32(ifc-ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+
+   /* wait for command complete flag or timeout */
+   wait_event_timeout(ctrl-nand_wait, ctrl-nand_stat,
+  IFC_TIMEOUT_MSECS * HZ/1000);
+
+   if (ctrl-nand_stat != IFC_NAND_EVTER_STAT_OPC)
+   printk(KERN_ERR fsl-ifc: Failed to Initialise SRAM\n);
+
+   /* Restore CSOR and CSOR_ext */
+   out_be32(ifc-csor_cs[cs].csor, csor);
+   out_be32(ifc-csor_cs[cs].csor_ext, csor_ext);
+}
+
 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 {
struct fsl_ifc_ctrl *ctrl = priv-ctrl;
struct fsl_ifc_regs __iomem *ifc = ctrl-regs;
struct nand_chip *chip = priv-chip;
struct nand_ecclayout *layout;
-   u32 csor;
+   u32 csor, ver;
 
/* Fill in fsl_ifc_mtd structure */
priv-mtd.priv = chip;
@@ -875,6 +925,10 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
chip-ecc.mode = NAND_ECC_SOFT;
}
 
+   ver = in_be32(ifc-ifc_rev);
+   if (ver == FSL_IFC_V1_1_0)
+   fsl_ifc_sram_init(priv);
+
return 0;
 }
 
-- 
1.7.9.5



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[PATCH] powerpc:Update Integrated Flash controller device tree bindings

[Prabhakar Kushwaha]

Freescale's Integrated Flash controller (IFC) may have one or two
interrupts. In case of single interrupt line, it will cover all IFC
interrupts.

Update this information in IFC device tree bindings

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Branch next

 .../devicetree/bindings/powerpc/fsl/ifc.txt|9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
index 939a26d..88c7a26 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -12,9 +12,12 @@ Properties:
 - #size-cells : Either one or two, depending on how large each chipselect
 can be.
 - reg : Offset and length of the register set for the device
-- interrupts : IFC has two interrupts. The first one is the common
-   interrupt(CM_EVTER_STAT), and second is the NAND interrupt
-   (NAND_EVTER_STAT).
+- interrupts: IFC may have one or two interrupts.  If two interrupt
+  specifiers are present, the first is the common
+  interrupt (CM_EVTER_STAT), and the second is the NAND
+  interrupt (NAND_EVTER_STAT).  If there is only one,
+  that interrupt reports both types of event.
+
 
 - ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
-- 
1.7.9.5



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[PATCH] powerpc/mpc85xx:Add new ext fields to Integrated FLash Controller

[Prabhakar Kushwaha]

Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width. 
In case more than 32 bit address is used, the EXT registers should be set.

Add support of ext registers.

Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Branch next

 arch/powerpc/include/asm/fsl_ifc.h |   14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_ifc.h 
b/arch/powerpc/include/asm/fsl_ifc.h
index b955012..b8a4b9b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -768,22 +768,24 @@ struct fsl_ifc_gpcm {
  */
 struct fsl_ifc_regs {
__be32 ifc_rev;
-   u32 res1[0x3];
+   u32 res1[0x2];
struct {
+   __be32 cspr_ext;
__be32 cspr;
-   u32 res2[0x2];
+   u32 res2;
} cspr_cs[FSL_IFC_BANK_COUNT];
-   u32 res3[0x18];
+   u32 res3[0x19];
struct {
__be32 amask;
u32 res4[0x2];
} amask_cs[FSL_IFC_BANK_COUNT];
-   u32 res5[0x18];
+   u32 res5[0x17];
struct {
+   __be32 csor_ext;
__be32 csor;
-   u32 res6[0x2];
+   u32 res6;
} csor_cs[FSL_IFC_BANK_COUNT];
-   u32 res7[0x18];
+   u32 res7[0x19];
struct {
__be32 ftim[4];
u32 res8[0x8];
-- 
1.7.9.5



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[PATCH] driver/mtd: IFC NAND: Add support of ONFI NAND flash

[Prabhakar Kushwaha]

  - Fix NAND_CMD_READID command for ONFI detect.
  - Add NAND_CMD_PARAM command to read the ONFI parameter page.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Scott Wood scottw...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git 
 Branch master

 drivers/mtd/nand/fsl_ifc_nand.c |   22 --
 1 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index c30ac7b..4e7f31e 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -375,21 +375,31 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, 
unsigned int command,
 
return;
 
-   /* READID must read all 8 possible bytes */
case NAND_CMD_READID:
+   case NAND_CMD_PARAM: {
+   int timing = IFC_FIR_OP_RB;
+   if (command == NAND_CMD_PARAM)
+   timing = IFC_FIR_OP_RBCD;
+
out_be32(ifc-ifc_nand.nand_fir0,
(IFC_FIR_OP_CMD0  IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA   IFC_NAND_FIR0_OP1_SHIFT) |
-   (IFC_FIR_OP_RB  IFC_NAND_FIR0_OP2_SHIFT));
+   (timing  IFC_NAND_FIR0_OP2_SHIFT));
out_be32(ifc-ifc_nand.nand_fcr0,
-   NAND_CMD_READID  IFC_NAND_FCR0_CMD0_SHIFT);
-   /* 8 bytes for manuf, device and exts */
-   out_be32(ifc-ifc_nand.nand_fbcr, 8);
-   ifc_nand_ctrl-read_bytes = 8;
+   command  IFC_NAND_FCR0_CMD0_SHIFT);
+   out_be32(ifc-ifc_nand.row3, column);
+
+   /*
+* although currently it's 8 bytes for READID, we always read
+* the maximum 256 bytes(for PARAM)
+*/
+   out_be32(ifc-ifc_nand.nand_fbcr, 256);
+   ifc_nand_ctrl-read_bytes = 256;
 
set_addr(mtd, 0, 0, 0);
fsl_ifc_run_command(mtd);
return;
+   }
 
/* ERASE1 stores the block and page address */
case NAND_CMD_ERASE1:
-- 
1.7.5.4



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[PATCH][v2] powerpc/85xx:Add BSC9131 RDB Support

[Prabhakar Kushwaha]

BSC9131RDB is a Freescale reference design board for BSC9131 SoC.The BSC9131 is
integrated SoC that targets Femto base station market. It combines Power
Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
baseband acceleration processing elements.

The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte 
shared
  L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel 
Decoding/Encoding,
  Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel 
processing,
  and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
  Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix 
Inversion
  operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit 
with
  ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network 
acceleration
  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
  JESD207/three custom ADI RF interfaces (two dual port and one single port)
  and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
  communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 BSC9131RDB Overview
 --
 BSC9131 SoC
 1Gbyte DDR3 (on board DDR)
 128Mbyte 2K page size NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 USB-ULPI
 eTSEC1: Connected to RGMII PHY
 eTSEC2: Connected to RGMII PHY
 DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Akhil Goyal akhil.go...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Rajan Srivastava rajan.srivast...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Note:   Name of PSC9131 has been changed to BSC9131 because of new nomenclature
Please reject earlier patchpowerpc/85xx:Add PSC9131 RDB Support
  http://patchwork.ozlabs.org/patch/146349/

 Beased on http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
branch master

 Changes for v2: 
- Change board file name as bsc913x_rdb.c
- Removed all I2C's board device. A separate patch will be send.
- Combined SPI's 2 RFS partition into single RFS parition
- Added SEC/crypto node in dts

 arch/powerpc/boot/dts/bsc9131rdb.dts  |   34 +
 arch/powerpc/boot/dts/bsc9131rdb.dtsi |  142 ++
 arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi |  193 +
 arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi  |   59 
 arch/powerpc/platforms/85xx/Kconfig   |9 ++
 arch/powerpc/platforms/85xx/Makefile  |1 +
 arch/powerpc/platforms/85xx/bsc913x_rdb.c |   95 
 7 files changed, 533 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dts
 create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/bsc913x_rdb.c

diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dts 
b/arch/powerpc/boot/dts/bsc9131rdb.dts
new file mode 100644
index 000..e13d2d4
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dts
@@ -0,0 +1,34 @@
+/*
+ * BSC9131 RDB Device Tree Source
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation

[PATCH][v4] NAND Machine support for Integrated Flash Controller

[Prabhakar Kushwaha]

Integrated Flash Controller(IFC) can be used to hook NAND Flash
chips using NAND Flash Machine available on it.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Beased on http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
branch master

 Tested on P1010RDB

 Changes for v2: Ported IFC driver for linux-3.2.0-rc3 
- Use chip-bbt_options for BBT
- Use mtd_device_parse_register instead of old parse_mtd_partitions

  Changes for v3: Squashed following patch to make singe NAND driver patch
- mtd/nand:Fix wrong usage of is_blank() in fsl_ifc_run_command
http://patchwork.ozlabs.org/patch/136547/
- mtd/nand: Fix IFC driver to support 2K NAND page
http://patchwork.ozlabs.org/patch/135010/

  Changes for v4:
- fsl_ifc_run_command: handled wait_event_timeout timeout-return case
- Removed unused full_page variable
- fsl_ifc_read_page: Updated Error message
- fsl_ifc_nand_probe: removed possible memory leak for priv variable 


 drivers/mtd/nand/Kconfig|   10 +
 drivers/mtd/nand/Makefile   |1 +
 drivers/mtd/nand/fsl_ifc_nand.c | 1072 +++
 3 files changed, 1083 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_ifc_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index dd02792..2652bcc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -462,6 +462,16 @@ config MTD_NAND_FSL_ELBC
  Enabling this option will enable you to use this to control
  external NAND devices.
 
+config MTD_NAND_FSL_IFC
+   tristate NAND support for Freescale IFC controller
+   depends on MTD_NAND  FSL_SOC
+   select FSL_IFC
+   help
+ Various Freescale chips e.g P1010, include a NAND Flash machine
+ with built-in hardware ECC capabilities.
+ Enabling this option will enable you to use this to control
+ external NAND devices.
+
 config MTD_NAND_FSL_UPM
tristate Support for NAND on Freescale UPM
depends on PPC_83xx || PPC_85xx
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 618f4ba..19bc8cb 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MTD_ALAUDA)  += alauda.o
 obj-$(CONFIG_MTD_NAND_PASEMI)  += pasemi_nand.o
 obj-$(CONFIG_MTD_NAND_ORION)   += orion_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_ELBC)+= fsl_elbc_nand.o
+obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_MTD_NAND_SH_FLCTL)+= sh_flctl.o
 obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
new file mode 100644
index 000..c30ac7b
--- /dev/null
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -0,0 +1,1072 @@
+/*
+ * Freescale Integrated Flash Controller NAND driver
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include linux/module.h
+#include linux/types.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/mtd/mtd.h
+#include linux/mtd/nand.h
+#include linux/mtd/partitions.h
+#include linux/mtd/nand_ecc.h
+#include asm/fsl_ifc.h
+
+#define ERR_BYTE   0xFF /* Value returned for read
+   bytes when read failed  */
+#define IFC_TIMEOUT_MSECS  500  /* Maximum number of mSecs to wait
+   for IFC NAND Machine*/
+
+struct fsl_ifc_ctrl;
+
+/* mtd information per set */
+struct fsl_ifc_mtd {
+   struct mtd_info mtd;
+   struct nand_chip chip;
+   struct fsl_ifc_ctrl *ctrl;
+
+   struct device *dev;
+   int bank;   /* Chip select bank number  */
+   unsigned int bufnum_mask; /* bufnum = page

[PATCH] powerpc/85xx:Add BSC9131 RDB Support

[Prabhakar Kushwaha]

BSC9131RDB is a Freescale reference design board for BSC9131 SoC.The BSC9131 is
integrated SoC that targets Femto base station market. It combines Power
Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
baseband acceleration processing elements.

The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte 
shared
  L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel 
Decoding/Encoding,
  Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel 
processing,
  and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
  Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix 
Inversion
  operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit 
with
  ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network 
acceleration
  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
  JESD207/three custom ADI RF interfaces (two dual port and one single port)
  and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
  communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 BSC9131RDB Overview
 --
 BSC9131 SoC
 1Gbyte DDR3 (on board DDR)
 128Mbyte 2K page size NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 USB-ULPI
 eTSEC1: Connected to RGMII PHY
 eTSEC2: Connected to RGMII PHY
 DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Akhil Goyal akhil.go...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Rajan Srivastava rajan.srivast...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Note:   Name of PSC9131 has been changed to BSC9131 because of new nomenclature
Please reject earlier patchpowerpc/85xx:Add BSC9131 RDB Support
  http://patchwork.ozlabs.org/patch/146349/

 Beased on http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
branch master

 arch/powerpc/boot/dts/bsc9131rdb.dts  |   34 +
 arch/powerpc/boot/dts/bsc9131rdb.dtsi |  179 +
 arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi |  172 
 arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi  |   59 
 arch/powerpc/platforms/85xx/Kconfig   |9 ++
 arch/powerpc/platforms/85xx/Makefile  |1 +
 arch/powerpc/platforms/85xx/bsc913x_board.c   |   96 +
 7 files changed, 550 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dts
 create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/bsc913x_board.c

diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dts 
b/arch/powerpc/boot/dts/bsc9131rdb.dts
new file mode 100644
index 000..e13d2d4
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dts
@@ -0,0 +1,34 @@
+/*
+ * BSC9131 RDB Device Tree Source
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ fsl/bsc9131si-pre.dtsi
+
+/ {
+   model = fsl,bsc9131rdb;
+   compatible = fsl,bsc9131rdb;
+
+   memory {
+   device_type

[PATCH][v2] powerpc/85xx:Add PSC9131 RDB Support

[Prabhakar Kushwaha]

PSC9131RDB is a Freescale reference design board for PSC9131 SoC.The PSC9131 is
integrated SoC that targets Femto base station market. It combines Power
Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
baseband acceleration processing elements.

The PSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte 
shared
  L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel 
Decoding/Encoding,
  Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel 
processing,
  and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
  Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix 
Inversion
  operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit 
with
  ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network 
acceleration
  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
  JESD207/three custom ADI RF interfaces (two dual port and one single port)
  and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
  communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 PSC9131RDB Overview
 --
 PSC9131 SoC
 1Gbyte DDR3 (on board DDR)
 128Mbyte 2K page size NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 USB-ULPI
 eTSEC1: Connected to RGMII PHY
 eTSEC2: Connected to RGMII PHY
 DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Akhil Goyal akhil.go...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Rajan Srivastava rajan.srivast...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Developed on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
 Branch master

 Changes for v2:
  - Used fsl/qoriq-dma-0.dtsi
  - Removed BUG_ON()
  - used pr_err instead of printk
  - removed all printk
  - updated dts for ifc and ethernet
  - removed unwanted node properties

 arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi |  172 +++
 arch/powerpc/boot/dts/fsl/psc9131si-pre.dtsi  |   59 
 arch/powerpc/boot/dts/psc9131rdb.dts  |   34 +
 arch/powerpc/boot/dts/psc9131rdb.dtsi |  186 +
 arch/powerpc/platforms/85xx/Kconfig   |   14 ++
 arch/powerpc/platforms/85xx/Makefile  |1 +
 arch/powerpc/platforms/85xx/psc913x_board.c   |   96 +
 7 files changed, 562 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/psc9131si-pre.dtsi
 create mode 100644 arch/powerpc/boot/dts/psc9131rdb.dts
 create mode 100644 arch/powerpc/boot/dts/psc9131rdb.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/psc913x_board.c

diff --git a/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
new file mode 100644
index 000..777da97
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
@@ -0,0 +1,172 @@
+/*
+ * PSC9131 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must

[PATCH] powerpc/85xx:Add PSC9131 RDB Support

[Prabhakar Kushwaha]

PSC9131RDB is a Freescale reference design board for PSC9131 SoC.The PSC9131 is
integrated SoC that targets Femto base station market. It combines Power
Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
baseband acceleration processing elements.

-The PSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte 
shared
  L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
  Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel 
Decoding/Encoding,
  Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel 
processing,
  and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
  Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix 
Inversion
  operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit 
with
  ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network 
acceleration
  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
  JESD207/three custom ADI RF interfaces (two dual port and one single port)
  and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
  communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 PSC9131RDB Overview
 --
 PSC9131 SoC
 1Gbyte DDR3 (on board DDR)
 128Mbyte 2K page size NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 USB-ULPI
 eTSEC1: Connected to RGMII PHY
 eTSEC2: Connected to RGMII PHY
 DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
Signed-off-by: Akhil Goyal akhil.go...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Rajan Srivastava rajan.srivast...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Applied on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
branch next

 arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi |  220 +
 arch/powerpc/boot/dts/fsl/psc9131si-pre.dtsi  |   59 +++
 arch/powerpc/boot/dts/psc9131rdb.dts  |   34 
 arch/powerpc/boot/dts/psc9131rdb.dtsi |  187 +
 arch/powerpc/platforms/85xx/Kconfig   |   13 ++
 arch/powerpc/platforms/85xx/Makefile  |1 +
 arch/powerpc/platforms/85xx/psc913x_board.c   |   99 +++
 7 files changed, 613 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/psc9131si-pre.dtsi
 create mode 100644 arch/powerpc/boot/dts/psc9131rdb.dts
 create mode 100644 arch/powerpc/boot/dts/psc9131rdb.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/psc913x_board.c

diff --git a/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
new file mode 100644
index 000..878126e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/psc9131si-post.dtsi
@@ -0,0 +1,220 @@
+/*
+ * PSC9131 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor

[PATCH][v3] NAND Machine support for Integrated Flash Controller

[Prabhakar Kushwaha]

Integrated Flash Controller(IFC) can be used to hook NAND Flash
chips using NAND Flash Machine available on it.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Tested on P1010RDB

 Changes for v2: Ported IFC driver for linux-3.2.0-rc3 
- Use chip-bbt_options for BBT
- Use mtd_device_parse_register instead of old parse_mtd_partitions

  Changes for v3: Squashed following patch to make singe NAND driver patch
- mtd/nand:Fix wrong usage of is_blank() in fsl_ifc_run_command
http://patchwork.ozlabs.org/patch/136547/
- mtd/nand: Fix IFC driver to support 2K NAND page
http://patchwork.ozlabs.org/patch/135010/

 drivers/mtd/nand/Kconfig|   10 +
 drivers/mtd/nand/Makefile   |1 +
 drivers/mtd/nand/fsl_ifc_nand.c | 1071 +++
 3 files changed, 1082 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_ifc_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index cce7b70..2fff5c7 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -463,6 +463,16 @@ config MTD_NAND_FSL_ELBC
  Enabling this option will enable you to use this to control
  external NAND devices.
 
+config MTD_NAND_FSL_IFC
+   tristate NAND support for Freescale IFC controller
+   depends on MTD_NAND  FSL_SOC
+   select FSL_IFC
+   help
+ Various Freescale chips e.g P1010, include a NAND Flash machine
+ with built-in hardware ECC capabilities.
+ Enabling this option will enable you to use this to control
+ external NAND devices.
+
 config MTD_NAND_FSL_UPM
tristate Support for NAND on Freescale UPM
depends on PPC_83xx || PPC_85xx
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 618f4ba..19bc8cb 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MTD_ALAUDA)  += alauda.o
 obj-$(CONFIG_MTD_NAND_PASEMI)  += pasemi_nand.o
 obj-$(CONFIG_MTD_NAND_ORION)   += orion_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_ELBC)+= fsl_elbc_nand.o
+obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_MTD_NAND_SH_FLCTL)+= sh_flctl.o
 obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
new file mode 100644
index 000..33b55d2
--- /dev/null
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -0,0 +1,1071 @@
+/*
+ * Freescale Integrated Flash Controller NAND driver
+ *
+ * Copyright 2011,2012 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include linux/module.h
+#include linux/types.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/mtd/mtd.h
+#include linux/mtd/nand.h
+#include linux/mtd/partitions.h
+#include linux/mtd/nand_ecc.h
+#include asm/fsl_ifc.h
+
+#define ERR_BYTE   0xFF /* Value returned for read
+   bytes when read failed  */
+#define IFC_TIMEOUT_MSECS  500  /* Maximum number of mSecs to wait
+   for IFC NAND Machine*/
+
+struct fsl_ifc_ctrl;
+
+/* mtd information per set */
+struct fsl_ifc_mtd {
+   struct mtd_info mtd;
+   struct nand_chip chip;
+   struct fsl_ifc_ctrl *ctrl;
+
+   struct device *dev;
+   int bank;   /* Chip select bank number  */
+   unsigned int bufnum_mask; /* bufnum = page  bufnum_mask */
+   u8 __iomem *vbase;  /* Chip select base virtual address */
+};
+
+/* overview of the fsl ifc controller */
+struct fsl_ifc_nand_ctrl {
+   struct nand_hw_control controller;
+   struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
+
+   u8

[PATCH] mtd/nand:Fix wrong usage of is_blank() in fsl_ifc_run_command

[Prabhakar Kushwaha]

Freescale IFC NAND Machine calculates ECC on 512byte sector and same is used in
fsl_ifc_run_command() during ECC status verification. Also this sector is passed
to is_blank() for blank checking. It is wrong at first place because
is_blank()'s implementation checks for Page size and OOB area size. 
is_blank() should be called per page for main and OOB area verification.

Variables name are redefined to avoid confusion between buffer and ecc sector.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)

 Tested on P1010RDB

 This patch is created on top of IFC driver patch (already floated in mailing
 list). Please find their link:
 http://patchwork.ozlabs.org/patch/133315/
 http://patchwork.ozlabs.org/patch/133316/

 This patch is replacement of my earlier patch
  mtd/nand:Fix wrong address read in is_blank()

 drivers/mtd/nand/fsl_ifc_nand.c |   52 +--
 1 files changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 854fe95..33b55d2 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -1,7 +1,7 @@
 /*
  * Freescale Integrated Flash Controller NAND driver
  *
- * Copyright 2011 Freescale Semiconductor, Inc
+ * Copyright 2011,2012 Freescale Semiconductor, Inc
  *
  * Author: Dipen Dudhat dipen.dud...@freescale.com
  *
@@ -216,24 +216,11 @@ static int check_read_ecc(struct mtd_info *mtd, struct 
fsl_ifc_ctrl *ctrl,
  u32 *eccstat, unsigned int bufnum)
 {
u32 reg = eccstat[bufnum / 4];
-   int errors = (reg  ((3 - bufnum % 4) * 8))  15;
+   int errors;
 
-   if (errors == 15) { /* uncorrectable */
-   /* Blank pages fail hw ECC checks */
-   if (is_blank(mtd, bufnum))
-   return 1;
+   errors = (reg  ((3 - bufnum % 4) * 8))  15;
 
-   /*
-* We disable ECCER reporting in hardware due to
-* erratum IFC-A002770 -- so report it now if we
-* see an uncorrectable error in ECCSTAT.
-*/
-   ctrl-nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
-   } else if (errors  0) {
-   mtd-ecc_stats.corrected += errors;
-   }
-
-   return 0;
+   return errors;
 }
 
 /*
@@ -273,16 +260,33 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
dev_err(priv-dev, NAND Flash Write Protect Error\n);
 
if (nctrl-eccread) {
-   int bufperpage = mtd-writesize / 512;
-   int bufnum = (nctrl-page  priv-bufnum_mask) * bufperpage;
-   int bufnum_end = bufnum + bufperpage - 1;
+   int errors;
+   int bufnum = nctrl-page  priv-bufnum_mask;
+   int sector = bufnum * chip-ecc.steps;
+   int sector_end = sector + chip-ecc.steps - 1;
 
-   for (i = bufnum / 4; i = bufnum_end / 4; i++)
+   for (i = sector / 4; i = sector_end / 4; i++)
eccstat[i] = in_be32(ifc-ifc_nand.nand_eccstat[i]);
 
-   for (i = bufnum; i = bufnum_end; i++) {
-   if (check_read_ecc(mtd, ctrl, eccstat, i))
+   for (i = sector; i = sector_end; i++) {
+   errors = check_read_ecc(mtd, ctrl, eccstat, i);
+
+   if (errors == 15) {
+   /*
+* Uncorrectable error.
+* OK only if the whole page is blank.
+*
+* We disable ECCER reporting due to...
+* erratum IFC-A002770 -- so report it now if we
+* see an uncorrectable error in ECCSTAT.
+*/
+   if (!is_blank(mtd, bufnum))
+   ctrl-nand_stat |=
+   IFC_NAND_EVTER_STAT_ECCER;
break;
+   }
+
+   mtd-ecc_stats.corrected += errors;
}
 
nctrl-eccread = 0;
-- 
1.7.5.4


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[PATCH 1/2][v2] mtd/nand:Fix wrong address read in is_blank()

[Prabhakar Kushwaha]

IFC NAND Machine calculates ECC on 512byte sector. Same is taken care in
fsl_ifc_run_command() while ECC status verification. Here buffer number is
calculated assuming 512byte sector and same is passed to is_blank.
However in is_blank() buffer address is calculated using mdt-writesize which is
wrong. It should be calculated on basis of ecc sector size.

Also, in fsl_ifc_run_command() bufferpage is calculated on the basis of ecc 
sector
size instead of hard coded value.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
  git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)

 This patch is created on top of IFC driver patch (already floated in mailing
 list). Please find their link:
 http://patchwork.ozlabs.org/patch/133315/
 http://patchwork.ozlabs.org/patch/133316/

 Tested on P1010RDB

 Changes for v2: Incorporated Scott's comments
- Updated copyright
- is_blank - works on ecc buffer block 
- check_read_ecc() - Calculate actual ecc buffer number

 drivers/mtd/nand/fsl_ifc_nand.c |   14 --
 1 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8475b88..c0529ea 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -1,7 +1,7 @@
 /*
  * Freescale Integrated Flash Controller NAND driver
  *
- * Copyright 2011 Freescale Semiconductor, Inc
+ * Copyright 2011,2012 Freescale Semiconductor, Inc
  *
  * Author: Dipen Dudhat dipen.dud...@freescale.com
  *
@@ -191,12 +191,12 @@ static int is_blank(struct mtd_info *mtd, unsigned int 
bufnum)
 {
struct nand_chip *chip = mtd-priv;
struct fsl_ifc_mtd *priv = chip-priv;
-   u8 __iomem *addr = priv-vbase + bufnum * (mtd-writesize * 2);
+   u8 __iomem *addr = priv-vbase + bufnum * chip-ecc.size;
u32 __iomem *mainarea = (u32 *)addr;
u8 __iomem *oob = addr + mtd-writesize;
int i;
 
-   for (i = 0; i  mtd-writesize / 4; i++) {
+   for (i = 0; i  chip-ecc.size / 4; i++) {
if (__raw_readl(mainarea[i]) != 0x)
return 0;
}
@@ -215,12 +215,15 @@ static int is_blank(struct mtd_info *mtd, unsigned int 
bufnum)
 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  u32 *eccstat, unsigned int bufnum)
 {
+   struct nand_chip *chip = mtd-priv;
+   int bufperpage = mtd-writesize / chip-ecc.size;
+   int eccbuf_num = bufnum + (bufnum / bufperpage) * bufperpage;
u32 reg = eccstat[bufnum / 4];
int errors = (reg  ((3 - bufnum % 4) * 8))  15;
 
if (errors == 15) { /* uncorrectable */
/* Blank pages fail hw ECC checks */
-   if (is_blank(mtd, bufnum))
+   if (is_blank(mtd, eccbuf_num))
return 1;
 
/*
@@ -273,7 +276,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
dev_err(priv-dev, NAND Flash Write Protect Error\n);
 
if (nctrl-eccread) {
-   int bufperpage = mtd-writesize / 512;
+   int bufperpage = mtd-writesize / chip-ecc.size;
int bufnum = (nctrl-page  priv-bufnum_mask) * bufperpage;
int bufnum_end = bufnum + bufperpage - 1;
 
-- 
1.7.5.4


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[PATCH 2/2][v2] mtd/nand: Fix IFC driver to support 2K NAND page

[Prabhakar Kushwaha]

1) OOB area should be updated irrespective of NAND page size. Earlier it was
updated only for 512byte NAND page.

2) During OOB update fbcr should be equal to OOB size.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)

 This patch is created on top of IFC driver patch (already floated in mailing
 list). Please find their link:
 http://patchwork.ozlabs.org/patch/133315/
 http://patchwork.ozlabs.org/patch/133316/

 Tested on P1010RDB

  Changes for v2: Incorporated Scott's comments
- Added missed NAND_CMD_READOOB
- Updated function as per Scott's advice

 drivers/mtd/nand/fsl_ifc_nand.c |   21 +
 1 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index c0529ea..52bd706d 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -440,22 +440,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, 
unsigned int command,
out_be32(ifc-ifc_nand.nand_fir1,
 (IFC_FIR_OP_CW1  IFC_NAND_FIR1_OP5_SHIFT));
 
-   if (column = mtd-writesize) {
-   /* OOB area -- READOOB */
-   column -= mtd-writesize;
-   nand_fcr0 |= NAND_CMD_READOOB 
-   IFC_NAND_FCR0_CMD0_SHIFT;
-   ifc_nand_ctrl-oob = 1;
-   } else if (column  256)
-   /* First 256 bytes -- READ0 */
+   if (column = mtd-writesize)
nand_fcr0 |=
-   NAND_CMD_READ0  IFC_NAND_FCR0_CMD0_SHIFT;
+   NAND_CMD_READOOB  IFC_NAND_FCR0_CMD0_SHIFT;
else
-   /* Second 256 bytes -- READ1 */
nand_fcr0 |=
-   NAND_CMD_READ1  IFC_NAND_FCR0_CMD0_SHIFT;
+   NAND_CMD_READ0  IFC_NAND_FCR0_CMD0_SHIFT;
}
 
+   if (column = mtd-writesize) {
+   /* OOB area -- READOOB */
+   column -= mtd-writesize;
+   ifc_nand_ctrl-oob = 1;
+   }
out_be32(ifc-ifc_nand.nand_fcr0, nand_fcr0);
set_addr(mtd, column, page_addr, ifc_nand_ctrl-oob);
return;
@@ -466,7 +463,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned 
int command,
int full_page;
if (ifc_nand_ctrl-oob) {
out_be32(ifc-ifc_nand.nand_fbcr,
-   ifc_nand_ctrl-index);
+   ifc_nand_ctrl-index - ifc_nand_ctrl-column);
full_page = 0;
} else {
out_be32(ifc-ifc_nand.nand_fbcr, 0);
-- 
1.7.5.4


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mtd/NAND:Fix issues with freescale IFC to support NAND 2K

[Prabhakar Kushwaha]

This Patch series takes care issues with Freescale IFC driver for supporting 2K
page size NAND with ECC enabled.

[PATCH 1/2] mtd/nand:Fix wrong address read in is_blank()
  Fix driver issue when ECC enabled.

[PATCH 2/2] mtd/nand: Fix IFC driver to support 2K NAND page
  Fix driver during OOB updation

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[PATCH 1/2] mtd/nand:Fix wrong address read in is_blank()

[Prabhakar Kushwaha]

IFC NAND Machine calculates ECC on 512byte sector. Same is taken care in
fsl_ifc_run_command() while ECC status verification. Here buffer number is
calculated assuming 512byte sector and same is passed to is_blank.
However in is_blank() buffer address is calculated using mdt-writesize which is
wrong. It should be calculated on basis of ecc sector size.

Also, in fsl_ifc_run_command() bufferpage is calculated on the basis of ecc 
sector
size instead of hard coded value.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)

 Tested on P1010RDB

 drivers/mtd/nand/fsl_ifc_nand.c |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8475b88..2df7206 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -191,7 +191,9 @@ static int is_blank(struct mtd_info *mtd, unsigned int 
bufnum)
 {
struct nand_chip *chip = mtd-priv;
struct fsl_ifc_mtd *priv = chip-priv;
-   u8 __iomem *addr = priv-vbase + bufnum * (mtd-writesize * 2);
+   int bufperpage = mtd-writesize / chip-ecc.size;
+   u8 __iomem *addr = priv-vbase + bufnum / bufperpage
+   * (mtd-writesize * 2);
u32 __iomem *mainarea = (u32 *)addr;
u8 __iomem *oob = addr + mtd-writesize;
int i;
@@ -273,7 +275,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
dev_err(priv-dev, NAND Flash Write Protect Error\n);
 
if (nctrl-eccread) {
-   int bufperpage = mtd-writesize / 512;
+   int bufperpage = mtd-writesize / chip-ecc.size;
int bufnum = (nctrl-page  priv-bufnum_mask) * bufperpage;
int bufnum_end = bufnum + bufperpage - 1;
 
-- 
1.7.5.4


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[PATCH 2/2] mtd/nand: Fix IFC driver to support 2K NAND page

[Prabhakar Kushwaha]

1) OOB area should be updated irrespective of NAND page size. Earlier it was
updated only for 512byte NAND page.

2) During OOB update fbcr should be equal to OOB size.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)

 Tested on P1010RDB

 drivers/mtd/nand/fsl_ifc_nand.c |   20 
 1 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 2df7206..2c02168 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -439,20 +439,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, 
unsigned int command,
out_be32(ifc-ifc_nand.nand_fir1,
 (IFC_FIR_OP_CW1  IFC_NAND_FIR1_OP5_SHIFT));
 
-   if (column = mtd-writesize) {
-   /* OOB area -- READOOB */
-   column -= mtd-writesize;
-   nand_fcr0 |= NAND_CMD_READOOB 
-   IFC_NAND_FCR0_CMD0_SHIFT;
-   ifc_nand_ctrl-oob = 1;
-   } else if (column  256)
+   if (column  256)
/* First 256 bytes -- READ0 */
nand_fcr0 |=
NAND_CMD_READ0  IFC_NAND_FCR0_CMD0_SHIFT;
-   else
-   /* Second 256 bytes -- READ1 */
-   nand_fcr0 |=
-   NAND_CMD_READ1  IFC_NAND_FCR0_CMD0_SHIFT;
+   }
+
+   if (column = mtd-writesize) {
+   /* OOB area -- READOOB */
+   column -= mtd-writesize;
+   ifc_nand_ctrl-oob = 1;
}
 
out_be32(ifc-ifc_nand.nand_fcr0, nand_fcr0);
@@ -465,7 +461,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned 
int command,
int full_page;
if (ifc_nand_ctrl-oob) {
out_be32(ifc-ifc_nand.nand_fbcr,
-   ifc_nand_ctrl-index);
+   ifc_nand_ctrl-index - ifc_nand_ctrl-column);
full_page = 0;
} else {
out_be32(ifc-ifc_nand.nand_fbcr, 0);
-- 
1.7.5.4


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[PATCH 1/2][v3] Integrated Flash Controller support

[Prabhakar Kushwaha]

Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Tested on P1010RDB

 Changes for v2: Incorporated Artem Bityutskiy's comment
- Error handling in fsl_ifc_ctrl_probe
- Use module_platform_driver() insted of module_init and module_exit
 
 Changes for v3: Incorporated Dmitry Pervushin's comments
- Memory mapped structures should be defined with packet attribute

 arch/powerpc/Kconfig   |4 +
 arch/powerpc/include/asm/fsl_ifc.h |  834 
 arch/powerpc/sysdev/Makefile   |1 +
 arch/powerpc/sysdev/fsl_ifc.c  |  310 +
 4 files changed, 1149 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/fsl_ifc.h
 create mode 100644 arch/powerpc/sysdev/fsl_ifc.c

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7c93c7e..d78cb6e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -688,6 +688,10 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
+config FSL_IFC
+   bool
+depends on FSL_SOC
+
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/include/asm/fsl_ifc.h 
b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 000..85472e7
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+
+#include linux/compiler.h
+#include linux/types.h
+#include linux/io.h
+
+#include linux/of_platform.h
+#include linux/interrupt.h
+
+#define FSL_IFC_BANK_COUNT 4
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA0x
+#define CSPR_BA_SHIFT  16
+#define CSPR_PORT_SIZE 0x0180
+#define CSPR_PORT_SIZE_SHIFT   7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8   0x0080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16  0x0100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32  0x0180
+/* Write Protect */
+#define CSPR_WP0x0040
+#define CSPR_WP_SHIFT  6
+/* Machine Select */
+#define CSPR_MSEL  0x0006
+#define CSPR_MSEL_SHIFT1
+/* NOR */
+#define CSPR_MSEL_NOR  0x
+/* NAND */
+#define CSPR_MSEL_NAND 0x0002
+/* GPCM */
+#define CSPR_MSEL_GPCM 0x0004
+/* Bank Valid */
+#define CSPR_V 0x0001
+#define CSPR_V_SHIFT   0
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0x
+#define IFC_AMASK_SHIFT16
+#define IFC_AMASK(n)   (IFC_AMASK_MASK  \
+   (__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN   0x8000
+#define CSOR_NAND_ECC_MODE_MASK0x3000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4   0x
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8   0x1000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN   0x0400
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK 0x0180
+#define CSOR_NAND_RAL_SHIFT20
+#define CSOR_NAND_RAL_10x
+#define CSOR_NAND_RAL_20x0080
+#define CSOR_NAND_RAL_3

[PATCH 1/2][v2] Integrated Flash Controller support

[Prabhakar Kushwaha]

Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Tested on P1010RDB

 Changes for v2: Incorporated Artem Bityutskiy's comment
- Error handling in fsl_ifc_ctrl_probe
- Use module_platform_driver() insted of module_init and module_exit

 arch/powerpc/Kconfig   |4 +
 arch/powerpc/include/asm/fsl_ifc.h |  834 
 arch/powerpc/sysdev/Makefile   |1 +
 arch/powerpc/sysdev/fsl_ifc.c  |  310 +
 4 files changed, 1149 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/fsl_ifc.h
 create mode 100644 arch/powerpc/sysdev/fsl_ifc.c

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7c93c7e..d78cb6e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -688,6 +688,10 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
+config FSL_IFC
+   bool
+depends on FSL_SOC
+
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/include/asm/fsl_ifc.h 
b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 000..b955012
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+
+#include linux/compiler.h
+#include linux/types.h
+#include linux/io.h
+
+#include linux/of_platform.h
+#include linux/interrupt.h
+
+#define FSL_IFC_BANK_COUNT 4
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA0x
+#define CSPR_BA_SHIFT  16
+#define CSPR_PORT_SIZE 0x0180
+#define CSPR_PORT_SIZE_SHIFT   7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8   0x0080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16  0x0100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32  0x0180
+/* Write Protect */
+#define CSPR_WP0x0040
+#define CSPR_WP_SHIFT  6
+/* Machine Select */
+#define CSPR_MSEL  0x0006
+#define CSPR_MSEL_SHIFT1
+/* NOR */
+#define CSPR_MSEL_NOR  0x
+/* NAND */
+#define CSPR_MSEL_NAND 0x0002
+/* GPCM */
+#define CSPR_MSEL_GPCM 0x0004
+/* Bank Valid */
+#define CSPR_V 0x0001
+#define CSPR_V_SHIFT   0
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0x
+#define IFC_AMASK_SHIFT16
+#define IFC_AMASK(n)   (IFC_AMASK_MASK  \
+   (__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN   0x8000
+#define CSOR_NAND_ECC_MODE_MASK0x3000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4   0x
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8   0x1000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN   0x0400
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK 0x0180
+#define CSOR_NAND_RAL_SHIFT20
+#define CSOR_NAND_RAL_10x
+#define CSOR_NAND_RAL_20x0080
+#define CSOR_NAND_RAL_30x0100
+#define CSOR_NAND_RAL_40x0180
+/* Page Size 512b, 2k, 4k */
+#define

[PATCH 1/2][v2] Integrated Flash Controller support

[Prabhakar Kushwaha]

Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Tested on P1010RDB

 Changes for v2: Incorporated Artem Bityutskiy's comment
- Error handling in fsl_ifc_ctrl_probe
- Use module_platform_driver() insted of module_init and module_exit

 arch/powerpc/Kconfig   |4 +
 arch/powerpc/include/asm/fsl_ifc.h |  834 
 arch/powerpc/sysdev/Makefile   |1 +
 arch/powerpc/sysdev/fsl_ifc.c  |  310 +
 4 files changed, 1149 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/fsl_ifc.h
 create mode 100644 arch/powerpc/sysdev/fsl_ifc.c

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7c93c7e..d78cb6e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -688,6 +688,10 @@ config FSL_LBC
  controller.  Also contains some common code used by
  drivers for specific local bus peripherals.
 
+config FSL_IFC
+   bool
+depends on FSL_SOC
+
 config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/include/asm/fsl_ifc.h 
b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 000..b955012
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+
+#include linux/compiler.h
+#include linux/types.h
+#include linux/io.h
+
+#include linux/of_platform.h
+#include linux/interrupt.h
+
+#define FSL_IFC_BANK_COUNT 4
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA0x
+#define CSPR_BA_SHIFT  16
+#define CSPR_PORT_SIZE 0x0180
+#define CSPR_PORT_SIZE_SHIFT   7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8   0x0080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16  0x0100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32  0x0180
+/* Write Protect */
+#define CSPR_WP0x0040
+#define CSPR_WP_SHIFT  6
+/* Machine Select */
+#define CSPR_MSEL  0x0006
+#define CSPR_MSEL_SHIFT1
+/* NOR */
+#define CSPR_MSEL_NOR  0x
+/* NAND */
+#define CSPR_MSEL_NAND 0x0002
+/* GPCM */
+#define CSPR_MSEL_GPCM 0x0004
+/* Bank Valid */
+#define CSPR_V 0x0001
+#define CSPR_V_SHIFT   0
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0x
+#define IFC_AMASK_SHIFT16
+#define IFC_AMASK(n)   (IFC_AMASK_MASK  \
+   (__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN   0x8000
+#define CSOR_NAND_ECC_MODE_MASK0x3000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4   0x
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8   0x1000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN   0x0400
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK 0x0180
+#define CSOR_NAND_RAL_SHIFT20
+#define CSOR_NAND_RAL_10x
+#define CSOR_NAND_RAL_20x0080
+#define CSOR_NAND_RAL_30x0100
+#define CSOR_NAND_RAL_40x0180
+/* Page Size 512b, 2k, 4k */
+#define

[PATCH 2/2][v2] NAND Machine support for Integrated Flash Controller

[Prabhakar Kushwaha]

Integrated Flash Controller(IFC) can be used to hook NAND Flash
chips using NAND Flash Machine available on it.

Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Tested on P1010RDB

 Changes for v2: Ported IFC driver for linux-3.2.0-rc3 
- Use chip-bbt_options for BBT
- Use mtd_device_parse_register instead of old parse_mtd_partitions

 drivers/mtd/nand/Kconfig|   10 +
 drivers/mtd/nand/Makefile   |1 +
 drivers/mtd/nand/fsl_ifc_nand.c | 1070 +++
 3 files changed, 1081 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_ifc_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index cce7b70..2fff5c7 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -463,6 +463,16 @@ config MTD_NAND_FSL_ELBC
  Enabling this option will enable you to use this to control
  external NAND devices.
 
+config MTD_NAND_FSL_IFC
+   tristate NAND support for Freescale IFC controller
+   depends on MTD_NAND  FSL_SOC
+   select FSL_IFC
+   help
+ Various Freescale chips e.g P1010, include a NAND Flash machine
+ with built-in hardware ECC capabilities.
+ Enabling this option will enable you to use this to control
+ external NAND devices.
+
 config MTD_NAND_FSL_UPM
tristate Support for NAND on Freescale UPM
depends on PPC_83xx || PPC_85xx
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 618f4ba..19bc8cb 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MTD_ALAUDA)  += alauda.o
 obj-$(CONFIG_MTD_NAND_PASEMI)  += pasemi_nand.o
 obj-$(CONFIG_MTD_NAND_ORION)   += orion_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_ELBC)+= fsl_elbc_nand.o
+obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_MTD_NAND_SH_FLCTL)+= sh_flctl.o
 obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
new file mode 100644
index 000..8475b88
--- /dev/null
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -0,0 +1,1070 @@
+/*
+ * Freescale Integrated Flash Controller NAND driver
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat dipen.dud...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include linux/module.h
+#include linux/types.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/slab.h
+#include linux/mtd/mtd.h
+#include linux/mtd/nand.h
+#include linux/mtd/partitions.h
+#include linux/mtd/nand_ecc.h
+#include asm/fsl_ifc.h
+
+#define ERR_BYTE   0xFF /* Value returned for read
+   bytes when read failed  */
+#define IFC_TIMEOUT_MSECS  500  /* Maximum number of mSecs to wait
+   for IFC NAND Machine*/
+
+struct fsl_ifc_ctrl;
+
+/* mtd information per set */
+struct fsl_ifc_mtd {
+   struct mtd_info mtd;
+   struct nand_chip chip;
+   struct fsl_ifc_ctrl *ctrl;
+
+   struct device *dev;
+   int bank;   /* Chip select bank number  */
+   unsigned int bufnum_mask; /* bufnum = page  bufnum_mask */
+   u8 __iomem *vbase;  /* Chip select base virtual address */
+};
+
+/* overview of the fsl ifc controller */
+struct fsl_ifc_nand_ctrl {
+   struct nand_hw_control controller;
+   struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
+
+   u8 __iomem *addr;   /* Address of assigned IFC buffer   */
+   unsigned int page;  /* Last page written to / read from */
+   unsigned int read_bytes;/* Number of bytes read during command  */
+   unsigned int column;/* Saved column from SEQIN  */
+   unsigned int index; /* Pointer to next byte to 'read'   */
+   unsigned int oob

[PATCH] powerpc/85xx:DTS: Fix tbi node location for Px020RDB

[Prabhakar Kushwaha]

ten-bit interface (TBI) module is part of SoC not board.

Move tbi entries from board related dts files to Si dts.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 arch/powerpc/boot/dts/p1020rdb.dts|9 -
 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts |8 
 arch/powerpc/boot/dts/p1020si.dtsi|6 +-
 arch/powerpc/boot/dts/p2020rdb.dts|8 
 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts |8 
 arch/powerpc/boot/dts/p2020si.dtsi|6 +-
 6 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts 
b/arch/powerpc/boot/dts/p1020rdb.dts
index d6a8ae4..a4e5d6c 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -211,14 +211,6 @@
};
};
 
-   mdio@25000 {
-
-   tbi0: tbi-phy@11 {
-   reg = 0x11;
-   device_type = tbi-phy;
-   };
-   };
-
enet0: ethernet@b {
fixed-link = 1 1 1000 0 0;
phy-connection-type = rgmii-id;
@@ -227,7 +219,6 @@
 
enet1: ethernet@b1000 {
phy-handle = phy0;
-   tbi-handle = tbi0;
phy-connection-type = sgmii;
 
};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts 
b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
index f0bf7f4..abab234 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -114,20 +114,12 @@
};
};
 
-   mdio@25000 {
-   tbi0: tbi-phy@11 {
-   reg = 0x11;
-   device_type = tbi-phy;
-   };
-   };
-
enet0: ethernet@b {
status = disabled;
};
 
enet1: ethernet@b1000 {
phy-handle = phy0;
-   tbi-handle = tbi0;
phy-connection-type = sgmii;
};
 
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi 
b/arch/powerpc/boot/dts/p1020si.dtsi
index 5c5acb6..7844d2e 100644
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -190,7 +190,10 @@
#size-cells = 0;
compatible = fsl,etsec2-tbi;
reg = 0x25000 0x1000 0xb1030 0x4;
-
+   tbi0: tbi-phy@11 {
+   reg = 0x11;
+   device_type = tbi-phy;
+   };
};
 
enet0: ethernet@b {
@@ -229,6 +232,7 @@
fsl,num_tx_queues = 0x8;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = mpic;
+   tbi-handle = tbi0;
 
queue-group@0 {
#address-cells = 1;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts 
b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f..2941cbb 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -213,13 +213,6 @@
};
};
 
-   mdio@25520 {
-   tbi0: tbi-phy@11 {
-   reg = 0x11;
-   device_type = tbi-phy;
-   };
-   };
-
mdio@26520 {
status = disabled;
};
@@ -243,7 +236,6 @@
};
 
enet1: ethernet@25000 {
-   tbi-handle = tbi0;
phy-handle = phy0;
phy-connection-type = sgmii;
};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts 
b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8..4641f3d 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -124,13 +124,6 @@
};
};
 
-   mdio@25520 {
-   tbi0: tbi-phy@11 {
-   reg = 0x11;
-   device_type = tbi-phy;
-   };
-   };
-
mdio@26520 {
status = disabled;
};
@@ -140,7 +133,6 @@
};
 
enet1: ethernet@25000 {
-   tbi-handle = tbi0;
phy-handle = phy0;
phy-connection-type = sgmii;
 
diff --git

[PATCH][v2] powerpc/85xx: Add P1010RDB board support

[Prabhakar Kushwaha]

 P1010RDB Overview
 -
 1Gbyte DDR3 (on board DDR)
 32Mbyte 16bit NOR flash
 32Mbyte SLC NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 I2C Board 128x8 bit memory
 SD/MMC connector to interface with the SD memory card
 2 SATA interface
 1 internal SATA connect to 2.5. 160G SATA2 HDD
 1 eSATA connector to rear panel
 USB 2.0
 x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
 x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
 eTSEC1: Connected to RGMII PHY VSC8641XKO
 eTSEC2: Connected to SGMII PHY VSC8221
 eTSEC3: Connected to SGMII PHY VSC8221 eCAN
 Two DB-9 female connectors for Field bus interface UART
 DUART interface: supports two UARTs up to 115200 bps for console display

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 Changes for v2:
- updated tbi-handle location

 arch/powerpc/boot/dts/p1010rdb.dts |  278 +++
 arch/powerpc/boot/dts/p1010si.dtsi |  378 
 arch/powerpc/configs/mpc85xx_defconfig |1 +
 arch/powerpc/platforms/85xx/Kconfig|   10 +
 arch/powerpc/platforms/85xx/Makefile   |1 +
 arch/powerpc/platforms/85xx/p1010rdb.c |  122 ++
 6 files changed, 790 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1010rdb.dts
 create mode 100644 arch/powerpc/boot/dts/p1010si.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/p1010rdb.c

diff --git a/arch/powerpc/boot/dts/p1010rdb.dts 
b/arch/powerpc/boot/dts/p1010rdb.dts
new file mode 100644
index 000..773cc16
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -0,0 +1,278 @@
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ p1010si.dtsi
+
+/ {
+   model = fsl,P1010RDB;
+   compatible = fsl,P1010RDB;
+
+   aliases {
+   serial0 = serial0;
+   serial1 = serial1;
+   ethernet0 = enet0;
+   ethernet1 = enet1;
+   ethernet2 = enet2;
+   pci0 = pci0;
+   pci1 = pci1;
+   };
+
+   memory {
+   device_type = memory;
+   };
+
+   ifc@ffe1e000 {
+   /* NOR, NAND Flashes and CPLD on board */
+   ranges = 0x0 0x0 0x0 0xee00 0x0200
+ 0x1 0x0 0x0 0xff80 0x0001
+ 0x3 0x0 0x0 0xffb0 0x0020;
+
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x200;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 7 MB for Linux Kernel Image */
+   reg = 0x0008 0x0070;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@80 {
+   /* 20MB for JFFS2 based Root file System */
+   reg = 0x0080 0x0140;
+   label = NOR JFFS2 Root File System;
+   };
+
+   partition@1f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image */
+   /* 512KB for u-boot Environment Variables */
+   reg = 0x01f0 0x0010;
+   label = NOR U-Boot Image;
+   read-only;
+   };
+   };
+
+   nand@1,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = fsl,ifc-nand;
+   reg = 0x1 0x0 0x1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 1MB for u-boot Bootloader Image */
+   reg = 0x0 0x0010;
+   label = NAND U-Boot Image;
+   read-only

[PATCH] powerpc/85xx: Add P1010RDB board support

[Prabhakar Kushwaha]

 P1010RDB Overview
 -
 1Gbyte DDR3 (on board DDR)
 32Mbyte 16bit NOR flash
 32Mbyte SLC NAND Flash
 256 Kbit M24256 I2C EEPROM
 128 Mbit SPI Flash memory
 I2C Board 128x8 bit memory
 SD/MMC connector to interface with the SD memory card
 2 SATA interface
 1 internal SATA connect to 2.5. 160G SATA2 HDD
 1 eSATA connector to rear panel
 USB 2.0
 x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
 x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
 eTSEC1: Connected to RGMII PHY VSC8641XKO
 eTSEC2: Connected to SGMII PHY VSC8221
 eTSEC3: Connected to SGMII PHY VSC8221 eCAN
 Two DB-9 female connectors for Field bus interface UART
 DUART interface: supports two UARTs up to 115200 bps for console display

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
(branch next)

 arch/powerpc/boot/dts/p1010rdb.dts |  280 
 arch/powerpc/boot/dts/p1010si.dtsi |  376 
 arch/powerpc/configs/mpc85xx_defconfig |1 +
 arch/powerpc/platforms/85xx/Kconfig|   10 +
 arch/powerpc/platforms/85xx/Makefile   |1 +
 arch/powerpc/platforms/85xx/p1010rdb.c |  122 +++
 6 files changed, 790 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1010rdb.dts
 create mode 100644 arch/powerpc/boot/dts/p1010si.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/p1010rdb.c

diff --git a/arch/powerpc/boot/dts/p1010rdb.dts 
b/arch/powerpc/boot/dts/p1010rdb.dts
new file mode 100644
index 000..6b33b73
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -0,0 +1,280 @@
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ p1010si.dtsi
+
+/ {
+   model = fsl,P1010RDB;
+   compatible = fsl,P1010RDB;
+
+   aliases {
+   serial0 = serial0;
+   serial1 = serial1;
+   ethernet0 = enet0;
+   ethernet1 = enet1;
+   ethernet2 = enet2;
+   pci0 = pci0;
+   pci1 = pci1;
+   };
+
+   memory {
+   device_type = memory;
+   };
+
+   ifc@ffe1e000 {
+   /* NOR, NAND Flashes and CPLD on board */
+   ranges = 0x0 0x0 0x0 0xee00 0x0200
+ 0x1 0x0 0x0 0xff80 0x0001
+ 0x3 0x0 0x0 0xffb0 0x0020;
+
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x200;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 7 MB for Linux Kernel Image */
+   reg = 0x0008 0x0070;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@80 {
+   /* 20MB for JFFS2 based Root file System */
+   reg = 0x0080 0x0140;
+   label = NOR JFFS2 Root File System;
+   };
+
+   partition@1f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image */
+   /* 512KB for u-boot Environment Variables */
+   reg = 0x01f0 0x0010;
+   label = NOR U-Boot Image;
+   read-only;
+   };
+   };
+
+   nand@1,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = fsl,ifc-nand;
+   reg = 0x1 0x0 0x1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 1MB for u-boot Bootloader Image */
+   reg = 0x0 0x0010;
+   label = NAND U-Boot Image;
+   read-only

[PATCH][v2] powerpc/85xx: add host-pci(e) bridge only for RC

[Prabhakar Kushwaha]

FSL PCIe controller can act as agent(EP) or host(RC).
Under Agent(EP) mode they are configured via Host. So it is not required to add
with the PCI(e) sub-system.

Add and configure PCIe controller only for RC mode.

Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 Chages for v2: Incorporated Kumar's comment
- Use PCI_CLASS_PROG instead of PCI_HEADER_TYPE 

 arch/powerpc/sysdev/fsl_pci.c |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 68ca929..4a1d37c 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
+   u8 progif;
 
if (!of_device_is_available(dev)) {
pr_warning(%s: disabled\n, dev-full_name);
@@ -353,6 +354,19 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
 
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+   early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, progif);
+   if (progif  1 ) {
+   u32 temp;
+
+   temp = (u32)hose-cfg_data  ~PAGE_MASK;
+   if (((u32)hose-cfg_data  PAGE_MASK) != (u32)hose-cfg_addr)
+   iounmap(hose-cfg_data - temp);
+   iounmap(hose-cfg_addr);
+   pcibios_free_controller(hose);
+   return 0;
+   }
+
setup_pci_cmd(hose);
 
/* check PCI express link status */
-- 
1.7.4.1


___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev

[PATCH][v3] powerpc/85xx: add host-pci(e) bridge only for RC

[Prabhakar Kushwaha]

FSL PCIe controller can act as agent(EP) or host(RC).
Under Agent(EP) mode they are configured via Host. So it is not required to add
with the PCI(e) sub-system.

Add and configure PCIe controller only for RC mode.

Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 Chages for v2: Incorporated Kumar's comment
- Use PCI_CLASS_PROG instead of PCI_HEADER_TYPE 
 Changes for v3: 
- updated if check condition
- removed checkpatch warning

 arch/powerpc/sysdev/fsl_pci.c |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 68ca929..4a1d37c 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
+   u8 progif;
 
if (!of_device_is_available(dev)) {
pr_warning(%s: disabled\n, dev-full_name);
@@ -353,6 +354,19 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
 
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+   early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, progif);
+   if ((progif  1) == 1) {
+   u32 temp;
+
+   temp = (u32)hose-cfg_data  ~PAGE_MASK;
+   if (((u32)hose-cfg_data  PAGE_MASK) != (u32)hose-cfg_addr)
+   iounmap(hose-cfg_data - temp);
+   iounmap(hose-cfg_addr);
+   pcibios_free_controller(hose);
+   return 0;
+   }
+
setup_pci_cmd(hose);
 
/* check PCI express link status */
-- 
1.7.4.1


___
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[PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM

[Prabhakar Kushwaha]

D3-cold state indicates removal of the clock and power. however auxiliary (AUX)
Power may remain available even after the main power rails are powered down.

wakeup from D3-cold state requires full context restore. Other things are taken
care in pci-driver except ATMUs.
ATMU windows needs to be saved and restored during suspend and resume.

Signed-off-by: Jiang Yutang b14...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 arch/powerpc/sysdev/fsl_pci.c |  116 +
 arch/powerpc/sysdev/fsl_pci.h |7 ++-
 2 files changed, 121 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f8f7f28..809fbfe 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -35,6 +35,9 @@
 #include sysdev/fsl_pci.h
 
 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
+static int pcie_saved_pow_piw;
+struct pci_outbound_window_regs pcie_saved_pow[PCIE_POW_NUMBER];
+struct pci_inbound_window_regs pcie_saved_piw[PCIE_PIW_NUMBER];
 
 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
 {
@@ -746,3 +749,116 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
 
return 0;
 }
+
+
+static int fsl_pcie_save_pow_piw(struct device_node *np,
+   struct resource *rsrc)
+{
+   struct ccsr_pci __iomem *pci;
+   int start_idx = 1, end_idx = 4;
+   unsigned int i;
+
+   pci = ioremap(rsrc-start, rsrc-end - rsrc-start + 1);
+
+   if (!pci) {
+   printk(KERN_WARNINGpcie_pow ioremap error!\n);
+   return -1;
+   }
+
+   if (of_device_is_compatible(np, fsl,qoriq-pcie-v2.2)) {
+   start_idx = 0;
+   end_idx = 3;
+   }
+
+   for (i = 0; i  PCIE_POW_NUMBER; i++) {
+   pcie_saved_pow[i].potar = in_be32(pci-pow[i].potar);
+   pcie_saved_pow[i].potear = in_be32(pci-pow[i].potear);
+   pcie_saved_pow[i].powbar = in_be32(pci-pow[i].powbar);
+   pcie_saved_pow[i].powar = in_be32(pci-pow[i].powar);
+   }
+
+   for (i = start_idx; i  end_idx; i++) {
+   pcie_saved_piw[i].pitar = in_be32(pci-piw[i].pitar);
+   pcie_saved_piw[i].piwbar = in_be32(pci-piw[i].piwbar);
+   pcie_saved_piw[i].piwbear = in_be32(pci-piw[i].piwbear);
+   pcie_saved_piw[i].piwar = in_be32(pci-piw[i].piwar);
+   }
+
+   iounmap(pci);
+   return 0;
+}
+
+static int fsl_pcie_restore_pow_piw(struct device_node *np,
+   struct resource *rsrc)
+{
+   struct ccsr_pci __iomem *pci;
+   int start_idx = 1, end_idx = 4;
+   unsigned int i;
+
+   pci = ioremap(rsrc-start, rsrc-end - rsrc-start + 1);
+
+   if (of_device_is_compatible(np, fsl,qoriq-pcie-v2.2)) {
+   start_idx = 0;
+   end_idx = 3;
+   }
+   if (!pci) {
+   printk(KERN_WARNINGpcie_pow ioremap error!\n);
+   return -1;
+   }
+
+   for (i = 0; i  PCIE_POW_NUMBER; i++) {
+   out_be32(pci-pow[i].potar, pcie_saved_pow[i].potar);
+   out_be32(pci-pow[i].potear, pcie_saved_pow[i].potear);
+   out_be32(pci-pow[i].powbar, pcie_saved_pow[i].powbar);
+   out_be32(pci-pow[i].powar, pcie_saved_pow[i].powar);
+   }
+
+   for (i = 0; i  PCIE_PIW_NUMBER; i++) {
+   out_be32(pci-piw[i].pitar, pcie_saved_piw[i].pitar);
+   out_be32(pci-piw[i].piwbar, pcie_saved_piw[i].piwbar);
+   out_be32(pci-piw[i].piwbear, pcie_saved_piw[i].piwbear);
+   out_be32(pci-piw[i].piwar, pcie_saved_piw[i].piwar);
+   }
+
+   iounmap(pci);
+   return 0;
+}
+
+static void fsl_pcie_suspend_save(struct pci_dev *dev)
+{
+   struct device_node *np;
+   struct resource rsrc;
+
+   if (pcie_saved_pow_piw == 1)
+   return;
+
+   for_each_node_by_type(np, pci) {
+   if (of_device_is_compatible(np, fsl,p1022-pcie)) {
+   of_address_to_resource(np, 0, rsrc);
+   fsl_pcie_save_pow_piw(np, rsrc);
+   }
+   }
+   pcie_saved_pow_piw = 1;
+}
+DECLARE_PCI_FIXUP_SUSPEND(0x1957, PCI_DEVICE_ID_P1022E, fsl_pcie_suspend_save);
+DECLARE_PCI_FIXUP_SUSPEND(0x1957, PCI_DEVICE_ID_P1022, fsl_pcie_suspend_save);
+
+static void fsl_pcie_resume_restore(struct pci_dev *dev)
+{
+   struct device_node *np;
+   struct resource rsrc;
+
+   if (pcie_saved_pow_piw == 0)
+   return;
+
+   for_each_node_by_type(np, pci) {
+   if (of_device_is_compatible(np, fsl,p1022-pcie)) {
+   of_address_to_resource(np, 0, rsrc);
+   fsl_pcie_restore_pow_piw(np, rsrc);
+   }
+   }
+   pcie_saved_pow_piw = 0

[PATCH] powerpc/85xx:Create dts of each core in CAMP mode for P1020RDB

[Prabhakar Kushwaha]

Create the dts files for each core and splits the devices between the two cores
for P1020RDB.

Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, eth1, eth2,
sdhc, crypto, global-util, message, pci0, pci1, msi.
Core1 has l2, eth0, crypto.

MPIC is shared between two cores but each core will protect its interrupts from
other core by using protected-sources of mpic.

Fix compatible property for global-util node of P1020si.dtsi.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)
 
 This patch depends on following patch
powerpc/85xx: P1020 DTS : re-organize dts files

 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts |  213 +
 arch/powerpc/boot/dts/p1020rdb_camp_core1.dts |  148 +
 arch/powerpc/boot/dts/p1020si.dtsi|2 +-
 3 files changed, 362 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
 create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core1.dts

diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts 
b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
new file mode 100644
index 000..f0bf7f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -0,0 +1,213 @@
+/*
+ * P1020 RDB  Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, 
usb,
+ * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
+ *
+ * Please note to add -b 0 for core0's dts compiling.
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ p1020si.dtsi
+
+/ {
+   model = fsl,P1020RDB;
+   compatible = fsl,P1020RDB, fsl,MPC85XXRDB-CAMP;
+
+   aliases {
+   ethernet1 = enet1;
+   ethernet2 = enet2;
+   serial0 = serial0;
+   pci0 = pci0;
+   pci1 = pci1;
+   };
+
+   cpus {
+   PowerPC,P1020@1 {
+   status = disabled;
+   };
+   };
+
+   memory {
+   device_type = memory;
+   };
+
+   localbus@ffe05000 {
+   status = disabled;
+   };
+
+   soc@ffe0 {
+   i2c@3000 {
+   rtc@68 {
+   compatible = dallas,ds1339;
+   reg = 0x68;
+   };
+   };
+
+   serial1: serial@4600 {
+   status = disabled;
+   };
+
+   spi@7000 {
+   fsl_m25p80@0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = fsl,espi-flash;
+   reg = 0;
+   linux,modalias = fsl_m25p80;
+   spi-max-frequency = 4000;
+
+   partition@0 {
+   /* 512KB for u-boot Bootloader Image */
+   reg = 0x0 0x0008;
+   label = SPI (RO) U-Boot Image;
+   read-only;
+   };
+
+   partition@8 {
+   /* 512KB for DTB Image */
+   reg = 0x0008 0x0008;
+   label = SPI (RO) DTB Image;
+   read-only;
+   };
+
+   partition@10 {
+   /* 4MB for Linux Kernel Image */
+   reg = 0x0010 0x0040;
+   label = SPI (RO) Linux Kernel Image;
+   read-only;
+   };
+
+   partition@50 {
+   /* 4MB for Compressed RFS Image */
+   reg = 0x0050 0x0040;
+   label = SPI (RO) Compressed RFS Image;
+   read-only;
+   };
+
+   partition@90 {
+   /* 7MB for JFFS2 based RFS */
+   reg = 0x0090 0x0070

[PATCH] powerpc/85xx: add host-pci(e) bridge only for RC

[Prabhakar Kushwaha]

FSL PCIe controller can act as agent(EP) or host(RC).
Under Agent(EP) mode they are configured via Host. So it is not required to add
with the PCI(e) sub-system.

Add and configure PCIe controller only for RC mode.

Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 arch/powerpc/sysdev/fsl_pci.c |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 68ca929..87ac11b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
+   u8 is_agent;
 
if (!of_device_is_available(dev)) {
pr_warning(%s: disabled\n, dev-full_name);
@@ -353,6 +354,19 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
 
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+   early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, is_agent);
+   if ((is_agent  0x7f) == PCI_HEADER_TYPE_NORMAL) {
+   u32 temp;
+
+   temp = (u32)hose-cfg_data  ~PAGE_MASK;
+   if (((u32)hose-cfg_data  PAGE_MASK) != (u32)hose-cfg_addr)
+   iounmap(hose-cfg_data - temp);
+   iounmap(hose-cfg_addr);
+   pcibios_free_controller(hose);
+   return 0;
+   }
+
setup_pci_cmd(hose);
 
/* check PCI express link status */
-- 
1.7.3


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[PATCH] powerpc/85xx:DTS: Fix PCIe IDSEL for Px020RDB

[Prabhakar Kushwaha]

PCIe device in legacy mode can trigger interrupts using the wires #INTA, #INTB
,#INTC and #INTD. PCI devices are obligated to use #INTx for interrupts under
legacy mode.  Each PCI slot or device is typically wired to different inputs on
the interrupt controller. 

So, Define interrupt-map and interrupt-map-mask properties for device tree to
of map each PCI interrupt signal to the inputs of the interrupt controller.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 This patch has depedency on following 2 patches
-- powerpc/85xx: P2020 DTS: re-organize dts files
-- powerpc/85xx: P1020 DTS : re-organize dts files

 arch/powerpc/boot/dts/p1020rdb.dts|   16 
 arch/powerpc/boot/dts/p2020rdb.dts|   16 
 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts |8 
 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts |8 
 4 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts 
b/arch/powerpc/boot/dts/p1020rdb.dts
index 7ed4793..d6a8ae4 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -257,6 +257,14 @@
pci0: pcie@ffe09000 {
ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
  0x100 0x0 0x 0 0xffc1 0x0 0x1;
+   interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0x0 0x0 0x1 mpic 0x4 0x1
+    0x0 0x0 0x2 mpic 0x5 0x1
+    0x0 0x0 0x3 mpic 0x6 0x1
+    0x0 0x0 0x4 mpic 0x7 0x1
+   ;
pcie@0 {
reg = 0x0 0x0 0x0 0x0 0x0;
#size-cells = 2;
@@ -275,6 +283,14 @@
pci1: pcie@ffe0a000 {
ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
  0x100 0x0 0x 0 0xffc0 0x0 0x1;
+   interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0x0 0x0 0x1 mpic 0x0 0x1
+    0x0 0x0 0x2 mpic 0x1 0x1
+    0x0 0x0 0x3 mpic 0x2 0x1
+    0x0 0x0 0x4 mpic 0x3 0x1
+   ;
pcie@0 {
reg = 0x0 0x0 0x0 0x0 0x0;
#size-cells = 2;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts 
b/arch/powerpc/boot/dts/p2020rdb.dts
index 60a0a8c..3782a58 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -249,6 +249,14 @@
pci1: pcie@ffe09000 {
ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
  0x100 0x0 0x 0 0xffc1 0x0 0x1;
+   interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0x0 0x0 0x1 mpic 0x4 0x1
+    0x0 0x0 0x2 mpic 0x5 0x1
+    0x0 0x0 0x3 mpic 0x6 0x1
+    0x0 0x0 0x4 mpic 0x7 0x1
+   ;
pcie@0 {
reg = 0x0 0x0 0x0 0x0 0x0;
#size-cells = 2;
@@ -267,6 +275,14 @@
pci2: pcie@ffe0a000 {
ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
  0x100 0x0 0x 0 0xffc0 0x0 0x1;
+   interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0x0 0x0 0x1 mpic 0x0 0x1
+    0x0 0x0 0x2 mpic 0x1 0x1
+    0x0 0x0 0x3 mpic 0x2 0x1
+    0x0 0x0 0x4 mpic 0x3 0x1
+   ;
pcie@0 {
reg = 0x0 0x0 0x0 0x0 0x0;
#size-cells = 2;
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts 
b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index 72c912f..fc8 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -175,6 +175,14 @@
pci1: pcie@ffe09000 {
ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
  0x100 0x0 0x 0 0xffc1 0x0 0x1;
+   interrupt-map-mask = 0xf800 0x0 0x0 0x7;
+   interrupt-map = 
+   /* IDSEL 0x0 */
+    0x0 0x0 0x1 mpic 0x4 0x1
+    0x0 0x0 0x2 mpic 0x5 0x1
+    0x0 0x0 0x3 mpic 0x6 0x1

[PATCH] driver/e1000e: Fix default interrupt mode select

[Prabhakar Kushwaha]

From: Prabhakar prabha...@freescale.com

e1000 default interrupt mode is MSI. No matter user select MSI or
disable MSI in kernel config.

Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 drivers/net/e1000e/param.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c
index a150e48..7b3bbec 100644
--- a/drivers/net/e1000e/param.c
+++ b/drivers/net/e1000e/param.c
@@ -390,7 +390,11 @@ void __devinit e1000e_check_options(struct e1000_adapter 
*adapter)
.type = range_option,
.name = Interrupt Mode,
.err  = defaulting to 2 (MSI-X),
+#ifdef CONFIG_PCI_MSI
.def  = E1000E_INT_MODE_MSIX,
+#else
+   .def  = E1000E_INT_MODE_LEGACY,
+#endif
.arg  = { .r = { .min = MIN_INTMODE,
 .max = MAX_INTMODE } }
};
-- 
1.7.3


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[PATCH] driver/e1000e: Fix default interrupt mode select

[Prabhakar Kushwaha]

From: Prabhakar prabha...@freescale.com

The Intel e1000 device driver defaults to MSI interrupt mode, even if MSI
support is not enabled

Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 added  netdev mail-list and e1000 mail-list  maintainer

 drivers/net/e1000e/param.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c
index a150e48..7b3bbec 100644
--- a/drivers/net/e1000e/param.c
+++ b/drivers/net/e1000e/param.c
@@ -390,7 +390,11 @@ void __devinit e1000e_check_options(struct e1000_adapter 
*adapter)
.type = range_option,
.name = Interrupt Mode,
.err  = defaulting to 2 (MSI-X),
+#ifdef CONFIG_PCI_MSI
.def  = E1000E_INT_MODE_MSIX,
+#else
+   .def  = E1000E_INT_MODE_LEGACY,
+#endif
.arg  = { .r = { .min = MIN_INTMODE,
 .max = MAX_INTMODE } }
};
-- 
1.7.3


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[PATCH] powerpc/85xx: P2020 DTS: re-organize dts files

[Prabhakar Kushwaha]

Creates P2020si.dtsi, containing information for P2020 SoC. Modifies dts files
for P2020 based systems to use dtsi file.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 Please see mpc5200b.dtsi for reference.
 
 Tested on P2020RDB and P2020DS

 arch/powerpc/boot/dts/p2020ds.dts |  374 ++--
 arch/powerpc/boot/dts/p2020rdb.dts|  362 ++-
 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts |  237 +++-
 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts |  142 ++
 arch/powerpc/boot/dts/p2020si.dtsi|  382 +
 5 files changed, 564 insertions(+), 933 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p2020si.dtsi

diff --git a/arch/powerpc/boot/dts/p2020ds.dts 
b/arch/powerpc/boot/dts/p2020ds.dts
index 1101914..2bcf368 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -1,7 +1,7 @@
 /*
  * P2020 DS Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,12 +9,11 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ p2020si.dtsi
+
 / {
-   model = fsl,P2020;
+   model = fsl,P2020DS;
compatible = fsl,P2020DS;
-   #address-cells = 2;
-   #size-cells = 2;
 
aliases {
ethernet0 = enet0;
@@ -27,35 +26,13 @@
pci2 = pci2;
};
 
-   cpus {
-   #address-cells = 1;
-   #size-cells = 0;
-
-   PowerPC,P2020@0 {
-   device_type = cpu;
-   reg = 0x0;
-   next-level-cache = L2;
-   };
-
-   PowerPC,P2020@1 {
-   device_type = cpu;
-   reg = 0x1;
-   next-level-cache = L2;
-   };
-   };
 
memory {
device_type = memory;
};
 
localbus@ffe05000 {
-   #address-cells = 2;
-   #size-cells = 1;
compatible = fsl,elbc, simple-bus;
-   reg = 0 0xffe05000 0 0x1000;
-   interrupts = 19 2;
-   interrupt-parent = mpic;
-
ranges = 0x0 0x0 0x0 0xe800 0x0800
  0x1 0x0 0x0 0xe000 0x0800
  0x2 0x0 0x0 0xffa0 0x0004
@@ -158,352 +135,77 @@
};
 
soc@ffe0 {
-   #address-cells = 1;
-   #size-cells = 1;
-   device_type = soc;
-   compatible = fsl,p2020-immr, simple-bus;
-   ranges = 0x0 0 0xffe0 0x10;
-   bus-frequency = 0;// Filled out by uboot.
-
-   ecm-law@0 {
-   compatible = fsl,ecm-law;
-   reg = 0x0 0x1000;
-   fsl,num-laws = 12;
-   };
-
-   ecm@1000 {
-   compatible = fsl,p2020-ecm, fsl,ecm;
-   reg = 0x1000 0x1000;
-   interrupts = 17 2;
-   interrupt-parent = mpic;
-   };
-
-   memory-controller@2000 {
-   compatible = fsl,p2020-memory-controller;
-   reg = 0x2000 0x1000;
-   interrupt-parent = mpic;
-   interrupts = 18 2;
-   };
-
-   i2c@3000 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 0;
-   compatible = fsl-i2c;
-   reg = 0x3000 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
-   };
-
-   i2c@3100 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 1;
-   compatible = fsl-i2c;
-   reg = 0x3100 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
-   };
 
-   serial0: serial@4500 {
-   cell-index = 0;
-   device_type = serial;
-   compatible = ns16550;
-   reg = 0x4500 0x100;
-   clock-frequency = 0;
-   interrupts = 42 2;
-   interrupt-parent = mpic;
-   };
-
-   serial1: serial@4600 {
-   cell-index = 1;
-   device_type = serial

[PATCH] powerpc/85xx: P1020 DTS : re-organize dts files

[Prabhakar Kushwaha]

Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Kumar Gala kumar.g...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 Please see mpc5200b.dtsi for reference.
 
 Tested on P1020RDB

 arch/powerpc/boot/dts/p1020rdb.dts |  315 +-
 arch/powerpc/boot/dts/p1020si.dtsi |  378 
 2 files changed, 380 insertions(+), 313 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts 
b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..8ae5ddf 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,10 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ p1020si.dtsi
+
 / {
-   model = fsl,P1020;
compatible = fsl,P1020RDB;
-   #address-cells = 2;
-   #size-cells = 2;
 
aliases {
serial0 = serial0;
@@ -26,34 +24,11 @@
pci1 = pci1;
};
 
-   cpus {
-   #address-cells = 1;
-   #size-cells = 0;
-
-   PowerPC,P1020@0 {
-   device_type = cpu;
-   reg = 0x0;
-   next-level-cache = L2;
-   };
-
-   PowerPC,P1020@1 {
-   device_type = cpu;
-   reg = 0x1;
-   next-level-cache = L2;
-   };
-   };
-
memory {
device_type = memory;
};
 
localbus@ffe05000 {
-   #address-cells = 2;
-   #size-cells = 1;
-   compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
-   reg = 0 0xffe05000 0 0x1000;
-   interrupts = 19 2;
-   interrupt-parent = mpic;
 
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0x0 0xef00 0x0100
@@ -165,88 +140,14 @@
};
 
soc@ffe0 {
-   #address-cells = 1;
-   #size-cells = 1;
-   device_type = soc;
-   compatible = fsl,p1020-immr, simple-bus;
-   ranges = 0x0  0x0 0xffe0 0x10;
-   bus-frequency = 0;// Filled out by uboot.
-
-   ecm-law@0 {
-   compatible = fsl,ecm-law;
-   reg = 0x0 0x1000;
-   fsl,num-laws = 12;
-   };
-
-   ecm@1000 {
-   compatible = fsl,p1020-ecm, fsl,ecm;
-   reg = 0x1000 0x1000;
-   interrupts = 16 2;
-   interrupt-parent = mpic;
-   };
-
-   memory-controller@2000 {
-   compatible = fsl,p1020-memory-controller;
-   reg = 0x2000 0x1000;
-   interrupt-parent = mpic;
-   interrupts = 16 2;
-   };
-
i2c@3000 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 0;
-   compatible = fsl-i2c;
-   reg = 0x3000 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
rtc@68 {
compatible = dallas,ds1339;
reg = 0x68;
};
};
 
-   i2c@3100 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 1;
-   compatible = fsl-i2c;
-   reg = 0x3100 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
-   };
-
-   serial0: serial@4500 {
-   cell-index = 0;
-   device_type = serial;
-   compatible = ns16550;
-   reg = 0x4500 0x100;
-   clock-frequency = 0;
-   interrupts = 42 2;
-   interrupt-parent = mpic;
-   };
-
-   serial1: serial@4600 {
-   cell-index = 1;
-   device_type = serial;
-   compatible = ns16550;
-   reg = 0x4600 0x100;
-   clock-frequency = 0;
-   interrupts = 42 2;
-   interrupt-parent = mpic;
-   };
-
spi@7000 {
-   cell-index = 0;
-   #address-cells = 1;
-   #size-cells

[PATCH][v2] powerpc/85xx: P1020 DTS : re-organize dts files

[Prabhakar Kushwaha]

Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Kumar Gala kumar.g...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 Please see mpc5200b.dtsi for reference.
 
 Tested on P1020RDB

 Changes for v2: Incorporated Grant Likely's comment
-updated model name

 arch/powerpc/boot/dts/p1020rdb.dts |  316 +--
 arch/powerpc/boot/dts/p1020si.dtsi |  377 
 2 files changed, 380 insertions(+), 313 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts 
b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..7ed4793 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,11 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ p1020si.dtsi
+
 / {
-   model = fsl,P1020;
+   model = fsl,P1020RDB;
compatible = fsl,P1020RDB;
-   #address-cells = 2;
-   #size-cells = 2;
 
aliases {
serial0 = serial0;
@@ -26,34 +25,11 @@
pci1 = pci1;
};
 
-   cpus {
-   #address-cells = 1;
-   #size-cells = 0;
-
-   PowerPC,P1020@0 {
-   device_type = cpu;
-   reg = 0x0;
-   next-level-cache = L2;
-   };
-
-   PowerPC,P1020@1 {
-   device_type = cpu;
-   reg = 0x1;
-   next-level-cache = L2;
-   };
-   };
-
memory {
device_type = memory;
};
 
localbus@ffe05000 {
-   #address-cells = 2;
-   #size-cells = 1;
-   compatible = fsl,p1020-elbc, fsl,elbc, simple-bus;
-   reg = 0 0xffe05000 0 0x1000;
-   interrupts = 19 2;
-   interrupt-parent = mpic;
 
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0x0 0xef00 0x0100
@@ -165,88 +141,14 @@
};
 
soc@ffe0 {
-   #address-cells = 1;
-   #size-cells = 1;
-   device_type = soc;
-   compatible = fsl,p1020-immr, simple-bus;
-   ranges = 0x0  0x0 0xffe0 0x10;
-   bus-frequency = 0;// Filled out by uboot.
-
-   ecm-law@0 {
-   compatible = fsl,ecm-law;
-   reg = 0x0 0x1000;
-   fsl,num-laws = 12;
-   };
-
-   ecm@1000 {
-   compatible = fsl,p1020-ecm, fsl,ecm;
-   reg = 0x1000 0x1000;
-   interrupts = 16 2;
-   interrupt-parent = mpic;
-   };
-
-   memory-controller@2000 {
-   compatible = fsl,p1020-memory-controller;
-   reg = 0x2000 0x1000;
-   interrupt-parent = mpic;
-   interrupts = 16 2;
-   };
-
i2c@3000 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 0;
-   compatible = fsl-i2c;
-   reg = 0x3000 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
rtc@68 {
compatible = dallas,ds1339;
reg = 0x68;
};
};
 
-   i2c@3100 {
-   #address-cells = 1;
-   #size-cells = 0;
-   cell-index = 1;
-   compatible = fsl-i2c;
-   reg = 0x3100 0x100;
-   interrupts = 43 2;
-   interrupt-parent = mpic;
-   dfsrr;
-   };
-
-   serial0: serial@4500 {
-   cell-index = 0;
-   device_type = serial;
-   compatible = ns16550;
-   reg = 0x4500 0x100;
-   clock-frequency = 0;
-   interrupts = 42 2;
-   interrupt-parent = mpic;
-   };
-
-   serial1: serial@4600 {
-   cell-index = 1;
-   device_type = serial;
-   compatible = ns16550;
-   reg = 0x4600 0x100;
-   clock-frequency = 0;
-   interrupts = 42 2;
-   interrupt-parent = mpic;
-   };
-
spi@7000

[PATCH] powerpc/kernel: Don't add disabled serial device

[Prabhakar Kushwaha]

serial port nodes with the property status=disabled are not usable and so
avoid adding disabled port with the system.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)
 
 This patch is made to support Re-organizing P1020RDB P2020RDB dts. Creation
 of Serial port node doesn't follow of_platform_device_create() way which takes
 care case status = disabled.

 arch/powerpc/kernel/legacy_serial.c |8 +---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/legacy_serial.c 
b/arch/powerpc/kernel/legacy_serial.c
index c834757..26566ca 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -330,9 +330,11 @@ void __init find_legacy_serial_ports(void)
if (!parent)
continue;
if (of_match_node(legacy_serial_parents, parent) != NULL) {
-   index = add_legacy_soc_port(np, np);
-   if (index = 0  np == stdout)
-   legacy_serial_console = index;
+   if (of_device_is_available(np)) {
+   index = add_legacy_soc_port(np, np);
+   if (index = 0  np == stdout)
+   legacy_serial_console = index;
+   }
}
of_node_put(parent);
}
-- 
1.7.3


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[PATCH] powerpc/85xx: Don't add disabled PCIe devices

[Prabhakar Kushwaha]

PCIe nodes with the property status=disabled are not usable and so
avoid adding disabled PCIe bridge with the system.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Kumar Gala kumar.g...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch 
master)

 arch/powerpc/sysdev/fsl_pci.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f8f7f28..68ca929 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -324,6 +324,11 @@ int __init fsl_add_bridge(struct device_node *dev, int 
is_primary)
struct resource rsrc;
const int *bus_range;
 
+   if (!of_device_is_available(dev)) {
+   pr_warning(%s: disabled\n, dev-full_name);
+   return -ENODEV;
+   }
+
pr_debug(Adding PCI host bridge %s\n, dev-full_name);
 
/* Fetch host bridge registers address */
-- 
1.7.3


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[PATCH] powerpc/dts:Update PCIe memory maps to match u-boot of Px020RDB

[Prabhakar Kushwaha]

PCIe memory address space is 1:1 mapped with u-boot.

Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map
changes in u-boot.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Kumar Gala kumar.g...@freescale.com
---
 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (Branch 
master)

 arch/powerpc/boot/dts/p1020rdb.dts|   12 ++--
 arch/powerpc/boot/dts/p2020rdb.dts|   12 ++--
 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts |4 ++--
 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts |   10 +-
 4 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts 
b/arch/powerpc/boot/dts/p1020rdb.dts
index 22f64b6..e0668f8 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P1020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -553,7 +553,7 @@
reg = 0 0xffe09000 0 0x1000;
bus-range = 0 255;
ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
- 0x100 0x0 0x 0 0xffc3 0x0 0x1;
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 16 2;
@@ -580,8 +580,8 @@
#address-cells = 3;
reg = 0 0xffe0a000 0 0x1000;
bus-range = 0 255;
-   ranges = 0x200 0x0 0xc000 0 0xc000 0x0 0x2000
- 0x100 0x0 0x 0 0xffc2 0x0 0x1;
+   ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc0 0x0 0x1;
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 16 2;
@@ -590,8 +590,8 @@
#size-cells = 2;
#address-cells = 3;
device_type = pci;
-   ranges = 0x200 0x0 0xc000
- 0x200 0x0 0xc000
+   ranges = 0x200 0x0 0x8000
+ 0x200 0x0 0x8000
  0x0 0x2000
 
  0x100 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts 
b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d..e2d48fd 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P2020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -537,7 +537,7 @@
reg = 0 0xffe09000 0 0x1000;
bus-range = 0 255;
ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
- 0x100 0x0 0x 0 0xffc3 0x0 0x1;
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 25 2;
@@ -564,8 +564,8 @@
#address-cells = 3;
reg = 0 0xffe0a000 0 0x1000;
bus-range = 0 255;
-   ranges = 0x200 0x0 0xc000 0 0xc000 0x0 0x2000
- 0x100 0x0 0x 0 0xffc2 0x0 0x1;
+   ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc0 0x0 0x1;
clock-frequency = ;
interrupt-parent = mpic;
interrupts = 26 2;
@@ -574,8 +574,8 @@
#size-cells = 2;
#address-cells = 3;
device_type = pci;
-   ranges = 0x200 0x0 0xc000
- 0x200 0x0 0xc000
+   ranges = 0x200 0x0 0x8000
+ 0x200 0x0 0x8000
  0x0 0x2000
 
  0x100 0x0 0x0
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts 
b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index 0fe93d0..b69c3a5 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -6,7 +6,7 @@
  * This dts file allows core0 to have

[PATCH][v3] driver/FSL SATA:Fix wrong Device Error Register usage

[Prabhakar Kushwaha]

When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.

Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.

Signed-off-by: Ashish Kalra b00...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---

 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 This patch is already gone through review of linuxppc-dev mail list.
 Making CC linuxppc-dev@lists.ozlabs.org

 Changes for v2: Incorporated Sergei Shtylyov's comment
- Put space after -
- added a line
 Changes for v3: Incorporated David Laight's comment
- Condition check for dereg 0 for hardware error

 drivers/ata/sata_fsl.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..ad84ddc 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,15 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
/* find out the offending link and qc */
if (ap-nr_pmp_links) {
+   unsigned int dev_num;
+
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
 
-   if (dereg  ap-nr_pmp_links) {
-   link = ap-pmp_link[dereg];
+   dev_num = ffs(dereg) - 1;
+   if (dev_num  ap-nr_pmp_links  dereg != 0) {
+   link = ap-pmp_link[dev_num];
ehi = link-eh_info;
qc = ata_qc_from_tag(ap, link-active_tag);
/*
-- 
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[PATCH][v2] driver/FSL SATA:Fix wrong Device Error Register usage

[Prabhakar Kushwaha]

When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.

Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.

Signed-off-by: Ashish Kalra b00...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---

 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 This patch is already gone through review of linuxppc-dev mail list.
 Making CC linuxppc-dev@lists.ozlabs.org

 Changes for v2: Incorporated Sergei Shtylyov's comment
- Put space after -

 Case when ffs return will never arise.This scenario is already been discussed
 on linuxppc-dev@lists.ozlabs.org. Please see below explanation:
 sata_fsl_error_intr() is called during device error.The mentioned scenario
 will never comes. It can be observed via code:-
if (cereg) {   -- cereg is set on command error. Means there is at 
least 1 device present.
abort = 1;
---
---
---
/* find out the offending link and qc */
if (ap-nr_pmp_links) {  -- if Port multiplier
---
---
if ((ffs(dereg)-1)  ap-nr_pmp_links) {
---
---
} else {  --  Single device
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);

 drivers/ata/sata_fsl.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..d71e7c2 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,15 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
/* find out the offending link and qc */
if (ap-nr_pmp_links) {
+   unsigned int dev_num;
+
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
 
-   if (dereg  ap-nr_pmp_links) {
-   link = ap-pmp_link[dereg];
+   dev_num = ffs(dereg) - 1;
+   if (dev_num  ap-nr_pmp_links) {
+   link = ap-pmp_link[dev_num];
ehi = link-eh_info;
qc = ata_qc_from_tag(ap, link-active_tag);
/*
-- 
1.7.3


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[PATCH] driver/FSL SATA:Fix wrong Device Error Register usage

[Prabhakar Kushwaha]

When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.

Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Ashish Kalra b00...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 This patch is already gone through review of linuxppc-dev mail list.
 Making CC linuxppc-dev@lists.ozlabs.org

 drivers/ata/sata_fsl.c |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..895771c 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,14 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
/* find out the offending link and qc */
if (ap-nr_pmp_links) {
+   unsigned int dev_num;
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
 
-   if (dereg  ap-nr_pmp_links) {
-   link = ap-pmp_link[dereg];
+   dev_num = ffs(dereg)-1;
+   if (dev_num  ap-nr_pmp_links) {
+   link = ap-pmp_link[dev_num];
ehi = link-eh_info;
qc = ata_qc_from_tag(ap, link-active_tag);
/*
-- 
1.7.3


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[PATCH] driver/FSL SATA: Update RX_WATER_MARK for TRANSCFG

[Prabhakar Kushwaha]

RX_WATER_MARK sets the number of locations in Rx FIFO that can be used before
the transport layer instructs the link layer to transmit HOLDS. Note that it
can take some time for the HOLDs to get to the other end, and that in the
interim there must be enough room in the FIFO to absorb all data that could
arrive.

Update the new recommended value to 16.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 This patch is already gone through review of linuxppc-dev mail list.
 Making CC linuxppc-dev@lists.ozlabs.org

 drivers/ata/sata_fsl.c |   12 
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 895771c..29d2f29 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -186,6 +186,11 @@ enum {
COMMANDSTAT = 0x20,
 };
 
+/* TRANSCFG (transport-layer) configuration control */
+enum {
+   TRANSCFG_RX_WATER_MARK = (1  4),
+};
+
 /* PHY (link-layer) configuration control */
 enum {
PHY_BIST_ENABLE = 0x01,
@@ -1305,6 +1310,7 @@ static int sata_fsl_probe(struct platform_device *ofdev,
struct sata_fsl_host_priv *host_priv = NULL;
int irq;
struct ata_host *host;
+   u32 temp;
 
struct ata_port_info pi = sata_fsl_port_info[0];
const struct ata_port_info *ppi[] = { pi, NULL };
@@ -1319,6 +1325,12 @@ static int sata_fsl_probe(struct platform_device *ofdev,
ssr_base = hcr_base + 0x100;
csr_base = hcr_base + 0x140;
 
+   if (!of_device_is_compatible(ofdev-dev.of_node, fsl,mpc8315-sata)) {
+   temp = ioread32(csr_base + TRANSCFG);
+   temp = temp  0xffe0;
+   iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
+   }
+
DPRINTK(@reset i/o = 0x%x\n, ioread32(csr_base + TRANSCFG));
DPRINTK(sizeof(cmd_desc) = %d\n, sizeof(struct command_desc));
DPRINTK(sizeof(#define cmd_desc) = %d\n, SATA_FSL_CMD_DESC_SIZE);
-- 
1.7.3


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[PATCH] fsl_pci: Add support for FSL PCIe controllers v2.x

[Prabhakar Kushwaha]

FSL PCIe controller v2.1:
 - New MSI inbound window
 - Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
 - Different addresses for PCIe inbound window 3,2,1
 - Exposed PCIe inbound window 0
 - New PCIe interrupt status register

Added new config and interrupt Status register to struct ccsr_pci  updated
pit_t array size to reflect the 4 inbound windows.

Device tree is used to maintain backward compatibility i.e. update inbound
window 1 index depending upon compatible field witin PCIE node.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Acked-by: Roy Zang tie-fei.z...@freescale.com
Acked-by: Kumar Gala kumar.g...@freescale.com
---

 Based upon 
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master )

 arch/powerpc/sysdev/fsl_pci.c |   15 +++
 arch/powerpc/sysdev/fsl_pci.h |   17 ++---
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 818f7c6..f8f7f28 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
 /*
  * MPC83xx/85xx/86xx PCI/PCIE support routing.
  *
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  * Copyright 2008-2009 MontaVista Software, Inc.
  *
  * Initial author: Xianghua Xiao x.x...@freescale.com
@@ -99,7 +99,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
  struct resource *rsrc)
 {
struct ccsr_pci __iomem *pci;
-   int i, j, n, mem_log, win_idx = 2;
+   int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 paddr_lo = ULLONG_MAX;
u32 pcicsrbar = 0, pcicsrbar_sz;
@@ -109,6 +109,13 @@ static void __init setup_pci_atmu(struct pci_controller 
*hose,
 
pr_debug(PCI memory map start 0x%016llx, size 0x%016llx\n,
(u64)rsrc-start, (u64)rsrc-end - (u64)rsrc-start + 1);
+
+   if (of_device_is_compatible(hose-dn, fsl,qoriq-pcie-v2.2)) {
+   win_idx = 2;
+   start_idx = 0;
+   end_idx = 3;
+   }
+
pci = ioremap(rsrc-start, rsrc-end - rsrc-start + 1);
if (!pci) {
dev_err(hose-parent, Unable to map ATMU registers\n);
@@ -118,7 +125,7 @@ static void __init setup_pci_atmu(struct pci_controller 
*hose,
/* Disable all windows (except powar0 since it's ignored) */
for(i = 1; i  5; i++)
out_be32(pci-pow[i].powar, 0);
-   for(i = 0; i  3; i++)
+   for (i = start_idx; i  end_idx; i++)
out_be32(pci-piw[i].piwar, 0);
 
/* Setup outbound MEM window */
@@ -204,7 +211,7 @@ static void __init setup_pci_atmu(struct pci_controller 
*hose,
mem_log++;
}
 
-   piwar |= (mem_log - 1);
+   piwar |= ((mem_log - 1)  PIWAR_SZ_MASK);
 
/* Setup inbound memory window */
out_be32(pci-piw[win_idx].pitar,  0x);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8ad72a1..a39ed5c 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx/86xx PCI Express structure define
  *
- * Copyright 2007 Freescale Semiconductor, Inc
+ * Copyright 2007,2011 Freescale Semiconductor, Inc
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -21,6 +21,7 @@
 #define PIWAR_TGI_LOCAL0x00f0  /* target - local 
memory */
 #define PIWAR_READ_SNOOP   0x0005
 #define PIWAR_WRITE_SNOOP  0x5000
+#define PIWAR_SZ_MASK  0x003f
 
 /* PCI/PCI Express outbound window reg */
 struct pci_outbound_window_regs {
@@ -49,7 +50,9 @@ struct ccsr_pci {
__be32  int_ack;/* 0x.008 - PCI Interrupt Acknowledge 
Register */
__be32  pex_otb_cpl_tor;/* 0x.00c - PCIE Outbound completion 
timeout register */
__be32  pex_conf_tor;   /* 0x.010 - PCIE configuration timeout 
register */
-   u8  res2[12];
+   __be32  pex_config; /* 0x.014 - PCIE CONFIG Register */
+   __be32  pex_int_status; /* 0x.018 - PCIE interrupt status */
+   u8  res2[4];
__be32  pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect 
register */
__be32  pex_pme_mes_disr;   /* 0x.024 - PCIE PME and message 
disable register */
__be32  pex_pme_mes_ier;/* 0x.028 - PCIE PME and message 
interrupt enable register */
@@ -62,14 +65,14 @@ struct ccsr_pci {
  * in all of the other outbound windows.
  */
struct pci_outbound_window_regs pow[5];
-
-   u8  res14

[PATCH][v2] driver/FSL SATA:Fix wrong Device Error Register usage

[Prabhakar Kushwaha]

When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.

Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Ashish Kalra b00...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 Changes for v1: Incorporated David Laight's comment
- Single usage of ffs()

 Changes for v2: Incorporated David Laight's comment
- Changed type of dev_num to unsigned

 drivers/ata/sata_fsl.c |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..895771c 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,14 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
/* find out the offending link and qc */
if (ap-nr_pmp_links) {
+   unsigned int dev_num;
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
 
-   if (dereg  ap-nr_pmp_links) {
-   link = ap-pmp_link[dereg];
+   dev_num = ffs(dereg)-1;
+   if (dev_num  ap-nr_pmp_links) {
+   link = ap-pmp_link[dev_num];
ehi = link-eh_info;
qc = ata_qc_from_tag(ap, link-active_tag);
/*
-- 
1.7.3


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[PATCH][v1] driver/FSL SATA:Fix wrong Device Error Register usage

[Prabhakar Kushwaha]

When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.

Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.

Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Ashish Kalra b00...@freescale.com
---
 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch 
master)

 Changes for v1: Incorporated David Laight's comment
- Single usage of ffs()

 drivers/ata/sata_fsl.c |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..895771c 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,14 @@ static void sata_fsl_error_intr(struct ata_port *ap)
 
/* find out the offending link and qc */
if (ap-nr_pmp_links) {
+   int dev_num;
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
 
-   if (dereg  ap-nr_pmp_links) {
-   link = ap-pmp_link[dereg];
+   dev_num = ffs(dereg)-1;
+   if (dev_num  ap-nr_pmp_links) {
+   link = ap-pmp_link[dev_num];
ehi = link-eh_info;
qc = ata_qc_from_tag(ap, link-active_tag);
/*
-- 
1.7.3


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