mmap() problem in own driver
Hi everyone there is a problem of my own driver I want to get data from kernel space to user space indirectly using mmap() but i dont know how I can do , anyone can give me some advices ? firstly, fetch data by DMA to a memory allocated by "kmalloc" then i want to mmap it to user space and save the data as a file Cheers everyone~ Martin -- View this message in context: http://www.nabble.com/mmap%28%29-problem-in-own-driver-tp24457031p24457031.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: question : DMA of PCI bridge
> > in the manual reference charpter 9.13 DMA, source and destination address > If you are DMAing from an internal peripheral, then it's > width will be hard-coded and can be read from the user-manual. you mean it will be set by hard circuit ? maybe i should talk with your hard engineer. but as you say, the width will be hard-coded, mean that the width can not be changed ? it can fetch 16 bits to 32bits, can not tetch 16bits to 16bits ? i am sorry about my poor English, i am not sure if i expressed clearly > If you are DMAing from a local bus then the local bus definition > should determine what happens. For example, on the MPC8349, you > can put 16-bit flash on the local bus, and configure the local > bus controller to know that it is 16-bits wide. A 32-bit access > by the CPU or DMA controller will generate two reads on the > local bus. that's right, BRx and ORx should be configured for setting width, but that is bus width, not data width. or bus width should be equal to data width what fetch from the bus ? > You can investigate to see whether the MPC8247 works similarly. all right, i will , thanks a lot -- View this message in context: http://www.nabble.com/question-%3A-DMA-of-PCI-bridge-tp23628338p23663840.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: question : DMA of PCI bridge
thank you dave for your reply my processor is MPC8247, on Linux 2.6.11 in MPC8247 manual reference, the interrupt of DMA unit belonged PCI bridge. that is different from SDMA and IDMA. through i do not know what 's the different. heard SDMA is used to transfer between CPM and 60x. DMA is used to transfer between 60x bus and PCI, or 60x bus - 60x bus. i am not sure. > Whether or not you get packing bytes when you access a > 16-bit device and transfer the data to a 32-bit destination > depends on how the device is mapped. For example, a 16-bit > device can be implemented such that it responds to 8-bit, > 16-bit, and 32-bit requests, but the 32-bit requests will > require more wait-states, since the device has to be > read from twice before constructing a 32-bit word to > place on the PCI bus. ya, that's it > Its also possible that the DMA controller can be configured > to deal with different source and destination widths. However > without knowing what processor or DMA controller you are > asking about, theres not much to say. in the manual reference charpter 9.13 DMA, source and destination address can be configured. i can not find the hint about source and destination widths configured. -- View this message in context: http://www.nabble.com/question-%3A-DMA-of-PCI-bridge-tp23628338p23647394.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
question : DMA of PCI bridge
excuse me I hate to bother everyone but I have a question about DMA of PCI bridge Now I attempt to fetch data from peripheral device to SDRAM, and it has been successed but how the DMA controller know the data bandwidth of src and dest. for example, if i get a 16bits data with a 32bits bus, and other 16bits will be set high and data will fetched into cache line of dma, then it will be wrote to 32bits SDRAM. i guess the data will be wrong, isn't ? please give me some advices. thank you -- View this message in context: http://www.nabble.com/question-%3A-DMA-of-PCI-bridge-tp23628338p23628338.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
get data failed with DMA
i tried to fetch data from periphial memories with DMA the flow as following flags = claim_dma_lock(); disable_dma(DMA_CH); clear_dma_ff(); set_dma_count(DMA_CH, 4); set_dma_addr(DMA_CH, virt_to_bus(kv_buf)); release_dma_lock(flags); enable_dma(DMA_CH); the code hault at disable_dma(DMA_CH) in addition, i defined DMA_CH as 0 for channel 0 'kv_buf' is an kernel space virtual address. i can red the correct value of periphal from this address i supposed the fault along with the configured of registers about DMA in processer. but i am not sure. give some suggestion about this, thanks! -- View this message in context: http://www.nabble.com/get-data-failed-with-DMA-tp23494879p23494879.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: PPC8247 booting error
thanks for Scott's following
> You need to pass your physical address (0xd000) to ioremap() to
> obtain a virtual address that you can dereference.
actually, i have done that like you said. pass my phy addr to a virtual
addr, but i suppose it is a kernel virtual addr. i wanna get data from phy
in my application of user space. i try it by copy_to_user transfer a kernel
virtual addr to a use virtual addr for using by user. but copy_to_user
failed...
i do it like this
ssize_t read(,char *buf,,)
{
kernel_buf = (void *)ioremap(0xD000, 4096);
copy_to_user(buf, kernel_buf, 4096);
}
--
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PPC8247 booting error
i want to mapping FIFO memory to bank 3 by configure br3 and or3 the boot info as following. in my code, i have mapped FIFO to 0xD000, then i red the value from this address. the prompts as following there is some wrong with BRx and ORx set? or something others? please give me some suggestion, thanks everyone. ## Booting image at 0040 ... Image Name: Linux-2.6.11 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:818473 Bytes = 799.3 kB Load Address: Entry Point: Verifying Checksum ... OK OK Linux version 2.6.11 (r...@localhost.localdomain) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #108 Mon May 4 22:54:23 EDT 2009 Motorola PQ2 ADS PowerPC port Built 1 zonelists Kernel command line: mem=32M console=ttyCPM0,9600 root=/dev/nfs/ rw nfsroot=192.168.0.131:/root/chengmo/fs_folder/rootfs ip=192.168.0.100:192.168.0.131:#:255.0.0.0:::off PID hash table entries: 256 (order: 8, 4096 bytes) Warning: real time clock seems stuck! Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 30632k available (1420k kernel code, 272k data, 88k init, 0k highmem) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) scheduling while atomic: swapper/0x0002/0 Call trace: [c015fe20] [c0003fe0] [c01a09b4] [c0194614] [35fc] NET: Registered protocol family 16 Sauce : fifo mapping to bank3 ! // here, indicate has enter fifo_init function, but after this... Oops: kernel access of bad area, sig: 11 [#1] PREEMPT NIP: C01A2108 LR: C01A2104 SP: C0227FC0 REGS: c0227f10 TRAP: 0300Not tainted MSR: 9032 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 11 DAR: D000, DSISR: 2000 TASK = c0220ab0[1] 'swapper' THREAD: c0226000 Last syscall: 120 GPR00: C01A2104 C0227FC0 C0220AB0 0025 0467 F0A0 0022 GPR08: 001FF1A0 D000 F0A8 C0227ED0 0001 7FBD 0200 GPR16: 0080 01FFF9E8 007FFF00 01FFA4DC 01BD92B8 0001 GPR24: 0040 C01B C016 C01A 0001 C0226000 C01A86A8 Call trace: [c0003a40] [c0006504] Kernel panic - not syncing: Attempted to kill init! here, i have other questions about these information. what dose mean by "NIP : C01A2108" ? i supposed "C01A2108" may be a address of user space, what about NIP ? and what the expression "DAR, DSISR, TASK, and GPR00-24" represent. i hope some will let me know those or recommand some book for me. thanks -- View this message in context: http://www.nabble.com/PPC8247-booting-error-tp23381214p23381214.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
read data from FIFO memories to SDRAM with DMA on MPC8247
hi all: now there was one question like this following: there are two chips which are dual-port FIFO memories on my target board. I attempt two read data with the way of DMA from FIFO to SDRAM In my point, i need a driver of DMA and a driver of FIFO but i have no idea at all that what should i do about this. anyone can give some suggestions to me? i.e. what i can do at frist? or what i can do in addition to the thing what i said. thanks Sauce -- View this message in context: http://www.nabble.com/read-data-from-FIFO-memories-to-SDRAM-with-DMA-on-MPC8247-tp23271549p23271549.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: issue at the beginning of kernel booting
evolution! kernel 2.6.11 has run on the board with u-boot 1.1.4, also, at early booting time LEDs are disabled due to MMU on and off. so i tried to turn LEDs on after start_kernel function, wow, blinking! that is before start_kernel will be done successfully. then i modified registers mapping in immap_cpm2.h and configure smc1 as serial. console worked normally. booting info as following U-Boot 1.1.4 (Apr 2 2009 - 20:05:19) MPC8272 Reset Status: External Soft, External Hard MPC8272 Clock Configuration - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300 - dfbrg 1, corecnf 0x1a, busdf 3, cpmdf 1, plldf 0, pllmf 3 - vco_out 4, scc_clk 1, brg_clk 2500 - cpu_clk 4, cpm_clk 2, bus_clk 1 Board: Motorola MPC8272ADS DRAM: 32 MB FLASH: 512 kB In:serial Out: serial Err: serial Net: FCC1 ETHERNET Hit any key to stop autoboot: 0 Using FCC1 ETHERNET device TFTP from server 192.168.0.99; our IP address is 192.168.0.100 Filename 'uImage'. Load address: 0x40 Loading: # # ### done Bytes transferred = 781091 (beb23 hex) => bootm ## Booting image at 0040 ... Image Name: Linux-2.6.11 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:781027 Bytes = 762.7 kB Load Address: Entry Point: Verifying Checksum ... OK OK Linux version 2.6.11 (r...@localhost.localdomain) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #49 Tue Apr 7 04:11:56 EDT 2009 Motorola PQ2 ADS PowerPC port Built 1 zonelists Kernel command line: mem=32M console=ttyCPM0,9600 root=/dev/mtdblock0 rw rootfstype=jffs2 PID hash table entries: 256 (order: 8, 4096 bytes) Warning: real time clock seems stuck! Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 30728k available (1304k kernel code, 276k data, 104k init, 0k highmem) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) Chengmo : Here will enter rest_init()! NET: Registered protocol family 16 PCI: Probing PCI hardware Generic RTC Driver v1.07 Serial: CPM driver $Revision: 0.01 $ ttyCPM0 at MMIO 0xf0011a80 (irq = 4) is a CPM UART io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize loop: loaded (max 8 devices) halt here~ i have tried to build newer kernel and bootloader. but LEDs were not blinking at start_kernel, i guessed something wrong with dts, i should check OF doc and dts. -- View this message in context: http://www.nabble.com/issue-at-the-beginning-of-kernel-booting-tp22741532p22931181.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: issue at the beginning of kernel booting
thanks Scott 's following > I don't quite follow the above, but what I meant is that you need to > put a mapping in place that covers your LED I/O once you have the MMU on. > Any mappings that U-boot made will be gone at that point. i am sorry for my poor expression. i think i have got your meaning about that. the suggestion from others that the situation that external access will be disabled at early booting time. i guess that means like yours, sometimes I/O disabled due to cache operating or something. certainly, if i have to turn LEDs at booting time, the way your said is the best. but i supposed i could operate LEDs after early booting time. >> i tried >> CONFIG_PPC_EARLY_DEBUG_CPM=y >> CONFIG_PPC_EARLY_DEBUG_CPM_ADDR=0xf0008 >> how can i make sure CPM_ADDR, 0xf008 is default value > Look at the u-boot source, or dump the memory and see if it looks like a > ring buffer. sorry, i mean that CPM_ADDR is address of what? address of CPM registers or something? > This is a dts-v0 tree, which implies it's fairly old. dose later dts be used in corresponding kernel version ? i guess i must read "booting-without-of.txt". many of contents in dts i have no idea. in addition, there is one more question. my RAM size is 32MBytes, my "vmlinux" size is 30MBytes, "vmlinux.o" size is 58MBytes. so , will there be something wrong at uncompressing time ? Sauce -- View this message in context: http://www.nabble.com/issue-at-the-beginning-of-kernel-booting-tp22741532p22930588.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: issue at the beginning of kernel booting
thanks Scott
> Another thing that would generally be good is to keep replies on the
> list rather than taking it to private e-mail as soon as someone replies.
> Someone else may have something helpful to say based on your followup,
> or may have the same problem and be helped by the conclusion.
ok~ excuse for my mistake, thank you for your words. i will do it like you
say from now on. it surely be better.
> I don't see where you set up a BAT that covers 0xf000.
if i have to set up a BAT that cover 0xF000. i had a debug with LEDs
like that in u-boot code. everything is //normal. 0xF is the value
of CFG_IMMR(CONFIG_SYS_IMMR) that memory map register, it is the phy address
and //base //address of all internal regishters, isnt? you mean that if i
set BATs, i should not get the phy address like in the //front ?
> Do you have a correct fdt, that matches a platform that is enabled in
> your .config?
i think so, i used mpc8272ads_defconfig becasue my processor is mpc8272, i
got a mail before about modifying and //config fdt file mpc8272ads.dts. i
fixed up my file like that.
i tried
CONFIG_PPC_EARLY_DEBUG_CPM=y
CONFIG_PPC_EARLY_DEBUG_CPM_ADDR=0xf0008
how can i make sure CPM_ADDR, 0xf008 is default value
now it show as follow. i select smc1 as console. please check it and give me
some advice.
/ {
model = "MPC8272ADS";
compatible = "fsl,mpc8272ads";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8...@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = ;
i-cache-line-size = ;
d-cache-size = ;
i-cache-size = ;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0 0>;
};
local...@f0010100 {
compatible = "fsl,mpc8272-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = ;
/* chengmo : modify by my own device */
ranges = <0 0 FFF0 0008 //CS0: Flahs 512k
2 0 0200 //CS2: SDRAM 32M
>;
fl...@0,0 {
compatible = "cfi-flash";
reg = <0 0 0008>;
bank-width = <4>;
device-width = <1>; // 16 bits
};
PCI_PIC: interrupt-control...@3,0 {
compatible = "fsl,mpc8272ads-pci-pic",
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
reg = <3 0 8>;
interrupt-parent = <&PIC>;
interrupts = <14 8>;
};
};
s...@f000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
ranges = < f000 00053000>;
// Temporary -- will go away once kernel uses ranges for
get_immrbase().
reg = ;
c...@119c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30>;
ranges;
mu...@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 1>;
d...@0 {
compatible = "fsl,cpm-muram-data";
reg = <0 2000 9800 800>;
};
};
b...@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
};
ser...@11a82 {
device_type = "serial";
compatible = "fsl,mpc8272-smc-uart",
"fsl,cpm2-smc-uart";
reg = <11a82 20 87FC 100>;
interrupts = <28 8>;
Re: issue at the beginning of kernel booting
thanks Scott! > That is very old code; you're more likely to get help when running > something up-to-date. i have a latest u-boot-2009.03 updated instead of mine, and kernel version is instead of 2.6.24.5 > This alternative was listed as text/plain. is not plaintext. > Please fix your mailer (and better yet, don't send HTML at all). yeah, it is my fault. i am a newer of mail lists , i will be careful next time. > I doubt that it is actually halting here; more likely, you're just > hitting a spot in the boot sequence where it's not safe to access your > LEDs or other I/O, because you have the MMU off and the cache enabled. > You'll typically be much better off leaving the very early code alone > (it's almost never the culprit), except to ensure that you have a BAT > mapping (cache-inhibited and guarded) for the I/O you want to use for > debugging. Then, only touch that I/O device *after* the MMU is on and > your mapping is in place. according to your point, i have moved the codes used for debuging to the place where after mmu being on, then there is nothing happened. it indicated that proforming had halt before this. i dont think there may be likely had some wrong in kernel source. but actually it halt there in early code. first i guess the reason that before i boot kernel without fdt. it still halt after wiht fdt. now i show my early code with debug code, please check it what fault is more likely. early code /* initialize LEDs, used by Port B */ lis r8, (0x00FF)@h ori r8, r8, (0x00FF)@l lis r9, (M8247_IOP_PDIRB(0xF000))@h //define 0x10D20 as M8247_IOP_PDIRB(Port B dir) lis r9, r9, (M8247_IOP_PDIRB(0xF000))@l //define 0x10D30 as M8247_IOP_PDATB(Port B dat) stw r8, 0(r9) /* turn D1 , successful */ lis r8, (0xFFFE)@h ori r8, r8, (0xFFFE)@l lis r9, (M8247_IOP_PDATB(0xF000))@h lis r9, r9, (M8247_IOP_PDATB(0xF000))@l stw r8, 0(r9) bl early_init /* here : mmu off: */ addir4, r3, __after_mmu_off - _start mfmsr r3 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ beqlr andcr3,r3,r0 mtspr SPRN_SRR0,r4 mtspr SPRN_SRR1,r3 sync RFI __after_mmu_off: /* here : clear_bats: */ li r10,0 mfspr r9,SPRN_PVR rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ cmpwi r9, 1 beq 1f // my core is 603e, so both DBATx and IBATx should be initialized. mtspr SPRN_DBAT0U,r10 . . . mtspr SPRN_DBAT3L,r10 1: mtspr SPRN_IBAT0U,r10 . . . mtspr SPRN_IBAT3L,r10 BEGIN_FTR_SECTION // CPU_FTR_HAS_HIGH_BATS is default feature for G2_LE core mtspr SPRN_DBAT4U,r10 . . . mtspr SPRN_IBAT7L,r10 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) blr /* here: flush_tlbs: */ lis r10, 0x40 1: addic. r10, r10, -0x1000 tlbie r10 blt 1b sync blr /* here : initial_bats: */ lis r11,kernelb...@h mfspr r9,SPRN_PVR rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ cmpwi 0,r9,1 bne 4f 4: tophys(r8,r11) ori r8,r8,2 /* R/W access */ ori r11,r11,BL_16M<<2|0x2 /* set up BAT registers for 604 */ mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ mtspr SPRN_IBAT0L,r8 mtspr SPRN_IBAT0U,r11 isync blr bl reloc_offset li r24,0 /* cpu# */ bl call_setup_cpu /* Call setup_cpu for this CPU */ here jump to call_setup_cpu, actually invoked setup_common_caches. setup_common_caches: /* turn D1 and D2 , successful */ lis r15, (0xFFFC)@h ori r15, r15, (0xFFFC)@l lis r16, (M8247_IOP_PDATB(0xF000))@h lis r16, r16, (M8247_IOP_PDATB(0xF000))@l stw r15, 0(r16) mfspr r11,SPRN_HID0 andi. r0,r11,HID0_DCE ori r11,r11,HID0_ICE|HID0_DCE ori r8,r11,HID0_ICFI bne 1f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ 1: sync mtspr SPRN_HID0,r8/* enable and invalidate caches */ /* turn D1,D2 and D3 , fault */ lis r15, (0xFFF8)@h ori r15, r15, (0xFFF8)@l lis r16,
