[PATCH] powerpc/t1023rdb/dts: set ifc nand chip select from 2 to 1
From: Jaiprakash Singh b44...@freescale.com IFC NAND chip select is wrongly mapped to 2 in reg property of NAND node. Due to this kernel is not able probe NAND flash. Set chip select to 1 in reg property. Signed-off-by: Jaiprakash Singh b44...@freescale.com Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/boot/dts/t1023rdb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/boot/dts/t1023rdb.dts b/arch/powerpc/boot/dts/t1023rdb.dts index 7db5093..4aa16c3 100644 --- a/arch/powerpc/boot/dts/t1023rdb.dts +++ b/arch/powerpc/boot/dts/t1023rdb.dts @@ -60,7 +60,7 @@ #address-cells = 1; #size-cells = 1; compatible = fsl,ifc-nand; - reg = 0x2 0x0 0x1; + reg = 0x1 0x0 0x1; }; }; -- 2.1.0.27.g96db324 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2 v2] powerpc/t1024rdb: add ina220 current sensor node
Add support for INA220 current sensor.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: rename node name to 'current-sensor' for generic.
arch/powerpc/boot/dts/t1024rdb.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
index 733e723..bf05e32 100644
--- a/arch/powerpc/boot/dts/t1024rdb.dts
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -114,6 +114,12 @@
reg = 0x4c;
};
+ current-sensor@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+
eeprom@50 {
compatible = atmel,24c256;
reg = 0x50;
--
2.1.0.27.g96db324
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[PATCH 2/2 v2] powerpc/t1023rdb: add ina220 current sensor node
Add support for INA220 current sensor.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: rename node name to 'current-sensor' for generic.
arch/powerpc/boot/dts/t1023rdb.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
index 06b090a..aa50885 100644
--- a/arch/powerpc/boot/dts/t1023rdb.dts
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -99,6 +99,17 @@
};
i2c@118100 {
+ current-sensor@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+
+ current-sensor@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
};
};
--
2.1.0.27.g96db324
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[PATCH 1/2] powerpc/t1024rdb: add ina220 current sense node
Add support for INA220 current sense.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024rdb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
index 733e723..43474d9 100644
--- a/arch/powerpc/boot/dts/t1024rdb.dts
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -114,6 +114,13 @@
reg = 0x4c;
};
+ /* INA220 Current Sense */
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+
eeprom@50 {
compatible = atmel,24c256;
reg = 0x50;
--
2.1.0.27.g96db324
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[PATCH 2/2] powerpc/t1023rdb: add ina220 current sense node
Add support for INA220 current sense.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1023rdb.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
index 06b090a..a1c647b 100644
--- a/arch/powerpc/boot/dts/t1023rdb.dts
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -99,6 +99,17 @@
};
i2c@118100 {
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+
+ ina220@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
};
};
--
2.1.0.27.g96db324
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[PATCH 1/4 v4] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v4: removed qoriq-tdm1.0.dtsi
v3: use qoriq-clockgen2.dtsi
v2: removed sleep.
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 330
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 100 +
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 87
3 files changed, 517 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..dbe6578
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,330 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+pci0 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ fsl,iommu-parent = pamu0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+pci1 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci
[PATCH 3/4 v3] powerpc/fsl-booke: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- Memory: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 1G RGMII ports, one 2.5G SGMII port and one 10G Base-T port
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management support
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: no change.
v2: Integrated scott's comments.
arch/powerpc/boot/dts/t1024rdb.dts| 185 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 187 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024rdb.dts
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
new file mode 100644
index 000..eb1d51b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -0,0 +1,185 @@
+/*
+ * T1024 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024RDB;
+ compatible = fsl,T1024RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+
+ board-control@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,t1024-cpld;
+ reg = 3 0 0x300;
+ ranges = 0 3 0 0x300;
+ bank-width = 1;
+ device-width = 1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f
[PATCH 4/4 v3] powerpc/fsl-booke: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC flash on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: no change
v2: no change
arch/powerpc/boot/dts/t1023rdb.dts| 151 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
2 files changed, 152 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t1023rdb.dts
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
new file mode 100644
index 000..3780e68
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -0,0 +1,151 @@
+/*
+ * T1023 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1023RDB;
+ compatible = fsl,T1023RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xff80 0x0001;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ status = disabled;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges = 0x 0xf 0x 0x01072000;
+ };
+
+ soc: soc@ffe00 {
+ ranges = 0x 0xf 0xfe00 0x100;
+ reg = 0xf 0xfe00 0 0x1000;
+ spi@11 {
+ flash@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion
[PATCH 2/4 v3] powerpc/fsl-booke: Add T1024 QDS board support
Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and
Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from
GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type
mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: no change
v2: no change
arch/powerpc/boot/dts/t1024qds.dts| 251 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024qds.dts
diff --git a/arch/powerpc/boot/dts/t1024qds.dts
b/arch/powerpc/boot/dts/t1024qds.dts
new file mode 100644
index 000..14122cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024qds.dts
@@ -0,0 +1,251 @@
+/*
+ * T1024 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024QDS;
+ compatible = fsl,T1024QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@2,0
[PATCH 1/4 v3] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: use qoriq-clockgen2.dtsi
v2: Integrated scott's comments.
note: qoriq-tdm1.0.dtsi depends on patch
http://patchwork.ozlabs.org/patch/457605/
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 330
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 102 +
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 87
3 files changed, 519 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..dbe6578
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,330 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+pci0 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ fsl,iommu-parent = pamu0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+pci1 {
+ compatible = fsl,t1023-pcie
[PATCH 3/4 v2] powerpc/fsl-booke: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- Memory: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 1G RGMII ports, one 2.5G SGMII port and one 10G Base-T port
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management support
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: Integrated scott's comments.
arch/powerpc/boot/dts/t1024rdb.dts| 185 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 187 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024rdb.dts
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
new file mode 100644
index 000..eb1d51b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -0,0 +1,185 @@
+/*
+ * T1024 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024RDB;
+ compatible = fsl,T1024RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+
+ board-control@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,t1024-cpld;
+ reg = 3 0 0x300;
+ ranges = 0 3 0 0x300;
+ bank-width = 1;
+ device-width = 1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges
[PATCH 1/4 v2] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: Integrated scott's comments.
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 343
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 103 +
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 87 +++
3 files changed, 533 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..cbb3500
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,343 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+pci0 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ fsl,iommu-parent = pamu0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+pci1 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3
[PATCH 2/4 v2] powerpc/fsl-booke: Add T1024 QDS board support
Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and
Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from
GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type
mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: no change
arch/powerpc/boot/dts/t1024qds.dts| 251 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024qds.dts
diff --git a/arch/powerpc/boot/dts/t1024qds.dts
b/arch/powerpc/boot/dts/t1024qds.dts
new file mode 100644
index 000..14122cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024qds.dts
@@ -0,0 +1,251 @@
+/*
+ * T1024 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024QDS;
+ compatible = fsl,T1024QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@2,0
[PATCH 4/4 v2] powerpc/fsl-booke: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC flash on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: no change
arch/powerpc/boot/dts/t1023rdb.dts| 151 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
2 files changed, 152 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t1023rdb.dts
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
new file mode 100644
index 000..3780e68
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -0,0 +1,151 @@
+/*
+ * T1023 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1023RDB;
+ compatible = fsl,T1023RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xff80 0x0001;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ status = disabled;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges = 0x 0xf 0x 0x01072000;
+ };
+
+ soc: soc@ffe00 {
+ ranges = 0x 0xf 0xfe00 0x100;
+ reg = 0xf 0xfe00 0 0x1000;
+ spi@11 {
+ flash@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25fl512s
[PATCH 2/4] powerpc/fsl-booke: Add T1024 QDS board support
Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and
Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from
GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type
mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024qds.dts| 89 ++
arch/powerpc/boot/dts/t102xqds.dtsi | 247 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
4 files changed, 338 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024qds.dts
create mode 100644 arch/powerpc/boot/dts/t102xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t1024qds.dts
b/arch/powerpc/boot/dts/t1024qds.dts
new file mode 100644
index 000..35e0d34
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024qds.dts
@@ -0,0 +1,89 @@
+/*
+ * T1024 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+/include/ t102xqds.dtsi
+
+/ {
+ model = fsl,T1024QDS;
+ compatible = fsl,T1024QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ qe: qe@ffe14 {
+ ranges = 0x0 0xf 0xfe14 0x4;
+ reg = 0xf 0xfe14 0 0x480;
+ brg-frequency = 0;
+ bus-frequency = 0;
+
+ si1: si@700 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,qe-si;
+ reg = 0x700 0x80;
+ };
+
+ siram1: siram@1000
[PATCH 1/4] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 349
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 97
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 87 +++
3 files changed, 533 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..5db23a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,349 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+pci0 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ fsl,iommu-parent = pamu0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+pci1 {
+ compatible = fsl,t1023-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 0xff
[PATCH 3/4] powerpc/fsl-booke: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- DDR: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 10M/100M/1Gbps RGMII ports and one 10Gbps Base-T port on-board
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management support
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024rdb.dts| 235 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024rdb.dts
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
new file mode 100644
index 000..4c85599
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -0,0 +1,235 @@
+/*
+ * T1024 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024RDB;
+ compatible = fsl,T1024RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+
+ board-control@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,t1024-cpld, fsl,deepsleep-cpld;
+ reg = 3 0 0x300;
+ ranges = 0 3 0 0x300;
+ bank-width = 1;
+ device-width = 1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges = 0x 0xf
[PATCH 4/4] powerpc/fsl-booke: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC flash on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1023rdb.dts| 151 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
2 files changed, 152 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t1023rdb.dts
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
new file mode 100644
index 000..3780e68
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -0,0 +1,151 @@
+/*
+ * T1023 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1023RDB;
+ compatible = fsl,T1023RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xff80 0x0001;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ status = disabled;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges = 0x 0xf 0x 0x01072000;
+ };
+
+ soc: soc@ffe00 {
+ ranges = 0x 0xf 0xfe00 0x100;
+ reg = 0xf 0xfe00 0 0x1000;
+ spi@11 {
+ flash@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25fl512s
[PATCH] t2080qds/rtc: fix rtc interrupt
RTC interrupt uses IRQ11 on T2080QDS.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t208xqds.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/t208xqds.dtsi
b/arch/powerpc/boot/dts/t208xqds.dtsi
index 5906183..024cc96 100644
--- a/arch/powerpc/boot/dts/t208xqds.dtsi
+++ b/arch/powerpc/boot/dts/t208xqds.dtsi
@@ -137,7 +137,7 @@
rtc@68 {
compatible = dallas,ds3232;
reg = 0x68;
- interrupts = 0x1 0x1 0 0;
+ interrupts = 0xb 0x1 0 0;
};
};
--
2.1.0.27.g96db324
___
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https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] mtd/spi: support en25s64 device
Add support for EON en25s64 spi device.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0f8ec3c..f8acef7 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -524,6 +524,7 @@ static const struct spi_device_id spi_nor_ids[] = {
{ en25q64,INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ en25qh128, INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
{ en25qh256, INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
+ { en25s64,INFO(0x1c3817, 0, 64 * 1024, 128, 0) },
/* ESMT */
{ f25l32pa, INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
--
2.1.0.27.g96db324
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[PATCH] powerpc/defconfig: enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x
By default we enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x, which are needed on T2080QDS, T4240QDS, B4860QDS, etc. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- against 'next' branch of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git arch/powerpc/configs/corenet32_smp_defconfig | 2 ++ arch/powerpc/configs/corenet64_smp_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 51866f1..6cf323f 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -114,6 +114,8 @@ CONFIG_NVRAM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index d6c0c81..9d8ca81 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -99,6 +99,8 @@ CONFIG_SERIAL_8250_RSA=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y -- 2.1.0.27.g96db324 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/4] powerpc/fsl-booke: Add T1024RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- DDR: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 10M/100M/1Gbps RGMII ports and one 10Gbps Base-T port on-board
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management implementaion
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024rdb.dts| 185 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
3 files changed, 187 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024rdb.dts
diff --git a/arch/powerpc/boot/dts/t1024rdb.dts
b/arch/powerpc/boot/dts/t1024rdb.dts
new file mode 100644
index 000..a6b88e3
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024rdb.dts
@@ -0,0 +1,185 @@
+/*
+ * T1024 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1024RDB;
+ compatible = fsl,T1024RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 2 0 0xf 0xff80 0x0001
+ 3 0 0xf 0xffdf 0x8000;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+
+ board-control@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,t1024-cpld, fsl,deepsleep-cpld;
+ reg = 3 0 0x300;
+ ranges = 0 3 0 0x300;
+ bank-width = 1;
+ device-width = 1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges
[PATCH 4/4] powerpc/fsl-booke: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC and eMMC card
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1023rdb.dts| 150 ++
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
2 files changed, 151 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t1023rdb.dts
diff --git a/arch/powerpc/boot/dts/t1023rdb.dts
b/arch/powerpc/boot/dts/t1023rdb.dts
new file mode 100644
index 000..b187cfe
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1023rdb.dts
@@ -0,0 +1,150 @@
+/*
+ * T1023 RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+
+/ {
+ model = fsl,T1023RDB;
+ compatible = fsl,T1023RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ ifc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x2000;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xff80 0x0001;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,ifc-nand;
+ reg = 0x2 0x0 0x1;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ };
+
+ dcsr: dcsr@f {
+ ranges = 0x 0xf 0x 0x01072000;
+ };
+
+ soc: soc@ffe00 {
+ ranges = 0x 0xf 0xfe00 0x100;
+ reg = 0xf 0xfe00 0 0x1000;
+ spi@11 {
+ flash@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25fl512s;
+ reg = 0;
+ spi
[PATCH 1/4] powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 351
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 50
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 88 +++
3 files changed, 489 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t1024si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
new file mode 100644
index 000..23fbc5d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -0,0 +1,351 @@
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+pci0 {
+ compatible = fsl,t1024-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ fsl,iommu-parent = pamu0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
+ ;
+ };
+};
+
+pci1 {
+ compatible = fsl,t1024-pcie, fsl,qoriq-pcie-v2.4, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 0xff
[PATCH 2/4] powerpc/fsl-booke: Add T1024 QDS board support
Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and
Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications
peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from
GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type
mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t1024qds.dts| 46 +
arch/powerpc/boot/dts/t102xqds.dtsi | 247 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 1 +
4 files changed, 295 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t1024qds.dts
create mode 100644 arch/powerpc/boot/dts/t102xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t1024qds.dts
b/arch/powerpc/boot/dts/t1024qds.dts
new file mode 100644
index 000..30d0d51
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1024qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1024 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t102xsi-pre.dtsi
+/include/ t102xqds.dtsi
+
+/ {
+ model = fsl,T1024QDS;
+ compatible = fsl,T1024QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+};
+
+/include/ fsl/t1024si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t102xqds.dtsi
b/arch/powerpc/boot/dts/t102xqds.dtsi
new file mode 100644
index 000..a7eae95
--- /dev/null
+++ b/arch/powerpc/boot/dts/t102xqds.dtsi
@@ -0,0 +1,247 @@
+/*
+ * T102x QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met
[PATCH v5] powerpc/t2080rdb: Add T2080RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts T2080 SoC.
The board feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 1Gbps RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
IFC/Local Bus
- NOR: 128MB 16-bit NOR flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 goldfinger(support SR-IOV)
- One PCIe x4 slot
- One PCIe x2 end-point device (C293 crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a MicroSD/TF card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v5: updated i2c nodes.
v4: no change.
v3: no change.
arch/powerpc/boot/dts/t2080rdb.dts| 57
arch/powerpc/boot/dts/t208xrdb.dtsi | 184 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +
4 files changed, 244 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080rdb.dts
create mode 100644 arch/powerpc/boot/dts/t208xrdb.dtsi
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts
b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000..e889104
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xrdb.dtsi
+
+/ {
+ model = fsl,T2080RDB;
+ compatible = fsl,T2080RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi
b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000..1481e19
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,184 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials
[PATCH] of: Add vendor prefix for EON Corporation
Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1a6793b..3c10a21 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -42,6 +42,7 @@ ebv EBV Elektronik edtEmerging Display Technologies emmicroEM Microelectronic epfl Ecole Polytechnique Fédérale de Lausanne +eonEon Silicon Solution, Inc. epson Seiko Epson Corp. estESTeem Wireless Modems eukrea Eukréa Electromatique -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3 v4] powerpc/fsl-booke: Add support for T2080/T2081 SoC
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
Architecture processor cores with high-performance datapath acceleration
logic and network and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and mil/aerospace applications.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 with following difference:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v4: add fsl,portid-mapping.
v3: added pamu node and updated clockgen.
v2: updated with some comments.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 69 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 435
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 99 +++
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 605 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..082ec20
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,69 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+ sata@22 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+ };
+
+/include/ qoriq-sata2-1.dtsi
+ sata@221000 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+ };
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2
[PATCH 2/3 v4] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP
- Dual DIMM slots up 2133MT/s with ECC
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 8MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0, SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
T2081QDS board shares the same PCB with T1040QDS with some differences.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v4: no change.
v3: no change.
arch/powerpc/boot/dts/t2080qds.dts| 57 ++
arch/powerpc/boot/dts/t2081qds.dts| 46 +
arch/powerpc/boot/dts/t208xqds.dtsi | 239 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t2081qds.dts
b/arch/powerpc/boot/dts/t2081qds.dts
new file mode 100644
index 000..8ec80a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2081qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T2081QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale
[PATCH 3/3 v4] powerpc/t2080rdb: Add T2080RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts T2080 SoC.
The board feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 1Gbps RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 MAC2)
- SerDes-1 Lane E-H: to PCIe slot (PEX4 Gen3 x4)
- SerDes-2 Lane A-D: to PCIe finger (PEX1 x4)
- SerDes-2 Lane E-F: to C293 secure co-processor (PEX2 x2)
- SerDes-2 Lane G-H: to SATA1 SATA2
IFC/Local Bus
- NOR: 128MB 16-bit NOR flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 goldfinger
- One PCIe x4 slot
- One PCIe x2 end-point device (C293 crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a MicroSD/TF card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v4: no change.
v3: no change.
arch/powerpc/boot/dts/t2080rdb.dts| 57
arch/powerpc/boot/dts/t208xrdb.dtsi | 197 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +
4 files changed, 257 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080rdb.dts
create mode 100644 arch/powerpc/boot/dts/t208xrdb.dtsi
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts
b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000..e889104
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xrdb.dtsi
+
+/ {
+ model = fsl,T2080RDB;
+ compatible = fsl,T2080RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi
b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000..3b85985
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,197 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must
[PATCH 1/3 v3] powerpc/fsl-booke: Add support for T2080/T2081 SoC
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
Architecture processor cores with high-performance datapath acceleration
logic and network and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and mil/aerospace applications.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 with following difference:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: added pamu node and updated clockgen.
v2: updated with some comments.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 69 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 434
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 91 ++
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 596 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..082ec20
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,69 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+ sata@22 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x550; /* SATA1LIODNR */
+ };
+
+/include/ qoriq-sata2-1.dtsi
+ sata@221000 {
+ fsl,iommu-parent = pamu1;
+ fsl,liodn-reg = guts 0x554; /* SATA2LIODNR */
+ };
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2
[PATCH 2/3 v3] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP
- Dual DIMM slots up 2133MT/s with ECC
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 8MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0, SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
T2081QDS board shares the same PCB with T1040QDS with some differences.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: no change.
v2: updated with some comments.
arch/powerpc/boot/dts/t2080qds.dts| 57 ++
arch/powerpc/boot/dts/t2081qds.dts| 46 +
arch/powerpc/boot/dts/t208xqds.dtsi | 239 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t2081qds.dts
b/arch/powerpc/boot/dts/t2081qds.dts
new file mode 100644
index 000..8ec80a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2081qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T2081QDS Device Tree Source
+ *
+ * Copyright
[PATCH 3/3 v3] powerpc/t2080rdb: Add T2080RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts T2080 SoC.
The board feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 1Gbps RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 MAC2)
- SerDes-1 Lane E-H: to PCIe slot (PEX4 Gen3 x4)
- SerDes-2 Lane A-D: to PCIe finger (PEX1 x4)
- SerDes-2 Lane E-F: to C293 secure co-processor (PEX2 x2)
- SerDes-2 Lane G-H: to SATA1 SATA2
IFC/Local Bus
- NOR: 128MB 16-bit NOR flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 goldfinger
- One PCIe x4 slot
- One PCIe x2 end-point device (C293 crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a MicroSD/TF card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: no change.
v2: updated with some comments.
arch/powerpc/boot/dts/t2080rdb.dts| 57
arch/powerpc/boot/dts/t208xrdb.dtsi | 197 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +
4 files changed, 257 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080rdb.dts
create mode 100644 arch/powerpc/boot/dts/t208xrdb.dtsi
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts
b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000..e889104
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xrdb.dtsi
+
+/ {
+ model = fsl,T2080RDB;
+ compatible = fsl,T2080RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi
b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000..3b85985
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,197 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions
[PATCH v2] powerpc/defconfig: update RTC support
- remove CONFIG_RTC_DRV_CMOS in corenet32_smp_defconfig(it's unused), reserve CONFIG_RTC_DRV_CMOS in mpc85xx_defconfig(needed on some CDS boards) - enable CONFIG_RTC_DRV_DS1307, CONFIG_RTC_DRV_DS1374, CONFIG_RTC_DRV_DS3232 in mpc85xx_defconfig, mpc85xx_smp_defconfig - enable RTC support in corenet64_smp_defconfig Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v2: updated with comments. arch/powerpc/configs/corenet32_smp_defconfig | 3 ++- arch/powerpc/configs/corenet64_smp_defconfig | 4 arch/powerpc/configs/mpc85xx_defconfig | 3 +++ arch/powerpc/configs/mpc85xx_smp_defconfig | 3 +++ 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index bbd794d..9866898 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -138,8 +138,9 @@ CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_MPC85XX=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_CMOS=y CONFIG_UIO=y CONFIG_STAGING=y CONFIG_VIRT_DRIVERS=y diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 63508dd..bdae4d0 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -125,6 +125,10 @@ CONFIG_USB_EHCI_FSL=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=y +CONFIG_RTC_DRV_DS3232=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_DMADEVICES=y diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index d2e0fab..541a5b6 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -210,6 +210,9 @@ CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=y +CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_CMOS=y CONFIG_DMADEVICES=y CONFIG_FSL_DMA=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 4cb7b59..105991a 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -211,6 +211,9 @@ CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=y +CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_CMOS=y CONFIG_DMADEVICES=y CONFIG_FSL_DMA=y -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3 v2] powerpc/fsl-booke: Add support for T2080/T2081 SoC
Add support for T2080/T2081 SoC without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 with following difference:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: updated with some comments.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 384
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 91 +++
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 537 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..4311560
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,384 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source
[PATCH v2] powerpc/t2080rdb: Add T2080RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts T2080 SoC.
The board feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 1Gbps RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 MAC2)
- SerDes-1 Lane E-H: to PCIe slot (PEX4 Gen3 x4)
- SerDes-2 Lane A-D: to PCIe finger (PEX1 x4)
- SerDes-2 Lane E-F: to C293 secure co-processor (PEX2 x2)
- SerDes-2 Lane G-H: to SATA1 SATA2
IFC/Local Bus
- NOR: 128MB 16-bit NOR flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 goldfinger
- One PCIe x4 slot
- One PCIe x2 end-point device (C293 crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a MicroSD/TF card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: updated with some comments.
arch/powerpc/boot/dts/t2080rdb.dts| 57
arch/powerpc/boot/dts/t208xrdb.dtsi | 197 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +
4 files changed, 257 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080rdb.dts
create mode 100644 arch/powerpc/boot/dts/t208xrdb.dtsi
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts
b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000..e889104
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xrdb.dtsi
+
+/ {
+ model = fsl,T2080RDB;
+ compatible = fsl,T2080RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi
b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000..3b85985
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,197 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must
[PATCH v2] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP
- Dual DIMM slots up 2133MT/s with ECC
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 8MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0, SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
T2081QDS board shares the same PCB with T1040QDS with some differences.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: updated with some comments.
arch/powerpc/boot/dts/t2080qds.dts| 57 ++
arch/powerpc/boot/dts/t2081qds.dts| 46 +
arch/powerpc/boot/dts/t208xqds.dtsi | 239 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t2081qds.dts
b/arch/powerpc/boot/dts/t2081qds.dts
new file mode 100644
index 000..8ec80a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2081qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T2081QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale
[PATCH 2/2] powerpc/corenet64_smp_defconfig: enable RTC support
Enable RTC support for DS1307, DS1374, DS3232, which is needed on some corenet boards. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet64_smp_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 63508dd..e9c9f86 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -125,6 +125,11 @@ CONFIG_USB_EHCI_FSL=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=y +CONFIG_RTC_DRV_DS3232=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_DMADEVICES=y -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] mtd/spi: support en25s64 device
Add support for EON en25s64 spi device.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/mtd/devices/m25p80.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7eda71d..6989311 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -745,6 +745,7 @@ static const struct spi_device_id m25p_ids[] = {
{ en25q32b, INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
{ en25p64,INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
{ en25q64,INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
+ { en25s64,INFO(0x1c3817, 0, 64 * 1024, 128, 0) },
{ en25qh256, INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
/* ESMT */
--
1.8.0
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[PATCH] powerpc/corenet64_smp_defconfig: enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x
By default we enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x, which are needed on T2080QDS, T4240QDS, B4860QDS, etc. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet64_smp_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 63508dd..bbd70bb 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -111,6 +111,8 @@ CONFIG_SERIAL_8250_RSA=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y -- 1.8.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] net/phy: tune get_phy_c45_ids to support more c45 phy
As some C45 10G PHYs(e.g. Cortina CS4315/CS4340 PHY) have
zero Devices In package, current driver can't get correct
devices_in_package value by non-zero Devices In package.
so let's probe more with zero Devices In package to support
more C45 PHYs which have zero Devices In package.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Tested with CS4315 on T2080RDB, this patch have no impact on previous XAUI phy
with verification.
drivers/net/phy/phy_device.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index cfb5110..8fd777e 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -244,12 +244,29 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr,
u32 *phy_id,
return -EIO;
c45_ids-devices_in_package |= (phy_reg 0x);
- /* If mostly Fs, there is no device there,
-* let's get out of here.
+ /* If mostly Fs, let's continue to probe more
+* as some 10G PHYs have zero Devices In package
+* e.g. Cortina CS4315/CS4340 PHY.
*/
if ((c45_ids-devices_in_package 0x1fff) == 0x1fff) {
- *phy_id = 0x;
- return 0;
+ reg_addr = MII_ADDR_C45 | 0 16 | 6;
+ phy_reg = mdiobus_read(bus, addr, reg_addr);
+ if (phy_reg 0)
+ return -EIO;
+ c45_ids-devices_in_package = (phy_reg 0x) 16;
+ reg_addr = MII_ADDR_C45 | 0 16 | 5;
+ phy_reg = mdiobus_read(bus, addr, reg_addr);
+ if (phy_reg 0)
+ return -EIO;
+ c45_ids-devices_in_package |= (phy_reg 0x);
+ /* If mostly Fs, there is no device there,
+* let's get out of here.
+*/
+ if ((c45_ids-devices_in_package 0x1fff) ==
+ 0x1fff) {
+ *phy_id = 0x;
+ return 0;
+ }
}
}
--
1.8.0
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[PATCH] net/phy: Add Cortina CS43xx PHY support
Add support for Cortina CS4315/CS4340 10G PHY.
(Tested with CS4315 on T2080RDB and CS4340 on T4240RDB).
Signed-off-by: YongHua Cao b43...@freescale.com
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/net/phy/Kconfig | 5 +++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/cortina.c | 92 +++
3 files changed, 98 insertions(+)
create mode 100644 drivers/net/phy/cortina.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1d18443..f7d6c8c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -60,6 +60,11 @@ config VITESSE_PHY
---help---
Currently supports the vsc8244
+config CORTINA_PHY
+ tristate Drivers for the Cortina PHYs
+ ---help---
+ Currently supports the CS4315 and CS4340 PHY.
+
config SMSC_PHY
tristate Drivers for SMSC PHYs
---help---
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a4f96b7..4047042 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_QSEMI_PHY)+= qsemi.o
obj-$(CONFIG_SMSC_PHY) += smsc.o
obj-$(CONFIG_VITESSE_PHY) += vitesse.o
+obj-$(CONFIG_CORTINA_PHY) += cortina.o
obj-$(CONFIG_BROADCOM_PHY) += broadcom.o
obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
new file mode 100644
index 000..154827c
--- /dev/null
+++ b/drivers/net/phy/cortina.c
@@ -0,0 +1,92 @@
+/* Driver for Cortina PHYs
+ *
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mii.h
+#include linux/ethtool.h
+#include linux/phy.h
+
+#define PHY_ID_CS4340 0x13e51002
+
+MODULE_DESCRIPTION(Cortina PHY driver);
+MODULE_AUTHOR(Caoyh);
+MODULE_LICENSE(GPL);
+
+static int cs4340_config_init(struct phy_device *phydev)
+{
+ phydev-supported = SUPPORTED_1baseT_Full;
+ phydev-advertising = SUPPORTED_1baseT_Full;
+
+ return 0;
+}
+
+static int cs4340_config_aneg(struct phy_device *phydev)
+{
+ return 0;
+}
+
+static int cs4340_read_status(struct phy_device *phydev)
+{
+ phydev-link = 1;
+ phydev-speed = 1;
+ phydev-duplex = DUPLEX_FULL;
+ return 0;
+}
+
+static int cs4340_ack_interrupt(struct phy_device *phydev)
+{
+ return 0;
+}
+
+static int cs4340_config_intr(struct phy_device *phydev)
+{
+ return 0;
+}
+
+static struct phy_driver cs4340_driver = {
+ .phy_id = PHY_ID_CS4340,
+ .phy_id_mask= 0x,
+ .name = Cortina CS4315/CS4340,
+ .features = 0,
+ .config_init= cs4340_config_init,
+ .config_aneg= cs4340_config_aneg,
+ .read_status= cs4340_read_status,
+ .ack_interrupt = cs4340_ack_interrupt,
+ .config_intr= cs4340_config_intr,
+ .driver = { .owner = THIS_MODULE,},
+};
+
+static int __init cs4340_init(void)
+{
+ int err;
+
+ err = phy_driver_register(cs4340_driver);
+ if (err 0)
+ return err;
+
+ return 0;
+}
+
+static void __exit cs4340_exit(void)
+{
+ phy_driver_unregister(cs4340_driver);
+}
+
+module_init(cs4340_init);
+module_exit(cs4340_exit);
+
+static struct mdio_device_id __maybe_unused cortina_tbl[] = {
+ { PHY_ID_CS4340, 0x},
+ {},
+};
+
+MODULE_DEVICE_TABLE(mdio, cortina_tbl);
--
1.8.0
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[PATCH 1/3] powerpc/fsl-booke: Add support for T2080/T2081 SoC
Add support for T2080/T2081 SoC without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 344
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 96
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 502 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..0f05be2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,344 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met
[PATCH 2/3] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t2080qds.dts| 57 +++
arch/powerpc/boot/dts/t2081qds.dts| 48 ++
arch/powerpc/boot/dts/t208xqds.dtsi | 213 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 323 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000
[PATCH 3/3] powerpc/t2080rdb: Add T2080RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
The board feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LP devices
- 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
- Two 10M/100M/1Gbps RGMII ports on-board
- Two 10Gbps SFP+ ports on-board
- Two 10Gbps Base-T ports on-board
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
- SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 MAC10)
- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 MAC2)
- SerDes-1 Lane E-H: to PCIe goldfinger (PCIe4 x4, Gen3)
- SerDes-2 Lane A-D: to PCIe slot (PCIe1 x4, Gen2)
- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
- SerDes-2 Lane G-H: to SATA1 SATA2
IFC/Local Bus
- NOR: 128MB 16-bit NOR flash
- NAND: 512MB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
eSPI:
- 64MB N25Q512 SPI flash
USB:
- Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
- One PCIe x4 gold-finger
- One PCIe x4 connector
- One PCIe x2 end-point device (C293 crypto co-processor)
SATA:
- Two SATA 2.0 ports on-board
SDHC:
- support a TF-card on-board
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
This board can work in two mode: standalone mode and PCIe endpoint mode.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t2080rdb.dts| 57 +++
arch/powerpc/boot/dts/t208xrdb.dtsi | 210 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +-
4 files changed, 271 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/boot/dts/t2080rdb.dts
create mode 100644 arch/powerpc/boot/dts/t208xrdb.dtsi
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts
b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000..e889104
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xrdb.dtsi
+
+/ {
+ model = fsl,T2080RDB;
+ compatible = fsl,T2080RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi
b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000..439a5c1
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,210 @@
+/*
+ * T2080/T2081PCIe-RDB Board Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided
[PATCH 3/4 v3] powerpc/fsl-booke: Add support for T2080/T2081 SoC
Add support for T2080/T2081 SoC without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3: add specific compatible strings.
v2: remove wildcards in compatible strings.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 344
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 100
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 506 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..0f05be2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,344 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
[PATCH 4/4 v2] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: rebase
arch/powerpc/boot/dts/t2080qds.dts| 59 +++
arch/powerpc/boot/dts/t2081qds.dts| 48 ++
arch/powerpc/boot/dts/t208xqds.dtsi | 213 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 325 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..2d8b5d2
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,59 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000
[PATCH 3/4 v2]powerpc/fsl-booke: Add support for T2080/T2081 SoC
Add support for T2080/T2081 SoC without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: remove wildcards in compatible strings.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 383
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 95 +++
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 540 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..d7e036c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,383 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided
[PATCH 1/4] powerpc/85xx/dts: add third elo3 dma component
Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, B4860, etc.
FSL MPIC v4.3 adds a new discontiguous address range for internal interrupts,
e.g. internal interrupt 0 is at offset 0x200 and thus interrupt number is:
0x200 5 = 16 in the device tree. DMA controller 3 channel 0 internal
interrupt 240 is at offset 0x3a00, and thus the corresponding interrupt
number is: 0x3a00 5 = 464, it's similar for other 7 interrupt numbers
of DMA 3 channels.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++
1 file changed, 82 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000..d3cc8d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma2: dma@102300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x102300 0x4,
+ 0x102600 0x4;
+ ranges = 0x0 0x102100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 464 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 465 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 466 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 467 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 468 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 469 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 470 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 471 2 0 0;
+ };
+};
--
1.8.0
___
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[PATCH 2/4] powerpc/fsl_pci: add versionless pci compatible
There are much pci compatible with version on existing platforms.
To stop putting version numbers in device tree later, we add a
generic compatible 'fsl,qoriq-pcie'.
The version number is readable directly from a register.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61d..a7c71ff 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1035,6 +1035,7 @@ static const struct of_device_id pci_ids[] = {
{ .compatible = fsl,mpc8548-pcie, },
{ .compatible = fsl,mpc8610-pci, },
{ .compatible = fsl,mpc8641-pcie, },
+ { .compatible = fsl,qoriq-pcie, },
{ .compatible = fsl,qoriq-pcie-v2.1, },
{ .compatible = fsl,qoriq-pcie-v2.2, },
{ .compatible = fsl,qoriq-pcie-v2.3, },
--
1.8.0
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[PATCH 3/4] powerpc/fsl-booke: Add support for T2080/T2081 SoC
Add support for T2080/T2081 SoC without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 384
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 100
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 546 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..6495fe9
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,384 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met
[PATCH 4/4] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t2080qds.dts| 57 +++
arch/powerpc/boot/dts/t2081qds.dts| 46 ++
arch/powerpc/boot/dts/t208xqds.dtsi | 213 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4 +
5 files changed, 321 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000
[PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, etc.
MPIC registers for internal interrupts is non-continous in address, any
internal interrupt number greater than 159 should be added (16+208) to work,
adding 16 is due to external interrupts as usual, adding 208 is due to
non-continous MPIC register space.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++
1 file changed, 82 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000..d3cc8d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma2: dma@102300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x102300 0x4,
+ 0x102600 0x4;
+ ranges = 0x0 0x102100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 464 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 465 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 466 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 467 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 468 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 469 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 470 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 471 2 0 0;
+ };
+};
--
1.8.0
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[PATCH 2/5] powerpc/fsl_pci: add versionless pci compatible
There are much pci compatible with version on existing platforms.
To stop putting version numbers in device tree later, we add a
generic compatible 'fsl,qoriq-pcie'.
The version number is readable directly from a register.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4dfd61d..a7c71ff 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1035,6 +1035,7 @@ static const struct of_device_id pci_ids[] = {
{ .compatible = fsl,mpc8548-pcie, },
{ .compatible = fsl,mpc8610-pci, },
{ .compatible = fsl,mpc8641-pcie, },
+ { .compatible = fsl,qoriq-pcie, },
{ .compatible = fsl,qoriq-pcie-v2.1, },
{ .compatible = fsl,qoriq-pcie-v2.2, },
{ .compatible = fsl,qoriq-pcie-v2.3, },
--
1.8.0
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[PATCH 3/5] powerpc/fsl-booke: Add initial device tree support for T2080/T2081
Add initial device tree for T2080/T2081 without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 personality is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 60 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 384
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 100
3 files changed, 544 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..1a902fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,60 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ t2081si-post.dtsi
+
+soc {
+/include/ qoriq-sata2-0.dtsi
+/include/ qoriq-sata2-1.dtsi
+};
+
+rio {
+ compatible = fsl,srio;
+ interrupts = 16 2 1 11;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ port1 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 1;
+ };
+
+ port2 {
+ #address-cells = 2;
+ #size-cells = 2;
+ cell-index = 2;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000..6495fe9
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,384 @@
+/*
+ * T2081 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code
[PATCH 4/5] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/t2080qds.dts | 57
arch/powerpc/boot/dts/t2081qds.dts | 46 +++
arch/powerpc/boot/dts/t208xqds.dtsi | 259
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 364 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git a/arch/powerpc/boot/dts
[PATCH 5/5] powerpc/fsl-booke: Enable T208xQDS board
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index 4d46349..e3578b7 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -259,7 +259,7 @@ config CORENET_GENERIC
For 32bit kernel, the following boards are supported:
P2041 RDB, P3041 DS and P4080 DS
For 64bit kernel, the following boards are supported:
- T4240 QDS and B4 QDS
+ T208x QDS, T4240 QDS and B4 QDS
The following boards are supported for both 32bit and 64bit kernel:
P5020 DS and P5040 DS
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..77fd71f 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -102,6 +102,8 @@ static const char * const boards[] __initconst = {
fsl,P4080DS,
fsl,P5020DS,
fsl,P5040DS,
+ fsl,T2080QDS,
+ fsl,T2081QDS,
fsl,T4240QDS,
fsl,B4860QDS,
fsl,B4420QDS,
@@ -115,6 +117,8 @@ static const char * const hv_boards[] __initconst = {
fsl,P4080DS-hv,
fsl,P5020DS-hv,
fsl,P5040DS-hv,
+ fsl,T2080QDS-hv,
+ fsl,T2081QDS-hv
fsl,T4240QDS-hv,
fsl,B4860QDS-hv,
fsl,B4420QDS-hv,
--
1.8.0
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[PATCH 1/4 v2] powerpc/85xx/dts: add third elo3 dma component
Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, etc.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Liu Gang gang@freescale.com
---
v2: no change
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++
1 file changed, 82 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000..b89d816
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma2: dma@102300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x102300 0x4,
+ 0x102600 0x4;
+ ranges = 0x0 0x102100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 256 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 257 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 258 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 259 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 260 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 261 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 262 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 263 2 0 0;
+ };
+};
--
1.8.0
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[PATCH 3/4 v2] powerpc/fsl-booke: Add initial T208x QDS board support
Add support for Freescale T2080/T2081 QDS Development System Board.
T2081QDS board shares the same PCB with T1040QDS with some differences.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
T2080QDS feature overview:
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/MMC/eMMC Card
DMA:
- Three 8-channels DMA controllers
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 168
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: separate patches per board-related.
arch/powerpc/boot/dts/t2080qds.dts | 57
arch/powerpc/boot/dts/t2081qds.dts | 46 +++
arch/powerpc/boot/dts/t208xqds.dtsi | 259
arch/powerpc/include/asm/mpc85xx.h | 2 +
4 files changed, 364 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
create mode 100644 arch/powerpc/boot/dts/t2081qds.dts
create mode 100644 arch/powerpc/boot/dts/t208xqds.dtsi
diff --git a/arch/powerpc/boot/dts/t2080qds.dts
b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000..aa1d6d8
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/t208xsi-pre.dtsi
+/include/ t208xqds.dtsi
+
+/ {
+ model = fsl,T2080QDS;
+ compatible = fsl,T2080QDS;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ rio: rapidio@ffe0c {
+ reg = 0xf 0xfe0c 0 0x11000;
+
+ port1 {
+ ranges = 0 0 0xc 0x2000 0 0x1000;
+ };
+ port2 {
+ ranges = 0 0 0xc 0x3000 0 0x1000;
+ };
+ };
+};
+
+/include/ fsl/t2080si-post.dtsi
diff --git
[PATCH 4/4 v2] powerpc/fsl-booke: Enable T208xQDS board
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: add T2081QDS compatible.
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index 4d46349..b3436f8 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -259,7 +259,7 @@ config CORENET_GENERIC
For 32bit kernel, the following boards are supported:
P2041 RDB, P3041 DS and P4080 DS
For 64bit kernel, the following boards are supported:
- T4240 QDS and B4 QDS
+ T208x QDS, T4240 QDS and B4 QDS
The following boards are supported for both 32bit and 64bit kernel:
P5020 DS and P5040 DS
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..77fd71f 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -102,6 +102,8 @@ static const char * const boards[] __initconst = {
fsl,P4080DS,
fsl,P5020DS,
fsl,P5040DS,
+ fsl,T2080QDS,
+ fsl,T2081QDS,
fsl,T4240QDS,
fsl,B4860QDS,
fsl,B4420QDS,
@@ -115,6 +117,8 @@ static const char * const hv_boards[] __initconst = {
fsl,P4080DS-hv,
fsl,P5020DS-hv,
fsl,P5040DS-hv,
+ fsl,T2080QDS-hv,
+ fsl,T2081QDS-hv
fsl,T4240QDS-hv,
fsl,B4860QDS-hv,
fsl,B4420QDS-hv,
--
1.8.0
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[PATCH 2/4 v2] powerpc/fsl-booke: Add initial device tree support for T2080/T2081
Add initial device tree for T2080/T2081 without DPAA components.
The T2080 SoC includes the following function and features:
- Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
T2081 personality is a reduced personality of T2080 without SATA, sRIO, RMan,
Aurora, and with less SerDes lanes and ethernet interfaces.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: separate patches per silicon-related.
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 406
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 384 ++
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 100 +++
3 files changed, 890 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..be3d8de
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,406 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+/* controller at 0x24 */
+pci0 {
+ compatible = fsl,t2080-pcie, fsl,qoriq-pcie-v3.0, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
+ 0 0 4 mpic 3 1 0 0
[PATCH 2/3] powerpc/fsl-booke: Add T2080QDS board support
Add support for Freescale T2080QDS Development System Board.
The T2080QDS Development System is a high-performance computing,
evaluation, and development platform that supports T2080 QorIQ
Power Architecture processor, with following major features:
- Four 64-bit dual-threaded e6500 cores up to 1.8 GHz
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support and memory pre-fetch engine
- Data Path Acceleration Architecture (DPAA) integrating FMAN, QMAN, BMAN,
SEC5.2, PME2.1, DCE and RMAN
- Ethernet interfaces: 8 mEMACs(four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- Sixteen SerDes lanes at up to 10.3125 GHz
- Eight Ethernet interfaces supporting combinations of eight 1Gbps/four 10Gbps
or four 2.5Gbps Ethernet MACs
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two SATA 2.0 controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers and four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/t2080si-post.dtsi | 406
arch/powerpc/boot/dts/fsl/t2080si-pre.dtsi | 100 +++
arch/powerpc/boot/dts/t2080qds.dts | 276 +++
3 files changed, 782 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t2080si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/t2080qds.dts
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000..d84c55a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,406 @@
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor AS IS AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,ifc, simple-bus;
+ interrupts = 25 2 0 0;
+};
+
+/* controller at 0x24 */
+pci0 {
+ compatible = fsl,t2080-pcie, fsl,qoriq-pcie-v3.0, fsl,qoriq-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0x0 0xff;
+ interrupts = 20 2 0 0;
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 20 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0 0 1 mpic 40 1 0 0
+ 0 0 2 mpic 1 1 0 0
+ 0 0 3 mpic 2 1 0 0
[PATCH 1/3] powerpc/85xx/dts: add third elo3 dma component
Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, etc.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++
1 file changed, 82 insertions(+)
create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
new file mode 100644
index 000..b89d816
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+dma2: dma@102300 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elo3-dma;
+ reg = 0x102300 0x4,
+ 0x102600 0x4;
+ ranges = 0x0 0x102100 0x500;
+ dma-channel@0 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x0 0x80;
+ interrupts = 256 2 0 0;
+ };
+ dma-channel@80 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x80 0x80;
+ interrupts = 257 2 0 0;
+ };
+ dma-channel@100 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x100 0x80;
+ interrupts = 258 2 0 0;
+ };
+ dma-channel@180 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x180 0x80;
+ interrupts = 259 2 0 0;
+ };
+ dma-channel@300 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x300 0x80;
+ interrupts = 260 2 0 0;
+ };
+ dma-channel@380 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x380 0x80;
+ interrupts = 261 2 0 0;
+ };
+ dma-channel@400 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x400 0x80;
+ interrupts = 262 2 0 0;
+ };
+ dma-channel@480 {
+ compatible = fsl,eloplus-dma-channel;
+ reg = 0x480 0x80;
+ interrupts = 263 2 0 0;
+ };
+};
--
1.8.0
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[PATCH 3/3] powerpc/fsl-booke: Enable T2080QDS board
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/include/asm/mpc85xx.h| 2 ++
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 ++
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mpc85xx.h
b/arch/powerpc/include/asm/mpc85xx.h
index 736d4ac..3bef74a 100644
--- a/arch/powerpc/include/asm/mpc85xx.h
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -77,6 +77,8 @@
#define SVR_T1020 0x852100
#define SVR_T1021 0x852101
#define SVR_T1022 0x852102
+#define SVR_T2080 0x853000
+#define SVR_T2081 0x853100
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index 4d46349..b3436f8 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -259,7 +259,7 @@ config CORENET_GENERIC
For 32bit kernel, the following boards are supported:
P2041 RDB, P3041 DS and P4080 DS
For 64bit kernel, the following boards are supported:
- T4240 QDS and B4 QDS
+ T2080 QDS, T4240 QDS and B4 QDS
The following boards are supported for both 32bit and 64bit kernel:
P5020 DS and P5040 DS
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e..5b8b10e 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -102,6 +102,7 @@ static const char * const boards[] __initconst = {
fsl,P4080DS,
fsl,P5020DS,
fsl,P5040DS,
+ fsl,T2080QDS,
fsl,T4240QDS,
fsl,B4860QDS,
fsl,B4420QDS,
@@ -115,6 +116,7 @@ static const char * const hv_boards[] __initconst = {
fsl,P4080DS-hv,
fsl,P5020DS-hv,
fsl,P5040DS-hv,
+ fsl,T2080QDS-hv,
fsl,T4240QDS-hv,
fsl,B4860QDS-hv,
fsl,B4420QDS-hv,
--
1.8.0
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[PATCH] powerpc/fsl/defconfig: enable CONFIG_AT803X_PHY
Enable CONFIG_AT803X_PHY to support AR8030/8033/8035 PHY. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig |1 + arch/powerpc/configs/mpc85xx_defconfig |1 + arch/powerpc/configs/mpc85xx_smp_defconfig |1 + 3 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 60027c2..ccb9d12 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -103,6 +103,7 @@ CONFIG_FSL_PQ_MDIO=y CONFIG_E1000=y CONFIG_E1000E=y CONFIG_VITESSE_PHY=y +CONFIG_AT803X_PHY=y CONFIG_FIXED_PHY=y # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 5a58882..2ddbba5 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -136,6 +136,7 @@ CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_CICADA_PHY=y CONFIG_VITESSE_PHY=y +CONFIG_AT803X_PHY=y CONFIG_FIXED_PHY=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 152fa05..b08ba94 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -136,6 +136,7 @@ CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_CICADA_PHY=y CONFIG_VITESSE_PHY=y +CONFIG_AT803X_PHY=y CONFIG_FIXED_PHY=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] fsl/ehci: fix failure of checking PHY_CLK_VALID during reinitialization
In case of usb phy reinitialization:
e.g. insmod usb-module(usb works well) - rmmod usb-module - insmod usb-module
It found the PHY_CLK_VALID bit didn't work if it's not with the power-on reset.
So we just check PHY_CLK_VALID bit during the stage with POR, this can be met
by the tricky of checking FSL_SOC_USB_PRICTRL register.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
based on master branch of upstream, from sdk1.4
drivers/usb/host/ehci-fsl.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index bd831ec..3156e12 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -270,8 +270,9 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
if (pdata-have_sysif_regs pdata-controller_ver
(phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
- if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL)
- PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
+ if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL)
+ PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
+ in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
printk(KERN_WARNING fsl-ehci: USB PHY clock
invalid\n);
return -EINVAL;
}
--
1.7.0.4
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[PATCH] powerpc/p1010rdb: update phy node in dts
Update phy node according to new P1010RDB-PB board.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/p1010rdb.dtsi |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi
b/arch/powerpc/boot/dts/p1010rdb.dtsi
index ec7c27a..da24b2d 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -193,17 +193,17 @@
mdio@24000 {
phy0: ethernet-phy@0 {
- interrupts = 3 1 0 0;
+ interrupts = 0 1;
reg = 0x1;
};
phy1: ethernet-phy@1 {
- interrupts = 2 1 0 0;
+ interrupts = 2 1;
reg = 0x0;
};
phy2: ethernet-phy@2 {
- interrupts = 2 1 0 0;
+ interrupts = 1 1;
reg = 0x2;
};
--
1.7.0.4
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[PATCH] usb: remove redundant tdi_reset
We remove the redundant tdi_reset in ehci_setup since there is already it in ehci_reset. It was observed that the duplicated tdi_reset was causing the PHY_CLK_VALID bit unstable. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- drivers/usb/host/ehci-hcd.c |3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 416a6dc..83b5a17 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -670,9 +670,6 @@ int ehci_setup(struct usb_hcd *hcd) if (retval) return retval; - if (ehci_is_TDI(ehci)) - tdi_reset(ehci); - ehci_reset(ehci); return 0; -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY
PHY_CLK_VALID bit doesn't work properly with UTMI PHY.
e.g. This bit is always zero on P5040, etc.
There is no need to check this bit for UTMI PHY, just keep
checking for ULPI PHY to prevent system hanging.
This patch should be squashed into previous commit 3735ba8db8e6e
powerpc/usb: fix bug of CPU hang when missing USB PHY clock
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/usb/host/ehci-fsl.c |3 +--
include/linux/fsl_devices.h |2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 11ff4b4..9bfde82 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -267,8 +267,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
break;
}
- if ((pdata-controller_ver) ((phy_mode == FSL_USB2_PHY_ULPI) ||
- (phy_mode == FSL_USB2_PHY_UTMI))) {
+ if (pdata-controller_ver (phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL)
PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index ccfc4bb..700bf31 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -19,7 +19,7 @@
#define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
PHY CLK to become stable - 10ms*/
-#define FSL_USB_PHY_CLK_TIMEOUT1000/* uSec */
+#define FSL_USB_PHY_CLK_TIMEOUT1 /* uSec */
#define FSL_USB_VER_OLD0
#define FSL_USB_VER_1_61
#define FSL_USB_VER_2_22
--
1.6.4
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[PATCH v3] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
when missing USB PHY clock, kernel booting up will hang during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hanging in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v3 change: no check for UTMI PHY.
v2 change: use spin_event_timeout() instead.
drivers/usb/host/ehci-fsl.c | 57 +-
drivers/usb/host/ehci-fsl.h |1 +
include/linux/fsl_devices.h |1 +
3 files changed, 41 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b7451b2..9bfde82 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -210,11 +210,11 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
usb_put_hcd(hcd);
}
-static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
+static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
enum fsl_usb2_phy_modes phy_mode,
unsigned int port_offset)
{
- u32 portsc, temp;
+ u32 portsc;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
void __iomem *non_ehci = hcd-regs;
struct device *dev = hcd-self.controller;
@@ -232,9 +232,15 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_ULPI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL,
+ ULPI_PHY_CLK_SEL);
+ /*
+* Due to controller issue of PHY_CLK_VALID in ULPI
+* mode, we set USB_CTRL_USB_EN before checking
+* PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+*/
+ clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
+ UTMI_PHY_EN, USB_CTRL_USB_EN);
}
portsc |= PORT_PTS_ULPI;
break;
@@ -247,9 +253,7 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_UTMI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- UTMI_PHY_EN | USB_CTRL_USB_EN);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
become stable - 10ms*/
}
@@ -262,23 +266,33 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_NONE:
break;
}
+
+ if (pdata-controller_ver (phy_mode == FSL_USB2_PHY_ULPI)) {
+ /* check PHY_CLK_VALID to get phy clk valid */
+ if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL)
+ PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
+ printk(KERN_WARNING fsl-ehci: USB PHY clock
invalid\n);
+ return -EINVAL;
+ }
+ }
+
ehci_writel(ehci, portsc, ehci-regs-port_status[port_offset]);
+
+ if (phy_mode != FSL_USB2_PHY_ULPI)
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
+
+ return 0;
}
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
void __iomem *non_ehci = hcd-regs;
- u32 temp;
pdata = hcd-self.controller-platform_data;
- /* Enable PHY interface in the control reg. */
if (pdata-have_sysif_regs) {
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x0004);
-
/*
* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent
@@ -293,7 +307,8 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
if ((pdata-operating_mode == FSL_USB2_DR_HOST) ||
(pdata-operating_mode == FSL_USB2_DR_OTG))
- ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0);
+ if (ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0))
+ return -EINVAL;
if (pdata-operating_mode == FSL_USB2_MPH_HOST) {
unsigned int chip, rev, svr;
@@ -307,9 +322,12 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
ehci
[PATCH v2] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
when missing USB PHY clock, kernel booting up will hang during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hanging in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2 changes: use spin_event_timeout() instead.
drivers/usb/host/ehci-fsl.c | 58 +-
drivers/usb/host/ehci-fsl.h |1 +
include/linux/fsl_devices.h |1 +
3 files changed, 42 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b7451b2..11ff4b4 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -210,11 +210,11 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
usb_put_hcd(hcd);
}
-static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
+static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
enum fsl_usb2_phy_modes phy_mode,
unsigned int port_offset)
{
- u32 portsc, temp;
+ u32 portsc;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
void __iomem *non_ehci = hcd-regs;
struct device *dev = hcd-self.controller;
@@ -232,9 +232,15 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_ULPI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL,
+ ULPI_PHY_CLK_SEL);
+ /*
+* Due to controller issue of PHY_CLK_VALID in ULPI
+* mode, we set USB_CTRL_USB_EN before checking
+* PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+*/
+ clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
+ UTMI_PHY_EN, USB_CTRL_USB_EN);
}
portsc |= PORT_PTS_ULPI;
break;
@@ -247,9 +253,7 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_UTMI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- UTMI_PHY_EN | USB_CTRL_USB_EN);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
become stable - 10ms*/
}
@@ -262,23 +266,34 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_NONE:
break;
}
+
+ if ((pdata-controller_ver) ((phy_mode == FSL_USB2_PHY_ULPI) ||
+ (phy_mode == FSL_USB2_PHY_UTMI))) {
+ /* check PHY_CLK_VALID to get phy clk valid */
+ if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL)
+ PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
+ printk(KERN_WARNING fsl-ehci: USB PHY clock
invalid\n);
+ return -EINVAL;
+ }
+ }
+
ehci_writel(ehci, portsc, ehci-regs-port_status[port_offset]);
+
+ if (phy_mode != FSL_USB2_PHY_ULPI)
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
+
+ return 0;
}
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
void __iomem *non_ehci = hcd-regs;
- u32 temp;
pdata = hcd-self.controller-platform_data;
- /* Enable PHY interface in the control reg. */
if (pdata-have_sysif_regs) {
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x0004);
-
/*
* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent
@@ -293,7 +308,8 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
if ((pdata-operating_mode == FSL_USB2_DR_HOST) ||
(pdata-operating_mode == FSL_USB2_DR_OTG))
- ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0);
+ if (ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0))
+ return -EINVAL;
if (pdata-operating_mode == FSL_USB2_MPH_HOST) {
unsigned int chip, rev, svr;
@@ -307,9 +323,12 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci
[PATCH 1/2] powerpc/p4080ds: dts - add usb controller version info and port0
Add the missing usb controller version info and port0, which is
required during setup usb phy.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 8d35d2c..4f9c9f6 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -345,6 +345,13 @@
/include/ qoriq-duart-1.dtsi
/include/ qoriq-gpio-0.dtsi
/include/ qoriq-usb2-mph-0.dtsi
+ usb@21 {
+ compatible = fsl-usb2-mph-v1.6, fsl,mpc85xx-usb2-mph,
fsl-usb2-mph;
+ port0;
+ };
/include/ qoriq-usb2-dr-0.dtsi
+ usb@211000 {
+ compatible = fsl-usb2-dr-v1.6, fsl,mpc85xx-usb2-dr,
fsl-usb2-dr;
+ };
/include/ qoriq-sec4.0-0.dtsi
};
--
1.6.4
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[PATCH 2/2] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
when missing USB PHY clock, kernel booting up will hang during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hanging in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/usb/host/ehci-fsl.c | 63 ++
drivers/usb/host/ehci-fsl.h |1 +
2 files changed, 46 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b7451b2..aeb6d03 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -210,11 +210,11 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
usb_put_hcd(hcd);
}
-static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
+static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
enum fsl_usb2_phy_modes phy_mode,
unsigned int port_offset)
{
- u32 portsc, temp;
+ u32 portsc, timeout;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
void __iomem *non_ehci = hcd-regs;
struct device *dev = hcd-self.controller;
@@ -232,9 +232,15 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_ULPI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL,
+ ULPI_PHY_CLK_SEL);
+ /*
+* Due to controller issue of PHY_CLK_VALID in ULPI
+* mode, we set USB_CTRL_USB_EN before checking
+* PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+*/
+ clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
+ UTMI_PHY_EN, USB_CTRL_USB_EN);
}
portsc |= PORT_PTS_ULPI;
break;
@@ -247,9 +253,7 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_UTMI:
if (pdata-controller_ver) {
/* controller version 1.6 or above */
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
- UTMI_PHY_EN | USB_CTRL_USB_EN);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
become stable - 10ms*/
}
@@ -262,23 +266,39 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_NONE:
break;
}
+
+ if ((pdata-controller_ver) ((phy_mode == FSL_USB2_PHY_ULPI) ||
+ (phy_mode == FSL_USB2_PHY_UTMI))) {
+ for (timeout = 1000; timeout 0; timeout--) {
+ /* check PHY_CLK_VALID to get phy clk valid */
+ if (in_be32(non_ehci + FSL_SOC_USB_CTRL)
+PHY_CLK_VALID)
+ break;
+ udelay(1);
+ }
+ if (timeout == 0) {
+ printk(KERN_WARNING fsl-ehci: USB PHY clock
invalid\n);
+ return -EINVAL;
+ }
+ }
+
ehci_writel(ehci, portsc, ehci-regs-port_status[port_offset]);
+
+ if (phy_mode != FSL_USB2_PHY_ULPI)
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
+
+ return 0;
}
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
void __iomem *non_ehci = hcd-regs;
- u32 temp;
pdata = hcd-self.controller-platform_data;
- /* Enable PHY interface in the control reg. */
if (pdata-have_sysif_regs) {
- temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
- out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x0004);
-
/*
* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent
@@ -293,7 +313,8 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
if ((pdata-operating_mode == FSL_USB2_DR_HOST) ||
(pdata-operating_mode == FSL_USB2_DR_OTG))
- ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0);
+ if (ehci_fsl_setup_phy(hcd, pdata-phy_mode, 0))
+ return -EINVAL;
if (pdata-operating_mode == FSL_USB2_MPH_HOST) {
unsigned int chip
[PATCH v2] PCI: use dev-irq instead of dev-pin to enable non MSI/INTx interrupt
On some platforms, root port has neither MSI/MSI-X nor INTx interrupt
generated in RC mode. In this case, we have to use other interrupt(e.g.
system shared interrupt) for port service irq to have AER, Hot-plug, etc,
services to work.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/pci/pcie/portdrv_core.c | 16
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b3..49acf72 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -200,10 +200,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
{
int i, irq = -1;
- /* We have to use INTx if MSI cannot be used for PCIe PME or pciehp. */
+ /*
+* We have to use INTx or other interrupts(e.g. system shared interrupt)
+* if MSI cannot be used for PCIe PME or pciehp.
+*/
if (((mask PCIE_PORT_SERVICE_PME) pcie_pme_no_msi()) ||
((mask PCIE_PORT_SERVICE_HP) pciehp_no_msi())) {
- if (dev-pin)
+ if (dev-irq)
irq = dev-irq;
goto no_msi;
}
@@ -212,8 +215,13 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
if (!pcie_port_enable_msix(dev, irqs, mask))
return 0;
- /* We're not going to use MSI-X, so try MSI and fall back to INTx */
- if (!pci_enable_msi(dev) || dev-pin)
+ /*
+* We're not going to use MSI-X, so try MSI and fall back to INTx.
+* If neither MSI/MSI-X nor INTx available, try other interrupt. (On
+* some platforms, root port doesn't support generating MSI/MSI-X/INTx
+* in RC mode)
+*/
+ if (!pci_enable_msi(dev) || dev-irq)
irq = dev-irq;
no_msi:
--
1.6.4
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[PATCH] PCI: use dev-irq instead of dev-pin to enable non MSI/INTx interrupt
On some platforms, root port has neither MSI/MSI-X nor INTx interrupt generated in RC mode. In this case, we have to use other interrupt(i.e. system shared interrupt) for port service irq to have AER, Hot-plug, etc, services to work. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- drivers/pci/pcie/portdrv_core.c |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 75915b3..a855254 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -212,8 +212,13 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask) if (!pcie_port_enable_msix(dev, irqs, mask)) return 0; - /* We're not going to use MSI-X, so try MSI and fall back to INTx */ - if (!pci_enable_msi(dev) || dev-pin) + /* +* We're not going to use MSI-X, so try MSI and fall back to INTx. +* If neither MSI/MSI-X nor INTx available, try other interrupt. (On +* some platforms, root port doesn't support generating MSI/MSI-X/INTx +* in RC mode) +*/ + if (!pci_enable_msi(dev) || dev-irq) irq = dev-irq; no_msi: -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2 v2] PCI: Add PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ to enable non MSI/INTx interrupt
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt for port service driver to have
AER, Hot-plug, etc, services to work.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: separated platform-specific part to arch/powerpc/sysdev.
drivers/pci/pcie/portdrv_core.c | 10 --
drivers/pci/quirks.c|9 +
include/linux/pci.h |5 +
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b3..837ad15 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -212,8 +212,14 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
if (!pcie_port_enable_msix(dev, irqs, mask))
return 0;
- /* We're not going to use MSI-X, so try MSI and fall back to INTx */
- if (!pci_enable_msi(dev) || dev-pin)
+ /*
+* We're not going to use MSI-X, so try MSI and fall back to INTx.
+* Eventually, if neither MSI/MSI-X nor INTx available, try other
+* interrupt. (On some platforms, root port doesn't support generating
+* MSI/MSI-X/INTx in RC mode)
+*/
+ if (!pci_enable_msi(dev) || dev-pin || ((dev-dev_flags
+ PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ) dev-irq))
irq = dev-irq;
no_msi:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a75216..2922cb8 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2640,6 +2640,15 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
quirk_msi_intx_disable_bug);
#endif /* CONFIG_PCI_MSI */
+/*
+ * Under some circumstances, root port has neither MSI/MSI-X nor INTx
generated,
+ * so try other interrupt if supported.
+ */
+void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev)
+{
+ dev-dev_flags |= PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ;
+}
+
/* Allow manual resource allocation for PCI hotplug bridges
* via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
* some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d8c379d..f051a66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -176,6 +176,11 @@ enum pci_dev_flags {
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
/* Provide indication device is assigned by a Virtual Machine Manager */
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
+ /*
+* Use other interrupt (i.e. system shared interrupt) when MSI/MSI-X
+* and INTx are not supported in RC mode on some platforms.
+*/
+ PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ = (__force pci_dev_flags_t) 8,
};
enum pci_irq_reroute_variant {
--
1.6.4
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[PATCH 2/2 v2] powerpc/fsl: PCI: add quirk_enable_non_msi_intx_interrupt
On current fsl powerpc platforms, the PCIe root port doesn't support
generating MSI/MSI-X and INTx interrupt in RC mode (those interrupts
are supported only in EP mode). So we use the shared error interrupt
by flag PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ for PCIe port driver to
support AER, Hot-plug etc, services.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: separated platform-specific part to arch/powerpc/sysdev.
arch/powerpc/sysdev/fsl_pci.c |2 ++
arch/powerpc/sysdev/fsl_pci.h |1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288..fb8862f 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -498,6 +498,8 @@ int __init fsl_add_bridge(struct device_node *dev, int
is_primary)
#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
+ quirk_enable_non_msi_intx_interrupt);
#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
struct mpc83xx_pcie_priv {
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..a98c6d8 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -91,6 +91,7 @@ struct ccsr_pci {
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
+extern void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
#endif /* __POWERPC_FSL_PCI_H */
--
1.6.4
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[PATCH][upstream] PCI: Add PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ to enable non MSI/INTx interrupt
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt for port service driver to have
AER, Hot-plug, etc, services to work. (i.e. there is the shared error interrupt
on platform P1010/P3041/P4080 etc)
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/pci/pcie/portdrv_core.c | 10 --
drivers/pci/quirks.c| 12
include/linux/pci.h |5 +
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b3..837ad15 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -212,8 +212,14 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
if (!pcie_port_enable_msix(dev, irqs, mask))
return 0;
- /* We're not going to use MSI-X, so try MSI and fall back to INTx */
- if (!pci_enable_msi(dev) || dev-pin)
+ /*
+* We're not going to use MSI-X, so try MSI and fall back to INTx.
+* Eventually, if neither MSI/MSI-X nor INTx available, try other
+* interrupt. (On some platforms, root port doesn't support generating
+* MSI/MSI-X/INTx in RC mode)
+*/
+ if (!pci_enable_msi(dev) || dev-pin || ((dev-dev_flags
+ PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ) dev-irq))
irq = dev-irq;
no_msi:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a75216..df54e2f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2640,6 +2640,18 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
quirk_msi_intx_disable_bug);
#endif /* CONFIG_PCI_MSI */
+/*
+ * Under some circumstances, root port has neither MSI/MSI-X nor INTx
generated,
+ * so try other interrupt if supported.
+ */
+static void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev)
+{
+ dev-dev_flags |= PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ;
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
+ quirk_enable_non_msi_intx_interrupt);
+
/* Allow manual resource allocation for PCI hotplug bridges
* via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
* some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d8c379d..f051a66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -176,6 +176,11 @@ enum pci_dev_flags {
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
/* Provide indication device is assigned by a Virtual Machine Manager */
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
+ /*
+* Use other interrupt (i.e. system shared interrupt) when MSI/MSI-X
+* and INTx are not supported in RC mode on some platforms.
+*/
+ PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ = (__force pci_dev_flags_t) 8,
};
enum pci_irq_reroute_variant {
--
1.6.4
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[PATCH 1/2] powerpc/fsl: Update corenet32_smp_defconfig
- Enable NAND support - Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 91db656..e54d5f0 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -36,6 +36,7 @@ CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_FSL_LBC=y CONFIG_PCI=y CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MSI=y # CONFIG_PCIEASPM is not set CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y @@ -76,6 +77,11 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y @@ -136,6 +142,8 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_MPC85XX=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] powerpc/fsl: Update corenet64_smp_defconfig
Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet64_smp_defconfig | 59 - 1 files changed, 56 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 6798343..7340be3 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -25,6 +25,9 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_BINFMT_MISC=m CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y +CONFIG_FSL_LBC=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MSI=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -51,6 +54,19 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y @@ -58,6 +74,9 @@ CONFIG_BLK_DEV_RAM_SIZE=131072 CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y CONFIG_NETDEVICES=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_SATA_SIL24=y CONFIG_DUMMY=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set @@ -73,32 +92,66 @@ CONFIG_SERIAL_8250_RSA=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_FSL_ESPI=y # CONFIG_HWMON is not set CONFIG_VIDEO_OUTPUT_CONTROL=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y CONFIG_DMADEVICES=y CONFIG_FSL_DMA=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_HUGETLBFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m # CONFIG_MISC_FILESYSTEMS is not set CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y CONFIG_NLS=y +CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y CONFIG_DEBUG_FS=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_CRYPTO_NULL=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc/fsl: Update corenet32_smp_defconfig
* Enable NAND, MSI, PAMU, * Enable FSL RAID on P5020 * Enable general RAID features (MD + async-tx) * Enable RTC on P2041RDB * Enable UIO SRIO UIO DMA Signed-off-by: Harninder Rai harninder@freescale.com Signed-off-by: Shaohui Xie shaohui@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig | 22 +- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 91db656..eafb64f 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -34,8 +34,10 @@ CONFIG_BINFMT_MISC=m CONFIG_KEXEC=y CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_FSL_LBC=y +CONFIG_FSL_PAMU=y CONFIG_PCI=y CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MSI=y # CONFIG_PCIEASPM is not set CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y @@ -76,11 +78,16 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_BLK_DEV_RAM_SIZE=262144 CONFIG_MISC_DEVICES=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -95,6 +102,10 @@ CONFIG_SATA_FSL=y CONFIG_SATA_SIL24=y CONFIG_SATA_SIL=y CONFIG_PATA_SIL680=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_RAID456=y +CONFIG_MULTICORE_RAID456=y CONFIG_NETDEVICES=y CONFIG_FSL_PQ_MDIO=y CONFIG_E1000=y @@ -136,13 +147,21 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_MPC85XX=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_RAID=y +CONFIG_ASYNC_TX_DMA=y CONFIG_UIO=y +CONFIG_UIO_FSL_SRIO=y +CONFIG_UIO_FSL_DMA=y CONFIG_STAGING=y CONFIG_VIRT_DRIVERS=y CONFIG_FSL_HV_MANAGER=y @@ -171,6 +190,7 @@ CONFIG_MAC_PARTITION=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc/fsl: Update corenet32_smp_defconfig
* Enable NAND, MSI, PAMU, * Enable FSL RAID on P5020 * Enable general RAID features (MD + async-tx) * Enable RTC on P2041RDB * Enable UIO SRIO UIO DMA Signed-off-by: Harninder Rai harninder@freescale.com Signed-off-by: Shaohui Xie shaohui@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig | 22 +- 1 files changed, 21 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 91db656..eafb64f 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -34,8 +34,10 @@ CONFIG_BINFMT_MISC=m CONFIG_KEXEC=y CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_FSL_LBC=y +CONFIG_FSL_PAMU=y CONFIG_PCI=y CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MSI=y # CONFIG_PCIEASPM is not set CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y @@ -76,11 +78,16 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_BLK_DEV_RAM_SIZE=262144 CONFIG_MISC_DEVICES=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y @@ -95,6 +102,10 @@ CONFIG_SATA_FSL=y CONFIG_SATA_SIL24=y CONFIG_SATA_SIL=y CONFIG_PATA_SIL680=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_RAID456=y +CONFIG_MULTICORE_RAID456=y CONFIG_NETDEVICES=y CONFIG_FSL_PQ_MDIO=y CONFIG_E1000=y @@ -136,13 +147,21 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_MPC85XX=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_CMOS=y +CONFIG_DMADEVICES=y +CONFIG_FSL_RAID=y +CONFIG_ASYNC_TX_DMA=y CONFIG_UIO=y +CONFIG_UIO_FSL_SRIO=y +CONFIG_UIO_FSL_DMA=y CONFIG_STAGING=y CONFIG_VIRT_DRIVERS=y CONFIG_FSL_HV_MANAGER=y @@ -171,6 +190,7 @@ CONFIG_MAC_PARTITION=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] powerpc/fsl: Update corenet64_smp_defconfig
* Enable USB, MMC, SATA, MTD, NAND, PAMU, RTC * Enable FSL RAID on P5020 * Enable general RAID features (MD + async-tx) * Enable RTC on P2041RDB * Enable UIO SRIO UIO DMA * Enable USDPAA SHMEM driver * Enable ePAPR HV support * Enable PCI-E support Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com Signed-off-by: Harninder Rai harninder@freescale.com Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/configs/corenet64_smp_defconfig | 94 -- 1 files changed, 89 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 6798343..14bbae7 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -5,14 +5,21 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y CONFIG_SPARSE_IRQ=y +CONFIG_RCU_TRACE=y +CONFIG_RCU_FANOUT=32 CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y @@ -25,11 +32,18 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_BINFMT_MISC=m CONFIG_RAPIDIO=y CONFIG_FSL_RIO=y +CONFIG_FSL_LBC=y +CONFIG_FSL_PAMU=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_MSI=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y @@ -45,60 +59,130 @@ CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_ARPD=y +CONFIG_INET_AH=y CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_BLK_DEV_RAM_SIZE=262144 CONFIG_MISC_DEVICES=y CONFIG_EEPROM_LEGACY=y -CONFIG_NETDEVICES=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_SATA_SIL24=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_RAID456=y +CONFIG_MULTICORE_RAID456=y CONFIG_DUMMY=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set CONFIG_SERIO_LIBPS2=y +CONFIG_PPC_EPAPR_HV_BYTECHAN=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MPC=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_FSL_ESPI=y # CONFIG_HWMON is not set CONFIG_VIDEO_OUTPUT_CONTROL=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_CMOS=y CONFIG_DMADEVICES=y CONFIG_FSL_DMA=y +CONFIG_FSL_RAID=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_UIO=y +CONFIG_UIO_FSL_SRIO=y +CONFIG_UIO_FSL_DMA=y +CONFIG_STAGING=y +CONFIG_VIRT_DRIVERS=y +CONFIG_FSL_HV_MANAGER=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_HUGETLBFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m # CONFIG_MISC_FILESYSTEMS is not set CONFIG_PARTITION_ADVANCED=y CONFIG_MAC_PARTITION=y CONFIG_NLS=y +CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=m CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=m CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y CONFIG_DEBUG_FS=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEBUG_INFO=y CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_CRYPTO_NULL=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y -- 1.6.4
[PATCH] PCI: Add pcie_irq=other to enable non MSI/INTx interrupt for port service driver
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt if supported (i.e. there is the
shared error interrupt on platform P1010, P3041, P4080, etc) to have AER,
Hot-plug, etc, services to work.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Documentation/kernel-parameters.txt |4
drivers/pci/pcie/portdrv_core.c | 19 +++
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel-parameters.txt
index a92c5eb..af97c81 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2218,6 +2218,10 @@ bytes respectively. Such letter suffixes can also be
entirely omitted.
nomsi Do not use MSI for native PCIe PME signaling (this makes
all PCIe root ports use INTx for all services).
+ pcie_irq= [PCIE] Native PCIe root port interrupt options:
+ other Try to use other interrupt when root port has
+ neither MSI/MSI-X nor INTx support.
+
pcmv= [HW,PCMCIA] BadgePAD 4
pd. [PARIDE]
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b3..653679e 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -30,6 +30,17 @@ static int __init pciehp_setup(char *str)
}
__setup(pcie_hp=, pciehp_setup);
+bool port_other_interrupt_enabled;
+
+static int __init portservice_setup(char *str)
+{
+ if (!strncmp(str, other, 5))
+ port_other_interrupt_enabled = true;
+
+ return 1;
+}
+__setup(pcie_irq=, portservice_setup);
+
/**
* release_pcie_device - free PCI Express port service device structure
* @dev: Port service device to release
@@ -216,6 +227,14 @@ static int init_service_irqs(struct pci_dev *dev, int
*irqs, int mask)
if (!pci_enable_msi(dev) || dev-pin)
irq = dev-irq;
+ /*
+* On some platforms, root port has neither MSI/MSI-X nor INTx
+* interrupt support in RC mode, so try to use other interrupt(i.e.
+* shared interrupt if supported).
+*/
+ else if (port_other_interrupt_enabled dev-irq)
+ irq = dev-irq;
+
no_msi:
for (i = 0; i PCIE_PORT_DEVICE_MAXSERVICES; i++)
irqs[i] = irq;
--
1.6.4
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[PATCH] powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and mpc85xx_smp_defconfig to support NOR, NAND flash. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- based on master branch of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git arch/powerpc/configs/mpc85xx_defconfig | 26 ++ arch/powerpc/configs/mpc85xx_smp_defconfig | 25 + 2 files changed, 51 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index d6b6df5..a42304d 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -39,6 +39,7 @@ CONFIG_TQM8560=y CONFIG_SBC8548=y CONFIG_QUICC_ENGINE=y CONFIG_QE_GPIO=y +CONFIG_MPC8xxx_GPIO=y CONFIG_HIGHMEM=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -74,6 +75,31 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 5b0e292..31ef74f 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -76,6 +76,31 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y -- 1.7.0.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and mpc85xx_smp_defconfig to support NOR, NAND flash. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- based on master branch of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git changes of v2: remove typo CONFIG_MPC8xxx_GPIO=y compared with v1. arch/powerpc/configs/mpc85xx_defconfig | 25 + arch/powerpc/configs/mpc85xx_smp_defconfig | 25 + 2 files changed, 50 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index d6b6df5..0f55408 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -74,6 +74,31 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 5b0e292..31ef74f 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -76,6 +76,31 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3] powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and mpc85xx_smp_defconfig to support NOR, NAND flash. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- based on master branch of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git tree. v3: remove CONFIG_MTD_NAND_VERIFY_WRITE=y v2: remove typo CONFIG_MPC8xxx_GPIO=y arch/powerpc/configs/mpc85xx_defconfig | 24 arch/powerpc/configs/mpc85xx_smp_defconfig | 24 2 files changed, 48 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index d6b6df5..8c3da78 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -74,6 +74,30 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 5b0e292..575c410 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -76,6 +76,30 @@ CONFIG_INET_ESP=y CONFIG_IPV6=y CONFIG_IP_SCTP=m CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_FTL=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSL_ELBC=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=y -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/dts: fix the compatible string of sec 4.0
From: Liu Shuo shuo@freescale.com
Fix the compatible string of sec 4.0 to match with CAMM driver according
to Documentation/devicetree/bindings/crypto/fsl-sec4.txt
Signed-off-by: Liu Shuo shuo@freescale.com
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: refine description.
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index bf957a7..d4c9d5d 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -33,32 +33,32 @@
*/
crypto@3 {
- compatible = fsl,sec4.4, fsl,sec4.0;
+ compatible = fsl,sec-v4.4, fsl,sec-v4.0;
#address-cells = 1;
#size-cells = 1;
reg = 0x3 0x1;
interrupts = 58 2 0 0;
sec_jr0: jr@1000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x1000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr1: jr@2000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x2000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr2: jr@3000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x3000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr3: jr@4000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x4000 0x1000;
interrupts = 45 2 0 0;
};
--
1.7.0.4
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[PATCH] powerpc/dts: fix the compatible string of sec 4.0
From: Liu Shuo shuo@freescale.com
Fix the compatible string of sec 4.0 to match with CAMM driver according
to the documentation file Documentation/devicetree/bindings/crypto/fsl-sec4.txt.
Signed-off-by: Liu Shuo shuo@freescale.com
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
against master branch of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index bf957a7..d4c9d5d 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -33,32 +33,32 @@
*/
crypto@3 {
- compatible = fsl,sec4.4, fsl,sec4.0;
+ compatible = fsl,sec-v4.4, fsl,sec-v4.0;
#address-cells = 1;
#size-cells = 1;
reg = 0x3 0x1;
interrupts = 58 2 0 0;
sec_jr0: jr@1000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x1000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr1: jr@2000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x2000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr2: jr@3000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x3000 0x1000;
interrupts = 45 2 0 0;
};
sec_jr3: jr@4000 {
- compatible = fsl,sec4.4-job-ring, fsl,sec4.0-job-ring;
+ compatible = fsl,sec-v4.4-job-ring, fsl,sec-v4.0-job-ring;
reg= 0x4000 0x1000;
interrupts = 45 2 0 0;
};
--
1.7.0.4
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[PATCH] powerpc/usb: fix bug of kernel hang when initializing usb
If USB UTMI PHY is not enable, writing to portsc register will lead to
kernel hang during boot up.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Apply for master branch of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Tested on P5020DS, the issue was reported by Benjamin Herrenschmidt.
drivers/usb/host/ehci-fsl.c |4
drivers/usb/host/ehci-fsl.h |1 +
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index c26a82e..0090ed2 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -216,6 +216,8 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
unsigned int port_offset)
{
u32 portsc;
+ struct usb_hcd *hcd = ehci_to_hcd(ehci);
+ void __iomem *non_ehci = hcd-regs;
portsc = ehci_readl(ehci, ehci-regs-port_status[port_offset]);
portsc = ~(PORT_PTS_MSK | PORT_PTS_PTW);
@@ -231,6 +233,8 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+ /* enable UTMI PHY */
+ setbits32(non_ehci + FSL_SOC_USB_CTRL, CTRL_UTMI_PHY_EN);
portsc |= PORT_PTS_UTMI;
break;
case FSL_USB2_PHY_NONE:
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index bdf43e2..0e400c2 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,6 +45,7 @@
#define FSL_SOC_USB_PRICTRL0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
+#define CTRL_UTMI_PHY_EN (19)
#define CTRL_PHY_CLK_VALID (1 17)
#define SNOOP_SIZE_2GB 0x1e
#endif /* _EHCI_FSL_H */
--
1.6.4
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[PATCH] powerpc/usb: fix issue of CPU halt when missing USB PHY clock
when missing USB PHY clock, kernel booting up will halt during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hang in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/usb/host/ehci-fsl.c | 11 +--
drivers/usb/host/ehci-fsl.h |1 +
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b556a72..834237e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
ehci_writel(ehci, portsc, ehci-regs-port_status[port_offset]);
}
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
@@ -299,12 +299,19 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x0001);
}
+
+ if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) CTRL_PHY_CLK_VALID)) {
+ printk(KERN_WARNING fsl-ehci: USB PHY clock invalid\n);
+ return -1;
+ }
+ return 0;
}
/* called after powerup, by probe or system-pm wakeup */
static int ehci_fsl_reinit(struct ehci_hcd *ehci)
{
- ehci_fsl_usb_setup(ehci);
+ if (ehci_fsl_usb_setup(ehci))
+ return -1;
ehci_port_power(ehci, 0);
return 0;
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 4918062..dd3dc47 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,5 +45,6 @@
#define FSL_SOC_USB_PRICTRL0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
+#define CTRL_PHY_CLK_VALID (1 17)
#define SNOOP_SIZE_2GB 0x1e
#endif /* _EHCI_FSL_H */
--
1.6.4
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[PATCH v2] powerpc/usb: fix issue of CPU halt when missing USB PHY clock
when missing USB PHY clock, kernel booting up will halt during USB
initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid
CPU hang in this case.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: changes: return -ENODEV instead of -1
drivers/usb/host/ehci-fsl.c | 11 +--
drivers/usb/host/ehci-fsl.h |1 +
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b556a72..c26a82e 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
ehci_writel(ehci, portsc, ehci-regs-port_status[port_offset]);
}
-static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
@@ -299,12 +299,19 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x0001);
}
+
+ if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) CTRL_PHY_CLK_VALID)) {
+ printk(KERN_WARNING fsl-ehci: USB PHY clock invalid\n);
+ return -ENODEV;
+ }
+ return 0;
}
/* called after powerup, by probe or system-pm wakeup */
static int ehci_fsl_reinit(struct ehci_hcd *ehci)
{
- ehci_fsl_usb_setup(ehci);
+ if (ehci_fsl_usb_setup(ehci))
+ return -ENODEV;
ehci_port_power(ehci, 0);
return 0;
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 4918062..dd3dc47 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,5 +45,6 @@
#define FSL_SOC_USB_PRICTRL0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
+#define CTRL_PHY_CLK_VALID (1 17)
#define SNOOP_SIZE_2GB 0x1e
#endif /* _EHCI_FSL_H */
--
1.6.4
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[PATCH 1/2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
There was a bug for fmr initialization, which lead to fmr was always 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value and not relying on the setting of bootloader. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v3: add more descriptions. v2: make fmr not relying on the setting of bootloader. drivers/mtd/nand/fsl_elbc_nand.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index eedd8ee..4f405a0 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) if (chip-pagemask 0xff00) al++; - /* add to ECCM mode set in fsl_elbc_init */ - priv-fmr |= (12 FMR_CWTO_SHIFT) | /* Timeout 12 ms */ -(al FMR_AL_SHIFT); + priv-fmr |= al FMR_AL_SHIFT; dev_dbg(priv-dev, fsl_elbc_init: nand-numchips = %d\n, chip-numchips); @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) priv-mtd.priv = chip; priv-mtd.owner = THIS_MODULE; - /* Set the ECCM according to the settings in bootloader.*/ - priv-fmr = in_be32(lbc-fmr) FMR_ECCM; + /* set timeout to maximum */ + priv-fmr = 15 FMR_CWTO_SHIFT; + if (in_be32(lbc-bank[priv-bank].or) OR_FCM_PGS) + priv-fmr |= FMR_ECCM; /* fill in nand_chip structure */ /* set up function call table */ -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] mtd/nand: Add ONFI support for FSL NAND controller
- fix NAND_CMD_READID command for ONFI detect. - add NAND_CMD_PARAM command to read the ONFI parameter page. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v3: unify the bytes of fbcr to 256. v2: no changes drivers/mtd/nand/fsl_elbc_nand.c | 18 ++ 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 4f405a0..320584a 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -349,20 +349,22 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, fsl_elbc_run_command(mtd); return; - /* READID must read all 5 possible bytes while CEB is active */ case NAND_CMD_READID: - dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD_READID.\n); + case NAND_CMD_PARAM: + dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD %x\n, command); out_be32(lbc-fir, (FIR_OP_CM0 FIR_OP0_SHIFT) | (FIR_OP_UA FIR_OP1_SHIFT) | (FIR_OP_RBW FIR_OP2_SHIFT)); - out_be32(lbc-fcr, NAND_CMD_READID FCR_CMD0_SHIFT); - /* nand_get_flash_type() reads 8 bytes of entire ID string */ - out_be32(lbc-fbcr, 8); - elbc_fcm_ctrl-read_bytes = 8; + out_be32(lbc-fcr, command FCR_CMD0_SHIFT); + /* +* although currently it's 8 bytes for READID, we always read +* the maximum 256 bytes(for PARAM) +*/ + out_be32(lbc-fbcr, 256); + elbc_fcm_ctrl-read_bytes = 256; elbc_fcm_ctrl-use_mdr = 1; - elbc_fcm_ctrl-mdr = 0; - + elbc_fcm_ctrl-mdr = column; set_addr(mtd, 0, 0, 0); fsl_elbc_run_command(mtd); return; -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2 v2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
There was a bug for fmr initialization, which lead to fmr was always 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum timeout value and not relying on the setting of bootloader. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v2: make fmr not relying on the setting of bootloader. drivers/mtd/nand/fsl_elbc_nand.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index eedd8ee..4f405a0 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) if (chip-pagemask 0xff00) al++; - /* add to ECCM mode set in fsl_elbc_init */ - priv-fmr |= (12 FMR_CWTO_SHIFT) | /* Timeout 12 ms */ -(al FMR_AL_SHIFT); + priv-fmr |= al FMR_AL_SHIFT; dev_dbg(priv-dev, fsl_elbc_init: nand-numchips = %d\n, chip-numchips); @@ -764,8 +762,10 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) priv-mtd.priv = chip; priv-mtd.owner = THIS_MODULE; - /* Set the ECCM according to the settings in bootloader.*/ - priv-fmr = in_be32(lbc-fmr) FMR_ECCM; + /* set timeout to maximum */ + priv-fmr = 15 FMR_CWTO_SHIFT; + if (in_be32(lbc-bank[priv-bank].or) OR_FCM_PGS) + priv-fmr |= FMR_ECCM; /* fill in nand_chip structure */ /* set up function call table */ -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2 v2] mtd/nand: Add ONFI support for FSL NAND controller
- fix NAND_CMD_READID command for ONFI detect.
- add NAND_CMD_PARAM command to read the ONFI parameter page.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: no changes
drivers/mtd/nand/fsl_elbc_nand.c | 19 ---
1 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 4f405a0..b4db407 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd,
unsigned int command,
fsl_elbc_run_command(mtd);
return;
- /* READID must read all 5 possible bytes while CEB is active */
case NAND_CMD_READID:
- dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD_READID.\n);
+ case NAND_CMD_PARAM:
+ dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD %x\n, command);
out_be32(lbc-fir, (FIR_OP_CM0 FIR_OP0_SHIFT) |
(FIR_OP_UA FIR_OP1_SHIFT) |
(FIR_OP_RBW FIR_OP2_SHIFT));
- out_be32(lbc-fcr, NAND_CMD_READID FCR_CMD0_SHIFT);
- /* nand_get_flash_type() reads 8 bytes of entire ID string */
- out_be32(lbc-fbcr, 8);
- elbc_fcm_ctrl-read_bytes = 8;
+ out_be32(lbc-fcr, command FCR_CMD0_SHIFT);
+ /* reads 8 bytes of entire ID string */
+ if (NAND_CMD_READID == command) {
+ out_be32(lbc-fbcr, 8);
+ elbc_fcm_ctrl-read_bytes = 8;
+ } else {
+ out_be32(lbc-fbcr, 256);
+ elbc_fcm_ctrl-read_bytes = 256;
+ }
elbc_fcm_ctrl-use_mdr = 1;
- elbc_fcm_ctrl-mdr = 0;
+ elbc_fcm_ctrl-mdr = column;
set_addr(mtd, 0, 0, 0);
fsl_elbc_run_command(mtd);
--
1.6.4
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[PATCH 2/2] mtd/nand: Add ONFI support for FSL NAND controller
- fix NAND_CMD_READID command for ONFI detect.
- add NAND_CMD_PARAM command to read the ONFI parameter page.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c | 19 ---
1 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 742bf73..08a3aba 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -349,19 +349,24 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd,
unsigned int command,
fsl_elbc_run_command(mtd);
return;
- /* READID must read all 5 possible bytes while CEB is active */
case NAND_CMD_READID:
- dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD_READID.\n);
+ case NAND_CMD_PARAM:
+ dev_vdbg(priv-dev, fsl_elbc_cmdfunc: NAND_CMD %x\n, command);
out_be32(lbc-fir, (FIR_OP_CM0 FIR_OP0_SHIFT) |
(FIR_OP_UA FIR_OP1_SHIFT) |
(FIR_OP_RBW FIR_OP2_SHIFT));
- out_be32(lbc-fcr, NAND_CMD_READID FCR_CMD0_SHIFT);
- /* nand_get_flash_type() reads 8 bytes of entire ID string */
- out_be32(lbc-fbcr, 8);
- elbc_fcm_ctrl-read_bytes = 8;
+ out_be32(lbc-fcr, command FCR_CMD0_SHIFT);
+ /* reads 8 bytes of entire ID string */
+ if (NAND_CMD_READID == command) {
+ out_be32(lbc-fbcr, 8);
+ elbc_fcm_ctrl-read_bytes = 8;
+ } else {
+ out_be32(lbc-fbcr, 256);
+ elbc_fcm_ctrl-read_bytes = 256;
+ }
elbc_fcm_ctrl-use_mdr = 1;
- elbc_fcm_ctrl-mdr = 0;
+ elbc_fcm_ctrl-mdr = column;
set_addr(mtd, 0, 0, 0);
fsl_elbc_run_command(mtd);
--
1.6.4
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[PATCH 1/2] mtd/nand: fixup for fmr initialization of Freescale NAND controller
There was a bug for fmr initialization, which lead to fmr was always 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before calling fsl_elbc_chip_init_tail(). Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- drivers/mtd/nand/fsl_elbc_nand.c |8 +++- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index eedd8ee..742bf73 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -659,9 +659,7 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) if (chip-pagemask 0xff00) al++; - /* add to ECCM mode set in fsl_elbc_init */ - priv-fmr |= (12 FMR_CWTO_SHIFT) | /* Timeout 12 ms */ -(al FMR_AL_SHIFT); + priv-fmr |= al FMR_AL_SHIFT; dev_dbg(priv-dev, fsl_elbc_init: nand-numchips = %d\n, chip-numchips); @@ -764,8 +762,8 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) priv-mtd.priv = chip; priv-mtd.owner = THIS_MODULE; - /* Set the ECCM according to the settings in bootloader.*/ - priv-fmr = in_be32(lbc-fmr) FMR_ECCM; + /* Set fmr according to the settings in bootloader.*/ + priv-fmr = in_be32(lbc-fmr); /* fill in nand_chip structure */ /* set up function call table */ -- 1.6.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] mtd/nand: Add NAND chip ID to support Micron 4k pagesize NAND chip
Add NAND chip ID 0x38 in ids table to support Micron 4k large-page NAND chip.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
drivers/mtd/nand/nand_ids.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 00cf1b0..23ed1d2 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -106,6 +106,7 @@ struct nand_flash_dev nand_flash_ids[] = {
/* 8 Gigabit */
{NAND 1GiB 1,8V 8-bit,0xA3, 0, 1024, 0, LP_OPTIONS},
{NAND 1GiB 3,3V 8-bit,0xD3, 0, 1024, 0, LP_OPTIONS},
+ {NAND 1GiB 3,3V 8-bit,0x38, 0, 1024, 0, LP_OPTIONS},
{NAND 1GiB 1,8V 16-bit, 0xB3, 0, 1024, 0, LP_OPTIONS16},
{NAND 1GiB 3,3V 16-bit, 0xC3, 0, 1024, 0, LP_OPTIONS16},
--
1.6.4
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[PATCH] Powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
Simultaneous FCM and GPCM or UPM operation may erroneously trigger
bus monitor timeout.
Set the local bus monitor timeout value to the maximum by setting
LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Gala Kumar kumar.g...@freescale.com
---
arch/powerpc/include/asm/fsl_lbc.h |2 ++
arch/powerpc/sysdev/fsl_lbc.c |9 +++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 5c1bf34..8a0b5ec 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -157,6 +157,8 @@ struct fsl_lbc_regs {
#define LBCR_EPAR_SHIFT16
#define LBCR_BMT 0xFF00
#define LBCR_BMT_SHIFT 8
+#define LBCR_BMTPS 0x000F
+#define LBCR_BMTPS_SHIFT0
#define LBCR_INIT 0x0004
__be32 lcrr;/** Clock Ratio Register */
#define LCRR_DBYP0x8000
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 4fcb5a4..19a4ecd 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -184,7 +184,8 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem
*io_base, u32 mar)
}
EXPORT_SYMBOL(fsl_upm_run_pattern);
-static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
+static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
+ struct device_node *node)
{
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
@@ -198,6 +199,10 @@ static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl
*ctrl)
/* Enable interrupts for any detected events */
out_be32(lbc-lteir, LTEIR_ENABLE);
+ /* Set the monitor timeout value to the maximum for erratum A001 */
+ if (of_device_is_compatible(node, fsl,elbc))
+ clrsetbits_be32(lbc-lbcr, LBCR_BMT, LBCR_BMTPS);
+
return 0;
}
@@ -304,7 +309,7 @@ static int __devinit fsl_lbc_ctrl_probe(struct
platform_device *dev)
fsl_lbc_ctrl_dev-dev = dev-dev;
- ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
+ ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, ofdev-node);
if (ret 0)
goto err;
--
1.6.4
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