Re: [PATCH 1/3] perf/e6500: Make event translations available in sysfs
On Mon, Feb 09, 2015 at 09:40:19PM +0100, Andi Kleen wrote: I'll NAK any external 'download area' (and I told that Andi before): tools/perf/event-tables/ or so is a good enough 'download area' with fast enough update cycles. The proposal was to put it on kernel.org, similar to how external firmware blobs are distributed. CPU event lists are data sheets, so are like firmware. They do not follow the normal kernel code licenses. They are not source code. They cannot be reviewed in the normal way. Could you provide more details about the license and review concern? How are the event list files different from hardware- specific information (e.g. reg mapping) in header files? If any 'update' of event descriptions is needed it can happen through the distro package mechanism, or via a simple 'git pull' if it's compiled directly. Lets not overengineer this with any dependence on an external site and with a separate update mechanism - lets just get the tables into tools/ and see it from there... That experiment has been already done for oprofile, didn't work very well. Please excuse my ignorance, could you say exactly what didn't work well for oprofile? Ingo's suggestion seems good to me because these event files will be transparent to the users, and it's just more convenient not having to go to a website to look for the event file that matches the machine to download. The distro package or the perf make mechanism can put these files into the appropriate directory. The users who are not perf developers won't need to know about these files. - Tom ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/3] perf/doc: Update perf_event_attr struct
Update the fields in perf_event_attr as currently seen in
include/uapi/linux/perf_event.h
Remove outdated comments on the config field
The doc has not account for commit a21ca2cac582 (perf_counter:
Separate out attr-type from attr-config).
Signed-off-by: Tom Huynh tom.hu...@freescale.com
---
tools/perf/design.txt | 159 +++---
1 file changed, 113 insertions(+), 46 deletions(-)
diff --git a/tools/perf/design.txt b/tools/perf/design.txt
index a28dca2..96bd261 100644
--- a/tools/perf/design.txt
+++ b/tools/perf/design.txt
@@ -32,60 +32,127 @@ can be used to set the blocking mode, etc.
Multiple counters can be kept open at a time, and the counters
can be poll()ed.
-When creating a new counter fd, 'perf_event_attr' is:
+When creating a new counter fd, 'perf_event_attr' is defined in
+include/linux/uapi/perf_event.h as:
struct perf_event_attr {
-/*
- * The MSB of the config word signifies if the rest contains cpu
- * specific (raw) counter configuration data, if unset, the next
- * 7 bits are an event type and the rest of the bits are the event
- * identifier.
- */
-__u64 config;
-
-__u64 irq_period;
-__u32 record_type;
-__u32 read_format;
-
-__u64 disabled : 1, /* off by default
*/
-inherit: 1, /* children inherit it
*/
-pinned : 1, /* must always be on PMU
*/
-exclusive : 1, /* only group on PMU
*/
-exclude_user : 1, /* don't count user
*/
-exclude_kernel : 1, /* ditto kernel
*/
-exclude_hv : 1, /* ditto hypervisor
*/
-exclude_idle : 1, /* don't count when idle
*/
-mmap : 1, /* include mmap data
*/
-munmap : 1, /* include munmap data
*/
-comm : 1, /* include comm data
*/
-
-__reserved_1 : 52;
-
-__u32 extra_config_len;
-__u32 wakeup_events; /* wakeup every n events */
-
-__u64 __reserved_2;
-__u64 __reserved_3;
-};
-The 'config' field specifies what the counter should count. It
-is divided into 3 bit-fields:
+ /*
+* Major type: hardware/software/tracepoint/etc.
+*/
+ __u32 type;
+
+ /*
+* Size of the attr structure, for fwd/bwd compat.
+*/
+ __u32 size;
+
+ /*
+* Type specific configuration information.
+*/
+ __u64 config;
+
+ union {
+ __u64 sample_period;
+ __u64 sample_freq;
+ };
+
+ __u64 sample_type;
+ __u64 read_format;
+
+ __u64 disabled : 1, /* off by default*/
+ inherit: 1, /* children inherit it */
+ pinned : 1, /* must always be on PMU */
+ exclusive : 1, /* only group on PMU */
+ exclude_user : 1, /* don't count user */
+ exclude_kernel : 1, /* ditto kernel */
+ exclude_hv : 1, /* ditto hypervisor */
+ exclude_idle : 1, /* don't count when idle */
+ mmap : 1, /* include mmap data */
+ comm : 1, /* include comm data */
+ freq : 1, /* use freq, not period */
+ inherit_stat : 1, /* per task counts */
+ enable_on_exec : 1, /* next exec enables */
+ task : 1, /* trace fork/exit */
+ watermark : 1, /* wakeup_watermark */
+ /*
+* precise_ip:
+*
+* 0 - SAMPLE_IP can have arbitrary skid
+* 1 - SAMPLE_IP must have constant skid
+* 2 - SAMPLE_IP requested to have 0 skid
+* 3 - SAMPLE_IP must have 0 skid
+*
+* See also PERF_RECORD_MISC_EXACT_IP
[PATCH 2/3] perf/e6500: Create a sysfs format entry for e6500 events
Create a sysfs entry, '/sys/bus/event_source/devices/cpu/format/event'
which describes the format of the e6500 PMU events. e6500 has = 512
events, so use the 9 lsb to specify the raw event code.
$ cat /sys/devices/cpu/format/event
config:0-8
Similar to commit 3bf7b07ece6e (perf/POWER7: Create a sysfs format
entry for Power7 events).
Signed-off-by: Kim Phillips kim.phill...@freescale.com
Signed-off-by: Tom Huynh tom.hu...@freescale.com
---
arch/powerpc/perf/e6500-pmu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/powerpc/perf/e6500-pmu.c b/arch/powerpc/perf/e6500-pmu.c
index abaa6d7..4bbdbb0 100644
--- a/arch/powerpc/perf/e6500-pmu.c
+++ b/arch/powerpc/perf/e6500-pmu.c
@@ -133,7 +133,20 @@ static struct attribute_group e6500_pmu_events_group = {
.attrs = e6500_events_attr,
};
+PMU_FORMAT_ATTR(event, config:0-8);
+
+static struct attribute *e6500_pmu_format_attr[] = {
+ format_attr_event.attr,
+ NULL,
+};
+
+struct attribute_group e6500_pmu_format_group = {
+ .name = format,
+ .attrs = e6500_pmu_format_attr,
+};
+
static const struct attribute_group *e6500_pmu_attr_groups[] = {
+ e6500_pmu_format_group,
e6500_pmu_events_group,
NULL,
};
--
1.9.1
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[PATCH 1/3] perf/e6500: Make event translations available in sysfs
Make the perf events in e6500 available via sysfs.
$ ls /sys/devices/cpu/events/
branch-instructions
branch-misses
cache-misses
cpu-cycles
instructions
FSL_0_INST_CMPL
FSL_1_INST_CMPL
...
$ cat /sys/devices/cpu/events/cpu-cycles
event=0x01
Similar to the following commits:
- 1c53a270724d (perf/POWER7: Make generic event translations
available in sysfs).
- 886c3b2d677f (perf/POWER7: Make some POWER7 events available
in sysfs)
- cfe0d8ba14a1 (perf tools: Make Power7 events available for perf)
Signed-off-by: Tom Huynh tom.hu...@freescale.com
---
arch/powerpc/include/asm/perf_event_fsl_emb.h | 20 +-
arch/powerpc/perf/core-fsl-emb.c | 12 ++
arch/powerpc/perf/e6500-events-list.h | 289 ++
arch/powerpc/perf/e6500-pmu.c | 50 -
4 files changed, 365 insertions(+), 6 deletions(-)
create mode 100644 arch/powerpc/perf/e6500-events-list.h
diff --git a/arch/powerpc/include/asm/perf_event_fsl_emb.h
b/arch/powerpc/include/asm/perf_event_fsl_emb.h
index a581654..d76124f 100644
--- a/arch/powerpc/include/asm/perf_event_fsl_emb.h
+++ b/arch/powerpc/include/asm/perf_event_fsl_emb.h
@@ -11,6 +11,7 @@
*/
#include linux/types.h
+#include linux/device.h
#include asm/hw_irq.h
#define MAX_HWEVENTS 6
@@ -39,7 +40,7 @@ struct fsl_emb_pmu {
/* Returns event flags and PMLCb (FSL_EMB_EVENT_*) */
u64 (*xlate_event)(u64 event_id);
-
+ const struct attribute_group**attr_groups;
int n_generic;
int *generic_events;
int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
@@ -48,3 +49,20 @@ struct fsl_emb_pmu {
};
int register_fsl_emb_pmu(struct fsl_emb_pmu *);
+
+extern ssize_t fsl_emb_events_sysfs_show(struct device *dev,
+struct device_attribute *attr,
+char *page);
+
+#define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix
+#define EVENT_PTR(_id, _suffix) (event_attr_##_id##_suffix.attr.attr)
+
+#define EVENT_ATTR(_name, _id, _suffix) \
+ PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_##_id, \
+ fsl_emb_events_sysfs_show)
+
+#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
+#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
+
+#define FSL_EMB_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p)
+#define FSL_EMB_EVENT_PTR(_id) EVENT_PTR(_id, _p)
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 4acaea0..d4af2f3 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -581,6 +581,16 @@ static int fsl_emb_pmu_event_init(struct perf_event *event)
return err;
}
+ssize_t fsl_emb_events_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct perf_pmu_events_attr *pmu_attr;
+
+ pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
+
+ return sprintf(page, event=0x%02llx\n, pmu_attr-id);
+}
+
static struct pmu fsl_emb_pmu = {
.pmu_enable = fsl_emb_pmu_enable,
.pmu_disable= fsl_emb_pmu_disable,
@@ -711,6 +721,8 @@ int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
pr_info(%s performance monitor hardware support registered\n,
pmu-name);
+ fsl_emb_pmu.attr_groups = ppmu-attr_groups;
+
perf_pmu_register(fsl_emb_pmu, cpu, PERF_TYPE_RAW);
return 0;
diff --git a/arch/powerpc/perf/e6500-events-list.h
b/arch/powerpc/perf/e6500-events-list.h
new file mode 100644
index 000..27be38a
--- /dev/null
+++ b/arch/powerpc/perf/e6500-events-list.h
@@ -0,0 +1,289 @@
+/*
+ * Performance counter support for e6500 family processors.
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+EVENT(FSL_CYC, 1)
+EVENT(FSL_INST_CMPL, 2)
+EVENT(FSL_UOPS_CMPL, 3)
+EVENT(FSL_UOPS_DECODED,5)
+EVENT(FSL_PM_EV_TRANS, 6)
+EVENT(FSL_PM_EV_CYC, 7)
+EVENT(FSL_BR_CMPL, 8)
+EVENT(FSL_BR_TKN, 67)
+EVENT(FSL_BLR_TKN, 68)
+EVENT(FSL_NUM_CQ_REDIR,11)
+EVENT(FSL_LD_UOPS_CMPL,9)
+EVENT(FSL_ST_UOPS_CMPL,10)
+EVENT(FSL_LSU_UOPS_CMPL, 181)
+EVENT(FSL_GPR_LD_CMPL
[PATCH 0/3] Add e6500 perf events to sysfs and update perf doc
This patch set adds generic events, specific events, and format attribute for the e6500 pmu to sysfs. This makes perf more convenient to use on the e6500 by allowing the users to see all supported events and specify events using meaningful names instead of raw event codes. This patchset includes similar features in the following commits: - 1c53a270724d (perf/POWER7: Make generic event translations available in sysfs). - 886c3b2d677f (perf/POWER7: Make some POWER7 events available in sysfs) - cfe0d8ba14a1 (perf tools: Make Power7 events available for perf) - 3bf7b07ece6e (perf/POWER7: Create a sysfs format entry for Power7 events). This patchset also update tool/perf/design.txt to account for the changes in commit a21ca2cac582 (perf_counter: Separate out attr-type from attr-config). Attached patches: 1/3 perf/e6500: Make event translations available in sysfs 2/3 perf/e6500: Create a sysfs format entry for e6500 events 3/3 perf/doc: Update perf_event_attr struct arch/powerpc/include/asm/perf_event_fsl_emb.h | 20 +- arch/powerpc/perf/core-fsl-emb.c | 12 ++ arch/powerpc/perf/e6500-events-list.h | 289 ++ arch/powerpc/perf/e6500-pmu.c | 63 +- tools/perf/design.txt | 159 ++ 5 files changed, 491 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/perf/e6500-events-list.h -- 1.9.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/perf: fix fsl_emb_pmu_start to write correct pmc value
PMCs on PowerPC increases towards 0x8000 and triggers an overflow
interrupt when the msb is set to collect a sample. Therefore, to setup
for the next sample collection, pmu_start should set the pmc value to
0x8000 - left instead of left which incorrectly delays the next
overflow interrupt. Same as commit 9a45a9407c69 (powerpc/perf:
power_pmu_start restores incorrect values, breaking frequency events)
for book3s.
Signed-off-by: Tom Huynh tom.hu...@freescale.com
---
arch/powerpc/perf/core-fsl-emb.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 4acaea0..e9fe904 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -389,6 +389,7 @@ static void fsl_emb_pmu_del(struct perf_event *event, int
flags)
static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags)
{
unsigned long flags;
+ unsigned long val;
s64 left;
if (event-hw.idx 0 || !event-hw.sample_period)
@@ -405,7 +406,10 @@ static void fsl_emb_pmu_start(struct perf_event *event,
int ef_flags)
event-hw.state = 0;
left = local64_read(event-hw.period_left);
- write_pmc(event-hw.idx, left);
+ val = 0;
+ if (left 0x8000L)
+ val = 0x8000L - left;
+ write_pmc(event-hw.idx, val);
perf_event_update_userpage(event);
perf_pmu_enable(event-pmu);
--
1.9.1
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