from:"Xie Xiaobo"

[PATCH] powerpc/qe: Setup clock source for TDM

2014-03-18 Thread Xie Xiaobo

Add tdm clock configuration in both qe clock system and
ucc fast controler.

Signed-off-by: Xie Xiaobo x@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
 arch/powerpc/include/asm/immap_qe.h   |   5 +-
 arch/powerpc/include/asm/qe.h |  13 +-
 arch/powerpc/include/asm/ucc.h|   6 +-
 arch/powerpc/include/asm/ucc_fast.h   |  10 +-
 arch/powerpc/sysdev/qe_lib/qe.c   |   9 +-
 arch/powerpc/sysdev/qe_lib/ucc.c  | 773 +-
 arch/powerpc/sysdev/qe_lib/ucc_fast.c |  40 +-
 7 files changed, 845 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/include/asm/immap_qe.h 
b/arch/powerpc/include/asm/immap_qe.h
index bedbff8..c76ef30 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -159,10 +159,7 @@ struct spi {
 
 /* SI */
 struct si1 {
-   __be16  siamr1; /* SI1 TDMA mode register */
-   __be16  sibmr1; /* SI1 TDMB mode register */
-   __be16  sicmr1; /* SI1 TDMC mode register */
-   __be16  sidmr1; /* SI1 TDMD mode register */
+   __be16  sixmr1[4];  /* SI1 TDMx (x = A B C D) mode register */
u8  siglmr1_h;  /* SI1 global mode register high */
u8  res0[0x1];
u8  sicmdr1_h;  /* SI1 command register high */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 32b9bfa..1c80fdc 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2006, 2014 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Authors:Shlomi Gridish grid...@freescale.com
  * Li Yang le...@freescale.com
@@ -75,6 +75,8 @@ enum qe_clock {
QE_CLK22,   /* Clock 22 */
QE_CLK23,   /* Clock 23 */
QE_CLK24,   /* Clock 24 */
+   QE_RSYNC_PIN,   /* RSYNC from pin */
+   QE_TSYNC_PIN,   /* TSYNC from pin */
QE_CLK_DUMMY
 };
 
@@ -636,6 +638,15 @@ struct ucc_slow_pram {
 #define UCC_BISYNC_UCCE_TXB0x0002
 #define UCC_BISYNC_UCCE_RXB0x0001
 
+/* Transparent UCC Event Register (UCCE) */
+#define UCC_TRANS_UCCE_GRA 0x0080
+#define UCC_TRANS_UCCE_TXE 0x0010
+#define UCC_TRANS_UCCE_RXF 0x0008
+#define UCC_TRANS_UCCE_BSY 0x0004
+#define UCC_TRANS_UCCE_TXB 0x0002
+#define UCC_TRANS_UCCE_RXB 0x0001
+
+
 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
 #define UCC_GETH_UCCE_MPD   0x8000
 #define UCC_GETH_UCCE_SCAR  0x4000
diff --git a/arch/powerpc/include/asm/ucc.h b/arch/powerpc/include/asm/ucc.h
index 6927ac2..0a942c9 100644
--- a/arch/powerpc/include/asm/ucc.h
+++ b/arch/powerpc/include/asm/ucc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2006, 2014 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Authors:Shlomi Gridish grid...@freescale.com
  * Li Yang le...@freescale.com
@@ -41,6 +41,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
 
 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
enum comm_dir mode);
+int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock,
+   enum comm_dir mode);
+int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock,
+   enum comm_dir mode);
 
 int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
 
diff --git a/arch/powerpc/include/asm/ucc_fast.h 
b/arch/powerpc/include/asm/ucc_fast.h
index 72ea9ba..98e19d8 100644
--- a/arch/powerpc/include/asm/ucc_fast.h
+++ b/arch/powerpc/include/asm/ucc_fast.h
@@ -1,7 +1,7 @@
 /*
  * Internal header file for UCC FAST unit routines.
  *
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2006, 2014 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Authors:Shlomi Gridish grid...@freescale.com
  * Li Yang le...@freescale.com
@@ -27,12 +27,15 @@
 #define R_I0x1000  /* interrupt on reception */
 #define R_L0x0800  /* last */
 #define R_F0x0400  /* first */
+#define R_CM   0x0200  /* CM */
 
 /* transmit BD's status */
 #define T_R0x8000  /* ready bit */
 #define T_W0x2000  /* wrap bit */
 #define T_I0x1000  /* interrupt on completion */
 #define T_L0x0800  /* last */
+#define T_TC   0x0400  /* crc */
+#define T_CM   0x0200  /* CM */
 
 /* Rx Data buffer must be 4 bytes aligned in most cases */
 #define UCC_FAST_RX_ALIGN  4
@@ -118,9 +121,12 @@ enum ucc_fast_transparent_tcrc {
 /* Fast UCC initialization structure */
 struct ucc_fast_info {
int ucc_num;
+   int tdm_num;
enum qe_clock rx_clock;
enum qe_clock tx_clock;
-   u32 regs;
+   enum qe_clock rx_sync

[PATCH V6 1/2] powerpc/85xx: Add QE common init function

2013-11-06 Thread Xie Xiaobo

Define a QE init function in common file, and avoid
the same codes being duplicated in board files.

Signed-off-by: Xie Xiaobo x@freescale.com
---
V6 - V5: add of_device_is_available check.
V5 - V4: add the board files modification, remove the qe_pic_init.
V4 - V3: Nochange

 arch/powerpc/platforms/85xx/common.c  | 38 +++
 arch/powerpc/platforms/85xx/mpc85xx.h |  6 +
 arch/powerpc/platforms/85xx/mpc85xx_mds.c | 29 ++-
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 25 ++--
 4 files changed, 48 insertions(+), 50 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..970576b 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,7 @@
  */
 #include linux/of_platform.h
 
+#include asm/qe.h
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
@@ -80,3 +81,40 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe);
+   if (!np) {
+   np = of_find_node_by_name(NULL, qe);
+   if (!np) {
+   pr_err(%s: Could not find Quicc Engine node\n,
+   __func__);
+   return;
+   }
+   }
+
+   if (!of_device_is_available(np)) {
+   of_node_put(np);
+   return;
+   }
+
+   qe_reset();
+   of_node_put(np);
+
+   np = of_find_node_by_name(NULL, par_io);
+   if (np) {
+   struct device_node *ucc;
+
+   par_io_init(np);
+   of_node_put(np);
+
+   for_each_node_by_name(ucc, ucc)
+   par_io_of_config(ucc);
+
+   }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h 
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..fc51dd4 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,10 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..34f3c5e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
  * All rights reserved.
  *
  * Author: Andy Fleming aflem...@freescale.com
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
 {
struct device_node *np;
 
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   np = of_find_node_by_name(NULL, qe);
-   if (!np)
-   return;
-   }
-
-   if (!of_device_is_available(np)) {
-   of_node_put(np);
-   return;
-   }
-
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-   }
-
+   mpc85xx_qe_init();
mpc85xx_mds_reset_ucc_phys();
 
if (machine_is(p1021_mds)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c 
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0..e15bdd1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
 /*
  * MPC85xx RDB Board Setup
  *
- * Copyright 2009,2012 Freescale Semiconductor Inc.
+ * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -98,26 +98,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
 
 #ifdef CONFIG_QUICC_ENGINE
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   pr_err(%s: Could not find Quicc Engine node\n, __func__);
-   goto qe_fail;
-   }
-
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-
-   }
+   mpc85xx_qe_init

[PATCH V6 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-11-06 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V6: Add a binding doc for ssd1289 device.
Patch V5: Miscellaneous modification. e.g. move the qe ucc node into dtsi.
Patch V4: Fix the mdio phy interrupt issue in dts
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file

 .../devicetree/bindings/video/ssd1289fb.txt|  13 +
 arch/powerpc/boot/dts/p1025twr.dts |  95 +++
 arch/powerpc/boot/dts/p1025twr.dtsi| 280 +
 arch/powerpc/platforms/85xx/Kconfig|   6 +
 arch/powerpc/platforms/85xx/Makefile   |   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c| 147 +++
 6 files changed, 542 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/ssd1289fb.txt
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dts
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/Documentation/devicetree/bindings/video/ssd1289fb.txt 
b/Documentation/devicetree/bindings/video/ssd1289fb.txt
new file mode 100644
index 000..4fcd5e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ssd1289fb.txt
@@ -0,0 +1,13 @@
+* Solomon SSD1289 Framebuffer Driver
+
+Required properties:
+  - compatible: Should be solomon,ssd1289fb. The only supported bus for
+now is lbc.
+  - reg: Should contain address of the controller on the LBC bus. The detail
+was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
+
+Examples:
+display@2,0 {
+   compatible = solomon,ssd1289fb;
+   reg = 0x2 0x 0x0004;
+};
diff --git a/arch/powerpc/boot/dts/p1025twr.dts 
b/arch/powerpc/boot/dts/p1025twr.dts
new file mode 100644
index 000..9036a49
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dts
@@ -0,0 +1,95 @@
+/*
+ * P1025 TWR Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1021si-pre.dtsi
+/ {
+   model = fsl,P1025;
+   compatible = fsl,TWR-P1025;
+
+   memory {
+   device_type = memory;
+   };
+
+   lbc: localbus@ffe05000 {
+   reg = 0 0xffe05000 0 0x1000;
+
+   /* NOR Flash and SSD1289 */
+   ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x2 0x0 0x0 0xe000 0x0002;
+   };
+
+   soc: soc@ffe0 {
+   ranges = 0x0 0x0 0xffe0 0x10;
+   };
+
+   pci0: pcie@ffe09000 {
+   ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+   reg = 0 0xffe09000 0 0x1000;
+   pcie@0 {
+   ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000

RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

2013-09-26 Thread Xie Xiaobo-R63061

 -Original Message-
 From: Wood Scott-B07421
 Sent: Thursday, September 26, 2013 7:10 AM
 To: Xie Xiaobo-R63061
 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Johnston Michael-
 R49610
 Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

 On Wed, 2013-09-25 at 04:50 -0500, Xie Xiaobo-R63061 wrote:
  Hi Scott,

  See the reply inline.

   -Original Message-
   From: Wood Scott-B07421
   Sent: Wednesday, September 25, 2013 7:22 AM
   To: Xie Xiaobo-R63061
   Cc: linuxppc-dev@lists.ozlabs.org; Johnston Michael-R49610
   Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board
   support

   On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
+   partition@8 {
+   /* 3.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0038;
+   label = NOR Linux Kernel Image;
+   };

   Is this enough?

  I will enlarge it to 6MB.

+   partition@40 {
+   /* 58.75MB for JFFS2 based Root file System */
+   reg = 0x0040 0x03ac;
+   label = NOR Root File System;
+   };

   Don't specify jffs2.

  OK, I will remove jffs2

+   /* CS2 for Display */
+   ssd1289@2,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = ssd1289;
+   reg = 0x2 0x 0x0002
+  0x2 0x0002 0x0002;
+   };

   Node names should be generic.  What does ssd1289 do?  If this is
   actually the display device, then it should be called display@2,0.

  OK. The ssd1289 is a LCD controller.

   How about a vendor prefix on that compatible?  Why
   #address-cells/#size- cells despite no child nodes?  Where is a
   binding that says what each of those two reg resources mean?

  I will add the vendor prefix. I review the ssd1289 driver, and the
 #address-cells/#size-cells were un-used. I will remove them.

 And a binding?

 Why do you need two separate reg resources rather than just 2 0 4?
 Will they ever be discontiguous?

[Xie] I review the ssd1289 driver code, and found the driver need two reg 
resources, if change the dts, the driver also should be modified accordingly. 
So I remove the ssd1289 node from this patch. I will submit new patch include 
the dts modification, ssd1289 driver and the binding.   

 -Scott

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[PATCH V5 1/2] powerpc/85xx: Add QE common init function

2013-09-26 Thread Xie Xiaobo

Define a QE init function in common file, and avoid
the same codes being duplicated in board files.

Signed-off-by: Xie Xiaobo x@freescale.com
---
V5 - V4: add the board files modification, remove the qe_pic_init.
V4 - V3: Nochange

 arch/powerpc/platforms/85xx/common.c  | 33 +++
 arch/powerpc/platforms/85xx/mpc85xx.h |  6 ++
 arch/powerpc/platforms/85xx/mpc85xx_mds.c | 29 ++-
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 25 ++-
 4 files changed, 43 insertions(+), 50 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..568fd1f 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,7 @@
  */
 #include linux/of_platform.h
 
+#include asm/qe.h
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
@@ -80,3 +81,35 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe);
+   if (!np) {
+   np = of_find_node_by_name(NULL, qe);
+   if (!np) {
+   pr_err(%s: Could not find Quicc Engine node\n,
+   __func__);
+   return;
+   }
+   }
+
+   qe_reset();
+   of_node_put(np);
+
+   np = of_find_node_by_name(NULL, par_io);
+   if (np) {
+   struct device_node *ucc;
+
+   par_io_init(np);
+   of_node_put(np);
+
+   for_each_node_by_name(ucc, ucc)
+   par_io_of_config(ucc);
+
+   }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h 
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..fc51dd4 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,10 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..34f3c5e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
  * All rights reserved.
  *
  * Author: Andy Fleming aflem...@freescale.com
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
 {
struct device_node *np;
 
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   np = of_find_node_by_name(NULL, qe);
-   if (!np)
-   return;
-   }
-
-   if (!of_device_is_available(np)) {
-   of_node_put(np);
-   return;
-   }
-
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-   }
-
+   mpc85xx_qe_init();
mpc85xx_mds_reset_ucc_phys();
 
if (machine_is(p1021_mds)) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c 
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0..e15bdd1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
 /*
  * MPC85xx RDB Board Setup
  *
- * Copyright 2009,2012 Freescale Semiconductor Inc.
+ * Copyright 2009,2012-2013 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -98,26 +98,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
 
 #ifdef CONFIG_QUICC_ENGINE
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   pr_err(%s: Could not find Quicc Engine node\n, __func__);
-   goto qe_fail;
-   }
-
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-
-   }
+   mpc85xx_qe_init();
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
 
@@ -148,8 +129,6 @@ static void __init

[PATCH V5 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-09-26 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V5: Miscellaneous modification. e.g. move the qe ucc node into dtsi.
Patch V4: Fix the mdio phy interrupt issue in dts
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file

 arch/powerpc/boot/dts/p1025twr.dtsi | 274 
 arch/powerpc/boot/dts/p1025twr_32b.dts  |  94 +++
 arch/powerpc/platforms/85xx/Kconfig |   6 +
 arch/powerpc/platforms/85xx/Makefile|   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c | 147 +
 5 files changed, 522 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi 
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..30cdf8d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,274 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+   aliases {
+   ethernet3 = enet3;
+   ethernet4 = enet4;
+   };
+};
+
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x400;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 256KB for Vitesse 7385 Switch firmware */
+   reg = 0x0 0x0004;
+   label = NOR Vitesse-7385 Firmware;
+   read-only;
+   };
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 5.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0058;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@40 {
+   /* 56.75MB for Root file System */
+   reg = 0x0060 0x038c;
+   label = NOR Root File System;
+   };
+
+   partition@ec {
+   /* This location must not be altered  */
+   /* 256KB for QE ucode firmware*/
+   reg = 0x03ec 0x0004;
+   label = NOR QE microcode firmware;
+   read-only;
+   };
+
+   partition@f0 {
+   /* This location must not be altered

RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

2013-09-25 Thread Xie Xiaobo-R63061

Hi Scott,

See the reply inline.

 -Original Message-
 From: Wood Scott-B07421
 Sent: Wednesday, September 25, 2013 7:22 AM
 To: Xie Xiaobo-R63061
 Cc: linuxppc-dev@lists.ozlabs.org; Johnston Michael-R49610
 Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support
 
 On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
  +   partition@8 {
  +   /* 3.5 MB for Linux Kernel Image */
  +   reg = 0x0008 0x0038;
  +   label = NOR Linux Kernel Image;
  +   };
 
 Is this enough?

I will enlarge it to 6MB.
 
 
  +   partition@40 {
  +   /* 58.75MB for JFFS2 based Root file System */
  +   reg = 0x0040 0x03ac;
  +   label = NOR Root File System;
  +   };
 
 Don't specify jffs2.

OK, I will remove jffs2

 
  +   /* CS2 for Display */
  +   ssd1289@2,0 {
  +   #address-cells = 1;
  +   #size-cells = 1;
  +   compatible = ssd1289;
  +   reg = 0x2 0x 0x0002
  +  0x2 0x0002 0x0002;
  +   };
 
 Node names should be generic.  What does ssd1289 do?  If this is actually
 the display device, then it should be called display@2,0.

OK. The ssd1289 is a LCD controller.

 
 How about a vendor prefix on that compatible?  Why #address-cells/#size-
 cells despite no child nodes?  Where is a binding that says what each of
 those two reg resources mean?

I will add the vendor prefix. I review the ssd1289 driver, and the 
#address-cells/#size-cells were un-used. I will remove them.

 
  diff --git a/arch/powerpc/boot/dts/p1025twr_32b.dts
  b/arch/powerpc/boot/dts/p1025twr_32b.dts
  new file mode 100644
  index 000..ccb173f
  --- /dev/null
  +++ b/arch/powerpc/boot/dts/p1025twr_32b.dts
  @@ -0,0 +1,135 @@
  +/*
  + * P1025 TWR Device Tree Source (32-bit address map)
  + *
  + * Copyright 2013 Freescale Semiconductor Inc.
  + *
  + * Redistribution and use in source and binary forms, with or without
  + * modification, are permitted provided that the following conditions
 are met:
  + * * Redistributions of source code must retain the above
 copyright
  + *   notice, this list of conditions and the following disclaimer.
  + * * Redistributions in binary form must reproduce the above
 copyright
  + *   notice, this list of conditions and the following disclaimer
 in the
  + *   documentation and/or other materials provided with the
 distribution.
  + * * Neither the name of Freescale Semiconductor nor the
  + *   names of its contributors may be used to endorse or promote
 products
  + *   derived from this software without specific prior written
 permission.
  + *
  + *
  + * ALTERNATIVELY, this software may be distributed under the terms of
  +the
  + * GNU General Public License (GPL) as published by the Free
  +Software
  + * Foundation, either version 2 of that License or (at your option)
  +any
  + * later version.
  + *
  + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND
  +ANY
  + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  +IMPLIED
  + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  +ARE
  + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE
  +FOR ANY
  + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  +DAMAGES
  + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  +SERVICES;
  + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  +CAUSED AND
  + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  +OR TORT
  + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  +USE OF THIS
  + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  + */
  +
  +/include/ fsl/p1021si-pre.dtsi
  +/ {
  +   model = fsl,P1025;
  +   compatible = fsl,TWR-P1025;
  +
  +   memory {
  +   device_type = memory;
  +   };
  +
  +   lbc: localbus@ffe05000 {
  +   reg = 0 0xffe05000 0 0x1000;
  +
  +   /* NOR Flash and SSD1289 */
  +   ranges = 0x0 0x0 0x0 0xec00 0x0400
  + 0x2 0x0 0x0 0xe000 0x0002;
  +   };
  +
  +   soc: soc@ffe0 {
  +   ranges = 0x0 0x0 0xffe0 0x10;
  +   };
  +
  +   pci0: pcie@ffe09000 {
  +   ranges = 0x200 0x0 0xa000 0 0xa000 0x0
 0x2000
  + 0x100 0x0 0x 0 0xffc1 0x0 0x1;
  +   reg = 0 0xffe09000 0 0x1000;
  +   pcie@0 {
  +   ranges = 0x200 0x0 0xa000
  + 0x200 0x0 0xa000
  + 0x0 0x2000
  +
  + 0x100 0x0 0x0
  + 0x100 0x0 0x0
  + 0x0 0x10;
  +   };
  +   };
  +
  +   pci1: pcie@ffe0a000 {
  +   reg = 0 0xffe0a000 0 0x1000

RE: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions

2013-09-25 Thread Xie Xiaobo-R63061

 -Original Message-
 From: Wood Scott-B07421
 Sent: Wednesday, September 25, 2013 7:13 AM
 To: Xie Xiaobo-R63061
 Cc: linuxppc-dev@lists.ozlabs.org
 Subject: Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions

 On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
  Define two QE init functions in common file, and avoid the same codes
  being duplicated in board files.

  Signed-off-by: Xie Xiaobo x@freescale.com
  ---
  V4 - V3: Nochange

   arch/powerpc/platforms/85xx/common.c  | 51
  +++
   arch/powerpc/platforms/85xx/mpc85xx.h |  8 ++
   2 files changed, 59 insertions(+)

  diff --git a/arch/powerpc/platforms/85xx/common.c
  b/arch/powerpc/platforms/85xx/common.c
  index d0861a0..08fff48 100644
  --- a/arch/powerpc/platforms/85xx/common.c
  +++ b/arch/powerpc/platforms/85xx/common.c
  @@ -7,6 +7,9 @@
*/
   #include linux/of_platform.h

  +#include asm/machdep.h
  +#include asm/qe.h
  +#include asm/qe_ic.h
   #include sysdev/cpm2_pic.h

   #include mpc85xx.h
  @@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
  irq_set_chained_handler(irq, cpm2_cascade);  }  #endif
  +
  +#ifdef CONFIG_QUICC_ENGINE
  +void __init mpc85xx_qe_pic_init(void) {
  +   struct device_node *np;
  +
  +   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
  +   if (np) {
  +   if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
  +   qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
  +   else
  +   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  +   qe_ic_cascade_high_mpic);
  +   of_node_put(np);
  +   } else
  +   pr_err(%s: Could not find qe-ic node\n, __func__); }

 Have the caller pass in a flag indicating the type of cascade.  Or,
 perhaps this function isn't worth factoring out.  Where is the check for
 p1021_mds?  Where did 8568/9 MDS come from?  I don't see those checks
 removed in patch 2.

[Xie] The qe_pic_init just call one function qe_ic_init(), So I just need 
factor out the qe_init function, Is it feasible?

 BTW, when you move code from one place to another, do it in one patch.
 Don't add it in one patch and then remove it in another.  A more useful
 split would have been one patch handling qe_init and another handling
 qe_pic_init.

[Xie] I will place these change into a patch. 

 -Scott

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[PATCH V4 2/3] powerpc/85xx: Use common init functions for QE

2013-09-24 Thread Xie Xiaobo

Use common init functions instead of the duplicated codes
in some platforms with QUICC Engine.

Signed-off-by: Xie Xiaobo x@freescale.com
---
V4: new patch

 arch/powerpc/platforms/85xx/mpc85xx_mds.c | 55 ++-
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 36 ++--
 2 files changed, 4 insertions(+), 87 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..da28d74 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
 {
struct device_node *np;
 
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   np = of_find_node_by_name(NULL, qe);
-   if (!np)
-   return;
-   }
-
-   if (!of_device_is_available(np)) {
-   of_node_put(np);
-   return;
-   }
-
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-   }
-
+   mpc85xx_qe_init();
mpc85xx_mds_reset_ucc_phys();
 
if (machine_is(p1021_mds)) {
@@ -293,34 +268,8 @@ static void __init mpc85xx_mds_qe_init(void)
 
}
 }
-
-static void __init mpc85xx_mds_qeic_init(void)
-{
-   struct device_node *np;
-
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!of_device_is_available(np)) {
-   of_node_put(np);
-   return;
-   }
-
-   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
-   if (!np) {
-   np = of_find_node_by_type(NULL, qeic);
-   if (!np)
-   return;
-   }
-
-   if (machine_is(p1021_mds))
-   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-   qe_ic_cascade_high_mpic);
-   else
-   qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
-   of_node_put(np);
-}
 #else
 static void __init mpc85xx_mds_qe_init(void) { }
-static void __init mpc85xx_mds_qeic_init(void) { }
 #endif /* CONFIG_QUICC_ENGINE */
 
 static void __init mpc85xx_mds_setup_arch(void)
@@ -395,7 +344,7 @@ static void __init mpc85xx_mds_pic_init(void)
BUG_ON(mpic == NULL);
 
mpic_init(mpic);
-   mpc85xx_mds_qeic_init();
+   mpc85xx_qe_pic_init();
 }
 
 static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c 
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0..67d78e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -49,10 +49,6 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
 
-#ifdef CONFIG_QUICC_ENGINE
-   struct device_node *np;
-#endif
-
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -69,16 +65,8 @@ void __init mpc85xx_rdb_pic_init(void)
mpic_init(mpic);
 
 #ifdef CONFIG_QUICC_ENGINE
-   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
-   if (np) {
-   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-   qe_ic_cascade_high_mpic);
-   of_node_put(np);
-
-   } else
-   pr_err(%s: Could not find qe-ic node\n, __func__);
+   mpc85xx_qe_pic_init();
 #endif
-
 }
 
 /*
@@ -98,26 +86,8 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
 
 #ifdef CONFIG_QUICC_ENGINE
-   np = of_find_compatible_node(NULL, NULL, fsl,qe);
-   if (!np) {
-   pr_err(%s: Could not find Quicc Engine node\n, __func__);
-   goto qe_fail;
-   }
+   mpc85xx_qe_init();
 
-   qe_reset();
-   of_node_put(np);
-
-   np = of_find_node_by_name(NULL, par_io);
-   if (np) {
-   struct device_node *ucc;
-
-   par_io_init(np);
-   of_node_put(np);
-
-   for_each_node_by_name(ucc, ucc)
-   par_io_of_config(ucc);
-
-   }
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
 
@@ -148,8 +118,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
 
}
 #endif
-
-qe_fail:
 #endif /* CONFIG_QUICC_ENGINE */
 
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
-- 
1.8.0


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[PATCH V4 1/3] powerpc/85xx: Add QE common init functions

2013-09-24 Thread Xie Xiaobo

Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.

Signed-off-by: Xie Xiaobo x@freescale.com
---
V4 - V3: Nochange

 arch/powerpc/platforms/85xx/common.c  | 51 +++
 arch/powerpc/platforms/85xx/mpc85xx.h |  8 ++
 2 files changed, 59 insertions(+)

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..08fff48 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,9 @@
  */
 #include linux/of_platform.h
 
+#include asm/machdep.h
+#include asm/qe.h
+#include asm/qe_ic.h
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
@@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+   if (np) {
+   if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
+   qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+   else
+   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+   qe_ic_cascade_high_mpic);
+   of_node_put(np);
+   } else
+   pr_err(%s: Could not find qe-ic node\n, __func__);
+}
+
+void __init mpc85xx_qe_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe);
+   if (!np) {
+   np = of_find_node_by_name(NULL, qe);
+   if (!np) {
+   pr_err(%s: Could not find Quicc Engine node\n,
+   __func__);
+   return;
+   }
+   }
+
+   qe_reset();
+   of_node_put(np);
+
+   np = of_find_node_by_name(NULL, par_io);
+   if (np) {
+   struct device_node *ucc;
+
+   par_io_init(np);
+   of_node_put(np);
+
+   for_each_node_by_name(ucc, ucc)
+   par_io_of_config(ucc);
+
+   }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h 
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..1d39095 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_pic_init(void);
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_pic_init(void) {}
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
-- 
1.8.0


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[PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

2013-09-24 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V4: Fix the mdio phy interrupt issue in dts
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file

 arch/powerpc/boot/dts/p1025twr.dtsi | 244 
 arch/powerpc/boot/dts/p1025twr_32b.dts  | 135 ++
 arch/powerpc/platforms/85xx/Kconfig |   6 +
 arch/powerpc/platforms/85xx/Makefile|   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c | 142 +++
 5 files changed, 528 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi 
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..4b1d5f7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+   aliases {
+   ethernet3 = enet3;
+   ethernet4 = enet4;
+   };
+};
+
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x400;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 256KB for Vitesse 7385 Switch firmware */
+   reg = 0x0 0x0004;
+   label = NOR Vitesse-7385 Firmware;
+   read-only;
+   };
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 3.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0038;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@40 {
+   /* 58.75MB for JFFS2 based Root file System */
+   reg = 0x0040 0x03ac;
+   label = NOR Root File System;
+   };
+
+   partition@ec {
+   /* This location must not be altered  */
+   /* 256KB for QE ucode firmware*/
+   reg = 0x03ec 0x0004;
+   label = NOR QE microcode firmware;
+   read-only;
+   };
+
+   partition@f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image

RE: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

2013-09-10 Thread Xie Xiaobo-R63061

Hi,

Thank you very much. I will submit updated patch soon.

Best Regards
Xie Xiaobo
-Original Message-
From: Wood Scott-B07421 
Sent: Friday, September 06, 2013 11:25 PM
To: Xie Xiaobo-R63061
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: Re: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

On Fri, 2013-09-06 at 04:52 -0500, Xie Xiaobo-R63061 wrote:
 Hi Scott,

 I already remove these code from the P1025TWR platform file(see the 2/2 
 patch). Do you means I also need to remove these codes from the others 
 platforms and use the common call instead? 
 Thank you.

Yes.

-Scott

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RE: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-09-10 Thread Xie Xiaobo-R63061

Hi Scott,

I discuss it with Liu Shengzhou again. I tried interrupts = 1 1 0 0 instead 
of interrupts = 1 1 on P1025TWR, and it's OK. So I will add 2 cells for the 
interrupts property. Thank you.

Best Regards
Xie Xiaobo
-Original Message-
From: Wood Scott-B07421 
Sent: Friday, September 06, 2013 11:26 PM
To: Xie Xiaobo-R63061
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; 
ga...@kernel.crashing.org; Johnston Michael-R49610
Subject: Re: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

On Fri, 2013-09-06 at 05:01 -0500, Xie Xiaobo-R63061 wrote:
 Hi Scott,
 
 Thanks for your reminding and advice.
 
 I discuss this with Liu Shengzhou(the first person that remind me 
 #interrupt-cells is 4), he advised removing the interrupts property 
 from the phy node, because the mdio used the poll way preferentially.

I don't follow... if the PHYs have interrupts, why would we prefer to poll?

In any case, the device tree describes the hardware, not how you'd prefer to 
use it.

-Scott


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RE: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

2013-09-06 Thread Xie Xiaobo-R63061

Hi Scott,

I already remove these code from the P1025TWR platform file(see the 2/2 patch). 
Do you means I also need to remove these codes from the others platforms and 
use the common call instead? 
Thank you.

Best Regards
Xie Xiaobo
-Original Message-
From: Wood Scott-B07421 
Sent: Thursday, September 05, 2013 12:27 AM
To: Xie Xiaobo-R63061
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: Re: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

On Mon, 2013-09-02 at 18:11 +0800, Xie Xiaobo wrote:
 Define two QE init functions in common file, and avoid the same codes 
 being duplicated in board files.
 
 Signed-off-by: Xie Xiaobo x@freescale.com
 ---
 V3 - V2: Nochange
 
  arch/powerpc/platforms/85xx/common.c  | 47 
 +++
  arch/powerpc/platforms/85xx/mpc85xx.h |  8 ++
  2 files changed, 55 insertions(+)

Don't just copy it; remove it from the place you copied from and have that code 
call the common version.

-Scott


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RE: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-09-06 Thread Xie Xiaobo-R63061

Hi Scott,

Thanks for your reminding and advice.

I discuss this with Liu Shengzhou(the first person that remind me 
#interrupt-cells is 4), he advised removing the interrupts property from the 
phy node, because the mdio used the poll way preferentially.

Best Regards
Xie Xiaobo

-Original Message-
From: Wood Scott-B07421 
Sent: Thursday, September 05, 2013 12:26 AM
To: Xie Xiaobo-R63061
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Johnston 
Michael-R49610
Subject: Re: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

On Mon, 2013-09-02 at 18:11 +0800, Xie Xiaobo wrote:
 +soc {
 + usb@22000 {
 + phy_type = ulpi;
 + };
 +
 + mdio@24000 {
 + phy0: ethernet-phy@2 {
 + interrupt-parent = mpic;
 + interrupts = 1 1;
 + reg = 0x2;
 + };
 +
 + phy1: ethernet-phy@1 {
 + interrupt-parent = mpic;
 + interrupts = 2 1;
 + reg = 0x1;
 + };

Again, #interrupt-cells is 4.

Please respond to feedback rather than ignoring it and reposting the same thing 
without comment.

-Scott


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[PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-09-02 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file

 arch/powerpc/boot/dts/p1025twr.dtsi | 244 
 arch/powerpc/boot/dts/p1025twr_32b.dts  | 135 ++
 arch/powerpc/platforms/85xx/Kconfig |   6 +
 arch/powerpc/platforms/85xx/Makefile|   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c | 142 +++
 5 files changed, 528 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi 
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..07df721
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+   aliases {
+   ethernet3 = enet3;
+   ethernet4 = enet4;
+   };
+};
+
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x400;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 256KB for Vitesse 7385 Switch firmware */
+   reg = 0x0 0x0004;
+   label = NOR Vitesse-7385 Firmware;
+   read-only;
+   };
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 3.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0038;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@40 {
+   /* 58.75MB for JFFS2 based Root file System */
+   reg = 0x0040 0x03ac;
+   label = NOR Root File System;
+   };
+
+   partition@ec {
+   /* This location must not be altered  */
+   /* 256KB for QE ucode firmware*/
+   reg = 0x03ec 0x0004;
+   label = NOR QE microcode firmware;
+   read-only;
+   };
+
+   partition@f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image */
+   /* 512KB for u-boot Environment

[PATCH V3 1/2] powerpc/85xx: Add QE common init functions

2013-09-02 Thread Xie Xiaobo

Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.

Signed-off-by: Xie Xiaobo x@freescale.com
---
V3 - V2: Nochange

 arch/powerpc/platforms/85xx/common.c  | 47 +++
 arch/powerpc/platforms/85xx/mpc85xx.h |  8 ++
 2 files changed, 55 insertions(+)

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..fb3f5e6 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,8 @@
  */
 #include linux/of_platform.h
 
+#include asm/qe.h
+#include asm/qe_ic.h
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
@@ -80,3 +82,48 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+   if (np) {
+   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+   qe_ic_cascade_high_mpic);
+   of_node_put(np);
+   } else
+   pr_err(%s: Could not find qe-ic node\n, __func__);
+}
+
+void __init mpc85xx_qe_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe);
+   if (!np) {
+   np = of_find_node_by_name(NULL, qe);
+   if (!np) {
+   pr_err(%s: Could not find Quicc Engine node\n,
+   __func__);
+   return;
+   }
+   }
+
+   qe_reset();
+   of_node_put(np);
+
+   np = of_find_node_by_name(NULL, par_io);
+   if (np) {
+   struct device_node *ucc;
+
+   par_io_init(np);
+   of_node_put(np);
+
+   for_each_node_by_name(ucc, ucc)
+   par_io_of_config(ucc);
+
+   }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h 
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..1d39095 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_pic_init(void);
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_pic_init(void) {}
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
-- 
1.8.0


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[PATCH V2 2/2] powerpc/85xx: Add TWR-P1025 board support

2013-08-30 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
Patch V2: QE related init codes were factored out to a common file

 arch/powerpc/boot/dts/p1025twr.dtsi | 244 
 arch/powerpc/boot/dts/p1025twr_32b.dts  | 135 ++
 arch/powerpc/platforms/85xx/Kconfig |   6 +
 arch/powerpc/platforms/85xx/Makefile|   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c | 133 +
 5 files changed, 519 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi 
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..07df721
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+   aliases {
+   ethernet3 = enet3;
+   ethernet4 = enet4;
+   };
+};
+
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x400;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 256KB for Vitesse 7385 Switch firmware */
+   reg = 0x0 0x0004;
+   label = NOR Vitesse-7385 Firmware;
+   read-only;
+   };
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 3.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0038;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@40 {
+   /* 58.75MB for JFFS2 based Root file System */
+   reg = 0x0040 0x03ac;
+   label = NOR Root File System;
+   };
+
+   partition@ec {
+   /* This location must not be altered  */
+   /* 256KB for QE ucode firmware*/
+   reg = 0x03ec 0x0004;
+   label = NOR QE microcode firmware;
+   read-only;
+   };
+
+   partition@f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image */
+   /* 512KB for u-boot Environment Variables

[PATCH V2 1/2] powerpc/85xx: Add QE common init functions

2013-08-30 Thread Xie Xiaobo

Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.

Signed-off-by: Xie Xiaobo x@freescale.com
---
 arch/powerpc/platforms/85xx/common.c  | 47 +++
 arch/powerpc/platforms/85xx/mpc85xx.h |  8 ++
 2 files changed, 55 insertions(+)

diff --git a/arch/powerpc/platforms/85xx/common.c 
b/arch/powerpc/platforms/85xx/common.c
index d0861a0..fb3f5e6 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,8 @@
  */
 #include linux/of_platform.h
 
+#include asm/qe.h
+#include asm/qe_ic.h
 #include sysdev/cpm2_pic.h
 
 #include mpc85xx.h
@@ -80,3 +82,48 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
 }
 #endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+   if (np) {
+   qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+   qe_ic_cascade_high_mpic);
+   of_node_put(np);
+   } else
+   pr_err(%s: Could not find qe-ic node\n, __func__);
+}
+
+void __init mpc85xx_qe_init(void)
+{
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, fsl,qe);
+   if (!np) {
+   np = of_find_node_by_name(NULL, qe);
+   if (!np) {
+   pr_err(%s: Could not find Quicc Engine node\n,
+   __func__);
+   return;
+   }
+   }
+
+   qe_reset();
+   of_node_put(np);
+
+   np = of_find_node_by_name(NULL, par_io);
+   if (np) {
+   struct device_node *ucc;
+
+   par_io_init(np);
+   of_node_put(np);
+
+   for_each_node_by_name(ucc, ucc)
+   par_io_of_config(ucc);
+
+   }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h 
b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..1d39095 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void);
 static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #endif /* CONFIG_CPM2 */
 
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_pic_init(void);
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_pic_init(void) {}
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
 #endif
-- 
1.8.0


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[PATCH] powerpc/85xx: Add TWR-P1025 board support

2013-04-25 Thread Xie Xiaobo

TWR-P1025 Overview
 -
 512Mbyte DDR3 (on board DDR)
 64MB Nor Flash
 eTSEC1: Connected to RGMII PHY AR8035
 eTSEC3: Connected to RGMII PHY AR8035
 Two USB2.0 Type A
 One microSD Card slot
 One mini-PCIe slot
 One mini-USB TypeB dual UART

Signed-off-by: Michael Johnston michael.johns...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
 arch/powerpc/boot/dts/p1025twr.dtsi | 244 
 arch/powerpc/boot/dts/p1025twr_32b.dts  | 135 ++
 arch/powerpc/platforms/85xx/Kconfig |   6 +
 arch/powerpc/platforms/85xx/Makefile|   1 +
 arch/powerpc/platforms/85xx/twr_p102x.c | 176 +++
 5 files changed, 562 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
 create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c

diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi 
b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 000..0d550ad
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ *   names of its contributors may be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+   aliases {
+   ethernet3 = enet3;
+   ethernet4 = enet4;
+   };
+};
+
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x400;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   /* This location must not be altered  */
+   /* 256KB for Vitesse 7385 Switch firmware */
+   reg = 0x0 0x0004;
+   label = NOR Vitesse-7385 Firmware;
+   read-only;
+   };
+
+   partition@4 {
+   /* 256KB for DTB Image */
+   reg = 0x0004 0x0004;
+   label = NOR DTB Image;
+   };
+
+   partition@8 {
+   /* 3.5 MB for Linux Kernel Image */
+   reg = 0x0008 0x0038;
+   label = NOR Linux Kernel Image;
+   };
+
+   partition@40 {
+   /* 58.75MB for JFFS2 based Root file System */
+   reg = 0x0040 0x03ac;
+   label = NOR JFFS2 Root File System;
+   };
+
+   partition@ec {
+   /* This location must not be altered  */
+   /* 256KB for QE ucode firmware*/
+   reg = 0x03ec 0x0004;
+   label = NOR QE microcode firmware;
+   read-only;
+   };
+
+   partition@f0 {
+   /* This location must not be altered  */
+   /* 512KB for u-boot Bootloader Image */
+   /* 512KB for u-boot Environment Variables */
+   reg = 0x03f0 0x0010;
+   label

[PATCH 1/2] powerpc/dts: Add some DTS nodes and attributes for mpc8536ds

2012-01-17 Thread Xie Xiaobo

1. Add partitions for NOR and NAND Flash.
2. Additional attributes for sdhc.

Signed-off-by: Xie Xiaobo x@freescale.com
---
 arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi |5 ++
 arch/powerpc/boot/dts/mpc8536ds.dts   |6 ++-
 arch/powerpc/boot/dts/mpc8536ds.dtsi  |   93 +
 arch/powerpc/boot/dts/mpc8536ds_36b.dts   |8 ++-
 4 files changed, 109 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index 89af626..3ebfda3 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -236,6 +236,11 @@
};
 
 /include/ pq3-esdhc-0.dtsi
+
+   sdhc@2e000 {
+   compatible = fsl,mpc8536-esdhc, fsl,esdhc;
+   };
+
 /include/ pq3-sec3.0-0.dtsi
 /include/ pq3-mpic.dtsi
 /include/ pq3-mpic-timer-B.dtsi
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts 
b/arch/powerpc/boot/dts/mpc8536ds.dts
index c158815..1973622 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8536 DS Device Tree Source
  *
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -34,6 +34,10 @@
 
lbc: localbus@ffe05000 {
reg = 0 0xffe05000 0 0x1000;
+
+   ranges = 0x0 0x0 0x0 0xe800 0x0800
+ 0x2 0x0 0x0 0xffa0 0x0004
+ 0x3 0x0 0x0 0xffdf 0x8000;
};
 
board_soc: soc: soc@ffe0 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi 
b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index 1462e4c..cc46dbd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -32,6 +32,99 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+lbc {
+   nor@0,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = cfi-flash;
+   reg = 0x0 0x0 0x800;
+   bank-width = 2;
+   device-width = 1;
+
+   partition@0 {
+   reg = 0x0 0x0300;
+   label = ramdisk-nor;
+   };
+
+   partition@300 {
+   reg = 0x0300 0x00e0;
+   label = diagnostic-nor;
+   read-only;
+   };
+
+   partition@3e0 {
+   reg = 0x03e0 0x0020;
+   label = dink-nor;
+   read-only;
+   };
+
+   partition@400 {
+   reg = 0x0400 0x0040;
+   label = kernel-nor;
+   };
+
+   partition@440 {
+   reg = 0x0440 0x03b0;
+   label = fs-nor;
+   };
+
+   partition@7f0 {
+   reg = 0x07f0 0x0008;
+   label = dtb-nor;
+   };
+
+   partition@7f8 {
+   reg = 0x07f8 0x0008;
+   label = u-boot-nor;
+   read-only;
+   };
+   };
+
+   nand@2,0 {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = fsl,mpc8536-fcm-nand,
+fsl,elbc-fcm-nand;
+   reg = 0x2 0x0 0x4;
+
+   partition@0 {
+   reg = 0x0 0x0200;
+   label = u-boot-nand;
+   read-only;
+   };
+
+   partition@200 {
+   reg = 0x0200 0x1000;
+   label = fs-nand;
+   };
+
+   partition@1200 {
+   reg = 0x1200 0x0800;
+   label = ramdisk-nand;
+   };
+
+   partition@1a00 {
+   reg = 0x1a00 0x0400;
+   label = kernel-nand;
+   };
+
+   partition@1e00 {
+   reg = 0x1e00 0x0100;
+   label = dtb-nand;
+   };
+
+   partition@1f00 {
+   reg = 0x1f00 0x2100;
+   label = empty-nand;
+   };
+   };
+
+   board-control@3,0 {
+   compatible = fsl,mpc8536ds-fpga-pixis;
+   reg = 0x3 0x0 0x8000;
+   };
+};
+
 board_soc {
i2c@3100 {
rtc@68 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts 
b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index 8f4b929..f8a3b34

[PATCH 2/2] powerpc/dts: Add magic-packet properties for etsec

2012-01-17 Thread Xie Xiaobo

The properties indicates that the hardware supports waking up via magic packet.

Signed-off-by: Xie Xiaobo x@freescale.com
---
 arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi |3 ++-
 arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi |3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
index a1979ae..3b0650a 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@24000 {
compatible = gianfar;
reg = 0x24000 0x1000;
ranges = 0x0 0x24000 0x1000;
+   fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = 29 2 0 0 30 2 0 0 34 2 0 0;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
index 4c4fdde..96693b4 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@25000 {
compatible = gianfar;
reg = 0x25000 0x1000;
ranges = 0x0 0x25000 0x1000;
+   fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = 35 2 0 0 36 2 0 0 40 2 0 0;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
index 4b8ab43..6b3fab1 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@26000 {
compatible = gianfar;
reg = 0x26000 0x1000;
ranges = 0x0 0x26000 0x1000;
+   fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = 31 2 0 0 32 2 0 0 33 2 0 0;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
index 40c9137..0da592d 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@27000 {
compatible = gianfar;
reg = 0x27000 0x1000;
ranges = 0x0 0x27000 0x1000;
+   fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = 37 2 0 0 38 2 0 0 39 2 0 0;
 };
-- 
1.7.5.1


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[PATCH] net/ucc_geth: some fix in current kernel

2011-12-27 Thread Xie Xiaobo

* Revert commit ucc_geth: Fix hangs after switching from full to half duplex
  This commit impacted the driver in all link state change more than
  duplex change.
* Change some parameters.
  Increased the BD ring length.

Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Xie Xiaobo x@freescale.com
---
 drivers/net/ethernet/freescale/ucc_geth.c |   41 
 drivers/net/ethernet/freescale/ucc_geth.h |6 ++--
 2 files changed, 9 insertions(+), 38 deletions(-)

diff --git a/drivers/net/ethernet/freescale/ucc_geth.c 
b/drivers/net/ethernet/freescale/ucc_geth.c
index b5dc027..3e18902 100644
--- a/drivers/net/ethernet/freescale/ucc_geth.c
+++ b/drivers/net/ethernet/freescale/ucc_geth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Shlomi Gridish grid...@freescale.com
  *Li Yang le...@freescale.com
@@ -1570,28 +1570,6 @@ static int ugeth_disable(struct ucc_geth_private *ugeth, 
enum comm_dir mode)
return 0;
 }
 
-static void ugeth_quiesce(struct ucc_geth_private *ugeth)
-{
-   /* Prevent any further xmits, plus detach the device. */
-   netif_device_detach(ugeth-ndev);
-
-   /* Wait for any current xmits to finish. */
-   netif_tx_disable(ugeth-ndev);
-
-   /* Disable the interrupt to avoid NAPI rescheduling. */
-   disable_irq(ugeth-ug_info-uf_info.irq);
-
-   /* Stop NAPI, and possibly wait for its completion. */
-   napi_disable(ugeth-napi);
-}
-
-static void ugeth_activate(struct ucc_geth_private *ugeth)
-{
-   napi_enable(ugeth-napi);
-   enable_irq(ugeth-ug_info-uf_info.irq);
-   netif_device_attach(ugeth-ndev);
-}
-
 /* Called every time the controller might need to be made
  * aware of new link state.  The PHY code conveys this
  * information through variables in the ugeth structure, and this
@@ -1605,11 +1583,14 @@ static void adjust_link(struct net_device *dev)
struct ucc_geth __iomem *ug_regs;
struct ucc_fast __iomem *uf_regs;
struct phy_device *phydev = ugeth-phydev;
+   unsigned long flags;
int new_state = 0;
 
ug_regs = ugeth-ug_regs;
uf_regs = ugeth-uccf-uf_regs;
 
+   spin_lock_irqsave(ugeth-lock, flags);
+
if (phydev-link) {
u32 tempval = in_be32(ug_regs-maccfg2);
u32 upsmr = in_be32(uf_regs-upsmr);
@@ -1666,21 +1647,9 @@ static void adjust_link(struct net_device *dev)
}
 
if (new_state) {
-   /*
-* To change the MAC configuration we need to disable
-* the controller. To do so, we have to either grab
-* ugeth-lock, which is a bad idea since 'graceful
-* stop' commands might take quite a while, or we can
-* quiesce driver's activity.
-*/
-   ugeth_quiesce(ugeth);
-   ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
-
out_be32(ug_regs-maccfg2, tempval);
out_be32(uf_regs-upsmr, upsmr);
 
-   ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
-   ugeth_activate(ugeth);
}
} else if (ugeth-oldlink) {
new_state = 1;
@@ -1691,6 +1660,8 @@ static void adjust_link(struct net_device *dev)
 
if (new_state  netif_msg_link(ugeth))
phy_print_status(phydev);
+
+   spin_unlock_irqrestore(ugeth-lock, flags);
 }
 
 /* Initialize TBI PHY interface for communicating with the
diff --git a/drivers/net/ethernet/freescale/ucc_geth.h 
b/drivers/net/ethernet/freescale/ucc_geth.h
index d12fcad..b0b42b4 100644
--- a/drivers/net/ethernet/freescale/ucc_geth.h
+++ b/drivers/net/ethernet/freescale/ucc_geth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Shlomi Gridish grid...@freescale.com
  *
@@ -875,8 +875,8 @@ struct ucc_geth_hardware_statistics {
 #define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
 
 /* Driver definitions */
-#define TX_BD_RING_LEN  0x10
-#define RX_BD_RING_LEN  0x10
+#define TX_BD_RING_LEN  64
+#define RX_BD_RING_LEN  64
 
 #define TX_RING_MOD_MASK(size)  (size-1)
 #define RX_RING_MOD_MASK(size)  (size-1)
-- 
1.7.5.1


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RE: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk

2011-12-13 Thread Xie Xiaobo-R63061

Hi Changming,

OK, you can merge my patch into your patches.

Hi all,
Please ignore this patch. Changming will send the similar patch.

BRs
Xie Xiaobo

-Original Message-
From: Huang Changming-R66093 
Sent: 2011年12月13日 16:00
To: Xie Xiaobo-R63061; linuxppc-dev@lists.ozlabs.org
Cc: avoront...@ru.mvista.com; linux-...@vger.kernel.org; Xie Xiaobo-R63061
Subject: RE: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk

Xiaobo, I have one other similar patch, but the property is 
'sdhci,adjust-timeout'.
Maybe I can repost it with add your signed-off-by?

 -Original Message-
 From: linuxppc-dev-bounces+r66093=freescale@lists.ozlabs.org
 [mailto:linuxppc-dev-bounces+r66093=freescale@lists.ozlabs.org] On 
 Behalf Of Xie Xiaobo
 Sent: Monday, December 05, 2011 4:55 PM
 To: linuxppc-dev@lists.ozlabs.org
 Cc: avoront...@ru.mvista.com; linux-...@vger.kernel.org; Xie Xiaobo-
 R63061
 Subject: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk
 
 Some controller provides an incorrect timeout value for transfers, So 
 it need the quirk to adjust timeout value to 0xE.
 E.g. eSDHC of MPC8536, P1010, and P2020.
 
 Signed-off-by: Xie Xiaobo x@freescale.com
 ---
  drivers/mmc/host/sdhci-pltfm.c |5 -
  1 files changed, 4 insertions(+), 1 deletions(-)
 
 diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci- 
 pltfm.c index a9e12ea..b5d6b3f 100644
 --- a/drivers/mmc/host/sdhci-pltfm.c
 +++ b/drivers/mmc/host/sdhci-pltfm.c
 @@ -2,7 +2,7 @@
   * sdhci-pltfm.c Support for SDHCI platform devices
   * Copyright (c) 2009 Intel Corporation
   *
 - * Copyright (c) 2007 Freescale Semiconductor, Inc.
 + * Copyright (c) 2007, 2011 Freescale Semiconductor, Inc.
   * Copyright (c) 2009 MontaVista Software, Inc.
   *
   * Authors: Xiaobo Xie x@freescale.com @@ -68,6 +68,9 @@ void 
 sdhci_get_of_property(struct platform_device *pdev)
   if (of_get_property(np, sdhci,1-bit-only, NULL))
   host-quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
 
 + if (of_get_property(np, sdhci,sdhci-adjust-timeout, NULL))
 + host-quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 +
   if (sdhci_of_wp_inverted(np))
   host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
 
 --
 1.6.4
 
 
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[PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk

2011-12-05 Thread Xie Xiaobo

Some controller provides an incorrect timeout value for transfers,
So it need the quirk to adjust timeout value to 0xE.
E.g. eSDHC of MPC8536, P1010, and P2020.

Signed-off-by: Xie Xiaobo x@freescale.com
---
 drivers/mmc/host/sdhci-pltfm.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index a9e12ea..b5d6b3f 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -2,7 +2,7 @@
  * sdhci-pltfm.c Support for SDHCI platform devices
  * Copyright (c) 2009 Intel Corporation
  *
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2011 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  *
  * Authors: Xiaobo Xie x@freescale.com
@@ -68,6 +68,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
if (of_get_property(np, sdhci,1-bit-only, NULL))
host-quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
 
+   if (of_get_property(np, sdhci,sdhci-adjust-timeout, NULL))
+   host-quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+
if (sdhci_of_wp_inverted(np))
host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
 
-- 
1.6.4


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[PATCH] powerpc/qe: Setup clock source for TDM

[PATCH V6 1/2] powerpc/85xx: Add QE common init function

[PATCH V6 2/2] powerpc/85xx: Add TWR-P1025 board support

RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

[PATCH V5 1/2] powerpc/85xx: Add QE common init function

[PATCH V5 2/2] powerpc/85xx: Add TWR-P1025 board support

RE: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

RE: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions

[PATCH V4 2/3] powerpc/85xx: Use common init functions for QE

[PATCH V4 1/3] powerpc/85xx: Add QE common init functions

[PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support

RE: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

RE: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

RE: [PATCH V3 1/2] powerpc/85xx: Add QE common init functions

RE: [PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

[PATCH V3 2/2] powerpc/85xx: Add TWR-P1025 board support

[PATCH V3 1/2] powerpc/85xx: Add QE common init functions

[PATCH V2 2/2] powerpc/85xx: Add TWR-P1025 board support

[PATCH V2 1/2] powerpc/85xx: Add QE common init functions

[PATCH] powerpc/85xx: Add TWR-P1025 board support

[PATCH 1/2] powerpc/dts: Add some DTS nodes and attributes for mpc8536ds

[PATCH 2/2] powerpc/dts: Add magic-packet properties for etsec

[PATCH] net/ucc_geth: some fix in current kernel

RE: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk

[PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk

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