[PATCH v2] powerpc/dts: Fix the dts for p1025rdb 36bit
fix the following errors:
Error: arch/powerpc/boot/dts/p1025rdb.dtsi:326.2-3 label or path, 'qe',
not found
Error: arch/powerpc/boot/dts/fsl/p1021si-post.dtsi:242.2-3 label or
path, 'qe', not found
FATAL ERROR: Syntax error parsing input tree
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1025rdb_36b.dts |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts
b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 4ce4bfa..06deb6f 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -82,6 +82,11 @@
0x0 0x10;
};
};
+
+ qe: qe@fffe8 {
+ status = disabled; /* no firmware loaded */
+ };
+
};
/include/ p1025rdb.dtsi
--
1.7.0.4
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Re: [PATCH] powerpc/dts: Add qe support for 36bit
On 03/22/2013 02:42 AM, Timur Tabi wrote:
On Thu, Mar 21, 2013 at 4:26 AM, Zhicheng Fan b32...@freescale.com wrote:
+ qe: qe@fffe8 {
+ ranges = 0x0 0xf 0xffe8 0x4;
Are you sure this works? The QE can't handle 36-bit addresses, and I
think the MURAM is located inside the QE address space.
Hi Timur,
you are right ,the QE can not support the 36-bit , I test it on
the p1025 ,the qe can not work
but we need the qe node , becase the dts include the
fsl/p1021si-post.dtsi
that needed, I will send other patch
--
Regards Thanks
Zhicheng Fan
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[PATCH] powerpc/dts: Fix the dts for p1025rdb 36bit
fix the following errors:
Error: arch/powerpc/boot/dts/p1025rdb.dtsi:326.2-3 label or path, 'qe',
not found
Error: arch/powerpc/boot/dts/fsl/p1021si-post.dtsi:242.2-3 label or
path, 'qe', not found
FATAL ERROR: Syntax error parsing input tree
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1025rdb_36b.dts |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts
b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 4ce4bfa..18f52be 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -82,6 +82,15 @@
0x0 0x10;
};
};
+
+ qe: qe@fffe8 {
+ ranges = 0x0 0xf 0xffe8 0x4;
+ reg = 0xf 0xffe8 0 0x480;
+ brg-frequency = 0;
+ bus-frequency = 0;
+ status = disabled; /* no firmware loaded */
+ };
+
};
/include/ p1025rdb.dtsi
--
1.7.0.4
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[PATCH] powerpc/dts: Add qe support for 36bit
fixed the following errors:
Error: arch/powerpc/boot/dts/p1025rdb.dtsi:326.2-3 label or path, 'qe',
not found
Error: arch/powerpc/boot/dts/fsl/p1021si-post.dtsi:242.2-3 label or
path, 'qe', not found
FATAL ERROR: Syntax error parsing input tree
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1025rdb_36b.dts | 48
1 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts
b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 4ce4bfa..c74c39b 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -82,6 +82,54 @@
0x0 0x10;
};
};
+
+ qe: qe@fffe8 {
+ ranges = 0x0 0xf 0xffe8 0x4;
+ reg = 0xf 0xffe8 0 0x480;
+ brg-frequency = 0;
+ bus-frequency = 0;
+ status = disabled; /* no firmware loaded */
+
+ enet3: ucc@2000 {
+ device_type = network;
+ compatible = ucc_geth;
+ rx-clock-name = clk12;
+ tx-clock-name = clk9;
+ pio-handle = pio1;
+ phy-handle = qe_phy0;
+ phy-connection-type = mii;
+ };
+
+ mdio@2120 {
+ qe_phy0: ethernet-phy@0 {
+ interrupt-parent = mpic;
+ interrupts = 4 1 0 0;
+ reg = 0x6;
+ device_type = ethernet-phy;
+ };
+ qe_phy1: ethernet-phy@03 {
+ interrupt-parent = mpic;
+ interrupts = 5 1 0 0;
+ reg = 0x3;
+ device_type = ethernet-phy;
+ };
+ tbi-phy@11 {
+ reg = 0x11;
+ device_type = tbi-phy;
+ };
+ };
+
+ enet4: ucc@2400 {
+ device_type = network;
+ compatible = ucc_geth;
+ rx-clock-name = none;
+ tx-clock-name = clk13;
+ pio-handle = pio2;
+ phy-handle = qe_phy1;
+ phy-connection-type = rmii;
+ };
+ };
+
};
/include/ p1025rdb.dtsi
--
1.7.0.4
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[PATCH 1/2 v6] powerpc/85xx: Add Quicc Engine support for p1025rdb
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e95aef7..ca3c8e4 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,62 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n, __func__);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ if (machine_is(p1025_rdb)) {
+
+ struct ccsr_guts_85xx __iomem *guts;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+ guts = of_iomap(np, 0);
+ if (!guts) {
+
+ pr_err(mpc85xx-rdb: could not map global
utilities register\n);
+
+ } else {
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ MPC85xx_PMUXCR_QE(3) |
+ MPC85xx_PMUXCR_QE(9) |
+ MPC85xx_PMUXCR_QE(12));
+ iounmap(guts);
+ }
+ of_node_put(np);
+ }
+
+ }
+#endif
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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[PATCH 2/2 v6] powerpc/85xx: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe,
so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h |6 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 35
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..ce04530 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -4,7 +4,7 @@
* Authors: Jeff Brown
* Timur Tabi ti...@freescale.com
*
- * Copyright 2004,2007 Freescale Semiconductor, Inc
+ * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -114,6 +114,10 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE(x) (0x8000 (x))
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..71a316d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
+ * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
+ * All rights reserved.
*
* Author: Andy Fleming aflem...@freescale.com
*
@@ -51,6 +52,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,34 +270,27 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
- static __be32 __iomem *pmuxcr;
- np = of_find_node_by_name(NULL, global-utilities);
+ struct ccsr_guts_85xx __iomem *guts;
+ np = of_find_node_by_name(NULL, global-utilities);
if (np) {
- pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
-
- if (!pmuxcr)
- printk(KERN_EMERG Error: Alternate function
-signal multiplex control register not
-mapped!\n);
- else
+ guts = of_iomap(np, 0);
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global
utilities register\n);
+ else{
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
- MPC85xx_PMUXCR_QE3 |
- MPC85xx_PMUXCR_QE9 |
- MPC85xx_PMUXCR_QE12);
-
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ MPC85xx_PMUXCR_QE(3) |
+ MPC85xx_PMUXCR_QE(9) |
+ MPC85xx_PMUXCR_QE(12));
+ iounmap(guts);
+ }
of_node_put(np);
}
--
1.7.0.4
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[PATCH 1/2 v4] powerpc/85xx: Add p1025rdb platform support
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index d54772e..e95aef7 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -91,6 +91,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -120,6 +121,13 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1025_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P1025RDB);
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -161,3 +169,17 @@ define_machine(p1020_rdb_pc) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1025_rdb) {
+ .name = P1025 RDB,
+ .probe = p1025_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 2/2 v4] powerpc/dts: Add dts for p1025rdb board
From: Zhicheng Fan b32...@freescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1025rdb.dtsi| 286
arch/powerpc/boot/dts/p1025rdb_32b.dts | 135 +++
arch/powerpc/boot/dts/p1025rdb_36b.dts | 88 ++
3 files changed, 509 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1025rdb_36b.dts
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi
b/arch/powerpc/boot/dts/p1025rdb.dtsi
new file mode 100644
index 000..cf3676f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -0,0 +1,286 @@
+/*
+ * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR U-Boot Image;
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1
[PATCH 1/2 v4] powerpc/85xx: Add Quicc Engine support for p1025rdb
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 78 -
1 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e95aef7..52d5745 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,63 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n, __func__);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ if (machine_is(p1025_rdb)) {
+
+ struct ccsr_guts_85xx __iomem *guts;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+
+ guts = of_iomap(np, 0);
+ if (!guts) {
+
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+
+ } else {
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ iounmap(guts);
+ }
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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[PATCH 2/2 v4] powerpc/85xx: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe,
so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 18 ++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 24 ++--
2 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..8c78ee2 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,24 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..73e4801 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,34 +269,29 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
- static __be32 __iomem *pmuxcr;
+
+ struct ccsr_guts_85xx __iomem *guts;
np = of_find_node_by_name(NULL, global-utilities);
if (np) {
- pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+ guts = of_iomap(np, 0);
- if (!pmuxcr)
- printk(KERN_EMERG Error: Alternate function
-signal multiplex control register not
-mapped!\n);
- else
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+ else{
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
MPC85xx_PMUXCR_QE3 |
MPC85xx_PMUXCR_QE9 |
MPC85xx_PMUXCR_QE12);
-
+ iounmap(guts);
+ }
of_node_put(np);
}
--
1.7.0.4
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ignore [PATCH 1/2 v4] powerpc/85xx: Add Quicc Engine support for p1025rdb
hi all, ignore v4 patche for qe -- Zhicheng Fan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2 v5] powerpc/85xx: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe,
so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 18 ++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 24 ++--
2 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..8c78ee2 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,24 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..73e4801 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,34 +269,29 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
- static __be32 __iomem *pmuxcr;
+
+ struct ccsr_guts_85xx __iomem *guts;
np = of_find_node_by_name(NULL, global-utilities);
if (np) {
- pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+ guts = of_iomap(np, 0);
- if (!pmuxcr)
- printk(KERN_EMERG Error: Alternate function
-signal multiplex control register not
-mapped!\n);
- else
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+ else{
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
MPC85xx_PMUXCR_QE3 |
MPC85xx_PMUXCR_QE9 |
MPC85xx_PMUXCR_QE12);
-
+ iounmap(guts);
+ }
of_node_put(np);
}
--
1.7.0.4
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[PATCH 1/2 v5] powerpc/85xx: Add Quicc Engine support for p1025rdb
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 78 -
1 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e95aef7..b85180e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,63 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n, __func__);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ if (machine_is(p1025_rdb)) {
+
+ struct ccsr_guts_85xx __iomem *guts;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+
+ guts = of_iomap(np, 0);
+ if (!guts) {
+
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+
+ } else {
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+ iounmap(guts);
+ }
+ of_node_put(np);
+ }
+
+ }
+#endif
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
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[PATCH 2/2 v5] powerpc/85xx: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe,
so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 20 +++-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 27 ---
2 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..dcd5b70 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -4,7 +4,7 @@
* Authors: Jeff Brown
* Timur Tabi ti...@freescale.com
*
- * Copyright 2004,2007 Freescale Semiconductor, Inc
+ * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -114,6 +114,24 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..d55f869 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
+ * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
+ * All rights reserved.
*
* Author: Andy Fleming aflem...@freescale.com
*
@@ -51,6 +52,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,34 +270,29 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
- static __be32 __iomem *pmuxcr;
+
+ struct ccsr_guts_85xx __iomem *guts;
np = of_find_node_by_name(NULL, global-utilities);
if (np) {
- pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+ guts = of_iomap(np, 0);
- if (!pmuxcr)
- printk(KERN_EMERG Error: Alternate function
-signal multiplex control register not
-mapped!\n);
- else
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+ else{
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
MPC85xx_PMUXCR_QE3 |
MPC85xx_PMUXCR_QE9 |
MPC85xx_PMUXCR_QE12);
-
+ iounmap(guts);
+ }
of_node_put(np);
}
--
1.7.0.4
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[PATCH 1/2 v5] powerpc/85xx: Add Quicc Engine support for p1025rdb
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 78 -
1 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e95aef7..b85180e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,63 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n, __func__);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ if (machine_is(p1025_rdb)) {
+
+ struct ccsr_guts_85xx __iomem *guts;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+
+ guts = of_iomap(np, 0);
+ if (!guts) {
+
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+
+ } else {
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+ iounmap(guts);
+ }
+ of_node_put(np);
+ }
+
+ }
+#endif
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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[PATCH 2/2 v3] powerpc/85xx: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe
,so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 18 ++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 21 -
2 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..8c78ee2 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,24 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..dc5421c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,22 +269,16 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
- static __be32 __iomem *pmuxcr;
+
+ struct ccsr_guts_85xx __iomem *guts;
np = of_find_node_by_name(NULL, global-utilities);
if (np) {
- pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+ guts = of_iomap(np, 0);
- if (!pmuxcr)
- printk(KERN_EMERG Error: Alternate function
-signal multiplex control register not
-mapped!\n);
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
else
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
@@ -291,11 +286,11 @@ static void __init mpc85xx_mds_qe_init(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
MPC85xx_PMUXCR_QE3 |
MPC85xx_PMUXCR_QE9 |
MPC85xx_PMUXCR_QE12);
-
+ iounmap(guts);
of_node_put(np);
}
--
1.7.0.4
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[PATCH 1/2 v3] powerpc/85xx: Add Quicc Engine support for p1025rdb
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 78 -
1 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e95aef7..c9dfdcc 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(%s: Could not find qe-ic node\n, __func__);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,63 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(%s: Could not find Quicc Engine node\n, __func__);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+ if (machine_is(p1025_rdb)) {
+
+ struct ccsr_guts_85xx __iomem *guts;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+
+ guts = of_iomap(np, 0);
+ if (!guts) {
+
+ pr_err(mpc85xx-rdb: could not map global
utilties register!\n);
+
+ } else {
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(guts-pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ }
+ iounmap(guts);
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
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[PATCH 1/2 v3] powerpc/85xx: Add p1025rdb platform support
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index d54772e..e95aef7 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -91,6 +91,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -120,6 +121,13 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1025_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P1025RDB);
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -161,3 +169,17 @@ define_machine(p1020_rdb_pc) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1025_rdb) {
+ .name = P1025 RDB,
+ .probe = p1025_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
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[PATCH 2/2 v3] powerpc/dts: Add dts for p1025rdb board
From: Zhicheng Fan b32...@freescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1025rdb.dtsi| 286
arch/powerpc/boot/dts/p1025rdb_32b.dts | 137 +++
arch/powerpc/boot/dts/p1025rdb_36b.dts | 88 ++
3 files changed, 511 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1025rdb_36b.dts
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi
b/arch/powerpc/boot/dts/p1025rdb.dtsi
new file mode 100644
index 000..cf3676f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -0,0 +1,286 @@
+/*
+ * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x00f0 0x0010;
+ label = NOR U-Boot Image;
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1
[PATCH 1/2 v5] powerpc/85xx: Add p1020rdb-pc platform support
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e..d54772e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -90,10 +90,18 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P1020RDB-PC);
+}
+
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -139,3 +147,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
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[PATCH 2/2 v5] powerpc/dts: Add dts for p1020rdb-pc board
From: Zhicheng Fan b32...@freescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++
arch/powerpc/boot/dts/p1020rdb-pc_32b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 64 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 142 +
5 files changed, 633 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000..c952cd3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,247 @@
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = 0x0 0x0004;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@4 {
+ /* 256KB for DTB Image */
+ reg = 0x0004 0x0004;
+ label = NOR DTB Image;
+ };
+
+ partition@8 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = 0x0008 0x0038;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = 0x0040 0x00b0;
+ label = NOR JFFS2 Root File System;
+ };
+
+ partition@f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image
[PATCH 2/2 v2] powerpc: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan b32...@freeescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe
,so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 19 +++
arch/powerpc/platforms/85xx/mpc85xx_mds.c |7 ++-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..efacfe3 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,25 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_OFFSET 0x60
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..1bd339a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,11 +269,7 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
+
static __be32 __iomem *pmuxcr;
np = of_find_node_by_name(NULL, global-utilities);
--
1.7.0.4
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[PATCH 1/2 v2] P1025RDB: Add Quicc Engine support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 80 -
1 files changed, 79 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1950076..4c27b3b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err(Could not find qe-ic node\n);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,65 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ pr_err(Could not find Quicc Engine node\n);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+ if (machine_is(p1025_rdb)) {
+
+ __be32 __iomem *pmuxcr;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+
+ if (np) {
+ pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+
+ if (!pmuxcr)
+ pr_err(KERN_EMERG Error: Alternate function
+signal multiplex control register not
+mapped!\n);
+ else {
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ }
+
+ iounmap(pmuxcr);
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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[PATCH 1/2 v4] powerpc/85xx: Add p1020rdb-pc platform support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index dce8aaf..a0b9c92 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -168,10 +168,20 @@ qe_fail:
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
+
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -217,3 +227,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 2/2 v4] powerpc/dts: Add dts for p1020rdb-pc board
From: Zhicheng Fan b32...@freeescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 64 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 142 +
5 files changed, 633 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dts
b/arch/powerpc/boot/dts/p1020rdb-pc.dts
new file mode 100644
index 000..5c333b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PC;
+ compatible = fsl,P1020RDB-PC;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0 0xffe05000 0 0x1000;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002
+ 0x3 0x0 0x0 0xffa0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+ reg = 0 0xffe09000 0 0x1000;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0 0xffe0a000 0 0x1000;
+ ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
[PATCH 1/2 v2] powerpc/dts: Add dts for p1025rdb board
From: Zhicheng Fan b32...@freeescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/boot/dts/fsl/p1025si-post.dtsi | 228 +
arch/powerpc/boot/dts/fsl/p1025si-pre.dtsi | 70 +++
arch/powerpc/boot/dts/p1025rdb.dts | 137 +
arch/powerpc/boot/dts/p1025rdb.dtsi | 286 +++
arch/powerpc/boot/dts/p1025rdb_36b.dts | 88
5 files changed, 809 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p1025si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dts
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb_36b.dts
diff --git a/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
new file mode 100644
index 000..e0e3e4d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
@@ -0,0 +1,228 @@
+/*
+ * P1025 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1025-elbc, fsl,elbc, simple-bus;
+ interrupts = 19 2 0 0;
+};
+
+/* controller at 0x9000 */
+pci0 {
+ compatible = fsl,mpc8548-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 255;
+ clock-frequency = ;
+ interrupts = 16 2 0 0;
+
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 16 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x1 mpic 0x4 0x1 0x0 0x0
+ 0x0 0x0 0x2 mpic 0x5 0x1 0x0 0x0
+ 0x0 0x0 0x3 mpic 0x6 0x1 0x0 0x0
+ 0x0 0x0 0x4 mpic 0x7 0x1 0x0 0x0
+ ;
+ };
+};
+
+/* controller at 0xa000 */
+pci1 {
+ compatible = fsl,mpc8548-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 255;
+ clock-frequency = ;
+ interrupts = 16 2 0 0;
+
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address
[PATCH 2/2 v2] P1025RDB: Add p1025rdb platform support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 0d3d7c6..3381a80 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -91,6 +91,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -122,6 +123,15 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1025_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1025RDB))
+ return 1;
+ return 0;
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -163,3 +173,17 @@ define_machine(p1020_rdb_pc) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1025_rdb) {
+ .name = P1025 RDB,
+ .probe = p1025_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 1/2 v3] powerpc/85xx: Add p1020rdb-pc platform support
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 27 ++-
1 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index f5ff911..0b04bef 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -121,8 +121,10 @@ static int __init mpc85xxrdb_publish_devices(void)
{
return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
}
+
machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -145,6 +147,15 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -172,3 +183,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.6.4
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[PATCH 2/2 v3] powerpc/dts: Add dts for p1020rdb-pc board
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 247 ++
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 64 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 142 +
5 files changed, 633 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dts
b/arch/powerpc/boot/dts/p1020rdb-pc.dts
new file mode 100644
index 000..5c333b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PC;
+ compatible = fsl,P1020RDB-PC;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0 0xffe05000 0 0x1000;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002
+ 0x3 0x0 0x0 0xffa0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+ reg = 0 0xffe09000 0 0x1000;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0 0xffe0a000 0 0x1000;
+ ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
+ 0x100 0x0 0x 0
[PATCH 1/2 v2] powerpc/dts: Add dts for p1020rdb-pc
From: Zhicheng Fan b32...@freeescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 255 ++
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 90
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 63 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 141
5 files changed, 639 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dts
b/arch/powerpc/boot/dts/p1020rdb-pc.dts
new file mode 100644
index 000..5c333b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PC;
+ compatible = fsl,P1020RDB-PC;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0 0xffe05000 0 0x1000;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002
+ 0x3 0x0 0x0 0xffa0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+ reg = 0 0xffe09000 0 0x1000;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0 0xffe0a000 0 0x1000;
+ ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
[PATCH 2/2 v2] P1020RDB-PC: Add p1020rdb-pc platform support
From: Zhicheng Fan b32...@freeescale.com
Signed-off-by: Zhicheng Fan b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e..0d3d7c6 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -90,10 +90,20 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
+
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -139,3 +149,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 1/2] powerpc/dts: Add dts for p1020rdb-pc
From: Fanzc b32...@freeescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/boot/dts/p1020rdb-pc.dts| 67 ++
arch/powerpc/boot/dts/p1020rdb-pc.dtsi | 251 ++
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts| 67 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts | 63 ++
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts | 141
5 files changed, 589 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dts
b/arch/powerpc/boot/dts/p1020rdb-pc.dts
new file mode 100644
index 000..e283b94
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dts
@@ -0,0 +1,67 @@
+/*
+ * P1020 RDB-PC Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PC;
+ compatible = fsl,P1020RDB-PC;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0 0xffe05000 0 0x1000;
+
+ /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+ ranges = 0x0 0x0 0x0 0xef00 0x0100
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffb0 0x0002
+ 0x3 0x0 0x0 0xffa0 0x0002;
+ };
+
+ soc: soc@ffe0 {
+ ranges = 0x0 0x0 0xffe0 0x10;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = 0x200 0x0 0xa000 0 0xa000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc1 0x0 0x1;
+ reg = 0 0xffe09000 0 0x1000;
+ pcie@0 {
+ ranges = 0x200 0x0 0xa000
+ 0x200 0x0 0xa000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = 0 0xffe0a000 0 0x1000;
+ ranges = 0x200 0x0 0x8000 0 0x8000 0x0 0x2000
+ 0x100 0x0 0x 0 0xffc0 0x0 0x1;
+ pcie@0 {
+ ranges = 0x200 0x0 0x8000
+ 0x200 0x0 0x8000
+ 0x0 0x2000
+
+ 0x100 0x0 0x0
+ 0x100 0x0 0x0
+ 0x0 0x10;
+ };
+ };
+};
+
+/include/ p1020rdb-pc.dtsi
+/include/ fsl/p1020si-post.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000..1c4003f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,251 @@
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+
[PATCH 2/2] P1020RDB-PC: Add p1020rdb-pc platform support
From: Fanzc b32...@freeescale.com
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 27 ++-
1 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e..0583d38 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
/*
* MPC85xx RDB Board Setup
*
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -90,6 +90,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -112,6 +113,15 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1020_rdb_pc_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1020RDB-PC))
+ return 1;
+ return 0;
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -139,3 +149,18 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb_pc) {
+ .name = P1020RDB-PC,
+ .probe = p1020_rdb_pc_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
--
1.7.0.4
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[PATCH 2/2] powerpc: Abstract common define of signal multiplex control for qe
From: Fanzc b32...@freeescale.com
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe
,so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 19 +++
arch/powerpc/platforms/85xx/mpc85xx_mds.c |7 ++-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..efacfe3 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,25 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_OFFSET 0x60
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE10 0x0020
+#define MPC85xx_PMUXCR_QE11 0x0010
+#define MPC85xx_PMUXCR_QE12 0x0008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI0 /* DMA controller/channel set
to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..1bd339a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include asm/qe_ic.h
#include asm/mpic.h
#include asm/swiotlb.h
+#include asm/fsl_guts.h
#include smp.h
#include mpc85xx.h
@@ -268,11 +269,7 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x8000
-#define MPC85xx_PMUXCR_QE3 0x1000
-#define MPC85xx_PMUXCR_QE9 0x0040
-#define MPC85xx_PMUXCR_QE12 0x0008
+
static __be32 __iomem *pmuxcr;
np = of_find_node_by_name(NULL, global-utilities);
--
1.7.0.4
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[PATCH 1/2] P1025RDB: add Quicc Engine support
From: Fanzc b32...@freeescale.com
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 79 -
1 files changed, 78 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1950076..1ba67aa 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include asm/prom.h
#include asm/udbg.h
#include asm/mpic.h
+#include asm/qe.h
+#include asm/qe_ic.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, fsl,MPC85XXRDB-CAMP)) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe-ic);
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ printk(KERN_ERR Could not find qe-ic node\n);
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,64 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, fsl,qe);
+ if (!np) {
+ printk(KERN_ERR Could not find Quicc Engine node\n);
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, par_io);
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, ucc)
+ par_io_of_config(ucc);
+
+ }
+ if (machine_is(p1025_rdb)) {
+
+ __be32 __iomem *pmuxcr;
+
+ np = of_find_node_by_name(NULL, global-utilities);
+
+ if (np) {
+ pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+
+ if (!pmuxcr)
+ pr_err(KERN_EMERG Error: Alternate function
+signal multiplex control register not
+mapped!\n);
+ else {
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ }
+
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO MPC85xx RDB board from Freescale Semiconductor\n);
}
--
1.7.0.4
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[PATCH 1/2] P1025RDB: Add p1025rdb platform support
From: Fanzc b32...@freeescale.com
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e..1950076 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -90,6 +90,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -112,6 +113,15 @@ static int __init p1020_rdb_probe(void)
return 0;
}
+static int __init p1025_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, fsl,P1025RDB))
+ return 1;
+ return 0;
+}
+
define_machine(p2020_rdb) {
.name = P2020 RDB,
.probe = p2020_rdb_probe,
@@ -139,3 +149,17 @@ define_machine(p1020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1025_rdb) {
+ .name = P1025 RDB,
+ .probe = p1025_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq= mpic_get_irq,
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.7.0.4
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[PATCH 2/2] powerpc/dts: Add dts for p1025rdb board
From: Fanzc b32...@freeescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021
- eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221
- eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021
USB 2.0 port:
- Two USB2.0 Type A receptacles
- One USB2.0 signal to Mini PCIe slot
Dual RJ45 UART ports:
- DUART interface: supports two UARTs up to 115200 bps for console display
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/boot/dts/fsl/p1025si-post.dtsi | 228 +
arch/powerpc/boot/dts/fsl/p1025si-pre.dtsi | 70 +++
arch/powerpc/boot/dts/p1025rdb.dts | 113 +++
arch/powerpc/boot/dts/p1025rdb.dtsi | 286 +++
arch/powerpc/boot/dts/p1025rdb_36b.dts | 65 ++
5 files changed, 762 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p1025si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dts
create mode 100644 arch/powerpc/boot/dts/p1025rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025rdb_36b.dts
diff --git a/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
new file mode 100644
index 000..e0e3e4d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1025si-post.dtsi
@@ -0,0 +1,228 @@
+/*
+ * P1025 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,p1025-elbc, fsl,elbc, simple-bus;
+ interrupts = 19 2 0 0;
+};
+
+/* controller at 0x9000 */
+pci0 {
+ compatible = fsl,mpc8548-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 255;
+ clock-frequency = ;
+ interrupts = 16 2 0 0;
+
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ device_type = pci;
+ interrupts = 16 2 0 0;
+ interrupt-map-mask = 0xf800 0 0 7;
+ interrupt-map =
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x1 mpic 0x4 0x1 0x0 0x0
+ 0x0 0x0 0x2 mpic 0x5 0x1 0x0 0x0
+ 0x0 0x0 0x3 mpic 0x6 0x1 0x0 0x0
+ 0x0 0x0 0x4 mpic 0x7 0x1 0x0 0x0
+ ;
+ };
+};
+
+/* controller at 0xa000 */
+pci1 {
+ compatible = fsl,mpc8548-pcie;
+ device_type = pci;
+ #size-cells = 2;
+ #address-cells = 3;
+ bus-range = 0 255;
+ clock-frequency = ;
+ interrupts = 16 2 0 0;
+
+ pcie@0 {
+ reg = 0 0 0 0 0;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+
[SDK v1.2][PATCH] powerpc/dts: update dts for p1020rdb
nand: Sync base address with U-boot
sdhc: Add suppot auto cmd12
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi |3 +++
arch/powerpc/boot/dts/p1020rdb.dts |2 +-
arch/powerpc/boot/dts/p1020rdb_36b.dts |2 +-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index fc924c5..8e56ad2 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -145,6 +145,9 @@
/include/ pq3-usb2-dr-1.dtsi
/include/ pq3-esdhc-0.dtsi
+ sdhc@2e000 {
+ sdhci,auto-cmd12;
+ };
/include/ pq3-sec3.3-0.dtsi
/include/ pq3-mpic.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
index 518bf99..19b8c77 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -23,7 +23,7 @@
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0x0 0xef00 0x0100
- 0x1 0x0 0x0 0xffa0 0x0004
+ 0x1 0x0 0x0 0xff80 0x0004
0x2 0x0 0x0 0xffb0 0x0002;
};
diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts
b/arch/powerpc/boot/dts/p1020rdb_36b.dts
index bdbdb60..7c53ad7 100644
--- a/arch/powerpc/boot/dts/p1020rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_36b.dts
@@ -23,7 +23,7 @@
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0xf 0xef00 0x0100
- 0x1 0x0 0xf 0xffa0 0x0004
+ 0x1 0x0 0xf 0xff80 0x0004
0x2 0x0 0xf 0xffb0 0x0002;
};
--
1.6.4
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[PATCH] powerpc/dts: update dts for p1020rdb
nand: Sync base address with U-boot
sdhc: Add suppot auto cmd12
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi |3 +++
arch/powerpc/boot/dts/p1020rdb.dts |2 +-
arch/powerpc/boot/dts/p1020rdb_36b.dts |2 +-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index fc924c5..8e56ad2 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -145,6 +145,9 @@
/include/ pq3-usb2-dr-1.dtsi
/include/ pq3-esdhc-0.dtsi
+ sdhc@2e000 {
+ sdhci,auto-cmd12;
+ };
/include/ pq3-sec3.3-0.dtsi
/include/ pq3-mpic.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts
b/arch/powerpc/boot/dts/p1020rdb.dts
index 518bf99..19b8c77 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -23,7 +23,7 @@
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0x0 0xef00 0x0100
- 0x1 0x0 0x0 0xffa0 0x0004
+ 0x1 0x0 0x0 0xff80 0x0004
0x2 0x0 0x0 0xffb0 0x0002;
};
diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts
b/arch/powerpc/boot/dts/p1020rdb_36b.dts
index bdbdb60..7c53ad7 100644
--- a/arch/powerpc/boot/dts/p1020rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_36b.dts
@@ -23,7 +23,7 @@
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = 0x0 0x0 0xf 0xef00 0x0100
- 0x1 0x0 0xf 0xffa0 0x0004
+ 0x1 0x0 0xf 0xff80 0x0004
0x2 0x0 0xf 0xffb0 0x0002;
};
--
1.6.4
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