[alsa-devel][PATCH 1/3] ASoC: fsl_esai: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_esai.c | 69
1 file changed, 69 insertions(+)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 5c75971..b749a29 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -684,6 +684,32 @@ static bool fsl_esai_readable_reg(struct device *dev,
unsigned int reg)
}
}
+static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_ESAI_ETDR:
+ case REG_ESAI_ERDR:
+ case REG_ESAI_ESR:
+ case REG_ESAI_TFSR:
+ case REG_ESAI_RFSR:
+ case REG_ESAI_TX0:
+ case REG_ESAI_TX1:
+ case REG_ESAI_TX2:
+ case REG_ESAI_TX3:
+ case REG_ESAI_TX4:
+ case REG_ESAI_TX5:
+ case REG_ESAI_RX0:
+ case REG_ESAI_RX1:
+ case REG_ESAI_RX2:
+ case REG_ESAI_RX3:
+ case REG_ESAI_SAISR:
+ return true;
+ default:
+ return false;
+ }
+
+}
+
static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
@@ -722,7 +748,9 @@ static const struct regmap_config fsl_esai_regmap_config = {
.max_register = REG_ESAI_PCRC,
.readable_reg = fsl_esai_readable_reg,
+ .volatile_reg = fsl_esai_volatile_reg,
.writeable_reg = fsl_esai_writeable_reg,
+ .cache_type = REGCACHE_RBTREE,
};
static int fsl_esai_probe(struct platform_device *pdev)
@@ -853,10 +881,51 @@ static const struct of_device_id fsl_esai_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
+#if CONFIG_PM_SLEEP
+static int fsl_esai_suspend(struct device *dev)
+{
+ struct fsl_esai *esai = dev_get_drvdata(dev);
+
+ regcache_cache_only(esai-regmap, true);
+ regcache_mark_dirty(esai-regmap);
+
+ return 0;
+}
+
+static int fsl_esai_resume(struct device *dev)
+{
+ struct fsl_esai *esai = dev_get_drvdata(dev);
+ int ret;
+
+ regcache_cache_only(esai-regmap, false);
+
+ /* FIFO reset for safety */
+ regmap_update_bits(esai-regmap, REG_ESAI_TFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+ regmap_update_bits(esai-regmap, REG_ESAI_RFCR,
+ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
+
+ ret = regcache_sync(esai-regmap);
+ if (ret)
+ return ret;
+
+ /* FIFO reset done */
+ regmap_update_bits(esai-regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
+ regmap_update_bits(esai-regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
+
+ return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops fsl_esai_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
+};
+
static struct platform_driver fsl_esai_driver = {
.probe = fsl_esai_probe,
.driver = {
.name = fsl-esai-dai,
+ .pm = fsl_esai_pm_ops,
.of_match_table = fsl_esai_dt_ids,
},
};
--
1.9.1
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[alsa-devel][PATCH 2/3] ASoC: fsl_spdif: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_spdif.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 8e93221..caf20d1 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -300,6 +300,8 @@ static int spdif_softreset(struct fsl_spdif_priv
*spdif_priv)
struct regmap *regmap = spdif_priv-regmap;
u32 val, cycle = 1000;
+ regcache_cache_bypass(regmap, true);
+
regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
/*
@@ -310,6 +312,10 @@ static int spdif_softreset(struct fsl_spdif_priv
*spdif_priv)
regmap_read(regmap, REG_SPDIF_SCR, val);
} while ((val SCR_SOFT_RESET) cycle--);
+ regcache_cache_bypass(regmap, false);
+ regcache_mark_dirty(regmap);
+ regcache_sync(regmap);
+
if (cycle)
return 0;
else
@@ -1013,6 +1019,26 @@ static bool fsl_spdif_readable_reg(struct device *dev,
unsigned int reg)
}
}
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SIS:
+ case REG_SPDIF_SRL:
+ case REG_SPDIF_SRR:
+ case REG_SPDIF_SRCSH:
+ case REG_SPDIF_SRCSL:
+ case REG_SPDIF_SRU:
+ case REG_SPDIF_SRQ:
+ case REG_SPDIF_STL:
+ case REG_SPDIF_STR:
+ case REG_SPDIF_SRFM:
+ return true;
+ default:
+ return false;
+ }
+
+}
+
static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
@@ -1039,7 +1065,9 @@ static const struct regmap_config fsl_spdif_regmap_config
= {
.max_register = REG_SPDIF_STC,
.readable_reg = fsl_spdif_readable_reg,
+ .volatile_reg = fsl_spdif_volatile_reg,
.writeable_reg = fsl_spdif_writeable_reg,
+ .cache_type = REGCACHE_RBTREE,
};
static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
@@ -1262,6 +1290,30 @@ static int fsl_spdif_probe(struct platform_device *pdev)
return ret;
}
+#ifdef CONFIG_PM_SLEEP
+static int fsl_spdif_suspend(struct device *dev)
+{
+ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
+
+ regcache_cache_only(spdif_priv-regmap, true);
+ regcache_mark_dirty(spdif_priv-regmap);
+
+ return 0;
+}
+
+static int fsl_spdif_resume(struct device *dev)
+{
+ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
+
+ regcache_cache_only(spdif_priv-regmap, false);
+ return regcache_sync(spdif_priv-regmap);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops fsl_spdif_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
+};
+
static const struct of_device_id fsl_spdif_dt_ids[] = {
{ .compatible = fsl,imx35-spdif, },
{ .compatible = fsl,vf610-spdif, },
@@ -1273,6 +1325,7 @@ static struct platform_driver fsl_spdif_driver = {
.driver = {
.name = fsl-spdif-dai,
.of_match_table = fsl_spdif_dt_ids,
+ .pm = fsl_spdif_pm,
},
.probe = fsl_spdif_probe,
};
--
1.9.1
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[alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 5c73bea..62187e4 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -637,6 +637,8 @@ static bool fsl_sai_readable_reg(struct device *dev,
unsigned int reg)
static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
+ case FSL_SAI_TCSR:
+ case FSL_SAI_RCSR:
case FSL_SAI_TFR:
case FSL_SAI_RFR:
case FSL_SAI_TDR:
@@ -681,6 +683,7 @@ static const struct regmap_config fsl_sai_regmap_config = {
.readable_reg = fsl_sai_readable_reg,
.volatile_reg = fsl_sai_volatile_reg,
.writeable_reg = fsl_sai_writeable_reg,
+ .cache_type = REGCACHE_RBTREE,
};
static int fsl_sai_probe(struct platform_device *pdev)
@@ -802,10 +805,40 @@ static const struct of_device_id fsl_sai_ids[] = {
{ /* sentinel */ }
};
+#if CONFIG_PM_SLEEP
+static int fsl_sai_suspend(struct device *dev)
+{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+
+ regcache_cache_only(sai-regmap, true);
+ regcache_mark_dirty(sai-regmap);
+
+ return 0;
+}
+
+static int fsl_sai_resume(struct device *dev)
+{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+
+ regcache_cache_only(sai-regmap, false);
+ regmap_write(sai-regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
+ regmap_write(sai-regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
+ msleep(1);
+ regmap_write(sai-regmap, FSL_SAI_TCSR, 0);
+ regmap_write(sai-regmap, FSL_SAI_RCSR, 0);
+ return regcache_sync(sai-regmap);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops fsl_sai_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
+};
+
static struct platform_driver fsl_sai_driver = {
.probe = fsl_sai_probe,
.driver = {
.name = fsl-sai,
+ .pm = fsl_sai_pm_ops,
.of_match_table = fsl_sai_ids,
},
};
--
1.9.1
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[alsa-devel][PATCH 1/2] ASoC: fsl_ssi: Add driver suspend and resume to support MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power
source of modules during system suspend and resume procedure. Thus,
SSI needs to save all the values of registers before the system
suspend and restore them after the system resume.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_ssi.c | 113
1 file changed, 113 insertions(+)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index c7647e0..52b894f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -111,12 +111,98 @@ struct fsl_ssi_rxtx_reg_val {
struct fsl_ssi_reg_val rx;
struct fsl_ssi_reg_val tx;
};
+
+static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SRX0:
+ case CCSR_SSI_SRX1:
+ case CCSR_SSI_SCR:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SIER:
+ case CCSR_SSI_STCR:
+ case CCSR_SSI_SRCR:
+ case CCSR_SSI_STCCR:
+ case CCSR_SSI_SRCCR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_STR:
+ case CCSR_SSI_SOR:
+ case CCSR_SSI_SACNT:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_STMSK:
+ case CCSR_SSI_SRMSK:
+ case CCSR_SSI_SACCST:
+ case CCSR_SSI_SACCEN:
+ case CCSR_SSI_SACCDIS:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SRX0:
+ case CCSR_SSI_SRX1:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_SACCST:
+ return true;
+ default:
+ return false;
+ }
+
+}
+
+static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CCSR_SSI_STX0:
+ case CCSR_SSI_STX1:
+ case CCSR_SSI_SCR:
+ case CCSR_SSI_SISR:
+ case CCSR_SSI_SIER:
+ case CCSR_SSI_STCR:
+ case CCSR_SSI_SRCR:
+ case CCSR_SSI_STCCR:
+ case CCSR_SSI_SRCCR:
+ case CCSR_SSI_SFCSR:
+ case CCSR_SSI_STR:
+ case CCSR_SSI_SOR:
+ case CCSR_SSI_SACNT:
+ case CCSR_SSI_SACADD:
+ case CCSR_SSI_SACDAT:
+ case CCSR_SSI_SATAG:
+ case CCSR_SSI_STMSK:
+ case CCSR_SSI_SRMSK:
+ case CCSR_SSI_SACCEN:
+ case CCSR_SSI_SACCDIS:
+ return true;
+ default:
+ return false;
+ }
+}
+
static const struct regmap_config fsl_ssi_regconfig = {
.max_register = CCSR_SSI_SACCDIS,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
+ .readable_reg = fsl_ssi_readable_reg,
+ .volatile_reg = fsl_ssi_volatile_reg,
+ .writeable_reg = fsl_ssi_writeable_reg,
+ .cache_type = REGCACHE_RBTREE,
};
struct fsl_ssi_soc_data {
@@ -1461,10 +1547,37 @@ static int fsl_ssi_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int fsl_ssi_suspend(struct device *dev)
+{
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
+ struct regmap *regs = ssi_private-regs;
+
+ regcache_cache_only(regs, true);
+ regcache_mark_dirty(regs);
+
+ return 0;
+}
+
+static int fsl_ssi_resume(struct device *dev)
+{
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
+ struct regmap *regs = ssi_private-regs;
+
+ regcache_cache_only(regs, false);
+ return regcache_sync(regs);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops fsl_ssi_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
+};
+
static struct platform_driver fsl_ssi_driver = {
.driver = {
.name = fsl-ssi-dai,
.of_match_table = fsl_ssi_ids,
+ .pm = fsl_ssi_pm,
},
.probe = fsl_ssi_probe,
.remove = fsl_ssi_remove,
--
1.9.1
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[alsa-devel][PATCH 2/2] ASoC: fsl_ssi: sound is wrong after suspend/resume
The register SFCSR is volatile, but some bits in it need to be
recovered after suspend/resume.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_ssi.c | 12
1 file changed, 12 insertions(+)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 52b894f..e414f18 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -262,6 +262,9 @@ struct fsl_ssi_private {
unsigned int baudclk_streams;
unsigned int bitclk_freq;
+ /*regcache for SFCSR*/
+ u32 regcache_sfcsr;
+
/* DMA params */
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
@@ -1553,6 +1556,9 @@ static int fsl_ssi_suspend(struct device *dev)
struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
struct regmap *regs = ssi_private-regs;
+ regmap_read(regs, CCSR_SSI_SFCSR,
+ ssi_private-regcache_sfcsr);
+
regcache_cache_only(regs, true);
regcache_mark_dirty(regs);
@@ -1565,6 +1571,12 @@ static int fsl_ssi_resume(struct device *dev)
struct regmap *regs = ssi_private-regs;
regcache_cache_only(regs, false);
+
+ regmap_update_bits(regs, CCSR_SSI_SFCSR,
+ CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
+ CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
+ ssi_private-regcache_sfcsr);
+
return regcache_sync(regs);
}
#endif /* CONFIG_PM_SLEEP */
--
1.9.1
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Re: [alsa-devel][PATCH] ASoC: fsl: add imx-wm8960 machine driver
On Thu, Jun 11, 2015 at 08:51:07AM -0700, Nicolin Chen wrote: On Thu, Jun 11, 2015 at 07:10:00PM +0800, Zidan Wang wrote: This imx-wm8960 device-tree-only machine driver works with sai driver and have below feature. * support codec master and slave mode * support headphone jack detect * support headphone and micphone jack event * support asrc-sai-wm8960 mode Signed-off-by: Zidan Wang zidan.w...@freescale.com Above all, could you merge this into fsl-asoc-card? It'd be nicer to have jack detection over there. And we can put PLL settings to the codec driver as Mark suggested. I want to modify imx-wm8960 and upstream it because our release is using it now. After upstreaming imx-wm8960, i will try to merge it to fsl-asoc-card. I knew your intention. That's why I suggested you to merge it directly to fsl-asoc-card instead of making a duplicated copy of that. Remember that getting code upstream should be a chance for us to improve thing. If you find painstaking to handle it in parallel, you can focus on the improvements of the WM8960 driver while I would help you on the dai- link part. How about this? Nicolin The new imx7 release have two new codec wm8958 and wm8960. So we have two machine driver imx-wm8960 and imx-wm8958 which should be upstreamed. I am appreciate that you can help me merge the imx-wm8960 to fsl-asoc-card. And i will focus on wm8960 and wm8958 driver. And i will try to merge imx-wm8958 to fsl-asoc-card. Best Regards, Zidan Wang ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel][PATCH] ASoC: fsl: add imx-wm8960 machine driver
On Wed, Jun 10, 2015 at 11:36:21AM -0700, Nicolin Chen wrote: On Wed, Jun 10, 2015 at 04:26:27PM +0800, Zidan Wang wrote: This imx-wm8960 device-tree-only machine driver works with sai driver and have below feature. * support codec master and slave mode * support headphone jack detect * support headphone and micphone jack event * support asrc-sai-wm8960 mode Signed-off-by: Zidan Wang zidan.w...@freescale.com Above all, could you merge this into fsl-asoc-card? It'd be nicer to have jack detection over there. And we can put PLL settings to the codec driver as Mark suggested. Hi Nicolin, I want to modify imx-wm8960 and upstream it because our release is using it now. After upstreaming imx-wm8960, i will try to merge it to fsl-asoc-card. Best Regards, Zidan Wang Thanks Nicolin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[alsa-devel][PATCH] ASoC: fsl: add imx-wm8960 machine driver
This imx-wm8960 device-tree-only machine driver works with sai driver
and have below feature.
* support codec master and slave mode
* support headphone jack detect
* support headphone and micphone jack event
* support asrc-sai-wm8960 mode
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
.../devicetree/bindings/sound/imx-audio-wm8960.txt | 68 ++
sound/soc/fsl/Kconfig | 13 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-wm8960.c | 711 +
4 files changed, 794 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt
create mode 100644 sound/soc/fsl/imx-wm8960.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt
b/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt
new file mode 100644
index 000..300d027
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8960.txt
@@ -0,0 +1,68 @@
+Freescale i.MX audio complex with WM8960 codec
+
+Required properties:
+
+ - compatible : fsl,imx-audio-wm8960
+
+ - model : The user-visible name of this sound complex
+
+ - audio-codec: The phandle of the WM8960 audio codec
+
+ - hp-det : ADCLRC/GPIO1, LINPUT3/JD2 and RINPUT3/JD3 pins can
+ be selected as headphone jack detect inputs to
+ automatically disable the speaker output and enable
+ the headphone output.
+ hp-det = hp-det-pin hp-det-polarity;
+ hp-det-pin = 1: ADCLRC/GPIO1 used as detect pin
+ hp-det-pin = 2: LINPUT3/JD2 used as detect pin
+ hp-det-pin = 3: RINPUT3/JD3 used as detect pin
+ hp-det-polarity = 0: hp detect high for headphone
+ hp-det-polarity = 1: hp detect high for speaker
+
+ - codec-master : If codec-master present, codec works as master.
+ Otherwise, codec works as slave.
+
+ - audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's
+ source. Valid names could be power supplies, WM8962
+ pins, and the jacks on the board:
+
+ Power supplies:
+ * MICB
+
+ Board connectors:
+ * Hp MIC
+ * Main MIC
+ * Headset Jack
+ * Ext Spk
+
+Example:
+
+sound {
+ compatible = fsl,imx6ul-evk-wm8960,
+ fsl,imx-audio-wm8960;
+ model = wm8960-audio;
+ cpu-dai = sai2;
+ audio-codec = codec;
+ asrc-controller = asrc;
+ codec-master;
+ hp-det = 3 0;
+ audio-routing =
+ Headset Jack, HP_L,
+ Headset Jack, HP_R,
+ Ext Spk, SPK_LP,
+ Ext Spk, SPK_LN,
+ Ext Spk, SPK_RP,
+ Ext Spk, SPK_RN,
+ LINPUT2, Hp MIC,
+ LINPUT3, Hp MIC,
+ RINPUT1, Main MIC,
+ RINPUT2, Main MIC,
+ Hp MIC, MICB,
+ Main MIC, MICB,
+ CPU-Playback, ASRC-Playback,
+ Playback, CPU-Playback,
+ ASRC-Capture, CPU-Capture,
+ CPU-Capture, Capture;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19c302b..0d9aa56 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -229,6 +229,19 @@ config SND_SOC_EUKREA_TLV320
Enable I2S based access to the TLV320AIC23B codec attached
to the SSI interface
+config SND_SOC_IMX_WM8960
+ tristate SoC Audio support for i.MX boards with wm8960
+ depends on OF I2C
+ select SND_SOC_WM8960
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SAI
+ select SND_SOC_FSL_UTILS
+ select SND_KCTL_JACK
+ help
+SoC Audio support for i.MX boards with WM8960
+Say Y if you want to add support for SoC audio on an i.MX board with
+a wm8960 codec.
+
config SND_SOC_IMX_WM8962
tristate SoC Audio support for i.MX boards with wm8962
depends on OF I2C INPUT
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d28dc25..84a9a10 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -54,6 +54,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-es8328-objs := imx-es8328.o
Re: [alsa-devel] [PATCH] ASoC: fsl_spdif: Don't try to round-up for clock divisor calculation
On Mon, May 25, 2015 at 08:24:25AM -0700, Nicolin Chen wrote: On Mon, May 25, 2015 at 12:13:45PM -0300, Fabio Estevam wrote: Hi Nicolin, On Mon, May 25, 2015 at 12:11 PM, Nicolin Chen nicoleots...@gmail.com wrote: Hi Mark, Is that possible for you to provisionally revert this patch? I wanted to wait for the test result from Fabio or Zidan in the Cc list because I don't have a test environment for SPDIF even though this change seems to make sense. I currently don't have access to a SPDIF receiver to test it. Okay, let's wait for Zidan then. We only need to test the playback route of supporting sample rates. Thanks Nicolin I don't have the board which supported by community to test spdif out. So i used the imx7 board and test it with internal branch. I found that (txclk_df + 1) is better than txclk_df. I suspect the patch for clk_round_rate() is not in our branch. Could you please tell me which patch is for clk_round_rate? I want to cherry-pick it to our branch and test it. Best Regards, Zidan Wang ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[alsa-devel][PATCH v2 1/3] ASoC: fsl_sai: add sai master mode support
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_free() to disable the mclk.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
Signed-off-by: Mark Brown broo...@kernel.org
---
sound/soc/fsl/fsl_sai.c | 117 ++--
sound/soc/fsl/fsl_sai.h | 9 +++-
2 files changed, 121 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index ee2671b..1ccc10d1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1,7 +1,7 @@
/*
* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012-2015 Freescale Semiconductor, Inc.
*
* This program is free software, you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -251,12 +251,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai
*cpu_dai,
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
+ sai-is_slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFM:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
+ sai-is_slave_mode = true;
break;
default:
return -EINVAL;
@@ -288,6 +290,79 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai
*cpu_dai, unsigned int fmt)
return ret;
}
+static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
+ unsigned long clk_rate;
+ u32 savediv = 0, ratio, savesub = freq;
+ u32 id;
+ int ret = 0;
+
+ /* Don't apply to slave mode */
+ if (sai-is_slave_mode)
+ return 0;
+
+ for (id = 0; id FSL_SAI_MCLK_MAX; id++) {
+ clk_rate = clk_get_rate(sai-mclk_clk[id]);
+ if (!clk_rate)
+ continue;
+
+ ratio = clk_rate / freq;
+
+ ret = clk_rate - ratio * freq;
+
+ /*
+* Drop the source that can not be
+* divided into the required rate.
+*/
+ if (ret != 0 clk_rate / ret 1000)
+ continue;
+
+ dev_dbg(dai-dev,
+ ratio %d for freq %dHz based on clock %ldHz\n,
+ ratio, freq, clk_rate);
+
+ if (ratio % 2 == 0 ratio = 2 ratio = 512)
+ ratio /= 2;
+ else
+ continue;
+
+ if (ret savesub) {
+ savediv = ratio;
+ sai-mclk_id[tx] = id;
+ savesub = ret;
+ }
+
+ if (ret == 0)
+ break;
+ }
+
+ if (savediv == 0) {
+ dev_err(dai-dev, failed to derive required %cx rate: %d\n,
+ tx ? 'T' : 'R', freq);
+ return -EINVAL;
+ }
+
+ if ((tx sai-synchronous[TX]) || (!tx !sai-synchronous[RX])) {
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ } else {
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ }
+
+ dev_dbg(dai-dev, best fit: clock id=%d, div=%d, deviation =%d\n,
+ sai-mclk_id[tx], savediv, savesub);
+
+ return 0;
+}
+
static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
@@ -297,6 +372,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ int ret;
+
+ if (!sai-is_slave_mode) {
+ ret = fsl_sai_set_bclk(cpu_dai, tx,
+ 2 * word_width * params_rate(params));
+ if (ret)
+ return ret;
+
+ /* Do not enable the clock
[alsa-devel][PATCH v2 2/3] ASoC: fsl_sai: add tdm slots operation support
Add tdm slots operation support. If tdm slots and slot width have
been configured in machine driver, we should use these values.
Otherwise, using relevant channels and word length to set slots
and slot width.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be unused BCLK cycles before each LRCLK transition.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 34 --
sound/soc/fsl/fsl_sai.h | 3 +++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 1ccc10d1..7624dd0 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -115,6 +115,17 @@ out:
return IRQ_HANDLED;
}
+static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+
+ sai-slots = slots;
+ sai-slot_width = slot_width;
+
+ return 0;
+}
+
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int fsl_dir)
{
@@ -372,11 +383,22 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ u32 slots, slot_width;
int ret;
+ if (sai-slots == 0)
+ slots = (channels == 1) ? 2 : channels;
+ else
+ slots = sai-slots;
+
+ if (sai-slot_width == 0)
+ slot_width = word_width;
+ else
+ slot_width = sai-slot_width;
+
if (!sai-is_slave_mode) {
ret = fsl_sai_set_bclk(cpu_dai, tx,
- 2 * word_width * params_rate(params));
+ slots * slot_width * params_rate(params));
if (ret)
return ret;
@@ -388,21 +410,20 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
sai-mclk_streams |= BIT(substream-stream);
}
-
}
if (!sai-is_dsp_mode)
- val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
+ val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
- val_cr5 |= FSL_SAI_CR5_WNW(word_width);
- val_cr5 |= FSL_SAI_CR5_W0W(word_width);
+ val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
+ val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
if (sai-is_lsb_first)
val_cr5 |= FSL_SAI_CR5_FBT(0);
else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
- val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
+ val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
regmap_update_bits(sai-regmap, FSL_SAI_xCR4(tx),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
@@ -536,6 +557,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream
*substream,
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
.set_sysclk = fsl_sai_set_dai_sysclk,
.set_fmt= fsl_sai_set_dai_fmt,
+ .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
.hw_params = fsl_sai_hw_params,
.hw_free= fsl_sai_hw_free,
.trigger= fsl_sai_trigger,
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 0662809..1ec09d6 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -142,6 +142,9 @@ struct fsl_sai {
unsigned int mclk_id[2];
unsigned int mclk_streams;
+ unsigned int slots;
+ unsigned int slot_width;
+
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
};
--
1.9.1
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[alsa-devel][PATCH v2 3/3] ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support
Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't
have formal definition of 12kHz, 24kHz, but alsa supply a way to
support these sample rates. And add 176.4kHz and 192kHz support.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
Signed-off-by: Mark Brown broo...@kernel.org
---
sound/soc/fsl/fsl_sai.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 7624dd0..640bd5b 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -27,6 +27,17 @@
#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
FSL_SAI_CSR_FEIE)
+static u32 fsl_sai_rates[] = {
+ 8000, 11025, 12000, 16000, 22050,
+ 24000, 32000, 44100, 48000, 64000,
+ 88200, 96000, 176400, 192000
+};
+
+static struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
+ .count = ARRAY_SIZE(fsl_sai_rates),
+ .list = fsl_sai_rates,
+};
+
static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
struct fsl_sai *sai = (struct fsl_sai *)devid;
@@ -540,7 +551,10 @@ static int fsl_sai_startup(struct snd_pcm_substream
*substream,
regmap_update_bits(sai-regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
FSL_SAI_CR3_TRCE);
- return 0;
+ ret = snd_pcm_hw_constraint_list(substream-runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, fsl_sai_rate_constraints);
+
+ return ret;
}
static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
@@ -595,14 +609,18 @@ static struct snd_soc_dai_driver fsl_sai_dai = {
.stream_name = CPU-Playback,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.capture = {
.stream_name = CPU-Capture,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.ops = fsl_sai_pcm_dai_ops,
--
1.9.1
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[alsa-devel][PATCH 3/3] ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support
Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't
have formal definition of 12kHz, 24kHz, but alsa supply a way to
support these sample rates. And add 176.4kHz and 192kHz support.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 88f5861..7efcac4 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -27,6 +27,17 @@
#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
FSL_SAI_CSR_FEIE)
+static u32 fsl_sai_rates[] = {
+ 8000, 11025, 12000, 16000, 22050,
+ 24000, 32000, 44100, 48000, 64000,
+ 88200, 96000, 176400, 192000
+};
+
+static struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
+ .count = ARRAY_SIZE(fsl_sai_rates),
+ .list = fsl_sai_rates,
+};
+
static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
struct fsl_sai *sai = (struct fsl_sai *)devid;
@@ -531,7 +542,10 @@ static int fsl_sai_startup(struct snd_pcm_substream
*substream,
regmap_update_bits(sai-regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
FSL_SAI_CR3_TRCE);
- return 0;
+ ret = snd_pcm_hw_constraint_list(substream-runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, fsl_sai_rate_constraints);
+
+ return ret;
}
static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
@@ -586,14 +600,18 @@ static struct snd_soc_dai_driver fsl_sai_dai = {
.stream_name = CPU-Playback,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.capture = {
.stream_name = CPU-Capture,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.ops = fsl_sai_pcm_dai_ops,
--
1.9.1
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[alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add tdm slots operation for SAI master mode
Add tdm slot operation for SAI master mode. When using SAI as master
mode, we should use set_tdm_slot() helper function to set tdm slots
in machine driver, or it will using default value of slots and slot
width.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be unused BCLK cycles before each LRCLK transition.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 28 ++--
sound/soc/fsl/fsl_sai.h | 3 +++
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 1ccc10d1..88f5861 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -115,6 +115,17 @@ out:
return IRQ_HANDLED;
}
+static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+
+ sai-slots = slots;
+ sai-slot_width = slot_width;
+
+ return 0;
+}
+
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int fsl_dir)
{
@@ -372,11 +383,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ u32 slot_width = word_width;
int ret;
if (!sai-is_slave_mode) {
+ slot_width = sai-slot_width;
ret = fsl_sai_set_bclk(cpu_dai, tx,
- 2 * word_width * params_rate(params));
+ sai-slots * slot_width * params_rate(params));
if (ret)
return ret;
@@ -388,21 +401,20 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
sai-mclk_streams |= BIT(substream-stream);
}
-
}
if (!sai-is_dsp_mode)
- val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
+ val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
- val_cr5 |= FSL_SAI_CR5_WNW(word_width);
- val_cr5 |= FSL_SAI_CR5_W0W(word_width);
+ val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
+ val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
if (sai-is_lsb_first)
val_cr5 |= FSL_SAI_CR5_FBT(0);
else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
- val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
+ val_cr4 |= FSL_SAI_CR4_FRSZ(sai-slots);
regmap_update_bits(sai-regmap, FSL_SAI_xCR4(tx),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
@@ -536,6 +548,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream
*substream,
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
.set_sysclk = fsl_sai_set_dai_sysclk,
.set_fmt= fsl_sai_set_dai_fmt,
+ .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
.hw_params = fsl_sai_hw_params,
.hw_free= fsl_sai_hw_free,
.trigger= fsl_sai_trigger,
@@ -721,6 +734,9 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ sai-slots = 2;
+ sai-slot_width = 32;
+
irq = platform_get_irq(pdev, 0);
if (irq 0) {
dev_err(pdev-dev, no irq for node %s\n, pdev-name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 0662809..1ec09d6 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -142,6 +142,9 @@ struct fsl_sai {
unsigned int mclk_id[2];
unsigned int mclk_streams;
+ unsigned int slots;
+ unsigned int slot_width;
+
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
};
--
1.9.1
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[alsa-devel][PATCH 1/3] ASoC: fsl_sai: add sai master mode support
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_free() to disable the mclk.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 117 ++--
sound/soc/fsl/fsl_sai.h | 9 +++-
2 files changed, 121 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index ee2671b..1ccc10d1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1,7 +1,7 @@
/*
* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012-2015 Freescale Semiconductor, Inc.
*
* This program is free software, you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -251,12 +251,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai
*cpu_dai,
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
+ sai-is_slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFM:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
+ sai-is_slave_mode = true;
break;
default:
return -EINVAL;
@@ -288,6 +290,79 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai
*cpu_dai, unsigned int fmt)
return ret;
}
+static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
+ unsigned long clk_rate;
+ u32 savediv = 0, ratio, savesub = freq;
+ u32 id;
+ int ret = 0;
+
+ /* Don't apply to slave mode */
+ if (sai-is_slave_mode)
+ return 0;
+
+ for (id = 0; id FSL_SAI_MCLK_MAX; id++) {
+ clk_rate = clk_get_rate(sai-mclk_clk[id]);
+ if (!clk_rate)
+ continue;
+
+ ratio = clk_rate / freq;
+
+ ret = clk_rate - ratio * freq;
+
+ /*
+* Drop the source that can not be
+* divided into the required rate.
+*/
+ if (ret != 0 clk_rate / ret 1000)
+ continue;
+
+ dev_dbg(dai-dev,
+ ratio %d for freq %dHz based on clock %ldHz\n,
+ ratio, freq, clk_rate);
+
+ if (ratio % 2 == 0 ratio = 2 ratio = 512)
+ ratio /= 2;
+ else
+ continue;
+
+ if (ret savesub) {
+ savediv = ratio;
+ sai-mclk_id[tx] = id;
+ savesub = ret;
+ }
+
+ if (ret == 0)
+ break;
+ }
+
+ if (savediv == 0) {
+ dev_err(dai-dev, failed to derive required %cx rate: %d\n,
+ tx ? 'T' : 'R', freq);
+ return -EINVAL;
+ }
+
+ if ((tx sai-synchronous[TX]) || (!tx !sai-synchronous[RX])) {
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ } else {
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ }
+
+ dev_dbg(dai-dev, best fit: clock id=%d, div=%d, deviation =%d\n,
+ sai-mclk_id[tx], savediv, savesub);
+
+ return 0;
+}
+
static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
@@ -297,6 +372,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ int ret;
+
+ if (!sai-is_slave_mode) {
+ ret = fsl_sai_set_bclk(cpu_dai, tx,
+ 2 * word_width * params_rate(params));
+ if (ret)
+ return ret;
+
+ /* Do not enable the clock if it is already enabled
[PATCH 3/3] ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support
Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't
have formal definition of 12kHz, 24kHz, but alsa supply a way to
support these sample rates. And add 176.4kHz and 192kHz support.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 88f5861..7efcac4 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -27,6 +27,17 @@
#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
FSL_SAI_CSR_FEIE)
+static u32 fsl_sai_rates[] = {
+ 8000, 11025, 12000, 16000, 22050,
+ 24000, 32000, 44100, 48000, 64000,
+ 88200, 96000, 176400, 192000
+};
+
+static struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
+ .count = ARRAY_SIZE(fsl_sai_rates),
+ .list = fsl_sai_rates,
+};
+
static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
struct fsl_sai *sai = (struct fsl_sai *)devid;
@@ -531,7 +542,10 @@ static int fsl_sai_startup(struct snd_pcm_substream
*substream,
regmap_update_bits(sai-regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
FSL_SAI_CR3_TRCE);
- return 0;
+ ret = snd_pcm_hw_constraint_list(substream-runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE, fsl_sai_rate_constraints);
+
+ return ret;
}
static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
@@ -586,14 +600,18 @@ static struct snd_soc_dai_driver fsl_sai_dai = {
.stream_name = CPU-Playback,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.capture = {
.stream_name = CPU-Capture,
.channels_min = 1,
.channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.ops = fsl_sai_pcm_dai_ops,
--
1.9.1
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[PATCH 2/3] ASoC: fsl_sai: Add tdm slots operation for SAI master mode
Add tdm slot operation for SAI master mode. When using SAI as master
mode, we should use set_tdm_slot() helper function to set tdm slots
in machine driver, or it will using default value of slots and slot
width.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be unused BCLK cycles before each LRCLK transition.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 28 ++--
sound/soc/fsl/fsl_sai.h | 3 +++
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 1ccc10d1..88f5861 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -115,6 +115,17 @@ out:
return IRQ_HANDLED;
}
+static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+
+ sai-slots = slots;
+ sai-slot_width = slot_width;
+
+ return 0;
+}
+
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int fsl_dir)
{
@@ -372,11 +383,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ u32 slot_width = word_width;
int ret;
if (!sai-is_slave_mode) {
+ slot_width = sai-slot_width;
ret = fsl_sai_set_bclk(cpu_dai, tx,
- 2 * word_width * params_rate(params));
+ sai-slots * slot_width * params_rate(params));
if (ret)
return ret;
@@ -388,21 +401,20 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
sai-mclk_streams |= BIT(substream-stream);
}
-
}
if (!sai-is_dsp_mode)
- val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
+ val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
- val_cr5 |= FSL_SAI_CR5_WNW(word_width);
- val_cr5 |= FSL_SAI_CR5_W0W(word_width);
+ val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
+ val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
if (sai-is_lsb_first)
val_cr5 |= FSL_SAI_CR5_FBT(0);
else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
- val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
+ val_cr4 |= FSL_SAI_CR4_FRSZ(sai-slots);
regmap_update_bits(sai-regmap, FSL_SAI_xCR4(tx),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
@@ -536,6 +548,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream
*substream,
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
.set_sysclk = fsl_sai_set_dai_sysclk,
.set_fmt= fsl_sai_set_dai_fmt,
+ .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
.hw_params = fsl_sai_hw_params,
.hw_free= fsl_sai_hw_free,
.trigger= fsl_sai_trigger,
@@ -721,6 +734,9 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ sai-slots = 2;
+ sai-slot_width = 32;
+
irq = platform_get_irq(pdev, 0);
if (irq 0) {
dev_err(pdev-dev, no irq for node %s\n, pdev-name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 0662809..1ec09d6 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -142,6 +142,9 @@ struct fsl_sai {
unsigned int mclk_id[2];
unsigned int mclk_streams;
+ unsigned int slots;
+ unsigned int slot_width;
+
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
};
--
1.9.1
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[PATCH 0/3] Add sai master mode, tdm slot operation and add some sample rate support
Add SAI master mode support. Add tdm slots operation for SAI master mode. Add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support. Zidan Wang (3): SoC: fsl_sai: add sai master mode support ASoC: fsl_sai: Add tdm slots operation for SAI master mode ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate support sound/soc/fsl/fsl_sai.c | 165 +--- sound/soc/fsl/fsl_sai.h | 12 +++- 2 files changed, 165 insertions(+), 12 deletions(-) -- 1.9.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3] ASoC: fsl_sai: add sai master mode support
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_free() to disable the mclk.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 117 ++--
sound/soc/fsl/fsl_sai.h | 9 +++-
2 files changed, 121 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index ee2671b..1ccc10d1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1,7 +1,7 @@
/*
* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
*
- * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012-2015 Freescale Semiconductor, Inc.
*
* This program is free software, you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -251,12 +251,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai
*cpu_dai,
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
+ sai-is_slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFM:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
+ sai-is_slave_mode = true;
break;
default:
return -EINVAL;
@@ -288,6 +290,79 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai
*cpu_dai, unsigned int fmt)
return ret;
}
+static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
+ unsigned long clk_rate;
+ u32 savediv = 0, ratio, savesub = freq;
+ u32 id;
+ int ret = 0;
+
+ /* Don't apply to slave mode */
+ if (sai-is_slave_mode)
+ return 0;
+
+ for (id = 0; id FSL_SAI_MCLK_MAX; id++) {
+ clk_rate = clk_get_rate(sai-mclk_clk[id]);
+ if (!clk_rate)
+ continue;
+
+ ratio = clk_rate / freq;
+
+ ret = clk_rate - ratio * freq;
+
+ /*
+* Drop the source that can not be
+* divided into the required rate.
+*/
+ if (ret != 0 clk_rate / ret 1000)
+ continue;
+
+ dev_dbg(dai-dev,
+ ratio %d for freq %dHz based on clock %ldHz\n,
+ ratio, freq, clk_rate);
+
+ if (ratio % 2 == 0 ratio = 2 ratio = 512)
+ ratio /= 2;
+ else
+ continue;
+
+ if (ret savesub) {
+ savediv = ratio;
+ sai-mclk_id[tx] = id;
+ savesub = ret;
+ }
+
+ if (ret == 0)
+ break;
+ }
+
+ if (savediv == 0) {
+ dev_err(dai-dev, failed to derive required %cx rate: %d\n,
+ tx ? 'T' : 'R', freq);
+ return -EINVAL;
+ }
+
+ if ((tx sai-synchronous[TX]) || (!tx !sai-synchronous[RX])) {
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ } else {
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_MSEL_MASK,
+ FSL_SAI_CR2_MSEL(sai-mclk_id[tx]));
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ }
+
+ dev_dbg(dai-dev, best fit: clock id=%d, div=%d, deviation =%d\n,
+ sai-mclk_id[tx], savediv, savesub);
+
+ return 0;
+}
+
static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
@@ -297,6 +372,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ int ret;
+
+ if (!sai-is_slave_mode) {
+ ret = fsl_sai_set_bclk(cpu_dai, tx,
+ 2 * word_width * params_rate(params));
+ if (ret)
+ return ret;
+
+ /* Do not enable the clock if it is already enabled
Re: [alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation
On Thu, Jan 22, 2015 at 03:50:20PM -0800, Nicolin Chen wrote: On Thu, Jan 22, 2015 at 02:20:06PM +0800, Zidan Wang wrote: @@ -369,10 +380,25 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, u32 word_width = snd_pcm_format_width(params_format(params)); u32 val_cr4 = 0, val_cr5 = 0; int ret; + u32 bclk; + + if (channels == 1) + channels = 2; + + if (!sai-slots || sai-slots % channels) + sai-slots = channels; + + sai-slots = sai-slots / channels; + + if (sai-slot_width word_width || sai-is_dsp_mode) + sai-slot_width = word_width; Could you pls explain a bit what's this overriding for? Or it might be better to put into a comment. In machine driver, we should use snd_soc_dai_set_tdm_slot to set slots and slot width. In my opinion, slots in machine driver means the slot number of all channels. But in sai driver, the slots means the slot number of one channel. So snd_soc_calc_bclk use fs*sample_size*channels*tdm_slots to caculate bclk. Could you pls use the standard way as you described for slot number in machine driver instead of defining some other meanings? That one is really confusing, not to mention a code without any comment. You can add some extra local variables with extinguished names and calculate the slot number and channels you want without changing the original sai-slots and channels in the hw_params(). As you said, you only need that new slot number and channels for snd_soc_calc_bclk call. So you may also put this code right before the call -- a normal routine doesn't need to recalculate the special slots and channels, right? Actually i don't kown which meaning is the standard way. Because i found in wm8993 and wm8904 codec driver, they also use slots/channels to set tdm_slots in set_tdm_slot function. The slots via machine driver should be total slot number per frame. For I2S, we're passing 2 for slots parameter in our machine drivers. So why not just following that pattern. You code for calculating slot per channel is used to calculate bclk. But keeping slot per frame will also allow you to do that, meanwhile you can drop some code to do the extra calculation so as to keep it neat. I suggest you to take a look at fsl_esai.c and to follow that way: Override slots and slot_width if specified from machine driver. I will follow slot per frame pattern like fsl_esai.c, thanks very mush. I have another question. Can a channel have several slots? Or channel just means slot. And another problem of your patch is the configurations for FRSZ and xMR fields. For monaural case, the channels == 1, the current code passes it directly to set them while your code overrides it to 2. I'm not sure if you've tested the monaural case and confirmed it works. But, apparently, the configurations look pretty different. I have tested the mono case, it works well. Best Regards, Zidan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add support for Right-J mode
On Wed, Jan 21, 2015 at 10:53:20AM -0800, Nicolin Chen wrote: On Tue, Jan 20, 2015 at 08:21:20PM +0800, Zidan Wang wrote: Add Right-J mode and set TCR5 FBT bit to let data right justify. Signed-off-by: Zidan Wang zidan.w...@freescale.com - if (sai-is_lsb_first) + if (sai-is_lsb_first sai-is_right_j_mode) val_cr5 |= FSL_SAI_CR5_FBT(0); Are you sure that FBT(0) is correct for right justified mode? Because the original code is using FBT(0) for the lsb_first situation and it shouldn't be right justified mode as default. I am not sure about that. I assume lsb_first as big endian data. For 16 bit data format, the 2 bytes data will in high address of 4 bytes fifo. So the FBT is 16 for left-j and 0 for right-j. But big endian is bytes convert not bits convert. It makes me confuse. And send to community for help. Nicolin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation
On Wed, Jan 21, 2015 at 10:08:03AM -0800, Nicolin Chen wrote: On Tue, Jan 20, 2015 at 08:21:19PM +0800, Zidan Wang wrote: @@ -369,10 +380,25 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, u32 word_width = snd_pcm_format_width(params_format(params)); u32 val_cr4 = 0, val_cr5 = 0; int ret; + u32 bclk; + + if (channels == 1) + channels = 2; + + if (!sai-slots || sai-slots % channels) + sai-slots = channels; + + sai-slots = sai-slots / channels; + + if (sai-slot_width word_width || sai-is_dsp_mode) + sai-slot_width = word_width; Could you pls explain a bit what's this overriding for? Or it might be better to put into a comment. In machine driver, we should use snd_soc_dai_set_tdm_slot to set slots and slot width. In my opinion, slots in machine driver means the slot number of all channels. But in sai driver, the slots means the slot number of one channel. So snd_soc_calc_bclk use fs*sample_size*channels*tdm_slots to caculate bclk. So i use sai-slots = sai-slots / channels to calculate slots per channel. If we missing set slots, use channel number to set slots and get one slot per channel. If we missing set slot width, set default slot width to word width. If slot width is 32 and wrod width is 16, for 2 channels and one slot per channel, it will be 64 bit clock for one frame. val_cr5 |= FSL_SAI_CR5_WNW(sai-slot_width). val_cr5 |= FSL_SAI_CR5_W0W(sai-slot_width); So sai word length is 32, it will trans 32 bit data per channel. But dma only trans 16 bit data to fifo, the continues 16 bit will be 0. So for 16 bit data formate, it will just one channel has data. When it is dsp mode, let slot width equal to word width can fix the issue. Nicolin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation
On Wed, Jan 21, 2015 at 09:44:10PM -0800, Nicolin Chen wrote: On Thu, Jan 22, 2015 at 12:55:35PM +0800, Zidan Wang wrote: On Wed, Jan 21, 2015 at 10:08:03AM -0800, Nicolin Chen wrote: On Tue, Jan 20, 2015 at 08:21:19PM +0800, Zidan Wang wrote: @@ -369,10 +380,25 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, u32 word_width = snd_pcm_format_width(params_format(params)); u32 val_cr4 = 0, val_cr5 = 0; int ret; + u32 bclk; + + if (channels == 1) + channels = 2; + + if (!sai-slots || sai-slots % channels) + sai-slots = channels; + + sai-slots = sai-slots / channels; + + if (sai-slot_width word_width || sai-is_dsp_mode) + sai-slot_width = word_width; Could you pls explain a bit what's this overriding for? Or it might be better to put into a comment. In machine driver, we should use snd_soc_dai_set_tdm_slot to set slots and slot width. In my opinion, slots in machine driver means the slot number of all channels. But in sai driver, the slots means the slot number of one channel. So snd_soc_calc_bclk use fs*sample_size*channels*tdm_slots to caculate bclk. Could you pls use the standard way as you described for slot number in machine driver instead of defining some other meanings? That one is really confusing, not to mention a code without any comment. You can add some extra local variables with extinguished names and calculate the slot number and channels you want without changing the original sai-slots and channels in the hw_params(). As you said, you only need that new slot number and channels for snd_soc_calc_bclk call. So you may also put this code right before the call -- a normal routine doesn't need to recalculate the special slots and channels, right? Nicolin Actually i don't kown which meaning is the standard way. Because i found in wm8993 and wm8904 codec driver, they also use slots/channels to set tdm_slots in set_tdm_slot function. Best Regards, Zidan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master mode support
On Tue, Jan 20, 2015 at 10:07:03PM -0800, Nicolin Chen wrote:
On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote:
+static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
+ if ((tx sai-synchronous[TX]) || (!tx !sai-synchronous[RX])) {
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai-mclk_id));
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
Hmm...the case should be a bit more complicated here IMO.
tx sai-synchronous[TX] means the playback in synchronous
mode (TX following RX). What if the recording has been already
activated with an MSEL setting at this point? Then the playback
stream, as a secondary stream, will overwrite MSEL of the first
stream -- Record. Same would happen to the DIV configuration.
When TX following RX(or RX following TX), TX and RX works on same bit
clock and frame clock. They will use same MCLK source, and just need set
the bclk DIV for RX(or TX). The secondary stream will overwrite MSEL and
bclk DIV of the first stream, but it doesn't matter.
For RX(or TX) sync:
fsl_sai_dai.symmetric_rates = 1;
fsl_sai_dai.symmetric_channels = 1;
fsl_sai_dai.symmetric_samplebits = 1;
When TX and RX both works on async mode, TX and RX may works on
different bit clock and frame clock. We need set MCLK source and bclk
DIV for TX and RX. mclk_id just save a MCLK source id, so i need to define
mclk_id[2] for differnet stream.
For TX and RX async:
fsl_sai_dai.symmetric_rates = 0;
fsl_sai_dai.symmetric_channels = 0;
fsl_sai_dai.symmetric_samplebits = 0;
@@ -297,6 +368,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ int ret;
+
+ if (!sai-is_slave_mode) {
+ ret = fsl_sai_set_bclk(cpu_dai, tx,
+ 2 * word_width * params_rate(params));
+ if (ret)
+ return ret;
+
+ /* Do not enable the clock if it is already enabled */
It actually doesn't matter to enable the clock again since it
purely increaes its count. But we do need a protection for MSEL
overwritten issue resulted from the fsl_sai_set_bclk() call.
@@ -133,10 +135,13 @@ struct fsl_sai {
struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool is_lsb_first;
+ bool is_slave_mode;
bool is_dsp_mode;
bool sai_on_imx;
bool synchronous[2];
+ unsigned int mclk_id;
+ unsigned int mclk_streams;
Besides, I doubt that only one property of mclk_id can content
Asynchronous Mode -- TX and RX can fetch their clocks from
different MCLK sources.
When hw_params failed before mclk enable, hw_free will also decrease
the clk usecount. So add mclk_streams, when clk successful enabled,
set corresponding bit of mclk_stream. And clear such bit after clk disabled.
Nicolin
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[alsa-devel][PATCH 0/3] Add master mode, tmd and right-j mode support
Add sai master mode support. Add tdm slots support. Add Right-J mode support. Zidan Wang (3): SoC: fsl_sai: add sai master mode support ASoC: fsl_sai: Add support for tdm slots operation ASoC: fsl_sai: Add support for Right-J mode sound/soc/fsl/fsl_sai.c | 164 sound/soc/fsl/fsl_sai.h | 13 +++- 2 files changed, 164 insertions(+), 13 deletions(-) -- 1.9.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master mode support
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_free() to disable the mclk.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 110 +++-
sound/soc/fsl/fsl_sai.h | 9 +++-
2 files changed, 115 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index ec79c3d..499cbd9 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -251,12 +251,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai
*cpu_dai,
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFM:
+ sai-is_slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFM:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
+ sai-is_slave_mode = true;
break;
default:
return -EINVAL;
@@ -288,6 +290,75 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai
*cpu_dai, unsigned int fmt)
return ret;
}
+static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
+ unsigned long clk_rate;
+ u32 savediv = 0, ratio, savesub = freq;
+ u32 id;
+ int ret = 0;
+
+ /* Don't apply to slave mode */
+ if (sai-is_slave_mode)
+ return 0;
+
+ for (id = 0; id FSL_SAI_MCLK_MAX; id++) {
+ clk_rate = clk_get_rate(sai-mclk_clk[id]);
+ if (!clk_rate)
+ continue;
+
+ ratio = clk_rate / freq;
+
+ ret = clk_rate - ratio * freq;
+
+ /* Drop the source that can not be divided
+* into the required rate
+* */
+ if (ret != 0 clk_rate / ret 1000)
+ continue;
+
+ dev_dbg(dai-dev, ratio %d for freq %dHz based on clock
%ldHz\n,
+ ratio, freq, clk_rate);
+
+ if (ratio % 2 == 0 ratio = 2 ratio = 512)
+ ratio /= 2;
+ else
+ continue;
+
+ if (ret savesub) {
+ savediv = ratio;
+ sai-mclk_id = id;
+ savesub = ret;
+ }
+
+ if (ret == 0)
+ break;
+ }
+
+ if (savediv == 0) {
+ dev_err(dai-dev, failed to derive required %cx rate: %d\n,
+ tx ? 'T' : 'R', freq);
+ return -EINVAL;
+ }
+
+ if ((tx sai-synchronous[TX]) || (!tx !sai-synchronous[RX])) {
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai-mclk_id));
+ regmap_update_bits(sai-regmap, FSL_SAI_RCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ } else {
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai-mclk_id));
+ regmap_update_bits(sai-regmap, FSL_SAI_TCR2,
+ FSL_SAI_CR2_DIV_MASK, savediv - 1);
+ }
+
+ dev_dbg(dai-dev, best fit: clock id=%d, div=%d, deviation =%d\n,
+ sai-mclk_id, savediv, savesub);
+
+ return 0;
+}
+
static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
@@ -297,6 +368,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
unsigned int channels = params_channels(params);
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
+ int ret;
+
+ if (!sai-is_slave_mode) {
+ ret = fsl_sai_set_bclk(cpu_dai, tx,
+ 2 * word_width * params_rate(params));
+ if (ret)
+ return ret;
+
+ /* Do not enable the clock if it is already enabled */
+ if (!(sai-mclk_streams BIT(substream-stream))) {
+ ret = clk_prepare_enable(sai-mclk_clk[sai-mclk_id]);
+ if (ret)
+ return ret;
+
+ sai-mclk_streams |= BIT(substream-stream);
+ }
+
+ }
if (!sai-is_dsp_mode)
val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
@@ -322,6 +411,21 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
return 0;
}
+static
[alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation
slots and slot width is set from set_dai_tdm_slot in machine driver.
We should calculate the actual slots per channel using slots/channels.
When using tdm slots, we should generate bclk depends channels, slots
and slot width. And there may be unused BCLK cycles before each LRCLK
transition.
Set TCR2 WNW bit to slot width and TCR4 FRSZ bit to slots * channels to
configure frame Length. And it is no need to set TCR4 SYWD to set frame
sync length for sai slave mode, so just do it when it is sai master mode.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 46 +-
sound/soc/fsl/fsl_sai.h | 3 +++
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 499cbd9..4c5040d 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -115,6 +115,17 @@ out:
return IRQ_HANDLED;
}
+static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+
+ sai-slots = slots;
+ sai-slot_width = slot_width;
+
+ return 0;
+}
+
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int fsl_dir)
{
@@ -369,10 +380,25 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
u32 word_width = snd_pcm_format_width(params_format(params));
u32 val_cr4 = 0, val_cr5 = 0;
int ret;
+ u32 bclk;
+
+ if (channels == 1)
+ channels = 2;
+
+ if (!sai-slots || sai-slots % channels)
+ sai-slots = channels;
+
+ sai-slots = sai-slots / channels;
+
+ if (sai-slot_width word_width || sai-is_dsp_mode)
+ sai-slot_width = word_width;
if (!sai-is_slave_mode) {
- ret = fsl_sai_set_bclk(cpu_dai, tx,
- 2 * word_width * params_rate(params));
+ bclk = snd_soc_calc_bclk(params_rate(params), sai-slot_width,
+ channels, sai-slots);
+
+ ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
+
if (ret)
return ret;
@@ -385,20 +411,19 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
sai-mclk_streams |= BIT(substream-stream);
}
+ if (!sai-is_dsp_mode)
+ val_cr4 |= FSL_SAI_CR4_SYWD(sai-slot_width);
}
- if (!sai-is_dsp_mode)
- val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
-
- val_cr5 |= FSL_SAI_CR5_WNW(word_width);
- val_cr5 |= FSL_SAI_CR5_W0W(word_width);
+ val_cr5 |= FSL_SAI_CR5_WNW(sai-slot_width);
+ val_cr5 |= FSL_SAI_CR5_W0W(sai-slot_width);
if (sai-is_lsb_first)
val_cr5 |= FSL_SAI_CR5_FBT(0);
else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
- val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
+ val_cr4 |= FSL_SAI_CR4_FRSZ(sai-slots * channels);
regmap_update_bits(sai-regmap, FSL_SAI_xCR4(tx),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
@@ -406,7 +431,9 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
regmap_update_bits(sai-regmap, FSL_SAI_xCR5(tx),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
- regmap_write(sai-regmap, FSL_SAI_xMR(tx), ~0UL - ((1 channels) -
1));
+
+ regmap_write(sai-regmap, FSL_SAI_xMR(tx),
+~0UL - ((1 params_channels(params) * sai-slots) - 1));
return 0;
}
@@ -531,6 +558,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream
*substream,
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
.set_sysclk = fsl_sai_set_dai_sysclk,
.set_fmt= fsl_sai_set_dai_fmt,
+ .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
.hw_params = fsl_sai_hw_params,
.hw_free= fsl_sai_hw_free,
.trigger= fsl_sai_trigger,
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 2d8c830..111dfce 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -140,6 +140,9 @@ struct fsl_sai {
bool sai_on_imx;
bool synchronous[2];
+ unsigned int slots;
+ unsigned int slot_width;
+
unsigned int mclk_id;
unsigned int mclk_streams;
struct snd_dmaengine_dai_dma_data dma_params_rx;
--
1.9.1
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[alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add support for Right-J mode
Add Right-J mode and set TCR5 FBT bit to let data right justify.
Signed-off-by: Zidan Wang zidan.w...@freescale.com
---
sound/soc/fsl/fsl_sai.c | 14 +++---
sound/soc/fsl/fsl_sai.h | 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 4c5040d..19cd6f3 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -228,7 +228,11 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai
*cpu_dai,
sai-is_dsp_mode = true;
break;
case SND_SOC_DAIFMT_RIGHT_J:
- /* To be done */
+ /* Frame high, one word length for frame sync */
+ val_cr2 |= FSL_SAI_CR2_BCP;
+ sai-is_right_j_mode = true;
+ break;
+
default:
return -EINVAL;
}
@@ -418,9 +422,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream
*substream,
val_cr5 |= FSL_SAI_CR5_WNW(sai-slot_width);
val_cr5 |= FSL_SAI_CR5_W0W(sai-slot_width);
- if (sai-is_lsb_first)
+ if (sai-is_lsb_first sai-is_right_j_mode)
val_cr5 |= FSL_SAI_CR5_FBT(0);
- else
+ else if (sai-is_lsb_first !sai-is_right_j_mode)
+ val_cr5 |= FSL_SAI_CR5_FBT(sai-slot_width - word_width);
+ else if (!sai-is_lsb_first sai-is_right_j_mode)
+ val_cr5 |= FSL_SAI_CR5_FBT(sai-slot_width - 1);
+ else if (!sai-is_lsb_first !sai-is_right_j_mode)
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
val_cr4 |= FSL_SAI_CR4_FRSZ(sai-slots * channels);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 111dfce..e220940 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -137,6 +137,7 @@ struct fsl_sai {
bool is_lsb_first;
bool is_slave_mode;
bool is_dsp_mode;
+ bool is_right_j_mode;
bool sai_on_imx;
bool synchronous[2];
--
1.9.1
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