[PATCH v15 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v15: 1. Fixed some checkpatch errors. 2. Added spin lock check during read-modify-write of interrupt registers out side intr handlers. 3. Removed Kconfig var which is not used and not defined. v14: 1. Modifying dwc_reg_read/write functions to accepts offset as arg. 2. Adding spin_lock to common interrupt function. 3. Adding start/stop, vbus_power functions to gadget_opst struct. 4. Removed some unnecessary comments and prints. 5. op_state_str() replace with common function. 6. Removed some unnecessary checks from apmppc.c file. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions USB/ppc4xx: Add Synopsys DesignWare HS USB OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/usb/Kconfig |2 + drivers/usb/Makefile |1 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 + drivers/usb/dwc/apmppc.c | 355 ++ drivers/usb/dwc/cil.c | 890 + drivers/usb/dwc/cil.h | 1174 ++ drivers/usb/dwc/cil_intr.c| 616 + drivers/usb/dwc/driver.h | 76 ++ drivers/usb/dwc/hcd.c | 2471 + drivers/usb/dwc/hcd.h | 416 +++ drivers/usb/dwc/hcd_intr.c| 1477 ++ drivers/usb/dwc/hcd_queue.c | 696 +++ drivers/usb/dwc/param.c | 180 +++ drivers/usb/dwc/pcd.c | 1791 +++ drivers/usb/dwc/pcd.h | 139 +++ drivers/usb/dwc/pcd_intr.c| 2312 ++ drivers/usb/dwc/regs.h| 1326 drivers/usb/gadget/Kconfig| 10 + drivers/usb/gadget/gadget_chips.h |3 + 20 files changed, 14038 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile create mode 100644 drivers/usb/dwc/apmppc.c create mode 100644 drivers/usb/dwc/cil.c create mode 100644 drivers/usb/dwc/cil.h create mode 100644 drivers/usb/dwc/cil_intr.c create mode 100644 drivers/usb/dwc/driver.h create mode 100644 drivers/usb/dwc/hcd.c create mode 100644 drivers/usb/dwc/hcd.h create mode 100644 drivers/usb/dwc/hcd_intr.c create mode 100644 drivers/usb/dwc/hcd_queue.c create mode 100644 drivers/usb/dwc/param.c create mode 100644 drivers/usb/dwc/pcd.c create mode 100644 drivers/usb/dwc/pcd.h create mode 100644 drivers/usb/dwc/pcd_intr.c create mode 100644 drivers/usb/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v15 01/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions
From: Tirumala Marri tma...@apm.com Control and Status Register (CSR) are classified as follows: - Core Global Registers - Device Mode Registers - Device Global Registers - Device Endpoint Specific Registers - Host Mode Registers - Host Global Registers - Host Port CSRs - Host Channel Specific Registers Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/regs.h diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#define
[PATCH v15 02/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in apmppc.c.
Driver parameter and parameter checking are in param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/apmppc.c | 355 ++
drivers/usb/dwc/driver.h | 76 ++
drivers/usb/dwc/param.c | 180 +++
3 files changed, 611 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/apmppc.c
create mode 100644 drivers/usb/dwc/driver.h
create mode 100644 drivers/usb/dwc/param.c
diff --git a/drivers/usb/dwc/apmppc.c b/drivers/usb/dwc/apmppc.c
new file mode 100644
index 000..d373c4c
--- /dev/null
+++ b/drivers/usb/dwc/apmppc.c
@@ -0,0 +1,355 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+ struct dwc_hcd *dwc_hcd;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ spin_unlock(dwc_hcd-lock);
+ return IRQ_RETVAL(retval);
+}
+
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_reg_write(dwc_dev-core_if-host_if-hprt0, 0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int __devexit dwc_otg_driver_remove(struct platform_device *ofdev)
+{
+ struct device *dev =
[PATCH v15 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_intr.c
diff --git a/drivers/usb/dwc/hcd_intr.c b/drivers/usb/dwc/hcd_intr.c
new file mode 100644
index 000..b16934d
--- /dev/null
+++ b/drivers/usb/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_reg_read(hcd-core_if-host_if-host_global_regs,
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_reg_write(gintsts_reg(hcd), 0, gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_reg_read(hcd-core_if-core_global_regs, DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host
[PATCH v15 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_queue.c
diff --git a/drivers/usb/dwc/hcd_queue.c b/drivers/usb/dwc/hcd_queue.c
new file mode 100644
index 000..67f0409
--- /dev/null
+++ b/drivers/usb/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH v15 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/pcd.c | 1791 +
drivers/usb/dwc/pcd.h | 139
2 files changed, 1930 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/pcd.c
create mode 100644 drivers/usb/dwc/pcd.h
diff --git a/drivers/usb/dwc/pcd.c b/drivers/usb/dwc/pcd.c
new file mode 100644
index 000..155b730
--- /dev/null
+++ b/drivers/usb/dwc/pcd.c
@@ -0,0 +1,1791 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2)
[PATCH v15 09/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/Kconfig |2 + drivers/usb/Makefile |1 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 ++ 4 files changed, 106 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 48f1781..a584cec 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -120,6 +120,8 @@ source drivers/usb/musb/Kconfig source drivers/usb/renesas_usbhs/Kconfig +source drivers/usb/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 30ddf8d..a2daf43 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -50,4 +50,5 @@ obj-$(CONFIG_USB_SPEEDTOUCH) += atm/ obj-$(CONFIG_USB_MUSB_HDRC)+= musb/ obj-$(CONFIG_USB_RENESAS_USBHS)+= renesas_usbhs/ obj-$(CONFIG_USB_OTG_UTILS)+= otg/ +obj-$(CONFIG_USB_DWC_OTG) += dwc/ obj-$(CONFIG_USB_GADGET) += gadget/ diff --git a/drivers/usb/dwc/Kconfig b/drivers/usb/dwc/Kconfig new file mode 100644 index 000..eafc5ed --- /dev/null +++ b/drivers/usb/dwc/Kconfig @@ -0,0 +1,84 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc/Makefile b/drivers/usb/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v15 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 10 ++ drivers/usb/gadget/gadget_chips.h |3 +++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5a084b9..4908164 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -316,6 +316,16 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_M66592 tristate Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f3a83cd..cbf2ce7 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -49,6 +49,7 @@ #define gadget_is_s3c2410(g) (!strcmp(s3c2410_udc, (g)-name)) #define gadget_is_s3c_hsotg(g) (!strcmp(s3c-hsotg, (g)-name)) #define gadget_is_s3c_hsudc(g) (!strcmp(s3c-hsudc, (g)-name)) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) /** * usb_gadget_controller_number - support bcdDevice id convention @@ -115,6 +116,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x30; else if (gadget_is_net2272(gadget)) return 0x31; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x32; return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v14 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v14: 1. Modifying dwc_reg_read/write functions to accepts offset as arg. 2. Adding spin_lock to common interrupt function. 3. Adding start/stop, vbus_power functions to gadget_opst struct. 4. Removed some unnecessary comments and prints. 5. op_state_str() replace with common function. 6. Removed some unnecessary checks from apmppc.c file. v13: 1. Remove redundant CONFIG VARIABLE from drivers/usb/dwc/Kconfig. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions USB/ppc4xx: Add Synopsys DesignWare HS USB OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/usb/Kconfig |2 + drivers/usb/Makefile |1 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 + drivers/usb/dwc/apmppc.c | 353 ++ drivers/usb/dwc/cil.c | 889 + drivers/usb/dwc/cil.h | 1174 ++ drivers/usb/dwc/cil_intr.c| 616 + drivers/usb/dwc/driver.h | 76 ++ drivers/usb/dwc/hcd.c | 2465 + drivers/usb/dwc/hcd.h | 416 +++ drivers/usb/dwc/hcd_intr.c| 1477 ++ drivers/usb/dwc/hcd_queue.c | 696 +++ drivers/usb/dwc/param.c | 180 +++ drivers/usb/dwc/pcd.c | 1791 +++ drivers/usb/dwc/pcd.h | 139 +++ drivers/usb/dwc/pcd_intr.c| 2311 ++ drivers/usb/dwc/regs.h| 1326 drivers/usb/gadget/Kconfig| 11 + drivers/usb/gadget/gadget_chips.h |3 + 20 files changed, 14029 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile create mode 100644 drivers/usb/dwc/apmppc.c create mode 100644 drivers/usb/dwc/cil.c create mode 100644 drivers/usb/dwc/cil.h create mode 100644 drivers/usb/dwc/cil_intr.c create mode 100644 drivers/usb/dwc/driver.h create mode 100644 drivers/usb/dwc/hcd.c create mode 100644 drivers/usb/dwc/hcd.h create mode 100644 drivers/usb/dwc/hcd_intr.c create mode 100644 drivers/usb/dwc/hcd_queue.c create mode 100644 drivers/usb/dwc/param.c create mode 100644 drivers/usb/dwc/pcd.c create mode 100644 drivers/usb/dwc/pcd.h create mode 100644 drivers/usb/dwc/pcd_intr.c create mode 100644 drivers/usb/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v14 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/Makefile |1 + drivers/usb/gadget/Kconfig| 11 +++ drivers/usb/gadget/gadget_chips.h |3 +++ 3 files changed, 15 insertions(+), 0 deletions(-) diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 30ddf8d..a2daf43 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -50,4 +50,5 @@ obj-$(CONFIG_USB_SPEEDTOUCH) += atm/ obj-$(CONFIG_USB_MUSB_HDRC)+= musb/ obj-$(CONFIG_USB_RENESAS_USBHS)+= renesas_usbhs/ obj-$(CONFIG_USB_OTG_UTILS)+= otg/ +obj-$(CONFIG_USB_DWC_OTG) += dwc/ obj-$(CONFIG_USB_GADGET) += gadget/ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5a084b9..5f1f89f 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -316,6 +316,17 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_M66592 tristate Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f3a83cd..cbf2ce7 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -49,6 +49,7 @@ #define gadget_is_s3c2410(g) (!strcmp(s3c2410_udc, (g)-name)) #define gadget_is_s3c_hsotg(g) (!strcmp(s3c-hsotg, (g)-name)) #define gadget_is_s3c_hsudc(g) (!strcmp(s3c-hsudc, (g)-name)) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) /** * usb_gadget_controller_number - support bcdDevice id convention @@ -115,6 +116,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x30; else if (gadget_is_net2272(gadget)) return 0x31; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x32; return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v14 09/10] Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 ++ 3 files changed, 105 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 48f1781..a584cec 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -120,6 +120,8 @@ source drivers/usb/musb/Kconfig source drivers/usb/renesas_usbhs/Kconfig +source drivers/usb/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc/Kconfig b/drivers/usb/dwc/Kconfig new file mode 100644 index 000..eafc5ed --- /dev/null +++ b/drivers/usb/dwc/Kconfig @@ -0,0 +1,84 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc/Makefile b/drivers/usb/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v14 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_queue.c
diff --git a/drivers/usb/dwc/hcd_queue.c b/drivers/usb/dwc/hcd_queue.c
new file mode 100644
index 000..67f0409
--- /dev/null
+++ b/drivers/usb/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH v14 02/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in apmppc.c.
Driver parameter and parameter checking are in param.c.
Signed-off-by: Tirumala R Marritma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/apmppc.c | 353 ++
drivers/usb/dwc/driver.h | 76 ++
drivers/usb/dwc/param.c | 180 +++
3 files changed, 609 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/apmppc.c
create mode 100644 drivers/usb/dwc/driver.h
create mode 100644 drivers/usb/dwc/param.c
diff --git a/drivers/usb/dwc/apmppc.c b/drivers/usb/dwc/apmppc.c
new file mode 100644
index 000..5053c6a
--- /dev/null
+++ b/drivers/usb/dwc/apmppc.c
@@ -0,0 +1,353 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+ struct dwc_hcd *dwc_hcd;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ spin_unlock(dwc_hcd-lock);
+ return IRQ_RETVAL(retval);
+}
+
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_reg_write(dwc_dev-core_if-host_if-hprt0, 0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int __devexit dwc_otg_driver_remove(struct platform_device *ofdev)
+{
+ struct device *dev =
[PATCH v14 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/pcd.c | 1791 +
drivers/usb/dwc/pcd.h | 139
2 files changed, 1930 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/pcd.c
create mode 100644 drivers/usb/dwc/pcd.h
diff --git a/drivers/usb/dwc/pcd.c b/drivers/usb/dwc/pcd.c
new file mode 100644
index 000..eba5030
--- /dev/null
+++ b/drivers/usb/dwc/pcd.c
@@ -0,0 +1,1791 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2)
[PATCH v14 01/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions
From: Tirumala Marri tma...@apm.com Control and Status Register (CSR) are classified as follows: - Core Global Registers - Device Mode Registers - Device Global Registers - Device Endpoint Specific Registers - Host Mode Registers - Host Global Registers - Host Port CSRs - Host Channel Specific Registers Signed-off-by: Tirumala R Marritma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/regs.h diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#define
[PATCH v13 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v13: 1. Remove redundant CONFIG VARIABLE from drivers/usb/dwc/Kconfig. v12: 1. dwc directory moved from otg to usb directory. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 + drivers/usb/dwc/apmppc.c | 414 +++ drivers/usb/dwc/cil.c | 972 +++ drivers/usb/dwc/cil.h | 1177 ++ drivers/usb/dwc/cil_intr.c| 616 + drivers/usb/dwc/driver.h | 76 ++ drivers/usb/dwc/hcd.c | 2465 + drivers/usb/dwc/hcd.h | 416 +++ drivers/usb/dwc/hcd_intr.c| 1477 ++ drivers/usb/dwc/hcd_queue.c | 696 +++ drivers/usb/dwc/param.c | 180 +++ drivers/usb/dwc/pcd.c | 1766 ++ drivers/usb/dwc/pcd.h | 139 +++ drivers/usb/dwc/pcd_intr.c| 2311 ++ drivers/usb/dwc/regs.h| 1326 drivers/usb/gadget/Kconfig| 11 + drivers/usb/gadget/gadget_chips.h |9 + 20 files changed, 14157 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile create mode 100644 drivers/usb/dwc/apmppc.c create mode 100644 drivers/usb/dwc/cil.c create mode 100644 drivers/usb/dwc/cil.h create mode 100644 drivers/usb/dwc/cil_intr.c create mode 100644 drivers/usb/dwc/driver.h create mode 100644 drivers/usb/dwc/hcd.c create mode 100644 drivers/usb/dwc/hcd.h create mode 100644 drivers/usb/dwc/hcd_intr.c create mode 100644 drivers/usb/dwc/hcd_queue.c create mode 100644 drivers/usb/dwc/param.c create mode 100644 drivers/usb/dwc/pcd.c create mode 100644 drivers/usb/dwc/pcd.h create mode 100644 drivers/usb/dwc/pcd_intr.c create mode 100644 drivers/usb/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v13 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/regs.h diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
[PATCH v13 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/apmppc.c | 414 ++
drivers/usb/dwc/driver.h | 76 +
drivers/usb/dwc/param.c | 180
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/apmppc.c
create mode 100644 drivers/usb/dwc/driver.h
create mode 100644 drivers/usb/dwc/param.c
diff --git a/drivers/usb/dwc/apmppc.c b/drivers/usb/dwc/apmppc.c
new file mode 100644
index 000..ffbe6dd
--- /dev/null
+++ b/drivers/usb/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return
[PATCH v13 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_intr.c
diff --git a/drivers/usb/dwc/hcd_intr.c b/drivers/usb/dwc/hcd_intr.c
new file mode 100644
index 000..26079a6
--- /dev/null
+++ b/drivers/usb/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32(hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32(hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+
[PATCH v13 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_queue.c
diff --git a/drivers/usb/dwc/hcd_queue.c b/drivers/usb/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH v13 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/pcd.c | 1766 +
drivers/usb/dwc/pcd.h | 139
2 files changed, 1905 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/pcd.c
create mode 100644 drivers/usb/dwc/pcd.h
diff --git a/drivers/usb/dwc/pcd.c b/drivers/usb/dwc/pcd.c
new file mode 100644
index 000..04a0a4a
--- /dev/null
+++ b/drivers/usb/dwc/pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2)
[PATCH v13 09/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 84 ++ drivers/usb/dwc/Makefile | 19 ++ 4 files changed, 106 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a125e0b..d4133a6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..1daed15 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -115,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc/Kconfig b/drivers/usb/dwc/Kconfig new file mode 100644 index 000..eafc5ed --- /dev/null +++ b/drivers/usb/dwc/Kconfig @@ -0,0 +1,84 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc/Makefile b/drivers/usb/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v13 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 11 +++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bc5123c..b641c0a 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,17 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v11 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v11: 1. Kconfig corrections. 2. Changed the order of patch generation to follow dependencies. v10: 1. Change address argument type from u32 to ulong to make it arch independent. 2. Cleaning unnecessary changes from Kconfig. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/gadget/Kconfig| 11 + drivers/usb/gadget/gadget_chips.h |9 + drivers/usb/otg/dwc/Kconfig | 88 ++ drivers/usb/otg/dwc/Makefile | 19 + drivers/usb/otg/dwc/apmppc.c | 414 +++ drivers/usb/otg/dwc/cil.c | 972 +++ drivers/usb/otg/dwc/cil.h | 1177 ++ drivers/usb/otg/dwc/cil_intr.c| 616 + drivers/usb/otg/dwc/driver.h | 76 ++ drivers/usb/otg/dwc/hcd.c | 2465 + drivers/usb/otg/dwc/hcd.h | 416 +++ drivers/usb/otg/dwc/hcd_intr.c| 1477 ++ drivers/usb/otg/dwc/hcd_queue.c | 696 +++ drivers/usb/otg/dwc/param.c | 180 +++ drivers/usb/otg/dwc/pcd.c | 1766 ++ drivers/usb/otg/dwc/pcd.h | 139 +++ drivers/usb/otg/dwc/pcd_intr.c| 2311 ++ drivers/usb/otg/dwc/regs.h| 1326 20 files changed, 14161 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile create mode 100644 drivers/usb/otg/dwc/apmppc.c create mode 100644 drivers/usb/otg/dwc/cil.c create mode 100644 drivers/usb/otg/dwc/cil.h create mode 100644 drivers/usb/otg/dwc/cil_intr.c create mode 100644 drivers/usb/otg/dwc/driver.h create mode 100644 drivers/usb/otg/dwc/hcd.c create mode 100644 drivers/usb/otg/dwc/hcd.h create mode 100644 drivers/usb/otg/dwc/hcd_intr.c create mode 100644 drivers/usb/otg/dwc/hcd_queue.c create mode 100644 drivers/usb/otg/dwc/param.c create mode 100644 drivers/usb/otg/dwc/pcd.c create mode 100644 drivers/usb/otg/dwc/pcd.h create mode 100644 drivers/usb/otg/dwc/pcd_intr.c create mode 100644 drivers/usb/otg/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v11 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/otg/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/regs.h diff --git a/drivers/usb/otg/dwc/regs.h b/drivers/usb/otg/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/otg/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY
[PATCH v11 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/apmppc.c | 414 ++
drivers/usb/otg/dwc/driver.h | 76
drivers/usb/otg/dwc/param.c | 180 ++
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/apmppc.c
create mode 100644 drivers/usb/otg/dwc/driver.h
create mode 100644 drivers/usb/otg/dwc/param.c
diff --git a/drivers/usb/otg/dwc/apmppc.c b/drivers/usb/otg/dwc/apmppc.c
new file mode 100644
index 000..ffbe6dd
--- /dev/null
+++ b/drivers/usb/otg/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
[PATCH v11 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_intr.c
diff --git a/drivers/usb/otg/dwc/hcd_intr.c b/drivers/usb/otg/dwc/hcd_intr.c
new file mode 100644
index 000..26079a6
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32(hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32(hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the
[PATCH v11 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/pcd.c | 1766 +
drivers/usb/otg/dwc/pcd.h | 139
2 files changed, 1905 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/pcd.c
create mode 100644 drivers/usb/otg/dwc/pcd.h
diff --git a/drivers/usb/otg/dwc/pcd.c b/drivers/usb/otg/dwc/pcd.c
new file mode 100644
index 000..04a0a4a
--- /dev/null
+++ b/drivers/usb/otg/dwc/pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+
[PATCH v11 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_queue.c
diff --git a/drivers/usb/otg/dwc/hcd_queue.c b/drivers/usb/otg/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
[PATCH v11 09/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/otg/dwc/Kconfig | 88 ++ drivers/usb/otg/dwc/Makefile | 19 + 4 files changed, 110 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a125e0b..500e08f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/otg/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..28b4c54 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -115,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/otg/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/otg/dwc/Kconfig b/drivers/usb/otg/dwc/Kconfig new file mode 100644 index 000..a8f22cb --- /dev/null +++ b/drivers/usb/otg/dwc/Kconfig @@ -0,0 +1,88 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/otg/dwc/Makefile b/drivers/usb/otg/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/otg/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v11 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 11 +++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bc5123c..02eb5d5 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,17 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../otg/dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v12 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v12: 1. dwc directory moved from otg to usb directory. v11: 1. Kconfig corrections. 2. Changed the order of patch generation to follow dependencies. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile USB/ppc4xx:Synopsys DWC OTG driver enable gadget support drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 88 ++ drivers/usb/dwc/Makefile | 19 + drivers/usb/dwc/apmppc.c | 414 +++ drivers/usb/dwc/cil.c | 972 +++ drivers/usb/dwc/cil.h | 1177 ++ drivers/usb/dwc/cil_intr.c| 616 + drivers/usb/dwc/driver.h | 76 ++ drivers/usb/dwc/hcd.c | 2465 + drivers/usb/dwc/hcd.h | 416 +++ drivers/usb/dwc/hcd_intr.c| 1477 ++ drivers/usb/dwc/hcd_queue.c | 696 +++ drivers/usb/dwc/param.c | 180 +++ drivers/usb/dwc/pcd.c | 1766 ++ drivers/usb/dwc/pcd.h | 139 +++ drivers/usb/dwc/pcd_intr.c| 2311 ++ drivers/usb/dwc/regs.h| 1326 drivers/usb/gadget/Kconfig| 11 + drivers/usb/gadget/gadget_chips.h |9 + 20 files changed, 14161 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile create mode 100644 drivers/usb/dwc/apmppc.c create mode 100644 drivers/usb/dwc/cil.c create mode 100644 drivers/usb/dwc/cil.h create mode 100644 drivers/usb/dwc/cil_intr.c create mode 100644 drivers/usb/dwc/driver.h create mode 100644 drivers/usb/dwc/hcd.c create mode 100644 drivers/usb/dwc/hcd.h create mode 100644 drivers/usb/dwc/hcd_intr.c create mode 100644 drivers/usb/dwc/hcd_queue.c create mode 100644 drivers/usb/dwc/param.c create mode 100644 drivers/usb/dwc/pcd.c create mode 100644 drivers/usb/dwc/pcd.h create mode 100644 drivers/usb/dwc/pcd_intr.c create mode 100644 drivers/usb/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v12 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/regs.h diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
[PATCH v12 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/apmppc.c | 414 ++
drivers/usb/dwc/driver.h | 76 +
drivers/usb/dwc/param.c | 180
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/apmppc.c
create mode 100644 drivers/usb/dwc/driver.h
create mode 100644 drivers/usb/dwc/param.c
diff --git a/drivers/usb/dwc/apmppc.c b/drivers/usb/dwc/apmppc.c
new file mode 100644
index 000..ffbe6dd
--- /dev/null
+++ b/drivers/usb/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return
[PATCH v12 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_intr.c
diff --git a/drivers/usb/dwc/hcd_intr.c b/drivers/usb/dwc/hcd_intr.c
new file mode 100644
index 000..26079a6
--- /dev/null
+++ b/drivers/usb/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32(hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32(hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+
[PATCH v12 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/hcd_queue.c
diff --git a/drivers/usb/dwc/hcd_queue.c b/drivers/usb/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH v12 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc/pcd.c | 1766 +
drivers/usb/dwc/pcd.h | 139
2 files changed, 1905 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc/pcd.c
create mode 100644 drivers/usb/dwc/pcd.h
diff --git a/drivers/usb/dwc/pcd.c b/drivers/usb/dwc/pcd.c
new file mode 100644
index 000..04a0a4a
--- /dev/null
+++ b/drivers/usb/dwc/pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2)
[PATCH v12 09/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/dwc/Kconfig | 88 ++ drivers/usb/dwc/Makefile | 19 ++ 4 files changed, 110 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/dwc/Kconfig create mode 100644 drivers/usb/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a125e0b..d4133a6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..1daed15 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -115,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc/Kconfig b/drivers/usb/dwc/Kconfig new file mode 100644 index 000..a8f22cb --- /dev/null +++ b/drivers/usb/dwc/Kconfig @@ -0,0 +1,88 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc/Makefile b/drivers/usb/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v12 10/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 11 +++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bc5123c..b641c0a 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,17 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP which has host and device + modes. + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v10: 1. Change address argument type from u32 to ulong to make it arch independent. 2. Cleaning un-necasary changes from Kconfig. v9: 1. Move the source under usb/otg/dwc. 2. Rename the source files with out dwc_otg prefix. 3. Remove unused read/write modify functions. 4. Including changes related to register base print. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/gadget/Kconfig| 22 + drivers/usb/gadget/gadget_chips.h |9 + drivers/usb/otg/dwc/Kconfig | 88 ++ drivers/usb/otg/dwc/Makefile | 19 + drivers/usb/otg/dwc/apmppc.c | 414 +++ drivers/usb/otg/dwc/cil.c | 972 +++ drivers/usb/otg/dwc/cil.h | 1177 ++ drivers/usb/otg/dwc/cil_intr.c| 616 + drivers/usb/otg/dwc/driver.h | 76 ++ drivers/usb/otg/dwc/hcd.c | 2465 + drivers/usb/otg/dwc/hcd.h | 416 +++ drivers/usb/otg/dwc/hcd_intr.c| 1477 ++ drivers/usb/otg/dwc/hcd_queue.c | 696 +++ drivers/usb/otg/dwc/param.c | 180 +++ drivers/usb/otg/dwc/pcd.c | 1766 ++ drivers/usb/otg/dwc/pcd.h | 139 +++ drivers/usb/otg/dwc/pcd_intr.c| 2311 ++ drivers/usb/otg/dwc/regs.h| 1326 20 files changed, 14172 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile create mode 100644 drivers/usb/otg/dwc/apmppc.c create mode 100644 drivers/usb/otg/dwc/cil.c create mode 100644 drivers/usb/otg/dwc/cil.h create mode 100644 drivers/usb/otg/dwc/cil_intr.c create mode 100644 drivers/usb/otg/dwc/driver.h create mode 100644 drivers/usb/otg/dwc/hcd.c create mode 100644 drivers/usb/otg/dwc/hcd.h create mode 100644 drivers/usb/otg/dwc/hcd_intr.c create mode 100644 drivers/usb/otg/dwc/hcd_queue.c create mode 100644 drivers/usb/otg/dwc/param.c create mode 100644 drivers/usb/otg/dwc/pcd.c create mode 100644 drivers/usb/otg/dwc/pcd.h create mode 100644 drivers/usb/otg/dwc/pcd_intr.c create mode 100644 drivers/usb/otg/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bc5123c..61aca75 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |1 + drivers/usb/Kconfig |2 + drivers/usb/otg/dwc/Kconfig | 88 ++ drivers/usb/otg/dwc/Makefile | 19 + 4 files changed, 110 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index a125e0b..500e08f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/otg/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..28b4c54 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -115,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/otg/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/otg/dwc/Kconfig b/drivers/usb/otg/dwc/Kconfig new file mode 100644 index 000..a8f22cb --- /dev/null +++ b/drivers/usb/otg/dwc/Kconfig @@ -0,0 +1,88 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + tristate Synopsys DWC OTG Controller + depends on USB || USB_GADGET + select NOP_USB_XCEIV + select USB_OTG_UTILS + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config DWC_OTG_REG_LE + bool DWC Little Endian Register + depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool DWC FIFO Little Endian + depends on USB_DWC_OTG + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + bool DWC Endpoint Limited Xfer Size + depends on USB_GADGET_DWC_HDRC + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/otg/dwc/Makefile b/drivers/usb/otg/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/otg/dwc/Makefile @@ -0,0 +1,19 @@ +# +# OTG infrastructure and transceiver drivers +# +obj-$(CONFIG_USB_DWC_OTG) += dwc.o + +dwc-objs := cil.o cil_intr.o param.o + +ifeq ($(CONFIG_4xx_SOC),y) +dwc-objs += apmppc.o +endif + +ifneq ($(CONFIG_DWC_DEVICE_ONLY),y) +dwc-objs += hcd.o hcd_intr.o \ + hcd_queue.o +endif + +ifneq ($(CONFIG_DWC_HOST_ONLY),y) +dwc-objs += pcd.o pcd_intr.o +endif -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v10 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_queue.c
diff --git a/drivers/usb/otg/dwc/hcd_queue.c b/drivers/usb/otg/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
[PATCH v10 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/apmppc.c | 414 ++
drivers/usb/otg/dwc/driver.h | 76
drivers/usb/otg/dwc/param.c | 180 ++
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/apmppc.c
create mode 100644 drivers/usb/otg/dwc/driver.h
create mode 100644 drivers/usb/otg/dwc/param.c
diff --git a/drivers/usb/otg/dwc/apmppc.c b/drivers/usb/otg/dwc/apmppc.c
new file mode 100644
index 000..ffbe6dd
--- /dev/null
+++ b/drivers/usb/otg/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
[PATCH v10 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_intr.c
diff --git a/drivers/usb/otg/dwc/hcd_intr.c b/drivers/usb/otg/dwc/hcd_intr.c
new file mode 100644
index 000..26079a6
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32(hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32(hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the
[PATCH v10 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/pcd.c | 1766 +
drivers/usb/otg/dwc/pcd.h | 139
2 files changed, 1905 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/pcd.c
create mode 100644 drivers/usb/otg/dwc/pcd.h
diff --git a/drivers/usb/otg/dwc/pcd.c b/drivers/usb/otg/dwc/pcd.c
new file mode 100644
index 000..04a0a4a
--- /dev/null
+++ b/drivers/usb/otg/dwc/pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+
[PATCH v10 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/otg/dwc/regs.h | 1326 1 files changed, 1326 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/regs.h diff --git a/drivers/usb/otg/dwc/regs.h b/drivers/usb/otg/dwc/regs.h new file mode 100644 index 000..d3694f3 --- /dev/null +++ b/drivers/usb/otg/dwc/regs.h @@ -0,0 +1,1326 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h +/*Bit fields in the Device EP Transfer Size Register is 11 bits */ +#undef DWC_LIMITED_XFER_SIZE +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY
[PATCH V9 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v9: 1. Move the source under usb/otg/dwc. 2. Rename the source files with out dwc_otg prefix. 3. Remove unused read/write modify functions. 4. Including changes related to register base print. v8: 1. Add set_wedge to usb_ep_ops. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/gadget/Kconfig| 22 + drivers/usb/gadget/gadget_chips.h |9 + drivers/usb/otg/dwc/Kconfig | 96 ++ drivers/usb/otg/dwc/Makefile | 19 + drivers/usb/otg/dwc/apmppc.c | 414 +++ drivers/usb/otg/dwc/cil.c | 972 +++ drivers/usb/otg/dwc/cil.h | 1179 ++ drivers/usb/otg/dwc/cil_intr.c| 616 + drivers/usb/otg/dwc/driver.h | 76 ++ drivers/usb/otg/dwc/hcd.c | 2467 + drivers/usb/otg/dwc/hcd.h | 416 +++ drivers/usb/otg/dwc/hcd_intr.c| 1477 ++ drivers/usb/otg/dwc/hcd_queue.c | 696 +++ drivers/usb/otg/dwc/param.c | 180 +++ drivers/usb/otg/dwc/pcd.c | 1765 ++ drivers/usb/otg/dwc/pcd.h | 139 +++ drivers/usb/otg/dwc/pcd_intr.c| 2311 ++ drivers/usb/otg/dwc/regs.h| 1325 20 files changed, 14183 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile create mode 100644 drivers/usb/otg/dwc/apmppc.c create mode 100644 drivers/usb/otg/dwc/cil.c create mode 100644 drivers/usb/otg/dwc/cil.h create mode 100644 drivers/usb/otg/dwc/cil_intr.c create mode 100644 drivers/usb/otg/dwc/driver.h create mode 100644 drivers/usb/otg/dwc/hcd.c create mode 100644 drivers/usb/otg/dwc/hcd.h create mode 100644 drivers/usb/otg/dwc/hcd_intr.c create mode 100644 drivers/usb/otg/dwc/hcd_queue.c create mode 100644 drivers/usb/otg/dwc/param.c create mode 100644 drivers/usb/otg/dwc/pcd.c create mode 100644 drivers/usb/otg/dwc/pcd.h create mode 100644 drivers/usb/otg/dwc/pcd_intr.c create mode 100644 drivers/usb/otg/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/otg/dwc/regs.h | 1325 1 files changed, 1325 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/otg/dwc/regs.h diff --git a/drivers/usb/otg/dwc/regs.h b/drivers/usb/otg/dwc/regs.h new file mode 100644 index 000..bd53bf6 --- /dev/null +++ b/drivers/usb/otg/dwc/regs.h @@ -0,0 +1,1325 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define
[PATCH 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/apmppc.c | 414 ++
drivers/usb/otg/dwc/driver.h | 76
drivers/usb/otg/dwc/param.c | 180 ++
3 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/apmppc.c
create mode 100644 drivers/usb/otg/dwc/driver.h
create mode 100644 drivers/usb/otg/dwc/param.c
diff --git a/drivers/usb/otg/dwc/apmppc.c b/drivers/usb/otg/dwc/apmppc.c
new file mode 100644
index 000..f5cfebd
--- /dev/null
+++ b/drivers/usb/otg/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
[PATCH 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_intr.c
diff --git a/drivers/usb/otg/dwc/hcd_intr.c b/drivers/usb/otg/dwc/hcd_intr.c
new file mode 100644
index 000..978ad80
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32) hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32) hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the
[PATCH 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/hcd_queue.c
diff --git a/drivers/usb/otg/dwc/hcd_queue.c b/drivers/usb/otg/dwc/hcd_queue.c
new file mode 100644
index 000..f188229
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
[PATCH 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/pcd.c | 1765 +
drivers/usb/otg/dwc/pcd.h | 139
2 files changed, 1904 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/otg/dwc/pcd.c
create mode 100644 drivers/usb/otg/dwc/pcd.h
diff --git a/drivers/usb/otg/dwc/pcd.c b/drivers/usb/otg/dwc/pcd.c
new file mode 100644
index 000..5b07d9c
--- /dev/null
+++ b/drivers/usb/otg/dwc/pcd.c
@@ -0,0 +1,1765 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+
[PATCH 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5df8a8d..de7c10b 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/otg/dwc/Kconfig | 96 ++ drivers/usb/otg/dwc/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile diff --git a/drivers/Makefile b/drivers/Makefile index 2cbb4b7..3bfc728 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/otg/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..887f702 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -55,7 +55,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -115,6 +114,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/otg/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/otg/dwc/Kconfig b/drivers/usb/otg/dwc/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/otg/dwc/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/otg/dwc/Makefile
[PATCH V9 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v9: 1. Move the source under usb/otg/dwc. 2. Rename the source files with out dwc_otg prefix. 3. Remove unused read/write modify functions. 4. Including changes related to register base print. v8: 1. Add set_wedge to usb_ep_ops. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/gadget/Kconfig| 22 + drivers/usb/gadget/gadget_chips.h |9 + drivers/usb/otg/dwc/Kconfig | 96 ++ drivers/usb/otg/dwc/Makefile | 19 + drivers/usb/otg/dwc/apmppc.c | 414 +++ drivers/usb/otg/dwc/cil.c | 972 +++ drivers/usb/otg/dwc/cil.h | 1179 ++ drivers/usb/otg/dwc/cil_intr.c| 616 + drivers/usb/otg/dwc/driver.h | 76 ++ drivers/usb/otg/dwc/hcd.c | 2467 + drivers/usb/otg/dwc/hcd.h | 416 +++ drivers/usb/otg/dwc/hcd_intr.c| 1477 ++ drivers/usb/otg/dwc/hcd_queue.c | 696 +++ drivers/usb/otg/dwc/param.c | 180 +++ drivers/usb/otg/dwc/pcd.c | 1765 ++ drivers/usb/otg/dwc/pcd.h | 139 +++ drivers/usb/otg/dwc/pcd_intr.c| 2311 ++ drivers/usb/otg/dwc/regs.h| 1325 20 files changed, 14183 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/otg/dwc/Kconfig create mode 100644 drivers/usb/otg/dwc/Makefile create mode 100644 drivers/usb/otg/dwc/apmppc.c create mode 100644 drivers/usb/otg/dwc/cil.c create mode 100644 drivers/usb/otg/dwc/cil.h create mode 100644 drivers/usb/otg/dwc/cil_intr.c create mode 100644 drivers/usb/otg/dwc/driver.h create mode 100644 drivers/usb/otg/dwc/hcd.c create mode 100644 drivers/usb/otg/dwc/hcd.h create mode 100644 drivers/usb/otg/dwc/hcd_intr.c create mode 100644 drivers/usb/otg/dwc/hcd_queue.c create mode 100644 drivers/usb/otg/dwc/param.c create mode 100644 drivers/usb/otg/dwc/pcd.c create mode 100644 drivers/usb/otg/dwc/pcd.h create mode 100644 drivers/usb/otg/dwc/pcd_intr.c create mode 100644 drivers/usb/otg/dwc/regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V9 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/otg/dwc/regs.h | 1325 1 files changed, 1325 insertions(+), 0 deletions(-) diff --git a/drivers/usb/otg/dwc/regs.h b/drivers/usb/otg/dwc/regs.h new file mode 100644 index 000..bd53bf6 --- /dev/null +++ b/drivers/usb/otg/dwc/regs.h @@ -0,0 +1,1325 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define DWC_PTXEMPTYLVL_EMPTY 0x0100 +#define
[PATCH V9 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/apmppc.c | 414 ++
drivers/usb/otg/dwc/driver.h | 76
drivers/usb/otg/dwc/param.c | 180 ++
3 files changed, 670 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/otg/dwc/apmppc.c b/drivers/usb/otg/dwc/apmppc.c
new file mode 100644
index 000..f5cfebd
--- /dev/null
+++ b/drivers/usb/otg/dwc/apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function is called when a device is unregistered with the
+ * dwc_otg_driver. This
[PATCH V9 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/otg/dwc/hcd_intr.c b/drivers/usb/otg/dwc/hcd_intr.c
new file mode 100644
index 000..978ad80
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32) hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32) hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if
[PATCH V9 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/otg/dwc/hcd_queue.c b/drivers/usb/otg/dwc/hcd_queue.c
new file mode 100644
index 000..1f99573
--- /dev/null
+++ b/drivers/usb/otg/dwc/hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+ qh-sched_frame =
[PATCH V9 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/otg/dwc/pcd.c | 1765 +
drivers/usb/otg/dwc/pcd.h | 139
2 files changed, 1904 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/otg/dwc/pcd.c b/drivers/usb/otg/dwc/pcd.c
new file mode 100644
index 000..5b07d9c
--- /dev/null
+++ b/drivers/usb/otg/dwc/pcd.c
@@ -0,0 +1,1765 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
+
[PATCH V9 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5df8a8d..de7c10b 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e896f63..d1fab43 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -136,6 +136,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V9 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/otg/dwc/Kconfig | 96 ++ drivers/usb/otg/dwc/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 2cbb4b7..3bfc728 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ obj-$(CONFIG_TC) += tc/ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ +obj-$(CONFIG_USB_DWC_OTG) += usb/otg/dwc/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ obj-$(CONFIG_PCI) += usb/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 41b6e51..887f702 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -55,7 +55,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -115,6 +114,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/otg/dwc/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/otg/dwc/Kconfig b/drivers/usb/otg/dwc/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/otg/dwc/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/otg/dwc/Makefile b/drivers/usb/otg/dwc/Makefile new file mode 100644 index 000..4102add --- /dev/null +++ b/drivers/usb/otg/dwc/Makefile
[PATCH V8 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc_otg/dwc_otg_regs.h | 1325 1 files changed, 1325 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 000..bd53bf6 --- /dev/null +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,1325 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define DWC_PTXEMPTYLVL_EMPTY
[PATCH V8 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 414 ++
drivers/usb/dwc_otg/dwc_otg_driver.h | 76 ++
drivers/usb/dwc_otg/dwc_otg_param.c | 180 +++
3 files changed, 670 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c
b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 000..d925548
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include dwc_otg_driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function is called when a device is
[PATCH V8 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000..027635d
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include dwc_otg_hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32) hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32) hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host
[PATCH V8 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000..a083a54
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include dwc_otg_hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH V8 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1766 +
drivers/usb/dwc_otg/dwc_otg_pcd.h | 139 +++
2 files changed, 1905 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c
b/drivers/usb/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000..79c63c4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include dwc_otg_pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+
[PATCH V8 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 1dc9739..ab7d210 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5c2720d..7a7623a 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -142,6 +142,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -215,6 +221,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V8 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 2cbb4b7..9a9aa05 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SERIO)+= input/serio/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index fceea5e..fa8b879 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -56,7 +56,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -116,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc_otg/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile new file mode 100644 index 000..31dd5e8 --- /dev/null +++
[PATCH V7 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v7: 1. Fix sparse tool warnings. 2. Fix checkpatch errors and warnings. 3. Rename USB_OTG config variable to USB_DWC_CONFIG v6: 1. Replaced register definitions and bit fields with macros. 2. Replace printks with dev_dbg or dev_err functions. 3. Cleanup some assignments. 4. Remove chip specific selections in Kconfig file. Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile|2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile| 19 + drivers/usb/dwc_otg/dwc_otg_apmppc.c| 414 ++ drivers/usb/dwc_otg/dwc_otg_cil.c | 972 drivers/usb/dwc_otg/dwc_otg_cil.h | 1219 +++ drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 616 drivers/usb/dwc_otg/dwc_otg_driver.h| 76 + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2466 +++ drivers/usb/dwc_otg/dwc_otg_hcd.h | 416 ++ drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1477 ++ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 696 + drivers/usb/dwc_otg/dwc_otg_param.c | 180 +++ drivers/usb/dwc_otg/dwc_otg_pcd.c | 1752 ++ drivers/usb/dwc_otg/dwc_otg_pcd.h | 139 ++ drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2311 + drivers/usb/dwc_otg/dwc_otg_regs.h | 1325 + drivers/usb/gadget/Kconfig | 22 + drivers/usb/gadget/gadget_chips.h |9 + 20 files changed, 14209 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V7 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc_otg/dwc_otg_regs.h | 1325 1 files changed, 1325 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 000..bd53bf6 --- /dev/null +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,1325 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define DWC_PTXEMPTYLVL_EMPTY
[PATCH V7 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000..027635d
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include dwc_otg_hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32) hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32) hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host
[PATCH V7 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 414 ++
drivers/usb/dwc_otg/dwc_otg_driver.h | 76 ++
drivers/usb/dwc_otg/dwc_otg_param.c | 180 +++
3 files changed, 670 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c
b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 000..d925548
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include dwc_otg_driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function is called when a device is
[PATCH V7 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000..a083a54
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include dwc_otg_hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH V7 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1752 +
drivers/usb/dwc_otg/dwc_otg_pcd.h | 139 +++
2 files changed, 1891 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c
b/drivers/usb/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000..857dcee
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
@@ -0,0 +1,1752 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include dwc_otg_pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+
[PATCH V7 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 1dc9739..ab7d210 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5c2720d..7a7623a 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -142,6 +142,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -215,6 +221,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V7 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 2cbb4b7..9a9aa05 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SERIO)+= input/serio/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index fceea5e..fa8b879 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -56,7 +56,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -116,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc_otg/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile new file mode 100644 index 000..31dd5e8 --- /dev/null +++
[PATCH V6 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v6: 1. Replaced register definitions and bit fields with macros. 2. Replace printks with dev_dbg or dev_err functions. 3. Cleanup some assignments. 4. Remove chip specific selections in Kconfig file. v5: 1. PATCH V5 has a new license header from Synopsys and APM Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile|2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile| 19 + drivers/usb/dwc_otg/dwc_otg_apmppc.c| 413 ++ drivers/usb/dwc_otg/dwc_otg_cil.c | 944 drivers/usb/dwc_otg/dwc_otg_cil.h | 1215 drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 617 drivers/usb/dwc_otg/dwc_otg_driver.h| 78 + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2408 +++ drivers/usb/dwc_otg/dwc_otg_hcd.h | 416 ++ drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1470 +++ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 + drivers/usb/dwc_otg/dwc_otg_param.c | 182 +++ drivers/usb/dwc_otg/dwc_otg_pcd.c | 1736 ++ drivers/usb/dwc_otg/dwc_otg_pcd.h | 138 ++ drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2278 + drivers/usb/dwc_otg/dwc_otg_regs.h | 1313 + drivers/usb/gadget/Kconfig | 22 + drivers/usb/gadget/gadget_chips.h |8 + 20 files changed, 14054 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 00/10] Add-Synopsys-DesignWare-HS-USB-OTG-driver
From: Tirumala Marri tma...@apm.com v6: 1. Replaced register definitions and bit fields with macros. 2. Replace printks with dev_dbg or dev_err functions. 3. Cleanup some assignments. 4. Remove chip specific selections in Kconfig file. v5: 1. PATCH V5 has a new license header from Synopsys and APM Tirumala Marri (10): USB/ppc4xx: Add Synopsys DWC OTG Register definitions USB/ppc4xx: Add Synopsys DWC OTG driver framework USB/ppc4xx: Add Synopsys DWC OTG Core Interface Layer (CIL) USB/ppc4xx: Add Synopsys DWC OTG HCD function USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function USB/ppc4xx: Add Synopsys DWC OTG HCD queue function USB/ppc4xx: Add Synopsys DWC OTG PCD function USB ppc4xx: Add Synopsys DWC OTG PCD interrupt function USB/ppc4xx:Synopsys DWC OTG driver enable gadget support USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile drivers/Makefile|2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile| 19 + drivers/usb/dwc_otg/dwc_otg_apmppc.c| 413 ++ drivers/usb/dwc_otg/dwc_otg_cil.c | 944 drivers/usb/dwc_otg/dwc_otg_cil.h | 1215 drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 617 drivers/usb/dwc_otg/dwc_otg_driver.h| 78 + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2408 +++ drivers/usb/dwc_otg/dwc_otg_hcd.h | 416 ++ drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1470 +++ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 + drivers/usb/dwc_otg/dwc_otg_param.c | 182 +++ drivers/usb/dwc_otg/dwc_otg_pcd.c | 1736 ++ drivers/usb/dwc_otg/dwc_otg_pcd.h | 138 ++ drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2278 + drivers/usb/dwc_otg/dwc_otg_regs.h | 1313 + drivers/usb/gadget/Kconfig | 22 + drivers/usb/gadget/gadget_chips.h |8 + 20 files changed, 14054 insertions(+), 1 deletions(-) create mode 100644 drivers/usb/dwc_otg/Kconfig create mode 100644 drivers/usb/dwc_otg/Makefile create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marritma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc_otg/dwc_otg_regs.h | 1313 1 files changed, 1313 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 000..995252a --- /dev/null +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,1313 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1*/ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define DWC_PTXEMPTYLVL_EMPTY
[PATCH V6 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marritma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 413 ++
drivers/usb/dwc_otg/dwc_otg_driver.h | 78 +++
drivers/usb/dwc_otg/dwc_otg_param.c | 182 +++
3 files changed, 673 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c
b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 000..d109ac0
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,413 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include dwc_otg_driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0,
+ hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function
[PATCH V6 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marritma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1470
1 files changed, 1470 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000..ad07fe5
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1470 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include dwc_otg_hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32)hcd-core_if-host_if-host_global_regs +
DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32)hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+
[PATCH V6 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marritma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++
1 files changed, 697 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000..4e190db
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,697 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include dwc_otg_hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type == USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+ qh-sched_frame = dwc_frame_num_inc(hcd-frame_number,
+ SCHEDULE_SLOP);
+
[PATCH V6 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marritma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |8 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 747b0d3..b2bcc4e 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_OTG + help + This OTG-capable Designware USB IP + +config USB_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index d7b3bbe..e008e07 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -142,6 +142,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -207,6 +213,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x26; else if (gadget_is_pch(gadget)) return 0x27; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x28; return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marritma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 14152fc..0ecbf42 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SERIO)+= input/serio/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 6585f0b..8b3623d 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -55,7 +55,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -113,6 +112,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc_otg/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile new file mode 100644 index 000..31dd5e8 --- /dev/null +++
[PATCH] ppc4xx: Add USB DWC DTS entry to Canyonlands board
From: Tirumala Marri tma...@apm.com
Add Synopsys Designware DTS entry for 460EX based Canyonlands board.
Signed-off-by: Tirumala R Marritma...@apm.com
---
arch/powerpc/boot/dts/canyonlands.dts | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index 5b27a4b..54caec6 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -172,6 +172,19 @@
interrupts = 0x1e 4;
};
+ USBOTG0: usb...@bff8 {
+ compatible = amcc,dwc-otg;
+ reg = 0x4 0xbff8 0x1;
+ interrupt-parent = USBOTG0;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupts = 0x0 0x1 0x2;
+ interrupt-map = /* USB-OTG */ 0x0 UIC2 0x1c 0x4
+/* HIGH-POWER */ 0x1 UIC1 0x1a 0x8
+/* DMA */ 0x2 UIC0 0xc 0x4;
+ };
+
SATA0: s...@bffd1000 {
compatible = amcc,sata-460ex;
reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
--
1.6.1.rc3
___
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[PATCH] ppc4xx: Add USB DWC DTS entry to Canyonlands board
From: Tirumala Marri tma...@apm.com
Add Synopsys Designware DTS entry for 460EX based Canyonlands board.
Signed-off-by: Tirumala R Marritma...@apm.com
---
arch/powerpc/boot/dts/canyonlands.dts | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index 5b27a4b..54caec6 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -172,6 +172,19 @@
interrupts = 0x1e 4;
};
+ USBOTG0: usb...@bff8 {
+ compatible = amcc,dwc-otg;
+ reg = 0x4 0xbff8 0x1;
+ interrupt-parent = USBOTG0;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupts = 0x0 0x1 0x2;
+ interrupt-map = /* USB-OTG */ 0x0 UIC2 0x1c 0x4
+/* HIGH-POWER */ 0x1 UIC1 0x1a 0x8
+/* DMA */ 0x2 UIC0 0xc 0x4;
+ };
+
SATA0: s...@bffd1000 {
compatible = amcc,sata-460ex;
reg = 4 0xbffd1000 0x800 4 0xbffd0800 0x400;
--
1.6.1.rc3
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[PATCH v3] PPC4xx: Adding PCI(E) MSI support
From: Tirumala Marri tma...@apm.com
This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
v3:
* Rebased to Josh next tree
* Cleanup and remove some unwanted log msg.
* Remove list member and its references.
* Keep msi_data local reference.
v2:
* Remove or add blank lines at appropriate places.
* Added BITMAP as it is easy to request and free the MSIs
* Removed UPPER_4BITS_OF36BIT LOWER_32BITS_OF36BIT;
* Remove unused feature variable.
* Remove initialization of virq.
* remove static int_no varaible and replace with bitmap.
* Eliminated reading count from DTS tree and added a macro.
* Remove printK.
* Remove else in setup_irqs.
* Free interrupts in teardown_msi_interrupts().
* Print contraints in check_device().
* Replace ioremap with of_iomap().
* Use msi_data in setup_pcieh_hw().
* Don't unmap in the setup_pcieh_hw().
* don't use WARN_ON.
* Remove ppc4xx_msi_ids[].
---
arch/powerpc/boot/dts/canyonlands.dts | 18 ++
arch/powerpc/boot/dts/katmai.dts | 18 ++
arch/powerpc/boot/dts/kilauea.dts | 28 +++
arch/powerpc/boot/dts/redwood.dts | 20 +++
arch/powerpc/platforms/40x/Kconfig|2 +
arch/powerpc/platforms/44x/Kconfig|6 +
arch/powerpc/sysdev/Kconfig |7 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/ppc4xx_msi.c | 291 +
9 files changed, 391 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index 5b27a4b..5142a4a 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -506,5 +506,23 @@
0x0 0x0 0x0 0x3 UIC3 0x12 0x4 /* swizzled int
C */
0x0 0x0 0x0 0x4 UIC3 0x13 0x4 /* swizzled int
D */;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0xC 0x1000 0x100;
+ sdr-base = 0x36C;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts = 0 1 2 3;
+ interrupt-parent = UIC3;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC3 0x18 1
+ 1 UIC3 0x19 1
+ 2 UIC3 0x1A 1
+ 3 UIC3 0x1B 1;
+ };
};
};
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 7c3be5e..f913dbe 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -442,6 +442,24 @@
0x0 0x0 0x0 0x4 UIC3 0xb 0x4 /* swizzled int D
*/;
};
+ MSI: ppc4xx-...@40030 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x4 0x0030 0x100;
+ sdr-base = 0x3B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts =0 1 2 3;
+ interrupt-parent = UIC0;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC0 0xC 1
+ 1 UIC0 0x0D 1
+ 2 UIC0 0x0E 1
+ 3 UIC0 0x0F 1;
+ };
+
I2O: i...@40010 {
compatible = ibm,i2o-440spe;
reg = 0x0004 0x0010 0x100;
diff --git a/arch/powerpc/boot/dts/kilauea.dts
b/arch/powerpc/boot/dts/kilauea.dts
index 89edb16..1613d6e 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -403,5 +403,33 @@
0x0 0x0 0x0 0x3 UIC2 0xd 0x4 /* swizzled int C
*/
0x0 0x0 0x0 0x4 UIC2 0xe 0x4 /* swizzled int D
*/;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x0 0xEF62 0x100;
+ sdr-base = 0x4B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 12;
+ interrupts = 0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD;
+
[PATCH v2] PPC4xx: Adding PCI(E) MSI support
From: Tirumala Marri tma...@apm.com
This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
v1:
* Get rid of bitmap functions.
* Remove irq mapping as each MSI is tied to UIC.
* Cleaning up of prints.
v2:
* Remove or add blank lines at appropriate places.
* Added BITMAP as it is easy to request and free the MSIs
* Removed UPPER_4BITS_OF36BIT LOWER_32BITS_OF36BIT;
* Remove unused feature variable.
* Remove initialization of virq.
* remove static int_no varaible and replace with bitmap.
* Eliminated reading count from DTS tree and added a macro.
* Remove printK.
* Remove else in setup_irqs.
* Free interrupts in teardown_msi_interrupts().
* Print contraints in check_device().
* Replace ioremap with of_iomap().
* Use msi_data in setup_pcieh_hw().
* Don't unmap in the setup_pcieh_hw().
* don't use WARN_ON.
* Remove ppc4xx_msi_ids[].
---
arch/powerpc/boot/dts/canyonlands.dts | 18 ++
arch/powerpc/boot/dts/katmai.dts | 18 ++
arch/powerpc/boot/dts/kilauea.dts | 28 +++
arch/powerpc/boot/dts/redwood.dts | 20 ++
arch/powerpc/platforms/40x/Kconfig|2 +
arch/powerpc/platforms/44x/Kconfig|6 +
arch/powerpc/sysdev/Kconfig |7 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/ppc4xx_msi.c | 311 +
9 files changed, 411 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index a303703..5a8e04e 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -519,5 +519,23 @@
0x0 0x0 0x0 0x3 UIC3 0x12 0x4 /* swizzled int
C */
0x0 0x0 0x0 0x4 UIC3 0x13 0x4 /* swizzled int
D */;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0xC 0x1000 0x100;
+ sdr-base = 0x36C;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts = 0 1 2 3;
+ interrupt-parent = UIC3;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC3 0x18 1
+ 1 UIC3 0x19 1
+ 2 UIC3 0x1A 1
+ 3 UIC3 0x1B 1;
+ };
};
};
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 7c3be5e..f913dbe 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -442,6 +442,24 @@
0x0 0x0 0x0 0x4 UIC3 0xb 0x4 /* swizzled int D
*/;
};
+ MSI: ppc4xx-...@40030 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x4 0x0030 0x100;
+ sdr-base = 0x3B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts =0 1 2 3;
+ interrupt-parent = UIC0;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC0 0xC 1
+ 1 UIC0 0x0D 1
+ 2 UIC0 0x0E 1
+ 3 UIC0 0x0F 1;
+ };
+
I2O: i...@40010 {
compatible = ibm,i2o-440spe;
reg = 0x0004 0x0010 0x100;
diff --git a/arch/powerpc/boot/dts/kilauea.dts
b/arch/powerpc/boot/dts/kilauea.dts
index 083e68e..21e88f5 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -394,5 +394,33 @@
0x0 0x0 0x0 0x3 UIC2 0xd 0x4 /* swizzled int C
*/
0x0 0x0 0x0 0x4 UIC2 0xe 0x4 /* swizzled int D
*/;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x0 0xEF62 0x100;
+ sdr-base = 0x4B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 12;
+ interrupts = 0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD;
+ interrupt-parent =
[PATHC v1] PPC4xx: Adding PCI(E) MSI support
From: Tirumala Marri tma...@apm.com
This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
v1:
* Get rid of bitmap functions.
* Remove irq mapping as each MSI is tied to UIC.
* Cleaning up of prints.
---
arch/powerpc/boot/dts/canyonlands.dts | 18 +++
arch/powerpc/boot/dts/katmai.dts | 18 +++
arch/powerpc/boot/dts/kilauea.dts | 28
arch/powerpc/boot/dts/redwood.dts | 20 +++
arch/powerpc/platforms/40x/Kconfig|2 +
arch/powerpc/platforms/44x/Kconfig|6 +
arch/powerpc/sysdev/Kconfig |6 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/ppc4xx_msi.c | 251 +
9 files changed, 350 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts
b/arch/powerpc/boot/dts/canyonlands.dts
index a303703..5a8e04e 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -519,5 +519,23 @@
0x0 0x0 0x0 0x3 UIC3 0x12 0x4 /* swizzled int
C */
0x0 0x0 0x0 0x4 UIC3 0x13 0x4 /* swizzled int
D */;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0xC 0x1000 0x100;
+ sdr-base = 0x36C;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts = 0 1 2 3;
+ interrupt-parent = UIC3;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC3 0x18 1
+ 1 UIC3 0x19 1
+ 2 UIC3 0x1A 1
+ 3 UIC3 0x1B 1;
+ };
};
};
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 7c3be5e..f913dbe 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -442,6 +442,24 @@
0x0 0x0 0x0 0x4 UIC3 0xb 0x4 /* swizzled int D
*/;
};
+ MSI: ppc4xx-...@40030 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x4 0x0030 0x100;
+ sdr-base = 0x3B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 3;
+ interrupts =0 1 2 3;
+ interrupt-parent = UIC0;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC0 0xC 1
+ 1 UIC0 0x0D 1
+ 2 UIC0 0x0E 1
+ 3 UIC0 0x0F 1;
+ };
+
I2O: i...@40010 {
compatible = ibm,i2o-440spe;
reg = 0x0004 0x0010 0x100;
diff --git a/arch/powerpc/boot/dts/kilauea.dts
b/arch/powerpc/boot/dts/kilauea.dts
index 083e68e..21e88f5 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -394,5 +394,33 @@
0x0 0x0 0x0 0x3 UIC2 0xd 0x4 /* swizzled int C
*/
0x0 0x0 0x0 0x4 UIC2 0xe 0x4 /* swizzled int D
*/;
};
+
+ MSI: ppc4xx-...@c1000 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x0 0xEF62 0x100;
+ sdr-base = 0x4B0;
+ msi-data = 0x;
+ msi-mask = 0x;
+ interrupt-count = 12;
+ interrupts = 0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD;
+ interrupt-parent = UIC2;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC2 0x10 1
+ 1 UIC2 0x11 1
+ 2 UIC2 0x12 1
+ 2 UIC2 0x13 1
+ 2 UIC2 0x14 1
+ 2 UIC2 0x15 1
+ 2 UIC2 0x16 1
+ 2 UIC2 0x17 1
+ 2 UIC2 0x18 1
+ 2 UIC2
[PATCH v1 3/4] PPC4xx: New file with SoC specific functions
From: Tirumala Marri tma...@apm.com
This patch creates new file with SoC dependent functions.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
V1:
* Remove all 440SPe specific references.
* Move some of the code from header file to c file.
---
drivers/dma/ppc4xx/ppc4xx-adma.c | 1658 ++
1 files changed, 1658 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/ppc4xx/ppc4xx-adma.c
diff --git a/drivers/dma/ppc4xx/ppc4xx-adma.c b/drivers/dma/ppc4xx/ppc4xx-adma.c
new file mode 100644
index 000..5a5da23
--- /dev/null
+++ b/drivers/dma/ppc4xx/ppc4xx-adma.c
@@ -0,0 +1,1658 @@
+/*
+ * Copyright (C) 2006-2009 DENX Software Engineering.
+ *
+ * Author: Yuri Tikhonov y...@emcraft.com
+ *
+ * Further porting to arch/powerpc by
+ * Anatolij Gustschin ag...@denx.de
+ * Tirumala R Marri tma...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING.
+ */
+
+/*
+ * This driver supports the asynchrounous DMA copy and RAID engines available
+ * on the AMCC PPC440SPe Processors.
+ * Based on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
+ * ADMA driver written by D.Williams.
+ */
+
+#include linux/of.h
+#include linux/of_platform.h
+#include asm/dcr.h
+#include asm/dcr-regs.h
+#include linux/async_tx.h
+#include linux/dma-mapping.h
+#include linux/slab.h
+#include adma.h
+#if defined(CONFIG_440SPe) || defined(CONFIG_440SP)
+#include ppc440spe-dma.h
+#endif
+#include ppc4xx-adma.h
+
+/* This array is used in data-check operations for storing a pattern */
+static char ppc4xx_qword[16];
+static atomic_t ppc4xx_adma_err_irq_ref;
+static unsigned int ppc4xx_mq_dcr_len;
+
+/* These are used in enable check routines
+ */
+static u32 ppc4xx_r6_enabled;
+static struct completion ppc4xx_r6_test_comp;
+
+static struct page *ppc4xx_rxor_srcs[32];
+
+static dcr_host_t ppc4xx_mq_dcr_host;
+/* Pointer to DMA0, DMA1 CP/CS FIFO */
+static void *ppc4xx_dma_fifo_buf;
+
+static char *ppc_adma_errors[] = {
+ [PPC_ADMA_INIT_OK] = ok,
+ [PPC_ADMA_INIT_MEMRES] = failed to get memory resource,
+ [PPC_ADMA_INIT_MEMREG] = failed to request memory region,
+ [PPC_ADMA_INIT_ALLOC] = failed to allocate memory for adev
+ structure,
+ [PPC_ADMA_INIT_COHERENT] = failed to allocate coherent memory for
+ hardware descriptors,
+ [PPC_ADMA_INIT_CHANNEL] = failed to allocate memory for channel,
+ [PPC_ADMA_INIT_IRQ1] = failed to request first irq,
+ [PPC_ADMA_INIT_IRQ2] = failed to request second irq,
+ [PPC_ADMA_INIT_REGISTER] = failed to register dma async device,
+};
+
+static void ppc4xx_adma_dma2rxor_set_mult(struct ppc4xx_adma_desc_slot *desc,
+ int index, u8 mult);
+static void print_cb_list(struct ppc4xx_adma_chan *chan,
+ struct ppc4xx_adma_desc_slot *iter);
+/**
+ * ppc4xx_can_rxor - check if the operands may be processed with RXOR
+ */
+static int ppc4xx_can_rxor(struct page **srcs, int src_cnt, size_t len)
+{
+ int i, order = 0, state = 0;
+ int idx = 0;
+
+ if (unlikely(!(src_cnt 1)))
+ return 0;
+
+ BUG_ON(src_cnt ARRAY_SIZE(ppc4xx_rxor_srcs));
+
+ /* Skip holes in the source list before checking */
+ for (i = 0; i src_cnt; i++) {
+ if (!srcs[i])
+ continue;
+ ppc4xx_rxor_srcs[idx++] = srcs[i];
+ }
+ src_cnt = idx;
+
+ for (i = 1; i src_cnt; i++) {
+ char *cur_addr = page_address(ppc4xx_rxor_srcs[i]);
+ char *old_addr = page_address(ppc4xx_rxor_srcs[i - 1]);
+
+ switch (state) {
+ case 0:
+ if (cur_addr == old_addr + len) {
+ /* direct RXOR */
+ order = 1;
+ state = 1;
+ } else if (old_addr == cur_addr + len) {
+ /* reverse RXOR */
+ order = -1;
+ state = 1;
+ } else
+ goto out;
+
[PATCH v1 4/4] PPC4xx: Merge files to create single 440spe header
From: Tirumala Marri tma...@apm.com
This patch merges dma.h and xor.h to create ppc440spe-dma.h
Signed-off-by: Tirumala R Marri tma...@apm.com
---
V1:
* No change.
---
drivers/dma/ppc4xx/dma.h | 223 -
drivers/dma/ppc4xx/ppc440spe-dma.h | 318
drivers/dma/ppc4xx/xor.h | 110 -
3 files changed, 318 insertions(+), 333 deletions(-)
delete mode 100644 drivers/dma/ppc4xx/dma.h
create mode 100644 drivers/dma/ppc4xx/ppc440spe-dma.h
delete mode 100644 drivers/dma/ppc4xx/xor.h
diff --git a/drivers/dma/ppc4xx/dma.h b/drivers/dma/ppc4xx/dma.h
deleted file mode 100644
index bcde2df..000
--- a/drivers/dma/ppc4xx/dma.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * 440SPe's DMA engines support header file
- *
- * 2006-2009 (C) DENX Software Engineering.
- *
- * Author: Yuri Tikhonov y...@emcraft.com
- *
- * This file is licensed under the term of the GNU General Public License
- * version 2. The program licensed as is without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef_PPC440SPE_DMA_H
-#define _PPC440SPE_DMA_H
-
-#include linux/types.h
-
-/* Number of elements in the array with statical CDBs */
-#defineMAX_STAT_DMA_CDBS 16
-/* Number of DMA engines available on the contoller */
-#define DMA_ENGINES_NUM2
-
-/* Maximum h/w supported number of destinations */
-#define DMA_DEST_MAX_NUM 2
-
-/* FIFO's params */
-#define DMA0_FIFO_SIZE 0x1000
-#define DMA1_FIFO_SIZE 0x1000
-#define DMA_FIFO_ENABLE(112)
-
-/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
-#define DMA_CFG_DXEPR_LP (026)
-#define DMA_CFG_DXEPR_HP (326)
-#define DMA_CFG_DXEPR_HHP (226)
-#define DMA_CFG_DXEPR_HHHP (126)
-
-/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
-#define DMA_CFG_DFMPP_LP (023)
-#define DMA_CFG_DFMPP_HP (323)
-#define DMA_CFG_DFMPP_HHP (223)
-#define DMA_CFG_DFMPP_HHHP (123)
-
-/* DMA Configuration Register. Force 64-byte Alignment */
-#define DMA_CFG_FALGN (1 19)
-
-/*UIC0:*/
-#define D0CPF_INT (112)
-#define D0CSF_INT (111)
-#define D1CPF_INT (110)
-#define D1CSF_INT (19)
-/*UIC1:*/
-#define DMAE_INT (19)
-
-/* I2O IOP Interrupt Mask Register */
-#define I2O_IOPIM_P0SNE(13)
-#define I2O_IOPIM_P0EM (15)
-#define I2O_IOPIM_P1SNE(16)
-#define I2O_IOPIM_P1EM (18)
-
-/* DMA CDB fields */
-#define DMA_CDB_MSK(0xF)
-#define DMA_CDB_64B_ADDR (12)
-#define DMA_CDB_NO_INT (13)
-#define DMA_CDB_STATUS_MSK (0x3)
-#define DMA_CDB_ADDR_MSK (0xFFF0)
-
-/* DMA CDB OpCodes */
-#define DMA_CDB_OPC_NO_OP (0x00)
-#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
-#define DMA_CDB_OPC_MULTICAST (0x05)
-#define DMA_CDB_OPC_DFILL128 (0x24)
-#define DMA_CDB_OPC_DCHECK128 (0x23)
-
-#define DMA_CUED_XOR_BASE (0x1000)
-#define DMA_CUED_XOR_HB(0x0008)
-
-#ifdef CONFIG_440SP
-#define DMA_CUED_MULT1_OFF 0
-#define DMA_CUED_MULT2_OFF 8
-#define DMA_CUED_MULT3_OFF 16
-#define DMA_CUED_REGION_OFF24
-#define DMA_CUED_XOR_WIN_MSK (0xFC00)
-#else
-#define DMA_CUED_MULT1_OFF 2
-#define DMA_CUED_MULT2_OFF 10
-#define DMA_CUED_MULT3_OFF 18
-#define DMA_CUED_REGION_OFF26
-#define DMA_CUED_XOR_WIN_MSK (0xF000)
-#endif
-
-#define DMA_CUED_REGION_MSK0x3
-#define DMA_RXOR1230x0
-#define DMA_RXOR1240x1
-#define DMA_RXOR1250x2
-#define DMA_RXOR12 0x3
-
-/* S/G addresses */
-#define DMA_CDB_SG_SRC 1
-#define DMA_CDB_SG_DST12
-#define DMA_CDB_SG_DST23
-
-/*
- * DMAx engines Command Descriptor Block Type
- */
-struct dma_cdb {
- /*
-* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
-*/
- u8 pad0[2];/* reserved */
- u8 attr; /* attributes */
- u8 opc;/* opcode */
- u32 sg1u; /* upper SG1 address */
- u32 sg1l; /* lower SG1 address */
- u32 cnt;/* SG count, 3B used */
- u32 sg2u; /* upper SG2 address */
- u32 sg2l; /* lower SG2 address */
- u32 sg3u; /* upper SG3 address */
- u32 sg3l; /* lower SG3 address */
-};
-
-/*
- * DMAx hardware registers (p.515 in 440SPe UM 1.22)
- */
-struct dma_regs {
- u32 cpfpl;
- u32 cpfph;
- u32 csfpl;
- u32 csfph;
- u32 dsts;
- u32 cfg;
- u8 pad0[0x8];
- u16 cpfhp;
- u16 cpftp;
- u16 csfhp;
- u16 csftp;
- u8 pad1[0x8];
- u32 acpl;
- u32 acph;
- u32 s1bpl;
- u32
[PATCH 2/2] PPC4xx: Merge xor.h and dma.h into onefile ppc440spe-dma.h
From: Tirumala Marri tma...@apm.com
This patch combines drivers/dma/ppc4xx/xor.h and driver/dma/dma/ppc4xx/dma.h
into drivers/dma/ppc4xx/ppx440spe-dma.h .
Signed-off-by: Tirumala R Marri tma...@apm.com
---
drivers/dma/ppc4xx/dma.h | 223 -
drivers/dma/ppc4xx/ppc440spe-dma.h | 318
drivers/dma/ppc4xx/xor.h | 110 -
3 files changed, 318 insertions(+), 333 deletions(-)
delete mode 100644 drivers/dma/ppc4xx/dma.h
create mode 100644 drivers/dma/ppc4xx/ppc440spe-dma.h
delete mode 100644 drivers/dma/ppc4xx/xor.h
diff --git a/drivers/dma/ppc4xx/dma.h b/drivers/dma/ppc4xx/dma.h
deleted file mode 100644
index bcde2df..000
--- a/drivers/dma/ppc4xx/dma.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * 440SPe's DMA engines support header file
- *
- * 2006-2009 (C) DENX Software Engineering.
- *
- * Author: Yuri Tikhonov y...@emcraft.com
- *
- * This file is licensed under the term of the GNU General Public License
- * version 2. The program licensed as is without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef_PPC440SPE_DMA_H
-#define _PPC440SPE_DMA_H
-
-#include linux/types.h
-
-/* Number of elements in the array with statical CDBs */
-#defineMAX_STAT_DMA_CDBS 16
-/* Number of DMA engines available on the contoller */
-#define DMA_ENGINES_NUM2
-
-/* Maximum h/w supported number of destinations */
-#define DMA_DEST_MAX_NUM 2
-
-/* FIFO's params */
-#define DMA0_FIFO_SIZE 0x1000
-#define DMA1_FIFO_SIZE 0x1000
-#define DMA_FIFO_ENABLE(112)
-
-/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
-#define DMA_CFG_DXEPR_LP (026)
-#define DMA_CFG_DXEPR_HP (326)
-#define DMA_CFG_DXEPR_HHP (226)
-#define DMA_CFG_DXEPR_HHHP (126)
-
-/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
-#define DMA_CFG_DFMPP_LP (023)
-#define DMA_CFG_DFMPP_HP (323)
-#define DMA_CFG_DFMPP_HHP (223)
-#define DMA_CFG_DFMPP_HHHP (123)
-
-/* DMA Configuration Register. Force 64-byte Alignment */
-#define DMA_CFG_FALGN (1 19)
-
-/*UIC0:*/
-#define D0CPF_INT (112)
-#define D0CSF_INT (111)
-#define D1CPF_INT (110)
-#define D1CSF_INT (19)
-/*UIC1:*/
-#define DMAE_INT (19)
-
-/* I2O IOP Interrupt Mask Register */
-#define I2O_IOPIM_P0SNE(13)
-#define I2O_IOPIM_P0EM (15)
-#define I2O_IOPIM_P1SNE(16)
-#define I2O_IOPIM_P1EM (18)
-
-/* DMA CDB fields */
-#define DMA_CDB_MSK(0xF)
-#define DMA_CDB_64B_ADDR (12)
-#define DMA_CDB_NO_INT (13)
-#define DMA_CDB_STATUS_MSK (0x3)
-#define DMA_CDB_ADDR_MSK (0xFFF0)
-
-/* DMA CDB OpCodes */
-#define DMA_CDB_OPC_NO_OP (0x00)
-#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
-#define DMA_CDB_OPC_MULTICAST (0x05)
-#define DMA_CDB_OPC_DFILL128 (0x24)
-#define DMA_CDB_OPC_DCHECK128 (0x23)
-
-#define DMA_CUED_XOR_BASE (0x1000)
-#define DMA_CUED_XOR_HB(0x0008)
-
-#ifdef CONFIG_440SP
-#define DMA_CUED_MULT1_OFF 0
-#define DMA_CUED_MULT2_OFF 8
-#define DMA_CUED_MULT3_OFF 16
-#define DMA_CUED_REGION_OFF24
-#define DMA_CUED_XOR_WIN_MSK (0xFC00)
-#else
-#define DMA_CUED_MULT1_OFF 2
-#define DMA_CUED_MULT2_OFF 10
-#define DMA_CUED_MULT3_OFF 18
-#define DMA_CUED_REGION_OFF26
-#define DMA_CUED_XOR_WIN_MSK (0xF000)
-#endif
-
-#define DMA_CUED_REGION_MSK0x3
-#define DMA_RXOR1230x0
-#define DMA_RXOR1240x1
-#define DMA_RXOR1250x2
-#define DMA_RXOR12 0x3
-
-/* S/G addresses */
-#define DMA_CDB_SG_SRC 1
-#define DMA_CDB_SG_DST12
-#define DMA_CDB_SG_DST23
-
-/*
- * DMAx engines Command Descriptor Block Type
- */
-struct dma_cdb {
- /*
-* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
-*/
- u8 pad0[2];/* reserved */
- u8 attr; /* attributes */
- u8 opc;/* opcode */
- u32 sg1u; /* upper SG1 address */
- u32 sg1l; /* lower SG1 address */
- u32 cnt;/* SG count, 3B used */
- u32 sg2u; /* upper SG2 address */
- u32 sg2l; /* lower SG2 address */
- u32 sg3u; /* upper SG3 address */
- u32 sg3l; /* lower SG3 address */
-};
-
-/*
- * DMAx hardware registers (p.515 in 440SPe UM 1.22)
- */
-struct dma_regs {
- u32 cpfpl;
- u32 cpfph;
- u32 csfpl;
- u32 csfph;
- u32 dsts;
- u32 cfg;
- u8 pad0[0x8];
- u16 cpfhp;
- u16 cpftp;
- u16 csfhp;
- u16 csftp;
- u8 pad1[0x8];
- u32 acpl;
- u32 acph;
-
[PATCH v2] APM821xx: Add support for new SoC APM821xx
From: Tirumala Marri tma...@apm.com
This patch adds CPU, device tree, defconfig and bluestone board
support for APM821xx SoC.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
V1:
* CPU name changed to 464.
* defconfig is created using make savedefconfig.
V2:
* CPU name changed back to apm821xx for now.
* some white space problem in device tree.
---
arch/powerpc/boot/dts/bluestone.dts | 254 ++
arch/powerpc/configs/44x/bluestone_defconfig | 68 +++
arch/powerpc/kernel/cpu_setup_44x.S |1 +
arch/powerpc/kernel/cputable.c | 15 ++
arch/powerpc/platforms/44x/Kconfig | 16 ++
arch/powerpc/platforms/44x/ppc44x_simple.c |1 +
6 files changed, 355 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/bluestone.dts
create mode 100644 arch/powerpc/configs/44x/bluestone_defconfig
diff --git a/arch/powerpc/boot/dts/bluestone.dts
b/arch/powerpc/boot/dts/bluestone.dts
new file mode 100644
index 000..9bb3d72
--- /dev/null
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -0,0 +1,254 @@
+/*
+ * Device Tree for Bluestone (APM821xx) board.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri tma...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = apm,bluestone;
+ compatible = apm,bluestone;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ ethernet0 = EMAC0;
+ serial0 = UART0;
+ serial1 = UART1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,apm821xx;
+ reg = 0x;
+ clock-frequency = 0; /* Filled in by U-Boot */
+ timebase-frequency = 0; /* Filled in by U-Boot */
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ next-level-cache = L2C0;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x 0x; /* Filled in by
U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 0;
+ dcr-reg = 0x0c0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 1;
+ dcr-reg = 0x0d0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x1e 0x4 0x1f 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 2;
+ dcr-reg = 0x0e0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0xa 0x4 0xb 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 3;
+ dcr-reg = 0x0f0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x10 0x4 0x11 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ SDR0: sdr {
+ compatible = ibm,sdr-apm821xx;
+ dcr-reg = 0x00e 0x002;
+ };
+
+ CPR0: cpr {
+ compatible = ibm,cpr-apm821xx;
+ dcr-reg = 0x00c 0x002;
+ };
+
+ plb {
[PATCH v1] APM821xx: Add support for new SoC APM821xx
From: Tirumala Marri tma...@apm.com
This patch adds CPU, device tree, defconfig and bluestone board
support for APM821xx SoC.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
V1:
* CPU name changed to 464.
* defconfig is created using make savedefconfig.
---
arch/powerpc/boot/dts/bluestone.dts | 254 ++
arch/powerpc/configs/44x/bluestone_defconfig | 68 +++
arch/powerpc/kernel/cpu_setup_44x.S |1 +
arch/powerpc/kernel/cputable.c | 15 ++
arch/powerpc/platforms/44x/Kconfig | 16 ++
arch/powerpc/platforms/44x/ppc44x_simple.c |1 +
6 files changed, 355 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/bluestone.dts
create mode 100644 arch/powerpc/configs/44x/bluestone_defconfig
diff --git a/arch/powerpc/boot/dts/bluestone.dts
b/arch/powerpc/boot/dts/bluestone.dts
new file mode 100644
index 000..bedcb8b
--- /dev/null
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -0,0 +1,254 @@
+/*
+ * Device Tree for Bluestone (APM821xx) board.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * All rights reserved. Tirumala R Marri tma...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = apm,bluestone;
+ compatible = apm,bluestone;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ ethernet0 = EMAC0;
+ serial0 = UART0;
+ serial1 = UART1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,464;
+ reg = 0x;
+ clock-frequency = 0; /* Filled in by U-Boot */
+ timebase-frequency = 0; /* Filled in by U-Boot */
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ next-level-cache = L2C0;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x 0x; /* Filled in by
U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 0;
+ dcr-reg = 0x0c0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 1;
+ dcr-reg = 0x0d0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x1e 0x4 0x1f 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 2;
+ dcr-reg = 0x0e0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0xa 0x4 0xb 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 3;
+ dcr-reg = 0x0f0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x10 0x4 0x11 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ SDR0: sdr {
+ compatible = ibm,sdr-apm821xx;
+ dcr-reg = 0x00e 0x002;
+ };
+
+ CPR0: cpr {
+ compatible = ibm,cpr-apm821xx;
+ dcr-reg = 0x00c 0x002;
+ };
+
+ plb {
+ compatible = ibm,plb4;
+ #address-cells = 2;
+
[PATCH] APM821xx: Add support for new SoC APM821xx
From: Tirumala Marri tma...@apm.com
This patch adds CPU, device tree, defconfig and bluestone board
support for APM821xx SoC.
Signed-off-by: Tirumala R Marri tma...@apm.com
---
APM821xx is Applied Micro Circuits Corporations naming convention for
new line of SoCs.
arch/powerpc/boot/dts/bluestone.dts | 254 +
arch/powerpc/configs/44x/bluestone_defconfig | 1330 ++
arch/powerpc/kernel/cpu_setup_44x.S |1 +
arch/powerpc/kernel/cputable.c | 15 +
arch/powerpc/platforms/44x/Kconfig | 16 +
arch/powerpc/platforms/44x/ppc44x_simple.c |1 +
6 files changed, 1617 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/bluestone.dts
create mode 100644 arch/powerpc/configs/44x/bluestone_defconfig
diff --git a/arch/powerpc/boot/dts/bluestone.dts
b/arch/powerpc/boot/dts/bluestone.dts
new file mode 100644
index 000..46b5e68
--- /dev/null
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -0,0 +1,254 @@
+/*
+ * Device Tree for Bluestone (APM821xx) board.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * All rights reserved. Tirumala R Marri tma...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = 2;
+ #size-cells = 1;
+ model = apm,bluestone;
+ compatible = apm,bluestone;
+ dcr-parent = {/cpus/c...@0};
+
+ aliases {
+ ethernet0 = EMAC0;
+ serial0 = UART0;
+ serial1 = UART1;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ c...@0 {
+ device_type = cpu;
+ model = PowerPC,APM821xx;
+ reg = 0x;
+ clock-frequency = 0; /* Filled in by U-Boot */
+ timebase-frequency = 0; /* Filled in by U-Boot */
+ i-cache-line-size = 32;
+ d-cache-line-size = 32;
+ i-cache-size = 32768;
+ d-cache-size = 32768;
+ dcr-controller;
+ dcr-access-method = native;
+ next-level-cache = L2C0;
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x 0x; /* Filled in by
U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 0;
+ dcr-reg = 0x0c0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 1;
+ dcr-reg = 0x0d0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x1e 0x4 0x1f 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 2;
+ dcr-reg = 0x0e0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0xa 0x4 0xb 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = ibm,uic;
+ interrupt-controller;
+ cell-index = 3;
+ dcr-reg = 0x0f0 0x009;
+ #address-cells = 0;
+ #size-cells = 0;
+ #interrupt-cells = 2;
+ interrupts = 0x10 0x4 0x11 0x4; /* cascade */
+ interrupt-parent = UIC0;
+ };
+
+ SDR0: sdr {
+ compatible = ibm,sdr-apm821xx;
+ dcr-reg = 0x00e 0x002;
+ };
+
+ CPR0: cpr {
+ compatible = ibm,cpr-apm821xx;
+ dcr-reg = 0x00c 0x002;
+ };
+
+ plb {
+ compatible = ibm,plb4;
+ #address-cells = 2;
+
[PATCH 2/2] Adding PCI-E MSI support for PowerPC 460SX SOC.
From: Tirumala Marri tma...@amcc.com
Signed-off-by: Tirumala Marri tma...@amcc.com
---
When 460SX configured as root as a end point E1000(Intell Ethernet card)
was plugged into the one of the PCI-E ports. I was able to run the
traffic
with MSI interrupts.
---
arch/powerpc/boot/dts/redwood.dts | 15 ++
arch/powerpc/configs/44x/redwood_defconfig |5 +-
arch/powerpc/platforms/44x/Kconfig |1 +
arch/powerpc/sysdev/Kconfig|7 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/ppc4xx_msi.c | 333
arch/powerpc/sysdev/ppc4xx_msi.h | 39
7 files changed, 399 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.h
diff --git a/arch/powerpc/boot/dts/redwood.dts
b/arch/powerpc/boot/dts/redwood.dts
index 81636c0..6c20faf 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -357,6 +357,21 @@
0x0 0x0 0x0 0x3 UIC3 0xa 0x4 /* swizzled int C
*/
0x0 0x0 0x0 0x4 UIC3 0xb 0x4 /* swizzled int D
*/;
};
+ MSI: ppc4xx-...@40030 {
+ compatible = amcc,ppc4xx-460sx-msi, ppc4xx-msi;
+ reg = 0x4 0x0030 0x100
+ 0x4 0x0030 0x100;
+ sdr-base = 0x3B0;
+ interrupts =0 1 2 3;
+ interrupt-parent = MSI;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC0 0xC 1
+ 1 UIC0 0x0D 1
+ 2 UIC0 0x0E 1
+ 3 UIC0 0x0F 1;
+ };
};
diff --git a/arch/powerpc/configs/44x/redwood_defconfig
b/arch/powerpc/configs/44x/redwood_defconfig
index ed31d4f..5d16c88 100644
--- a/arch/powerpc/configs/44x/redwood_defconfig
+++ b/arch/powerpc/configs/44x/redwood_defconfig
@@ -158,6 +158,7 @@ CONFIG_DEFAULT_AS=y
CONFIG_DEFAULT_IOSCHED=anticipatory
# CONFIG_FREEZER is not set
CONFIG_PPC4xx_PCI_EXPRESS=y
+CONFIG_PPC_MSI_BITMAP=y
#
# Platform support
@@ -264,7 +265,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
# CONFIG_PCIEASPM is not set
CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
+CONFIG_PCI_MSI=y
# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
@@ -1062,7 +1063,7 @@ CONFIG_PRINT_STACK_DEPTH=64
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
-# CONFIG_MSI_BITMAP_SELFTEST is not set
+CONFIG_MSI_BITMAP_SELFTEST=y
# CONFIG_XMON is not set
# CONFIG_IRQSTACKS is not set
# CONFIG_VIRQ_DEBUG is not set
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
index 7486bff..9c3b8ca 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -126,6 +126,7 @@ config REDWOOD
select 460SX
select PCI
select PPC4xx_PCI_EXPRESS
+ select PPC4xx_MSI
help
This option enables support for the AMCC PPC460SX Redwood board.
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 3965828..c8f1486 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -7,8 +7,15 @@ config PPC4xx_PCI_EXPRESS
depends on PCI 4xx
default n
+config PPC4xx_MSI
+ bool
+ depends on PCI_MSI
+ depends on PCI 4xx
+ default n
+
config PPC_MSI_BITMAP
bool
depends on PCI_MSI
default y if MPIC
default y if FSL_PCI
+ default y if PPC4xx_MSI
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5642924..4c67d2d 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
obj-$(CONFIG_4xx) += uic.o
obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
+obj-$(CONFIG_PPC4xx_MSI) += ppc4xx_msi.o
obj-$(CONFIG_XILINX_VIRTEX)+= xilinx_intc.o
obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
new file mode 100644
index 000..44b8962
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright (C) 2009 Applied Micro Circuits corporation.
+ *
+ * Author: Tirumala Marri tma...@amcc.com
+ *Feng Kan f...@amcc.com
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation;
[PATCH 1/2] Adding PCI-E support for PowerPC 460SX based SOC.
From: Tirumala Marri tma...@amcc.com
Signed-off-by: Tirumala Marri tma...@amcc.com
---
Kerenl:2.6.33-rc1
Testing: This patch has been tested on 460SX based redwood board . One board
configured as
root complex and other as Endpoint. Checked for link up . From root complex
lspci command
shows the end point. Also programmed IO tested using loop back as well as board
to board.
---
arch/powerpc/boot/dts/redwood.dts | 122 +
arch/powerpc/sysdev/ppc4xx_pci.c | 119
arch/powerpc/sysdev/ppc4xx_pci.h | 58 +
3 files changed, 299 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/redwood.dts
b/arch/powerpc/boot/dts/redwood.dts
index d2af32e..81636c0 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -234,10 +234,132 @@
has-inverted-stacr-oc;
has-new-stacr-staopc;
};
+ };
+ PCIE0: pc...@d {
+ device_type = pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+ primary;
+ port = 0x0; /* port number */
+ reg = 0x000d 0x 0x2000 /* Config space
access */
+ 0x000c 0x1000 0x1000; /*
Registers */
+ dcr-reg = 0x100 0x020;
+ sdr-base = 0x300;
+
+ /* Outbound ranges, one memory and one IO,
+* later cannot be changed
+*/
+ ranges = 0x0200 0x 0x8000 0x000e
0x 0x 0x8000
+ 0x0100 0x 0x 0x000f
0x8000 0x 0x0001;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0
0x8000;
+ /* This drives busses 10 to 0x1f */
+ bus-range = 0x10 0x1f;
+
+ /* Legacy interrupts (note the weird polarity, the
bridge seems
+* to invert PCIe legacy interrupts).
+* We are de-swizzling here because the numbers are
actually for
+* port of the root complex virtual P2P bridge. But I
want
+* to avoid putting a node for it in the tree, so the
numbers
+* below are basically de-swizzled numbers.
+* The real slot is on idsel 0, so the swizzling is 1:1
+*/
+ interrupt-map-mask = 0x0 0x0 0x0 0x7;
+ interrupt-map =
+ 0x0 0x0 0x0 0x1 UIC3 0x0 0x4 /* swizzled int A
*/
+ 0x0 0x0 0x0 0x2 UIC3 0x1 0x4 /* swizzled int B
*/
+ 0x0 0x0 0x0 0x3 UIC3 0x2 0x4 /* swizzled int C
*/
+ 0x0 0x0 0x0 0x4 UIC3 0x3 0x4 /* swizzled int D
*/;
+ };
+
+ PCIE1: pc...@d2000 {
+ device_type = pci;
+ #interrupt-cells = 1;
+ #size-cells = 2;
+ #address-cells = 3;
+ compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+ primary;
+ port = 0x1; /* port number */
+ reg = 0x000d 0x2000 0x2000 /* Config space
access */
+ 0x000c 0x10001000 0x1000; /*
Registers */
+ dcr-reg = 0x120 0x020;
+ sdr-base = 0x340;
+
+ /* Outbound ranges, one memory and one IO,
+* later cannot be changed
+*/
+ ranges = 0x0200 0x 0x8000 0x000e
0x8000 0x 0x8000
+ 0x0100 0x 0x 0x000f
0x8001 0x 0x0001;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0
0x8000;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = 0x20 0x2f;
+
+ /* Legacy interrupts (note the weird polarity, the
bridge seems
+* to invert PCIe legacy interrupts).
+* We are de-swizzling here because the numbers are
actually for
+* port of the root complex virtual P2P bridge. But I
want
+* to avoid putting a node for it
[PATCH 2/2] Adding PCI-E MSI support for PowerPC 460SX SOC.
From: Tirumala Marri tma...@amcc.com
Signed-off-by: Tirumala Marri tma...@amcc.com
---
Kernel version: 2.6.33-rc1
Testing:
When 460SX configured as root as a end point E1000(Intell Ethernet
card)
was plugged into the one of the PCI-E ports. I was able to run the
traffic
with MSI interrupts.
---
arch/powerpc/boot/dts/redwood.dts | 15 ++
arch/powerpc/configs/44x/redwood_defconfig |5 +-
arch/powerpc/platforms/44x/Kconfig |1 +
arch/powerpc/sysdev/Kconfig|7 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/ppc4xx_msi.c | 335
arch/powerpc/sysdev/ppc4xx_msi.h | 49
7 files changed, 411 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.h
diff --git a/arch/powerpc/boot/dts/redwood.dts
b/arch/powerpc/boot/dts/redwood.dts
index 81636c0..412d5f9 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -357,6 +357,21 @@
0x0 0x0 0x0 0x3 UIC3 0xa 0x4 /* swizzled int C
*/
0x0 0x0 0x0 0x4 UIC3 0xb 0x4 /* swizzled int D
*/;
};
+ MSI: ppc4xx-...@40030 {
+ compatible = amcc,ppc4xx-msi, ppc4xx-msi;
+ reg = 0x4 0x0030 0x100
+ 0x4 0x0030 0x100;
+ sdr-base = 0x3B0;
+ interrupts =0 1 2 3;
+ interrupt-parent = MSI;
+ #interrupt-cells = 1;
+ #address-cells = 0;
+ #size-cells = 0;
+ interrupt-map = 0 UIC0 0xC 1
+ 1 UIC0 0x0D 1
+ 2 UIC0 0x0E 1
+ 3 UIC0 0x0F 1;
+ };
};
diff --git a/arch/powerpc/configs/44x/redwood_defconfig
b/arch/powerpc/configs/44x/redwood_defconfig
index ed31d4f..5d16c88 100644
--- a/arch/powerpc/configs/44x/redwood_defconfig
+++ b/arch/powerpc/configs/44x/redwood_defconfig
@@ -158,6 +158,7 @@ CONFIG_DEFAULT_AS=y
CONFIG_DEFAULT_IOSCHED=anticipatory
# CONFIG_FREEZER is not set
CONFIG_PPC4xx_PCI_EXPRESS=y
+CONFIG_PPC_MSI_BITMAP=y
#
# Platform support
@@ -264,7 +265,7 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCIEAER=y
# CONFIG_PCIEASPM is not set
CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
+CONFIG_PCI_MSI=y
# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
@@ -1062,7 +1063,7 @@ CONFIG_PRINT_STACK_DEPTH=64
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
-# CONFIG_MSI_BITMAP_SELFTEST is not set
+CONFIG_MSI_BITMAP_SELFTEST=y
# CONFIG_XMON is not set
# CONFIG_IRQSTACKS is not set
# CONFIG_VIRQ_DEBUG is not set
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
index 7486bff..85b9c33 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -126,6 +126,7 @@ config REDWOOD
select 460SX
select PCI
select PPC4xx_PCI_EXPRESS
+ select 4xx_MSI
help
This option enables support for the AMCC PPC460SX Redwood board.
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 3965828..32f5a40 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -7,8 +7,15 @@ config PPC4xx_PCI_EXPRESS
depends on PCI 4xx
default n
+config 4xx_MSI
+ bool
+ depends on PCI_MSI
+ depends on PCI 4xx
+ default n
+
config PPC_MSI_BITMAP
bool
depends on PCI_MSI
default y if MPIC
default y if FSL_PCI
+ default y if 4xx_MSI
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5642924..d60c33b 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
obj-$(CONFIG_4xx) += uic.o
obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
+obj-$(CONFIG_4xx_MSI) += ppc4xx_msi.o
obj-$(CONFIG_XILINX_VIRTEX)+= xilinx_intc.o
obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
new file mode 100644
index 000..752da4b
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2009 Applied Micro Circuits corporation,
+ * All rights reserved.
+ *
+ * Author: Feng Kan f...@amcc.com
+ *Tirumala Marri tma...@amcc.com
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as
