When in consumer mode with BCLK disabled (FSL_SAI_CSR_BCE = 0) the
FIFO's can still contain data when resumed. It might also be possible
with BCLK enabled but just less likely.
When the FIFO's still contain data on resume it can cause channel
shifting on e.g. XRUNS. A Software Reset will reset the FIFO's and make
sure channels are aligned.
Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
Signed-off-by: Emil Svendsen
---
sound/soc/fsl/fsl_sai.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 1e4020fae05a..1da5c17cd329 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -730,13 +730,18 @@ static void fsl_sai_config_disable(struct fsl_sai *sai,
int dir)
* anymore. Add software reset to fix this issue.
* This is a hardware bug, and will be fix in the
* next sai version.
+*
+* When in consumer mode with BCLK disabled
+* (FSL_SAI_CSR_BCE = 0) the FIFO's can still contain
+* data when resumed. This can cause channel shifting
+* on e.g. XRUNS. A Software Reset will reset the
+* FIFO's and make sure the channels aren't shifted.
*/
- if (!sai->is_consumer_mode) {
- /* Software Reset */
- regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_SR);
- /* Clear SR bit to finish the reset */
- regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
- }
+
+ /* Software Reset */
+ regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
+ /* Clear SR bit to finish the reset */
+ regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
}
static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
--
2.34.1
