Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227 --
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed as is without any warranty of any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
What Stephen said.
#define NUM_REGS 2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address of the control
+ registers */
Is this driver usable on the 440 based Xilinx devices? If so, is it possible
to have the physical address of the registers above 4GiB, so is common with
almost all the I/O on the other 440 boards?
+ void __iomem*regs; /* virt. address of the control
+ registers */
+
dcr_host_t dcr_host;
unsigned intdcr_start;
unsigned intdcr_len;
@@ -120,6 +136,10 @@ struct xilinxfb_drvdata {
dma_addr_t fb_phys;/* phys. address of the frame buffer */
int fb_alloced; /* Flag, was the fb memory alloced? */
+ u32 dcr_splb_slave_if;
+ /* True, if control interface is
+ connected through plb */
+
Do you need a full 32-bit variable for a simple boolean? It might be best for
structure alignment, but you might want to look at using a flags variable or
something that could be extended with feature bits in a single word.
u32 reg_ctrl_default;
u32 pseudo_palette[PALETTE_ENTRIES_NO];
@@ -130,14 +150,19 @@ struct xilinxfb_drvdata {
container_of(_info, struct xilinxfb_drvdata, info)
/*
- * The LCD controller has DCR interface to its registers, but all
- * the boards and configurations the driver has been tested with
- * use opb2dcr bridge. So the registers are seen as memory mapped.
- * This macro is to make it simple to add the direct DCR access
- * when it's needed.
+ * The XPS TFT Controller can be accessed through PLB or DCR interface.
+ * To perform the read/write on the registers we need to check on
+ * which bus its connected and call the appropriate write API.
*/
-#define xilinx_fb_out_be32(driverdata, offset, val) \
- dcr_write(driverdata-dcr_host, offset, val)
+static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+ u32 val)
+{
+ if (drvdata-dcr_splb_slave_if == 1)
+ out_be32(drvdata-regs + (offset 2), val);
+ else
+ dcr_write(drvdata-dcr_host, offset, val);
+
+}
static int
xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned
blue,
@@ -175,7 +200,8 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
- xilinx_fb_out_be32(drvdata, REG_CTRL,
drvdata-reg_ctrl_default);
+ xilinx_fb_out_be32(drvdata, REG_CTRL,
+ drvdata-reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
@@ -191,8 +217,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
return 0; /* success */
}
-static struct fb_ops xilinxfb_ops =
-{
+static struct fb_ops xilinxfb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = xilinx_fb_setcolreg,
.fb_blank =
RE: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
-Original Message- From: Stephen Rothwell [mailto:s...@canb.auug.org.au] Sent: Wednesday, April 08, 2009 7:52 PM To: John Linn Cc: grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com; linuxppc-dev@ozlabs.org; linux-fbdev-de...@lists.sourceforge.net; akonova...@ru.mvista.com; adap...@gmail.com; Suneel Garapati; Suneel Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) Hi John, On Wed, 8 Apr 2009 15:11:25 -0600 John Linn john.l...@xilinx.com wrote: * 2002-2007 (c) MontaVista Software, Inc. * 2007 (c) Secret Lab Technologies, Ltd. + * 2009 (c) Xilinx Inc. * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed as is without any warranty of any - * kind, whether express or implied. + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General Public + * License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any + * later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. This changes the license for this file (from GPLv2 to GPLv2 or later). Have you asked the other copyright owners about that? Andrei was copied on the patch, we'll see if he has any thoughts about it. Thanks, John -- Cheers, Stephen Rothwells...@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer jwbo...@linux.vnet.ibm.comwrote:
On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227
--
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU General Public
License
- * version 2. This program is licensed as is without any warranty of
any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
What Stephen said.
#define NUM_REGS 2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address of the control
+ registers */
Is this driver usable on the 440 based Xilinx devices? If so, is it
possible
to have the physical address of the registers above 4GiB, so is common with
almost all the I/O on the other 440 boards?
The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440
core). It might be nice to move physical addresses above 4GB for devices but
in all Xilinx tools and reference designs addresses below 4GB are used for
periperhals and I think even below 2GB (or even below 1GB). It depends on
the design.
Roderick Colenbrander
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Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
On Thu, Apr 9, 2009 at 7:16 AM, John Linn john.l...@xilinx.com wrote: -Original Message- From: Stephen Rothwell [mailto:s...@canb.auug.org.au] Sent: Wednesday, April 08, 2009 7:52 PM To: John Linn Cc: grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com; linuxppc-dev@ozlabs.org; linux-fbdev-de...@lists.sourceforge.net; akonova...@ru.mvista.com; adap...@gmail.com; Suneel Garapati; Suneel Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) Hi John, On Wed, 8 Apr 2009 15:11:25 -0600 John Linn john.l...@xilinx.com wrote: * 2002-2007 (c) MontaVista Software, Inc. * 2007 (c) Secret Lab Technologies, Ltd. + * 2009 (c) Xilinx Inc. * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed as is without any warranty of any - * kind, whether express or implied. + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General Public + * License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any + * later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. This changes the license for this file (from GPLv2 to GPLv2 or later). Have you asked the other copyright owners about that? Andrei was copied on the patch, we'll see if he has any thoughts about it. I also hold copyright on this file and I want the license to stay GPLv2. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
On Thu, Apr 09, 2009 at 04:06:56PM +0200, Roderick Colenbrander wrote:
On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer jwbo...@linux.vnet.ibm.comwrote:
#define NUM_REGS 2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address of the control
+ registers */
Is this driver usable on the 440 based Xilinx devices? If so, is it
possible
to have the physical address of the registers above 4GiB, so is common with
almost all the I/O on the other 440 boards?
The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440
core). It might be nice to move physical addresses above 4GB for devices but
in all Xilinx tools and reference designs addresses below 4GB are used for
periperhals and I think even below 2GB (or even below 1GB). It depends on
the design.
Right. The depends on the design part is what I'm worried about. Perhaps
using resource_size_t here is more appropriate, given that designs can change
and put the regs above 4GiB. That way you can set the Kconfig option
appropriately for both cases.
josh
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RE: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
-Original Message-
From: Josh Boyer [mailto:jwbo...@linux.vnet.ibm.com]
Sent: Thursday, April 09, 2009 6:47 AM
To: John Linn
Cc: grant.lik...@secretlab.ca; linuxppc-dev@ozlabs.org;
linux-fbdev-de...@lists.sourceforge.net;
akonova...@ru.mvista.com; adap...@gmail.com; Suneel; Suneel Garapati
Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB
support (non-DCR)
On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227
--
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU General
Public License
- * version 2. This program is licensed as is without any
warranty of any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
What Stephen said.
Grant commented, I'll respin it after other comments to leave that
alone.
#define NUM_REGS2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+u32 regs_phys; /* phys. address of the control
+registers */
Is this driver usable on the 440 based Xilinx devices? If
so, is it possible
to have the physical address of the registers above 4GiB, so
is common with
almost all the I/O on the other 440 boards?
It is used on the 440. As Roderick said,
devices are mapped using the 32 bits of address in the Xilinx tools so
it would be best to stay below 4 Gig to my knowledge.
+void __iomem*regs; /* virt. address of the control
+registers */
+
dcr_host_t dcr_host;
unsigned intdcr_start;
unsigned intdcr_len;
@@ -120,6 +136,10 @@ struct xilinxfb_drvdata {
dma_addr_t fb_phys;/* phys. address of the
frame buffer */
int fb_alloced; /* Flag, was the fb
memory alloced? */
+u32 dcr_splb_slave_if;
+/* True, if control interface is
+connected through plb */
+
Do you need a full 32-bit variable for a simple boolean? It
might be best for
structure alignment, but you might want to look at using a
flags variable or
something that could be extended with feature bits in a single word.
It could be a flag I think. This was easy as it mapped to the device
tree property.
u32 reg_ctrl_default;
u32 pseudo_palette[PALETTE_ENTRIES_NO];
@@ -130,14 +150,19 @@ struct xilinxfb_drvdata {
container_of(_info, struct xilinxfb_drvdata, info)
/*
- * The LCD controller has DCR interface to its registers, but all
- * the boards and configurations the driver has been tested with
- * use opb2dcr bridge. So the registers are seen as memory mapped.
- * This macro is to make it simple to add the direct DCR access
- * when it's needed.
+ * The XPS TFT Controller can be accessed through PLB or
DCR interface.
+ * To perform the read/write on the registers we need to check on
+ * which bus its connected and call the appropriate write API.
*/
-#define xilinx_fb_out_be32(driverdata, offset, val) \
-dcr_write(driverdata-dcr_host, offset, val)
+static void xilinx_fb_out_be32(struct xilinxfb_drvdata
*drvdata, u32 offset,
+u32 val)
+{
+if (drvdata-dcr_splb_slave_if == 1)
+out_be32(drvdata-regs + (offset 2), val);
+else
+dcr_write(drvdata-dcr_host, offset, val);
+
+}
static int
Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
On Thu, Apr 9, 2009 at 7:06 AM, Roderick Colenbrander
thunderbir...@gmail.com wrote:
On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer jwbo...@linux.vnet.ibm.com
wrote:
On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227
--
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU General Public
License
- * version 2. This program is licensed as is without any warranty of
any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
What Stephen said.
#define NUM_REGS 2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address of the control
+ registers */
Is this driver usable on the 440 based Xilinx devices? If so, is it
possible
to have the physical address of the registers above 4GiB, so is common
with
almost all the I/O on the other 440 boards?
The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440
core). It might be nice to move physical addresses above 4GB for devices but
in all Xilinx tools and reference designs addresses below 4GB are used for
periperhals and I think even below 2GB (or even below 1GB). It depends on
the design.
Regardless, it is good practice to use phys_addr_t instead of u32 for
physical addresses.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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RE: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
-Original Message-
From: Grant Likely [mailto:grant.lik...@secretlab.ca]
Sent: Thursday, April 09, 2009 8:35 AM
To: Roderick Colenbrander
Cc: Josh Boyer; linux-fbdev-de...@lists.sourceforge.net;
adap...@gmail.com; Suneel Garapati; linuxppc-dev@ozlabs.org;
akonova...@ru.mvista.com; John Linn
Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB
support (non-DCR)
On Thu, Apr 9, 2009 at 7:06 AM, Roderick Colenbrander
thunderbir...@gmail.com wrote:
On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer
jwbo...@linux.vnet.ibm.com
wrote:
On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote:
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227
--
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU
General Public
License
- * version 2. This program is licensed as is without
any warranty of
any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
What Stephen said.
#define NUM_REGS 2
#define REG_FB_ADDR 0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address
of the control
+ registers */
Is this driver usable on the 440 based Xilinx devices? If
so, is it
possible
to have the physical address of the registers above 4GiB,
so is common
with
almost all the I/O on the other 440 boards?
The driver works fine on 440 based Xilinx boards (the ML510
I use has a 440
core). It might be nice to move physical addresses above
4GB for devices but
in all Xilinx tools and reference designs addresses below
4GB are used for
periperhals and I think even below 2GB (or even below 1GB).
It depends on
the design.
Regardless, it is good practice to use phys_addr_t instead of u32 for
physical addresses.
I can change that when I respin to incorporate comments.
Thanks,
John
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
This email and any attachments are intended for the sole use of the named
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privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
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RE: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
-Original Message- From: Dale Farnsworth [mailto:d...@farnsworth.org] Sent: Thursday, April 09, 2009 9:36 AM To: John Linn; linuxppc-dev@ozlabs.org Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) -Original Message- From: Stephen Rothwell [mailto:s...@canb.auug.org.au] Sent: Wednesday, April 08, 2009 7:52 PM To: John Linn Cc: grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com; linuxppc-dev@ozlabs.org; linux-fbdev-de...@lists.sourceforge.net; akonova...@ru.mvista.com; adap...@gmail.com; Suneel Garapati; Suneel Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) Hi John, On Wed, 8 Apr 2009 15:11:25 -0600 John Linn john.l...@xilinx.com wrote: * 2002-2007 (c) MontaVista Software, Inc. * 2007 (c) Secret Lab Technologies, Ltd. + * 2009 (c) Xilinx Inc. * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed as is without any warranty of any - * kind, whether express or implied. + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General Public + * License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any + * later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. This changes the license for this file (from GPLv2 to GPLv2 or later). Have you asked the other copyright owners about that? Andrei was copied on the patch, we'll see if he has any thoughts about it. Although I work for MontaVista, I don't speak for them on licensing issues. In my opinion, unless someone can come up with a compelling reason for changing the license terms of a file, they shouldn't be changed. MontaVista made a deliberate, considered decision to license that file under GPLv2 and not GPLv2 or later. Those who use and distribute modifications to GPLv2 licensed work need to respect the license. Thanks Dale, we agree, Grant said the same thing. I'll fix that when I respin the patch. -- John -Dale This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
-Original Message- From: Stephen Rothwell [mailto:s...@canb.auug.org.au] Sent: Wednesday, April 08, 2009 7:52 PM To: John Linn Cc: grant.lik...@secretlab.ca; jwbo...@linux.vnet.ibm.com; linuxppc-dev@ozlabs.org; linux-fbdev-de...@lists.sourceforge.net; akonova...@ru.mvista.com; adap...@gmail.com; Suneel Garapati; Suneel Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) Hi John, On Wed, 8 Apr 2009 15:11:25 -0600 John Linn john.l...@xilinx.com wrote: * 2002-2007 (c) MontaVista Software, Inc. * 2007 (c) Secret Lab Technologies, Ltd. + * 2009 (c) Xilinx Inc. * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed as is without any warranty of any - * kind, whether express or implied. + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General Public + * License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any + * later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. This changes the license for this file (from GPLv2 to GPLv2 or later). Have you asked the other copyright owners about that? Andrei was copied on the patch, we'll see if he has any thoughts about it. Although I work for MontaVista, I don't speak for them on licensing issues. In my opinion, unless someone can come up with a compelling reason for changing the license terms of a file, they shouldn't be changed. MontaVista made a deliberate, considered decision to license that file under GPLv2 and not GPLv2 or later. Those who use and distribute modifications to GPLv2 licensed work need to respect the license. -Dale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
From: Suneel [mailto:suneel.garap...@xilinx.com]
Added support for the new xps tft controller.
The new core has PLB interface support in addition to existing
DCR interface.
The driver has been modified to support this new core which
can be connected on PLB or DCR bus.
Signed-off-by: Suneel sune...@xilinx.com
Signed-off-by: John Linn john.l...@xilinx.com
---
drivers/video/xilinxfb.c | 227 --
1 files changed, 160 insertions(+), 67 deletions(-)
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index a82c530..a28a834 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -1,17 +1,24 @@
/*
- * xilinxfb.c
*
- * Xilinx TFT LCD frame buffer driver
+ * Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* sou...@mvista.com
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
+ * 2009 (c) Xilinx Inc.
*
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed as is without any warranty of any
- * kind, whether express or implied.
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ * 02139, USA.
*/
/*
@@ -31,27 +38,31 @@
#include linux/fb.h
#include linux/init.h
#include linux/dma-mapping.h
-#if defined(CONFIG_OF)
#include linux/of_device.h
#include linux/of_platform.h
-#endif
-#include asm/io.h
+#include linux/io.h
#include linux/xilinxfb.h
#include asm/dcr.h
#define DRIVER_NAMExilinxfb
-#define DRIVER_DESCRIPTION Xilinx TFT LCD frame buffer driver
+
/*
* Xilinx calls it PLB TFT LCD Controller though it can also be used for
- * the VGA port on the Xilinx ML40x board. This is a hardware display
controller
- * for a 640x480 resolution TFT or VGA screen.
+ * the VGA port on the Xilinx ML40x board. This is a hardware display
+ * controller for a 640x480 resolution TFT or VGA screen.
*
* The interface to the framebuffer is nice and simple. There are two
* control registers. The first tells the LCD interface where in memory
* the frame buffer is (only the 11 most significant bits are used, so
* don't start thinking about scrolling). The second allows the LCD to
* be turned on or off as well as rotated 180 degrees.
+ *
+ * In case of direct PLB access the second control register will be at
+ * an offset of 4 as compared to the DCR access where the offset is 1
+ * i.e. REG_CTRL. So this is taken care in the function
+ * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
+ * direct PLB access.
*/
#define NUM_REGS 2
#define REG_FB_ADDR0
@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
+ u32 regs_phys; /* phys. address of the control
+ registers */
+ void __iomem*regs; /* virt. address of the control
+ registers */
+
dcr_host_t dcr_host;
unsigned intdcr_start;
unsigned intdcr_len;
@@ -120,6 +136,10 @@ struct xilinxfb_drvdata {
dma_addr_t fb_phys;/* phys. address of the frame buffer */
int fb_alloced; /* Flag, was the fb memory alloced? */
+ u32 dcr_splb_slave_if;
+ /* True, if control interface is
+ connected through plb */
+
u32 reg_ctrl_default;
u32 pseudo_palette[PALETTE_ENTRIES_NO];
@@ -130,14 +150,19 @@ struct xilinxfb_drvdata {
container_of(_info, struct xilinxfb_drvdata, info)
/*
- * The LCD controller has DCR interface to its registers, but all
- * the boards and configurations the driver has been tested with
- * use opb2dcr bridge. So the registers are seen as memory mapped.
- * This macro is to make it simple to add the direct DCR access
- * when it's needed.
+ * The XPS TFT Controller can be accessed through PLB or DCR interface.
+ * To perform the read/write on the registers we need to check on
+ * which bus its connected and call the appropriate write API.
*/
-#define xilinx_fb_out_be32(driverdata, offset, val) \
- dcr_write(driverdata-dcr_host, offset, val)
+static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
+ u32 val)
+{
+ if (drvdata-dcr_splb_slave_if == 1)
+ out_be32(drvdata-regs + (offset 2), val);
+
Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)
Hi John, On Wed, 8 Apr 2009 15:11:25 -0600 John Linn john.l...@xilinx.com wrote: * 2002-2007 (c) MontaVista Software, Inc. * 2007 (c) Secret Lab Technologies, Ltd. + * 2009 (c) Xilinx Inc. * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed as is without any warranty of any - * kind, whether express or implied. + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General Public + * License as published by the Free Software Foundation; + * either version 2 of the License, or (at your option) any + * later version. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. This changes the license for this file (from GPLv2 to GPLv2 or later). Have you asked the other copyright owners about that? -- Cheers, Stephen Rothwells...@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ pgpvlWOQzo3Ac.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
