Re: [PATCH] powerpc/fsl: Add cache properties for T2080/T2081
On Wed, 2020-03-25 at 15:38 +1300, Chris Packham wrote:
> On Tue, 2020-03-24 at 21:08 -0500, Scott Wood wrote:
> > On Wed, 2020-03-25 at 12:59 +1100, Michael Ellerman wrote:
> > > Chris Packham writes:
> > > > Add the d-cache/i-cache properties for the T208x SoCs. The L1
> > > > cache on
> > > > these SoCs is 32KiB and is split into 64 byte blocks (lines).
> > > >
> > > > Signed-off-by: Chris Packham > > > >
> > > > ---
> > > > arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16
> > > >
> > > > 1 file changed, 16 insertions(+)
> > >
> > > LGTM.
> > >
> > > I'll wait a few days to see if Scott wants to ack it.
> > >
> > > cheers
> > >
> > >
> > > > diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > > b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > > index 3f745de44284..2ad27e16ac16 100644
> > > > --- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > > +++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > > @@ -81,6 +81,10 @@ cpus {
> > > > cpu0: PowerPC,e6500@0 {
> > > > device_type = "cpu";
> > > > reg = <0 1>;
> > > > + d-cache-line-size = <64>;
> > > > + i-cache-line-size = <64>;
> > > > + d-cache-size = <32768>;
> > > > + i-cache-size = <32768>;
> > > > clocks = <&clockgen 1 0>;
> > > > next-level-cache = <&L2_1>;
> > > > fsl,portid-mapping = <0x8000>;
> >
> > U-Boot should be setting d/i-cache-size and d/i-cache-block-size --
> > are you
> > using something else?
>
> Nope it is u-boot specifically
>
> U-Boot 2017.01-rc3-dirty
>
> I'm pretty sure the '-dirty' is just a change to use a different
> cross-
> compiler but I can't confirm and I'm a little hesitant to try
> updating
> as I've only got remote access to the board right now.
>
> >
> > The line size is the same as the block size so we don't need a
> > separate d/i-
> > cache-line-size.
> >
>
> I'm not sure that'll work looking at the code[1]. It has logic to set
> bsizep to lsizep if no block size is set but not the other way round.
> Looking at the spec from devicetree.org this actually seems wrong.
> Perhaps that is the real source of the error.
Sure enough without my change
# ls /sys/firmware/devicetree/base/cpus/PowerPC,e6500@0/
bus-frequency d-cache-sizename
cache-stash-id device_type next-level-cache
clock-frequency enable-method phandle
clocks fsl,portid-mapping reg
cpu-release-addri-cache-block-size status
d-cache-block-size i-cache-setstimebase-frequency
d-cache-setsi-cache-size
So it's the lack of handling the optional line-size. Different patch
incomming.
>
> --
> [1] -
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/setup_64.c#n510
>
>
Re: [PATCH] powerpc/fsl: Add cache properties for T2080/T2081
On Tue, 2020-03-24 at 21:08 -0500, Scott Wood wrote:
> On Wed, 2020-03-25 at 12:59 +1100, Michael Ellerman wrote:
> > Chris Packham writes:
> > > Add the d-cache/i-cache properties for the T208x SoCs. The L1
> > > cache on
> > > these SoCs is 32KiB and is split into 64 byte blocks (lines).
> > >
> > > Signed-off-by: Chris Packham
> > > ---
> > > arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16
> > > 1 file changed, 16 insertions(+)
> >
> > LGTM.
> >
> > I'll wait a few days to see if Scott wants to ack it.
> >
> > cheers
> >
> >
> > > diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > index 3f745de44284..2ad27e16ac16 100644
> > > --- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > +++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > > @@ -81,6 +81,10 @@ cpus {
> > > cpu0: PowerPC,e6500@0 {
> > > device_type = "cpu";
> > > reg = <0 1>;
> > > + d-cache-line-size = <64>;
> > > + i-cache-line-size = <64>;
> > > + d-cache-size = <32768>;
> > > + i-cache-size = <32768>;
> > > clocks = <&clockgen 1 0>;
> > > next-level-cache = <&L2_1>;
> > > fsl,portid-mapping = <0x8000>;
>
> U-Boot should be setting d/i-cache-size and d/i-cache-block-size --
> are you
> using something else?
Nope it is u-boot specifically
U-Boot 2017.01-rc3-dirty
I'm pretty sure the '-dirty' is just a change to use a different cross-
compiler but I can't confirm and I'm a little hesitant to try updating
as I've only got remote access to the board right now.
>
> The line size is the same as the block size so we don't need a
> separate d/i-
> cache-line-size.
>
I'm not sure that'll work looking at the code[1]. It has logic to set
bsizep to lsizep if no block size is set but not the other way round.
Looking at the spec from devicetree.org this actually seems wrong.
Perhaps that is the real source of the error.
--
[1] -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/setup_64.c#n510
Re: [PATCH] powerpc/fsl: Add cache properties for T2080/T2081
On Wed, 2020-03-25 at 12:59 +1100, Michael Ellerman wrote:
> Chris Packham writes:
> > Add the d-cache/i-cache properties for the T208x SoCs. The L1 cache on
> > these SoCs is 32KiB and is split into 64 byte blocks (lines).
> >
> > Signed-off-by: Chris Packham
> > ---
> > arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16
> > 1 file changed, 16 insertions(+)
>
> LGTM.
>
> I'll wait a few days to see if Scott wants to ack it.
>
> cheers
>
>
> > diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > index 3f745de44284..2ad27e16ac16 100644
> > --- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> > @@ -81,6 +81,10 @@ cpus {
> > cpu0: PowerPC,e6500@0 {
> > device_type = "cpu";
> > reg = <0 1>;
> > + d-cache-line-size = <64>;
> > + i-cache-line-size = <64>;
> > + d-cache-size = <32768>;
> > + i-cache-size = <32768>;
> > clocks = <&clockgen 1 0>;
> > next-level-cache = <&L2_1>;
> > fsl,portid-mapping = <0x8000>;
U-Boot should be setting d/i-cache-size and d/i-cache-block-size -- are you
using something else?
The line size is the same as the block size so we don't need a separate d/i-
cache-line-size.
-Scott
Re: [PATCH] powerpc/fsl: Add cache properties for T2080/T2081
Chris Packham writes:
> Add the d-cache/i-cache properties for the T208x SoCs. The L1 cache on
> these SoCs is 32KiB and is split into 64 byte blocks (lines).
>
> Signed-off-by: Chris Packham
> ---
> arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16
> 1 file changed, 16 insertions(+)
LGTM.
I'll wait a few days to see if Scott wants to ack it.
cheers
> diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> index 3f745de44284..2ad27e16ac16 100644
> --- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
> @@ -81,6 +81,10 @@ cpus {
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> @@ -88,6 +92,10 @@ cpu0: PowerPC,e6500@0 {
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> @@ -95,6 +103,10 @@ cpu1: PowerPC,e6500@2 {
> cpu2: PowerPC,e6500@4 {
> device_type = "cpu";
> reg = <4 5>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> @@ -102,6 +114,10 @@ cpu2: PowerPC,e6500@4 {
> cpu3: PowerPC,e6500@6 {
> device_type = "cpu";
> reg = <6 7>;
> + d-cache-line-size = <64>;
> + i-cache-line-size = <64>;
> + d-cache-size = <32768>;
> + i-cache-size = <32768>;
> clocks = <&clockgen 1 0>;
> next-level-cache = <&L2_1>;
> fsl,portid-mapping = <0x8000>;
> --
> 2.25.1
[PATCH] powerpc/fsl: Add cache properties for T2080/T2081
Add the d-cache/i-cache properties for the T208x SoCs. The L1 cache on
these SoCs is 32KiB and is split into 64 byte blocks (lines).
Signed-off-by: Chris Packham
---
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
index 3f745de44284..2ad27e16ac16 100644
--- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
@@ -81,6 +81,10 @@ cpus {
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
@@ -88,6 +92,10 @@ cpu0: PowerPC,e6500@0 {
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
@@ -95,6 +103,10 @@ cpu1: PowerPC,e6500@2 {
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
@@ -102,6 +114,10 @@ cpu2: PowerPC,e6500@4 {
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
+ d-cache-line-size = <64>;
+ i-cache-line-size = <64>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x8000>;
--
2.25.1
