Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.
Signed-off-by: Matt Evans
---
Boot-tested on pseries and G5.
arch/powerpc/include/asm/cputable.h| 52 ++-
arch/powerpc/include/asm/mmu.h | 28 +++
arch/powerpc/include/asm/mmu_context.h |2 +-
arch/powerpc/kernel/cputable.c | 39 ++---
arch/powerpc/kernel/entry_64.S |8 ++--
arch/powerpc/kernel/exceptions-64s.S |4 +-
arch/powerpc/kernel/process.c |4 +-
arch/powerpc/kernel/prom.c | 17 +
arch/powerpc/kernel/setup_64.c |2 +-
arch/powerpc/mm/hash_low_64.S |8 ++--
arch/powerpc/mm/hash_native_64.c |8 ++--
arch/powerpc/mm/hash_utils_64.c| 18 +-
arch/powerpc/mm/hugetlbpage.c |2 +-
arch/powerpc/mm/slb.c |4 +-
arch/powerpc/mm/slb_low.S |8 ++--
arch/powerpc/mm/stab.c |2 +-
arch/powerpc/platforms/iseries/exception.S |2 +-
arch/powerpc/platforms/iseries/setup.c |4 +-
arch/powerpc/platforms/pseries/lpar.c |2 +-
arch/powerpc/xmon/xmon.c |2 +-
20 files changed, 123 insertions(+), 93 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index be3cdf9..7b0fe7c 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
#define LONG_ASM_CONST(x) 0
#endif
-#define CPU_FTR_SLBLONG_ASM_CONST(0x0001)
-#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0002)
-#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0004)
#define CPU_FTR_IABR LONG_ASM_CONST(0x0020)
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0040)
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0080)
#define CPU_FTR_SMTLONG_ASM_CONST(0x0100)
-#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0400)
-#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x1000)
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x2000)
#define CPU_FTR_PURR LONG_ASM_CONST(0x4000)
#define CPU_FTR_CELL_TB_BUGLONG_ASM_CONST(0x8000)
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001)
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002)
-#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004)
-#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008)
#define CPU_FTR_VSXLONG_ASM_CONST(0x0010)
#define CPU_FTR_SAOLONG_ASM_CONST(0x0020)
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040)
@@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
#ifndef __ASSEMBLY__
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
-CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
-CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
+#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
+MMU_FTR_16M_PAGE)
/* We only set the altivec features if the kernel was compiled with altivec
* support
@@ -405,41 +399,49 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_POWER5(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
- CPU_FTR_POPCNTB)
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
+ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | CPU_FTR_SPURR | \
+ CPU_FTR_REAL_LE | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT |
