[PATCH 1/2] Adding PCI-E support for PowerPC 460SX based SOC.

2009-12-22 Thread tmarri 
From: Tirumala Marri tma...@amcc.com


Signed-off-by: Tirumala Marri tma...@amcc.com
---
Kerenl:2.6.33-rc1
Testing: This patch has been tested on 460SX based redwood board . One board 
configured as  
root complex and other as Endpoint. Checked for link up . From root complex 
lspci command
shows the end point. Also programmed IO tested using loop back as well as board 
to board.
---
 arch/powerpc/boot/dts/redwood.dts |  122 +
 arch/powerpc/sysdev/ppc4xx_pci.c  |  119 
 arch/powerpc/sysdev/ppc4xx_pci.h  |   58 +
 3 files changed, 299 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/redwood.dts 
b/arch/powerpc/boot/dts/redwood.dts
index d2af32e..81636c0 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -234,10 +234,132 @@
has-inverted-stacr-oc;
has-new-stacr-staopc;
};
+   };
+   PCIE0: pc...@d {
+   device_type = pci;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+   primary;
+   port = 0x0; /* port number */
+   reg = 0x000d 0x 0x2000 /* Config space 
access */
+  0x000c 0x1000 0x1000;   /* 
Registers */
+   dcr-reg = 0x100 0x020;
+   sdr-base = 0x300;
+
+   /* Outbound ranges, one memory and one IO,
+* later cannot be changed
+*/
+   ranges = 0x0200 0x 0x8000 0x000e 
0x 0x 0x8000
+ 0x0100 0x 0x 0x000f 
0x8000 0x 0x0001;
+
+   /* Inbound 2GB range starting at 0 */
+   dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0 
0x8000;
 
+   /* This drives busses 10 to 0x1f */
+   bus-range = 0x10 0x1f;
+
+   /* Legacy interrupts (note the weird polarity, the 
bridge seems
+* to invert PCIe legacy interrupts).
+* We are de-swizzling here because the numbers are 
actually for
+* port of the root complex virtual P2P bridge. But I 
want
+* to avoid putting a node for it in the tree, so the 
numbers
+* below are basically de-swizzled numbers.
+* The real slot is on idsel 0, so the swizzling is 1:1
+*/
+   interrupt-map-mask = 0x0 0x0 0x0 0x7;
+   interrupt-map = 
+   0x0 0x0 0x0 0x1 UIC3 0x0 0x4 /* swizzled int A 
*/
+   0x0 0x0 0x0 0x2 UIC3 0x1 0x4 /* swizzled int B 
*/
+   0x0 0x0 0x0 0x3 UIC3 0x2 0x4 /* swizzled int C 
*/
+   0x0 0x0 0x0 0x4 UIC3 0x3 0x4 /* swizzled int D 
*/;
+   };
+
+   PCIE1: pc...@d2000 {
+   device_type = pci;
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+   primary;
+   port = 0x1; /* port number */
+   reg = 0x000d 0x2000 0x2000 /* Config space 
access */
+  0x000c 0x10001000 0x1000;   /* 
Registers */
+   dcr-reg = 0x120 0x020;
+   sdr-base = 0x340;
+
+   /* Outbound ranges, one memory and one IO,
+* later cannot be changed
+*/
+   ranges = 0x0200 0x 0x8000 0x000e 
0x8000 0x 0x8000
+ 0x0100 0x 0x 0x000f 
0x8001 0x 0x0001;
+
+   /* Inbound 2GB range starting at 0 */
+   dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0 
0x8000;
+
+   /* This drives busses 10 to 0x1f */
+   bus-range = 0x20 0x2f;
+
+   /* Legacy interrupts (note the weird polarity, the 
bridge seems
+* to invert PCIe legacy interrupts).
+* We are de-swizzling here because the numbers are 
actually for
+* port of the root complex virtual P2P bridge. But I 
want
+* to avoid putting a node for it

Re: [PATCH 1/2] Adding PCI-E support for PowerPC 460SX based SOC.

2009-12-22 Thread Josh Boyer 
On Tue, Dec 22, 2009 at 12:49:41AM -0800, tma...@amcc.com wrote:
From: Tirumala Marri tma...@amcc.com


Signed-off-by: Tirumala Marri tma...@amcc.com

Acked-by: Josh Boyer jwbo...@linux.vnet.ibm.com

Ben, do you want to take this through your tree or mine?

josh

---
Kerenl:2.6.33-rc1
Testing: This patch has been tested on 460SX based redwood board . One board 
configured as  
root complex and other as Endpoint. Checked for link up . From root complex 
lspci command
shows the end point. Also programmed IO tested using loop back as well as 
board to board.
---
 arch/powerpc/boot/dts/redwood.dts |  122 +
 arch/powerpc/sysdev/ppc4xx_pci.c  |  119 
 arch/powerpc/sysdev/ppc4xx_pci.h  |   58 +
 3 files changed, 299 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/redwood.dts 
b/arch/powerpc/boot/dts/redwood.dts
index d2af32e..81636c0 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -234,10 +234,132 @@
   has-inverted-stacr-oc;
   has-new-stacr-staopc;
   };
+  };
+  PCIE0: pc...@d {
+  device_type = pci;
+  #interrupt-cells = 1;
+  #size-cells = 2;
+  #address-cells = 3;
+  compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+  primary;
+  port = 0x0; /* port number */
+  reg = 0x000d 0x 0x2000 /* Config space 
access */
+ 0x000c 0x1000 0x1000;   /* 
Registers */
+  dcr-reg = 0x100 0x020;
+  sdr-base = 0x300;
+
+  /* Outbound ranges, one memory and one IO,
+   * later cannot be changed
+   */
+  ranges = 0x0200 0x 0x8000 0x000e 
0x 0x 0x8000
+0x0100 0x 0x 0x000f 
0x8000 0x 0x0001;
+
+  /* Inbound 2GB range starting at 0 */
+  dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0 
0x8000;
 
+  /* This drives busses 10 to 0x1f */
+  bus-range = 0x10 0x1f;
+
+  /* Legacy interrupts (note the weird polarity, the 
bridge seems
+   * to invert PCIe legacy interrupts).
+   * We are de-swizzling here because the numbers are 
actually for
+   * port of the root complex virtual P2P bridge. But I 
want
+   * to avoid putting a node for it in the tree, so the 
numbers
+   * below are basically de-swizzled numbers.
+   * The real slot is on idsel 0, so the swizzling is 1:1
+   */
+  interrupt-map-mask = 0x0 0x0 0x0 0x7;
+  interrupt-map = 
+  0x0 0x0 0x0 0x1 UIC3 0x0 0x4 /* swizzled int A 
*/
+  0x0 0x0 0x0 0x2 UIC3 0x1 0x4 /* swizzled int B 
*/
+  0x0 0x0 0x0 0x3 UIC3 0x2 0x4 /* swizzled int C 
*/
+  0x0 0x0 0x0 0x4 UIC3 0x3 0x4 /* swizzled int D 
*/;
+  };
+
+  PCIE1: pc...@d2000 {
+  device_type = pci;
+  #interrupt-cells = 1;
+  #size-cells = 2;
+  #address-cells = 3;
+  compatible = ibm,plb-pciex-460sx, ibm,plb-pciex;
+  primary;
+  port = 0x1; /* port number */
+  reg = 0x000d 0x2000 0x2000 /* Config space 
access */
+ 0x000c 0x10001000 0x1000;   /* 
Registers */
+  dcr-reg = 0x120 0x020;
+  sdr-base = 0x340;
+
+  /* Outbound ranges, one memory and one IO,
+   * later cannot be changed
+   */
+  ranges = 0x0200 0x 0x8000 0x000e 
0x8000 0x 0x8000
+0x0100 0x 0x 0x000f 
0x8001 0x 0x0001;
+
+  /* Inbound 2GB range starting at 0 */
+  dma-ranges = 0x4200 0x0 0x0 0x0 0x0 0x0 
0x8000;
+
+  /* This drives busses 10 to 0x1f */
+  bus-range = 0x20 0x2f;
+
+  /* Legacy interrupts (note the weird polarity, the 
bridge seems
+   * to invert PCIe legacy interrupts).
+   * We are de-swizzling here because the numbers are 
actually for
+   *