Re: [PATCH 1/3] mpc83xx: Power Management support
Kumar Gala wrote: On Jul 2, 2008, at 12:12 PM, Scott Wood wrote: Kumar Gala wrote: +#define SS_MEMSAVE0x00 What is this? add a comment? There's a comment where MEMSAVE is used: /* The first 2 words of memory are used to communicate with the I read this as the memory address 0, 0x4. do you mean the first two words of the save area? Both. Memory addresses 0 and 4 are saved in the first two words of the save area, so that we can overwrite the former with the magic number and resume address. * bootloader, to tell it how to resume. * * The first word is the magic number 0xf5153ae5, and the second * is the pointer to mpc83xx_deep_resume. * * The original content of these two words is saved in the state * save area. */ We could stick a /* First 8 bytes of RAM */ after the #define if you want. ahh, might be useful to add SS_MEMSAVE into the comment. OK. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
On Jul 2, 2008, at 12:12 PM, Scott Wood wrote: Kumar Gala wrote: +#define SS_MEMSAVE0x00 What is this? add a comment? There's a comment where MEMSAVE is used: /* The first 2 words of memory are used to communicate with the I read this as the memory address 0, 0x4. do you mean the first two words of the save area? * bootloader, to tell it how to resume. * * The first word is the magic number 0xf5153ae5, and the second * is the pointer to mpc83xx_deep_resume. * * The original content of these two words is saved in the state * save area. */ We could stick a /* First 8 bytes of RAM */ after the #define if you want. ahh, might be useful to add SS_MEMSAVE into the comment. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
Kumar Gala wrote: +#define SS_MEMSAVE0x00 What is this? add a comment? There's a comment where MEMSAVE is used: /* The first 2 words of memory are used to communicate with the * bootloader, to tell it how to resume. * * The first word is the magic number 0xf5153ae5, and the second * is the pointer to mpc83xx_deep_resume. * * The original content of these two words is saved in the state * save area. */ We could stick a /* First 8 bytes of RAM */ after the #define if you want. +#define SS_HID0x08 /* 3 HIDs */ +#define SS_IABR0x14 /* 2 IABRs */ +#define SS_IBCR0x1c +#define SS_DABR0x20 /* 2 DABRs */ +#define SS_DBCR0x28 +#define SS_SP0x2c +#define SS_SR0x30 /* 16 segment registers */ +#define SS_CURRENT0x70 How about SS_R2 to match the pmac sleep.S code. It will make refactoring all this easier in the future. OK. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
diff --git a/arch/powerpc/platforms/83xx/suspend-asm.S b/arch/ powerpc/platforms/83xx/suspend-asm.S new file mode 100644 index 000..03e29a2 --- /dev/null +++ b/arch/powerpc/platforms/83xx/suspend-asm.S @@ -0,0 +1,539 @@ +/* + * Enter and leave sleep state on MPC83xx + * + * Author: Scott Wood <[EMAIL PROTECTED]> + * + * Copyright (c) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#define SS_MEMSAVE 0x00 What is this? add a comment? +#define SS_HID 0x08 /* 3 HIDs */ +#define SS_IABR0x14 /* 2 IABRs */ +#define SS_IBCR0x1c +#define SS_DABR0x20 /* 2 DABRs */ +#define SS_DBCR0x28 +#define SS_SP 0x2c +#define SS_SR 0x30 /* 16 segment registers */ +#define SS_CURRENT 0x70 How about SS_R2 to match the pmac sleep.S code. It will make refactoring all this easier in the future. +#define SS_MSR 0x74 +#define SS_SDR10x78 +#define SS_LR 0x7c +#define SS_SPRG0x80 /* 4 SPRGs */ +#define SS_DBAT0x90 /* 8 DBATs */ +#define SS_IBAT0xd0 /* 8 IBATs */ +#define SS_TB 0x110 +#define SS_CR 0x118 +#define SS_GPREG 0x11c /* r12-r31 */ +#define STATE_SAVE_SIZE 0x16c - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
Kumar Gala wrote: If we are going to allocate space for save area like this, can't we do this in C code. Its less error prone and easier to extend over time. I know the powermac code does something similar but it places the save area on the stack. Then we'd have to split it between things that can be saved from C versus things that can't (gpregs, cr, lr, etc), or mess around with exposing struct offsets to asm code. I think it's just easier to do it this way. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
diff --git a/arch/powerpc/platforms/83xx/suspend-asm.S b/arch/
powerpc/platforms/83xx/suspend-asm.S
new file mode 100644
index 000..03e29a2
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/suspend-asm.S
@@ -0,0 +1,539 @@
+/*
+ * Enter and leave sleep state on MPC83xx
+ *
+ * Author: Scott Wood <[EMAIL PROTECTED]>
+ *
+ * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License version 2 as
published
+ * by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+
+#define SS_MEMSAVE 0x00
+#define SS_HID 0x08 /* 3 HIDs */
+#define SS_IABR0x14 /* 2 IABRs */
+#define SS_IBCR0x1c
+#define SS_DABR0x20 /* 2 DABRs */
+#define SS_DBCR0x28
+#define SS_SP 0x2c
+#define SS_SR 0x30 /* 16 segment registers */
+#define SS_CURRENT 0x70
+#define SS_MSR 0x74
+#define SS_SDR10x78
+#define SS_LR 0x7c
+#define SS_SPRG0x80 /* 4 SPRGs */
+#define SS_DBAT0x90 /* 8 DBATs */
+#define SS_IBAT0xd0 /* 8 IBATs */
+#define SS_TB 0x110
+#define SS_CR 0x118
+#define SS_GPREG 0x11c /* r12-r31 */
+#define STATE_SAVE_SIZE 0x16c
+
+ .section .data
+ .align 5
+
+mpc83xx_sleep_save_area:
+ .space STATE_SAVE_SIZE
+immrbase:
+ .long 0
If we are going to allocate space for save area like this, can't we do
this in C code. Its less error prone and easier to extend over time.
I know the powermac code does something similar but it places the save
area on the stack.
It also seems like the core register save/restore should be shared
between 83xx and 5{1,2}xx but that would be a longer term goal.
- k
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Re: [PATCH 1/3] mpc83xx: Power Management support
On Jun 26, 2008, at 9:39 AM, Liu Dave wrote: Basic PM support for 83xx. Standby is implemented as sleep. Suspend-to-RAM is implemented as "deep sleep" (with the processor turned off) on 831x. PCI agent power management is supported. Device power management of SOC peripherals is not yet supported. (Not comments on this patch, but related) Do you know if anyone is looking at making sure DOZE/NAP work on 83xx? We clearly don't flush the L1 cache today in the 6xx code. I did the test on 837x, the NAP did *not* work, due to the cache coherence issue. You are right, currently no flush L1 in the 6xx code, maybe it depend on the platform hardware capability. Ben told me the pmac HW/chipsets did something here to ensure that the core never actually went into NAP (or something like that) so they didn't have to flush the caches. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: [PATCH 1/3] mpc83xx: Power Management support
> > Basic PM support for 83xx. Standby is implemented as sleep. > > Suspend-to-RAM is implemented as "deep sleep" (with the processor > > turned off) on 831x. PCI agent power management is supported. > > > > Device power management of SOC peripherals is not yet supported. > > (Not comments on this patch, but related) > > Do you know if anyone is looking at making sure DOZE/NAP work on > 83xx? We clearly don't flush the L1 cache today in the 6xx code. I did the test on 837x, the NAP did *not* work, due to the cache coherence issue. You are right, currently no flush L1 in the 6xx code, maybe it depend on the platform hardware capability. Dave ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
Kumar Gala wrote: On Jun 25, 2008, at 4:50 PM, Scott Wood wrote: Basic PM support for 83xx. Standby is implemented as sleep. Suspend-to-RAM is implemented as "deep sleep" (with the processor turned off) on 831x. PCI agent power management is supported. Device power management of SOC peripherals is not yet supported. (Not comments on this patch, but related) Do you know if anyone is looking at making sure DOZE/NAP work on 83xx? We clearly don't flush the L1 cache today in the 6xx code. Doze should work (a long time ago when I did power measurements I saw a drop in consumption once Linux started, and the system was idle)... Nap is not supported, and should probably be removed from the e300 cputable entry. I don't think it's worthwhile to flush the cache every time the cpu is idle just to nap instead of doze. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] mpc83xx: Power Management support
On Jun 25, 2008, at 4:50 PM, Scott Wood wrote: Basic PM support for 83xx. Standby is implemented as sleep. Suspend-to-RAM is implemented as "deep sleep" (with the processor turned off) on 831x. PCI agent power management is supported. Device power management of SOC peripherals is not yet supported. (Not comments on this patch, but related) Do you know if anyone is looking at making sure DOZE/NAP work on 83xx? We clearly don't flush the L1 cache today in the 6xx code. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/3] mpc83xx: Power Management support
Basic PM support for 83xx. Standby is implemented as sleep. Suspend-to-RAM is implemented as "deep sleep" (with the processor turned off) on 831x. PCI agent power management is supported. Device power management of SOC peripherals is not yet supported. Signed-off-by: Scott Wood <[EMAIL PROTECTED]> --- arch/powerpc/Kconfig |2 +- arch/powerpc/platforms/83xx/Makefile |1 + arch/powerpc/platforms/83xx/suspend-asm.S | 539 + arch/powerpc/platforms/83xx/suspend.c | 390 + arch/powerpc/sysdev/fsl_soc.h |1 + arch/powerpc/sysdev/ipic.c| 71 include/asm-powerpc/reg.h |4 + include/linux/fsl_devices.h |6 + 8 files changed, 1013 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/platforms/83xx/suspend-asm.S create mode 100644 arch/powerpc/platforms/83xx/suspend.c diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2cde4e3..8280b33 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -192,7 +192,7 @@ config ARCH_HIBERNATION_POSSIBLE config ARCH_SUSPEND_POSSIBLE def_bool y - depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 + depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx config PPC_DCR_NATIVE bool diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile index f331fd7..32c7ad1 100644 --- a/arch/powerpc/platforms/83xx/Makefile +++ b/arch/powerpc/platforms/83xx/Makefile @@ -3,6 +3,7 @@ # obj-y := misc.o usb.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o diff --git a/arch/powerpc/platforms/83xx/suspend-asm.S b/arch/powerpc/platforms/83xx/suspend-asm.S new file mode 100644 index 000..03e29a2 --- /dev/null +++ b/arch/powerpc/platforms/83xx/suspend-asm.S @@ -0,0 +1,539 @@ +/* + * Enter and leave sleep state on MPC83xx + * + * Author: Scott Wood <[EMAIL PROTECTED]> + * + * Copyright (c) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#define SS_MEMSAVE 0x00 +#define SS_HID 0x08 /* 3 HIDs */ +#define SS_IABR0x14 /* 2 IABRs */ +#define SS_IBCR0x1c +#define SS_DABR0x20 /* 2 DABRs */ +#define SS_DBCR0x28 +#define SS_SP 0x2c +#define SS_SR 0x30 /* 16 segment registers */ +#define SS_CURRENT 0x70 +#define SS_MSR 0x74 +#define SS_SDR10x78 +#define SS_LR 0x7c +#define SS_SPRG0x80 /* 4 SPRGs */ +#define SS_DBAT0x90 /* 8 DBATs */ +#define SS_IBAT0xd0 /* 8 IBATs */ +#define SS_TB 0x110 +#define SS_CR 0x118 +#define SS_GPREG 0x11c /* r12-r31 */ +#define STATE_SAVE_SIZE 0x16c + + .section .data + .align 5 + +mpc83xx_sleep_save_area: + .space STATE_SAVE_SIZE +immrbase: + .long 0 + + .section .text + .align 5 + + /* r3 = physical address of IMMR */ +_GLOBAL(mpc83xx_enter_deep_sleep) + /* Re-use the state saving/restoring code in +* arch/powerpc/kernel/swsusp_32.S, but have +* it call us instead of swsusp_save. +*/ + + lis r4, [EMAIL PROTECTED] + stw r3, [EMAIL PROTECTED](r4) + + /* The first 2 words of memory are used to communicate with the +* bootloader, to tell it how to resume. +* +* The first word is the magic number 0xf5153ae5, and the second +* is the pointer to mpc83xx_deep_resume. +* +* The original content of these two words is saved in the state +* save area. +*/ + + lis r3, [EMAIL PROTECTED] + ori r3, r3, [EMAIL PROTECTED] + + lis r4, [EMAIL PROTECTED] + lwz r5, 0(r4) + lwz r6, 4(r4) + + stw r5, SS_MEMSAVE+0(r3) + stw r6, SS_MEMSAVE+4(r3) + + mfspr r5, SPRN_HID0 + mfspr r6, SPRN_HID1 + mfspr r7, SPRN_HID2 + + stw r5, SS_HID+0(r3) + stw r6, SS_HID+4(r3) + stw r7, SS_HID+8(r3) + + mfspr r4, SPRN_IABR + mfspr r5, SPRN_IABR2 + mfspr r6, SPRN_IBCR + mfspr r7, SPRN_DABR + mfspr r8, SPRN_DABR2 + mfspr r9, SPRN_DBCR + + stw r4, SS_IABR+0(r3) + stw r5, SS_IABR+4(r3) + stw r6, SS_IBCR(r3) + stw r7, SS_DABR+0(r3) + stw r8, SS_DABR+4(r3) + stw r9, SS_DBCR(r3) + + mfspr r4, SPRN_SPRG0 + mfspr r5
