Re: [PATCH 1/3] powerpc/64s: Mask NIP before checking against SRR0

2021-12-26 Thread Michael Ellerman 
On Wed, 22 Dec 2021 00:50:59 +1100, Michael Ellerman wrote:
> When CONFIG_PPC_RFI_SRR_DEBUG=y we check that NIP and SRR0 match when
> returning from interrupts. This can trigger falsely if NIP has either of
> its two low bits set via sigreturn or ptrace, while SRR0 has its low two
> bits masked in hardware.
> 
> As a quick fix make sure to mask the low bits before doing the check.
> 
> [...]

Applied to powerpc/next.

[1/3] powerpc/64s: Mask NIP before checking against SRR0
  https://git.kernel.org/powerpc/c/314f6c23dd8d417281eb9e8a516dd98036f2e7b3
[2/3] powerpc/64s: Use EMIT_WARN_ENTRY for SRR debug warnings
  https://git.kernel.org/powerpc/c/fd1ea6864b5fb8f99880fcefb49760b8fe4e
[3/3] selftests/powerpc: Add a test of sigreturning to an unaligned address
  https://git.kernel.org/powerpc/c/beeac538c366cd2828092adecd1edab28326c55b

cheers

Re: [PATCH 1/3] powerpc/64s: Mask NIP before checking against SRR0

2021-12-22 Thread Sachin Sant 


> On 21-Dec-2021, at 7:20 PM, Michael Ellerman  wrote:
> 
> When CONFIG_PPC_RFI_SRR_DEBUG=y we check that NIP and SRR0 match when
> returning from interrupts. This can trigger falsely if NIP has either of
> its two low bits set via sigreturn or ptrace, while SRR0 has its low two
> bits masked in hardware.
> 
> As a quick fix make sure to mask the low bits before doing the check.
> 
> Fixes: 59dc5bfca0cb ("powerpc/64s: avoid reloading (H)SRR registers if they 
> are still valid")
> Reported-by: Sachin Sant 
> Signed-off-by: Michael Ellerman 
> ---

Tested this 3 patch series successfully (with and without PPC_RFI_SRR_DEBUG)
on Power9/Power10 LPAR as well as Power9 PowerNV. 

Tested-by: Sachin Sant

[PATCH 1/3] powerpc/64s: Mask NIP before checking against SRR0

2021-12-21 Thread Michael Ellerman 
When CONFIG_PPC_RFI_SRR_DEBUG=y we check that NIP and SRR0 match when
returning from interrupts. This can trigger falsely if NIP has either of
its two low bits set via sigreturn or ptrace, while SRR0 has its low two
bits masked in hardware.

As a quick fix make sure to mask the low bits before doing the check.

Fixes: 59dc5bfca0cb ("powerpc/64s: avoid reloading (H)SRR registers if they are 
still valid")
Reported-by: Sachin Sant 
Signed-off-by: Michael Ellerman 
---
 arch/powerpc/kernel/interrupt_64.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/kernel/interrupt_64.S 
b/arch/powerpc/kernel/interrupt_64.S
index 2ad223597ca2..4fd65d39d5d3 100644
--- a/arch/powerpc/kernel/interrupt_64.S
+++ b/arch/powerpc/kernel/interrupt_64.S
@@ -30,6 +30,7 @@
.ifc \srr,srr
mfspr   r11,SPRN_SRR0
ld  r12,_NIP(r1)
+   clrrdi  r12,r12,2
 100:   tdner11,r12
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
mfspr   r11,SPRN_SRR1
@@ -39,6 +40,7 @@
.else
mfspr   r11,SPRN_HSRR0
ld  r12,_NIP(r1)
+   clrrdi  r12,r12,2
 100:   tdner11,r12
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
mfspr   r11,SPRN_HSRR1
-- 
2.31.1