[PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood [EMAIL PROTECTED] --- arch/powerpc/kernel/head_8xx.S | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 901be47..e40e122 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -695,7 +695,7 @@ initial_mmu: mtspr SPRN_MI_AP, r8 mtspr SPRN_MD_AP, r8 - /* Map another 8 MByte at the IMMR to get the processor + /* Map another 512 KByte at the IMMR to get the processor * internal registers (among other things). */ #ifdef CONFIG_PIN_TLB @@ -703,12 +703,12 @@ initial_mmu: mtspr SPRN_MD_CTR, r10 #endif mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ + andis. r9, r9, 0xfff8 /* Get 512K boundary */ mr r8, r9 /* Create vaddr for TLB */ ori r8, r8, MD_EVALID /* Mark it valid */ mtspr SPRN_MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ + li r8, MD_PS512K /* Set 512K byte page */ ori r8, r8, MD_SVALID /* Make it valid */ mtspr SPRN_MD_TWC, r8 mr r8, r9 /* Create paddr for TLB */ @@ -730,13 +730,13 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT/* Create RPN for address 0 */ addis r11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we -- 1.5.3 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Sep 5, 2007, at 12:27 PM, Scott Wood wrote: 1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. The original reason to map 8M was so ioremap() could use the same wired TLB rather than allocate page table entries. It should also cover all addresses mapped to the flash as well. This was intentional, not a mistake. -- Dan ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Wed, Sep 05, 2007 at 01:36:43PM -0700, Dan Malek wrote: On Sep 5, 2007, at 12:27 PM, Scott Wood wrote: 1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. The original reason to map 8M was so ioremap() could use the same wired TLB rather than allocate page table entries. It should also cover all addresses mapped to the flash as well. This was intentional, not a mistake. intentional and mistake are not mutually exclusive. Where is the code that checks for pinned TLB entries on 8xx when doing ioremap? Why could this not be done with a 512K mapping? How was this even tested, given the obvious wrong-register mistake in the other CONFIG_PIN_TLB section? On what do you base the assumption that flash is within 8MB of the IMMR base? I didn't change it on a whim, I changed it because ioremap() wasn't working the way it currently is. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Wed, Sep 05, 2007 at 03:53:01PM -0500, Scott Wood wrote: I didn't change it on a whim, I changed it because ioremap() wasn't working the way it currently is. BTW, it seems I misremembered what the conflict was -- it's not with ioremap space, but with the default location of the consistent memory pool (at 0xff10). -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Sep 5, 2007, at 1:53 PM, Scott Wood wrote: Where is the code that checks for pinned TLB entries on 8xx when doing ioremap? I don't know. I haven't been the maintainer for the 2.6 changes. Why could this not be done with a 512K mapping? How was this even tested, given the obvious wrong-register mistake in the other CONFIG_PIN_TLB section? On what do you base the assumption that flash is within 8MB of the IMMR base? All of this worked in 2.4, many changes were part of the evolution in 2.6... configurable pinned entries, large page sizes, variations, I didn't keep track of all of this. I just assumed I'd have to fix it all if I ever needed to use it, which I haven't. The original version of 8xx could wire exactly three entries for 8M text, 8M data, and 8M IMMR plus upper device addresses. We would set the IMMR to ff80, cover the CPM, some other devices and the flash at the top of memory. If you have too much flash, this had to be adjusted accordingly, but for small systems this was a nice performance enhancement. I didn't change it on a whim, I changed it because ioremap() wasn't working the way it currently is. This processor is severely resource limited. It's far better to fix ioremap and take advantage of this performance enhancement than to further cripple it. Just like other processors test for mapping by BATs or CAMs, the 8xx and probably 4xx should test for wired mapping. Unfortunately, lots of things got messed up on 2.6 for the 8xx. I was not in the loop to approve changes, and most of my advice was ignored. :-) Thanks. -- Dan ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Wed, Sep 05, 2007 at 03:08:28PM -0700, Dan Malek wrote: All of this worked in 2.4, many changes were part of the evolution in 2.6... configurable pinned entries, large page sizes, variations, I didn't keep track of all of this. I just assumed I'd have to fix it all if I ever needed to use it, which I haven't. The original version of 8xx could wire exactly three entries for 8M text, 8M data, and 8M IMMR plus upper device addresses. We would set the IMMR to ff80, cover the CPM, some other devices and the flash at the top of memory. The IMMRs I've seen from the bootloader are ff00 (Freescale boards) and fa20 (Embedded Planet). AFAICT, the number of fixed TLB entries is fixed at 4 on these chips, so using the fourth for flash wouldn't take away any general-purpose TLB entries. I didn't change it on a whim, I changed it because ioremap() wasn't working the way it currently is. This processor is severely resource limited. It's far better to fix ioremap and take advantage of this performance enhancement than to further cripple it. Just like other processors test for mapping by BATs or CAMs, the 8xx and probably 4xx should test for wired mapping. I certainly agree that it would be nice to check -- my immediate goal is to get things working, though. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Sep 5, 2007, at 3:23 PM, Scott Wood wrote: The IMMRs I've seen from the bootloader are ff00 (Freescale boards) and fa20 (Embedded Planet). AFAICT, the number of fixed TLB entries is fixed at 4 on these chips, so using the fourth for flash wouldn't take away any general-purpose TLB entries. On these same boards, the memory controllers are usually configured to put the flash somewhere in that space as well. This is useful for flash file system performance. If you don't need that, you can allocate the space differently. The point is cover as much as you can with the IMMR entry and beyond. Some people like to map external devices out there. The 8xx variants have different TLB configurations. You can't assume anything here. Some parts don't have enough TLBs to make pinning useful, some allow hardware wiring of only 2. When using hardware wiring, it's always the upper entries that are wired. Since the number of entries varies, you can't assume which TLB index will be wired. I certainly agree that it would be nice to check -- my immediate goal is to get things working, though. It's more than nice. If you want this to work correctly and also get the performance enhancement, it needs to be done. Thanks. -- Dan ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Wed, Sep 05, 2007 at 03:42:03PM -0700, Dan Malek wrote: On Sep 5, 2007, at 3:23 PM, Scott Wood wrote: The IMMRs I've seen from the bootloader are ff00 (Freescale boards) and fa20 (Embedded Planet). AFAICT, the number of fixed TLB entries is fixed at 4 on these chips, so using the fourth for flash wouldn't take away any general-purpose TLB entries. On these same boards, the memory controllers are usually configured to put the flash somewhere in that space as well. Not on any of the boards I've worked with. I certainly agree that it would be nice to check -- my immediate goal is to get things working, though. It's more than nice. If you want this to work correctly and also get the performance enhancement, it needs to be done. And my point was that getting that performance enhancement is nice. It's not there now. If you want to submit a patch to add it, go right ahead, but it's not really related to this patch. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
On Tue, 28 Aug 2007 15:17:16 -0500 Scott Wood wrote: 1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood [EMAIL PROTECTED] Acked-by: Vitaly Bordug [EMAIL PROTECTED] --- arch/powerpc/kernel/head_8xx.S | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 901be47..e40e122 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -695,7 +695,7 @@ initial_mmu: mtspr SPRN_MI_AP, r8 mtspr SPRN_MD_AP, r8 - /* Map another 8 MByte at the IMMR to get the processor + /* Map another 512 KByte at the IMMR to get the processor * internal registers (among other things). */ #ifdef CONFIG_PIN_TLB @@ -703,12 +703,12 @@ initial_mmu: mtspr SPRN_MD_CTR, r10 #endif mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ + andis. r9, r9, 0xfff8 /* Get 512K boundary */ mr r8, r9 /* Create vaddr for TLB */ orir8, r8, MD_EVALID /* Mark it valid */ mtspr SPRN_MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ + li r8, MD_PS512K /* Set 512K byte page */ orir8, r8, MD_SVALID /* Make it valid */ mtspr SPRN_MD_TWC, r8 mr r8, r9 /* Create paddr for TLB */ @@ -730,13 +730,13 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT/* Create RPN for address 0 */ addisr11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we -- Sincerely, Vitaly ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with the default ioremap region. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood [EMAIL PROTECTED] --- arch/powerpc/kernel/head_8xx.S | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 901be47..e40e122 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -695,7 +695,7 @@ initial_mmu: mtspr SPRN_MI_AP, r8 mtspr SPRN_MD_AP, r8 - /* Map another 8 MByte at the IMMR to get the processor + /* Map another 512 KByte at the IMMR to get the processor * internal registers (among other things). */ #ifdef CONFIG_PIN_TLB @@ -703,12 +703,12 @@ initial_mmu: mtspr SPRN_MD_CTR, r10 #endif mfspr r9, 638 /* Get current IMMR */ - andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ + andis. r9, r9, 0xfff8 /* Get 512K boundary */ mr r8, r9 /* Create vaddr for TLB */ ori r8, r8, MD_EVALID /* Mark it valid */ mtspr SPRN_MD_EPN, r8 - li r8, MD_PS8MEG /* Set 8M byte page */ + li r8, MD_PS512K /* Set 512K byte page */ ori r8, r8, MD_SVALID /* Make it valid */ mtspr SPRN_MD_TWC, r8 mr r8, r9 /* Create paddr for TLB */ @@ -730,13 +730,13 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT/* Create RPN for address 0 */ addis r11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080/* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we -- 1.5.0.3 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
