subject:"\[PATCH 2\/2\] powerpc\: Add 2.06 tlbie mnemonics"

[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-29 Thread Michael Neuling

From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---

 arch/powerpc/include/asm/mmu.h|5 +
 arch/powerpc/include/asm/ppc-opcode.h |4 
 arch/powerpc/kernel/cputable.c|6 --
 arch/powerpc/mm/hash_native_64.c  |   13 +++--
 4 files changed, 24 insertions(+), 4 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -52,6 +52,11 @@
  */
 #define MMU_FTR_NEED_DTLB_SW_LRU   ASM_CONST(0x0020)
 
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206  ASM_CONST(0x0040)
+
 #ifndef __ASSEMBLY__
 #include asm/cputable.h
 
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -45,10 +45,12 @@
 #define PPC_INST_STSWX 0x7c00052a
 #define PPC_INST_TLBILX0x7c24
 #define PPC_INST_WAIT  0x7c7c
+#define PPC_INST_TLBIE 0x7c000264
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)(((a)  0x1f)  16)
 #define __PPC_RB(b)(((b)  0x1f)  11)
+#define __PPC_RS(s)(((s)  0x1f)  21)
 #define __PPC_XS(s)s)  0x1f)  21) | (((s)  0x20)  5))
 #define __PPC_T_TLB(t) (((t)  0x3)  21)
 #define __PPC_WC(w)(((w)  0x3)  21)
@@ -70,6 +72,8 @@
 #define PPC_TLBILX_VA(a, b)PPC_TLBILX(3, a, b)
 #define PPC_WAIT(w)stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
+#define PPC_TLBIE(lp,a)stringify_in_c(.long PPC_INST_TLBIE | \
+  __PPC_RB(a) | __PPC_RS(lp))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (architected),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
@@ -438,7 +439,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (raw),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.num_pmcs   = 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
 #include asm/cputable.h
 #include asm/udbg.h
 #include asm/kexec.h
+#include asm/ppc-opcode.h
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va = ~0xffful;
va |= ssize  8;
-   asm volatile(tlbie %0,0 : : r (va) : memory);
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,0, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
default:
penc = mmu_psize_defs[psize].penc;
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
-   asm volatile(tlbie %0,1 : : r (va) : memory);
+   va |= 1; /* L */
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,1, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Kumar Gala



On Apr 28, 2009, at 12:03 AM, Michael Neuling wrote:


From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---

arch/powerpc/include/asm/ppc-opcode.h |3 +++
arch/powerpc/kernel/cputable.c|6 --
arch/powerpc/mm/hash_native_64.c  |   11 +--


did you miss the update to mmu.h to add MMU_FTR_TLBIE_206?


3 files changed, 16 insertions(+), 4 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -79,4 +79,7 @@
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))

+#define TLBIE(lp,a) \
+   stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
+


Can you match the format of the file and define a PPC_INST_TLBIE

- k

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Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Michael Neuling

Kumar,

  From: Milton Miller milt...@bga.com
 
  This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
  compatibilty for CPUs before 2.06.
 
  Only useful for bare metal systems.
 
  Signed-off-by: Milton Miller milt...@bga.com
  Signed-off-by: Michael Neuling mi...@neuling.org
  ---
 
  arch/powerpc/include/asm/ppc-opcode.h |3 +++
  arch/powerpc/kernel/cputable.c|6 --
  arch/powerpc/mm/hash_native_64.c  |   11 +--
 
 did you miss the update to mmu.h to add MMU_FTR_TLBIE_206?

Yep a missing quilt add.  Thanks

 
  3 files changed, 16 insertions(+), 4 deletions(-)
 
  Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
  ===
  --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
  +++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
  @@ -79,4 +79,7 @@
  #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
  __PPC_WC(w))
 
  +#define TLBIE(lp,a) \
  +   stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
  +
 
 Can you match the format of the file and define a PPC_INST_TLBIE

Sorry, I obviously just stuck my crap in there without looking at the
nice macros I could use.

Repost coming.

Mikey
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[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Michael Neuling

From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---

 arch/powerpc/include/asm/mmu.h|5 +
 arch/powerpc/include/asm/ppc-opcode.h |4 
 arch/powerpc/kernel/cputable.c|6 --
 arch/powerpc/mm/hash_native_64.c  |   13 +++--
 4 files changed, 24 insertions(+), 4 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -58,6 +58,11 @@
  */
 #define MMU_FTR_TLBILX_EARLY_OPCODEASM_CONST(0x0040)
 
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206  ASM_CONST(0x0080)
+
 #ifndef __ASSEMBLY__
 #include asm/cputable.h
 
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -46,10 +46,12 @@
 #define PPC_INST_TLBILX0x7c24
 #define PPC_INST_TLBILX_EARLY  0x7c000626
 #define PPC_INST_WAIT  0x7c7c
+#define PPC_INST_TLBIE 0x7c000264
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)((a  0x1f)  16)
 #define __PPC_RB(b)((b  0x1f)  11)
+#define __PPC_RS(s)((s  0x1f)  21)
 #define __PPC_T_TLB(t) ((t  0x3)  21)
 #define __PPC_WC(w)((w  0x3)  21)
 
@@ -78,5 +80,7 @@
 #define PPC_TLBILX_VA_EARLY(a, b)  PPC_TLBILX_EARLY(3, a, b)
 #define PPC_WAIT(w)stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
+#define PPC_TLBIE(lp,a)stringify_in_c(.long PPC_INST_TLBIE | \
+  __PPC_RB(a) | __PPC_RS(lp))
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (architected),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
@@ -438,7 +439,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (raw),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.num_pmcs   = 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
 #include asm/cputable.h
 #include asm/udbg.h
 #include asm/kexec.h
+#include asm/ppc-opcode.h
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va = ~0xffful;
va |= ssize  8;
-   asm volatile(tlbie %0,0 : : r (va) : memory);
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,0, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
default:
penc = mmu_psize_defs[psize].penc;
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
-   asm volatile(tlbie %0,1 : : r (va) : memory);
+   va |= 1; /* L */
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,1, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
}
 }
@@ -80,6

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Kumar Gala



On Apr 28, 2009, at 7:45 AM, Michael Neuling wrote:


Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -58,6 +58,11 @@
 */
#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x0040)

+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206  ASM_CONST(0x0080)
+
#ifndef __ASSEMBLY__
#include asm/cputable.h


You aren't going to like me, but I just got rid of  
MMU_FTR_TLBILX_EARLY_OPCODE and thus freed up 0x0040.  So a) patch  
will probably bitch when being applied by Ben b) we should use  
0x0040.


(suggest pulling in paulus/merge as that has the revert patch that  
removes MMU_FTR_TLBILX_EARLY_OPCODE - and paul's sent a pull request  
to linus for it.)


- k
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Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Michael Neuling

  Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
  ===
  --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
  +++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
  @@ -58,6 +58,11 @@
   */
  #define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x0040)
 
  +/* This indicates that the processor uses the ISA 2.06 server tlbie
  + * mnemonics
  + */
  +#define MMU_FTR_TLBIE_206  ASM_CONST(0x0080)
  +
  #ifndef __ASSEMBLY__
  #include asm/cputable.h
 
 You aren't going to like me, but I just got rid of  
 MMU_FTR_TLBILX_EARLY_OPCODE and thus freed up 0x0040.  So a) patch  
 will probably bitch when being applied by Ben b) we should use  
 0x0040.

Kumar :-)

 (suggest pulling in paulus/merge as that has the revert patch that  
 removes MMU_FTR_TLBILX_EARLY_OPCODE - and paul's sent a pull request  
 to linus for it.)

OK, new patches coming.

Mikey
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[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-28 Thread Michael Neuling

From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---

 arch/powerpc/include/asm/mmu.h|5 +
 arch/powerpc/include/asm/ppc-opcode.h |4 
 arch/powerpc/kernel/cputable.c|6 --
 arch/powerpc/mm/hash_native_64.c  |   13 +++--
 4 files changed, 24 insertions(+), 4 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -52,6 +52,11 @@
  */
 #define MMU_FTR_NEED_DTLB_SW_LRU   ASM_CONST(0x0020)
 
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206  ASM_CONST(0x0040)
+
 #ifndef __ASSEMBLY__
 #include asm/cputable.h
 
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -45,10 +45,12 @@
 #define PPC_INST_STSWX 0x7c00052a
 #define PPC_INST_TLBILX0x7c24
 #define PPC_INST_WAIT  0x7c7c
+#define PPC_INST_TLBIE 0x7c000264
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)((a  0x1f)  16)
 #define __PPC_RB(b)((b  0x1f)  11)
+#define __PPC_RS(s)((s  0x1f)  21)
 #define __PPC_T_TLB(t) ((t  0x3)  21)
 #define __PPC_WC(w)((w  0x3)  21)
 
@@ -69,5 +71,7 @@
 #define PPC_TLBILX_VA(a, b)PPC_TLBILX(3, a, b)
 #define PPC_WAIT(w)stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
+#define PPC_TLBIE(lp,a)stringify_in_c(.long PPC_INST_TLBIE | \
+  __PPC_RB(a) | __PPC_RS(lp))
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (architected),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
@@ -438,7 +439,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (raw),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.num_pmcs   = 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
 #include asm/cputable.h
 #include asm/udbg.h
 #include asm/kexec.h
+#include asm/ppc-opcode.h
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va = ~0xffful;
va |= ssize  8;
-   asm volatile(tlbie %0,0 : : r (va) : memory);
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,0, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
default:
penc = mmu_psize_defs[psize].penc;
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
-   asm volatile(tlbie %0,1 : : r (va) : memory);
+   va |= 1; /* L */
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,1, PPC_TLBIE(%1,%0),
+  %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
}
 }
@@ -80,6 +88,7 @@

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-27 Thread Kumar Gala



On Apr 24, 2009, at 1:24 AM, Michael Neuling wrote:


Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -38,6 +38,9 @@

static DEFINE_SPINLOCK(native_tlbie_lock);

+#define TLBIE(lp,a) \
+   stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
+


Put this ppc-opcode.h now that we have it.

- k
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Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-27 Thread Kumar Gala



On Apr 24, 2009, at 1:24 AM, Michael Neuling wrote:


Index: linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/cputable.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
@@ -195,6 +195,7 @@ extern const char *powerpc_base_platform
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020)
#define CPU_FTR_CP_USE_DCBTZLONG_ASM_CONST(0x0040)
#define CPU_FTR_UNALIGNED_LD_STDLONG_ASM_CONST(0x0080)
+#define CPU_FTR_TLBIE_206  LONG_ASM_CONST(0x0100)

#ifndef __ASSEMBLY__

@@ -409,7 +410,7 @@ extern const char *powerpc_base_platform
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-   CPU_FTR_DSCR | CPU_FTR_SAO)
+   CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_TLBIE_206)
#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \


I think our preference is to use MMU features for such things now  
instead of burning a cpu feature for it.


- k
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Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-27 Thread Kumar Gala



On Apr 27, 2009, at 2:31 PM, Kumar Gala wrote:



On Apr 24, 2009, at 1:24 AM, Michael Neuling wrote:


Index: linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/cputable.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
@@ -195,6 +195,7 @@ extern const char *powerpc_base_platform
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020)
#define CPU_FTR_CP_USE_DCBTZLONG_ASM_CONST(0x0040)
#define CPU_FTR_UNALIGNED_LD_STDLONG_ASM_CONST(0x0080)
+#define CPU_FTR_TLBIE_206  LONG_ASM_CONST(0x0100)

#ifndef __ASSEMBLY__

@@ -409,7 +410,7 @@ extern const char *powerpc_base_platform
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-   CPU_FTR_DSCR | CPU_FTR_SAO)
+   CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_TLBIE_206)
#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \


I think our preference is to use MMU features for such things now  
instead of burning a cpu feature for it.


I see Ben has already made this comment.. so I just second his notion.

- k
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[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-27 Thread Michael Neuling

From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---

 arch/powerpc/include/asm/ppc-opcode.h |3 +++
 arch/powerpc/kernel/cputable.c|6 --
 arch/powerpc/mm/hash_native_64.c  |   11 +--
 3 files changed, 16 insertions(+), 4 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -79,4 +79,7 @@
 #define PPC_WAIT(w)stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))
 
+#define TLBIE(lp,a) \
+   stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
+
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (architected),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.machine_check  = machine_check_generic,
@@ -438,7 +439,8 @@ static struct cpu_spec __initdata cpu_sp
.cpu_name   = POWER7 (raw),
.cpu_features   = CPU_FTRS_POWER7,
.cpu_user_features  = COMMON_USER_POWER7,
-   .mmu_features   = MMU_FTR_HPTE_TABLE,
+   .mmu_features   = MMU_FTR_HPTE_TABLE |
+   MMU_FTR_TLBIE_206,
.icache_bsize   = 128,
.dcache_bsize   = 128,
.num_pmcs   = 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
 #include asm/cputable.h
 #include asm/udbg.h
 #include asm/kexec.h
+#include asm/ppc-opcode.h
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,19 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va = ~0xffful;
va |= ssize  8;
-   asm volatile(tlbie %0,0 : : r (va) : memory);
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,0, TLBIE(%1,%0), %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
default:
penc = mmu_psize_defs[psize].penc;
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
-   asm volatile(tlbie %0,1 : : r (va) : memory);
+   va |= 1; /* L */
+   asm volatile(ASM_MMU_FTR_IFCLR(tlbie %0,1, TLBIE(%1,%0), %2)
+: : r (va), r(0), i (MMU_FTR_TLBIE_206)
+: memory);
break;
}
 }
@@ -80,6 +86,7 @@ static inline void __tlbiel(unsigned lon
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
+   va |= 1; /* L */
asm volatile(.long 0x7c000224 | (%0  11) | (1  21)
 : : r(va) : memory);
break;
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Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-26 Thread Benjamin Herrenschmidt

On Fri, 2009-04-24 at 16:24 +1000, Michael Neuling wrote:
 From: Milton Miller milt...@bga.com
 
 This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
 compatibilty for CPUs before 2.06.
 
 Only useful for bare metal systems.  

I'd rather stick that in mmu features rather than cpu features to
save space in the later...

Cheers,
Ben.

 Signed-off-by: Milton Miller milt...@bga.com
 Signed-off-by: Michael Neuling mi...@neuling.org
 ---
 As they say, better out than in
 ---
 
  arch/powerpc/include/asm/cputable.h |3 ++-
  arch/powerpc/mm/hash_native_64.c|   13 +++--
  2 files changed, 13 insertions(+), 3 deletions(-)
 
 Index: linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
 ===
 --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/cputable.h
 +++ linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
 @@ -195,6 +195,7 @@ extern const char *powerpc_base_platform
  #define CPU_FTR_SAO  LONG_ASM_CONST(0x0020)
  #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040)
  #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080)
 +#define CPU_FTR_TLBIE_206LONG_ASM_CONST(0x0100)
  
  #ifndef __ASSEMBLY__
  
 @@ -409,7 +410,7 @@ extern const char *powerpc_base_platform
   CPU_FTR_MMCRA | CPU_FTR_SMT | \
   CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
   CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 - CPU_FTR_DSCR | CPU_FTR_SAO)
 + CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_TLBIE_206)
  #define CPU_FTRS_CELL(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
   CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
   CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
 ===
 --- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
 +++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
 @@ -38,6 +38,9 @@
  
  static DEFINE_SPINLOCK(native_tlbie_lock);
  
 +#define TLBIE(lp,a) \
 + stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
 +
  static inline void __tlbie(unsigned long va, int psize, int ssize)
  {
   unsigned int penc;
 @@ -49,14 +52,19 @@ static inline void __tlbie(unsigned long
   case MMU_PAGE_4K:
   va = ~0xffful;
   va |= ssize  8;
 - asm volatile(tlbie %0,0 : : r (va) : memory);
 + asm volatile(ASM_FTR_IFCLR(tlbie %0,0, TLBIE(%1,%0), %2)
 +  : : r (va), r(0), i (CPU_FTR_TLBIE_206)
 +  : memory);
   break;
   default:
   penc = mmu_psize_defs[psize].penc;
   va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
   va |= penc  12;
   va |= ssize  8;
 - asm volatile(tlbie %0,1 : : r (va) : memory);
 + va |= 1; /* L */
 + asm volatile(ASM_FTR_IFCLR(tlbie %0,1, TLBIE(%1,%0), %2)
 +  : : r (va), r(0), i (CPU_FTR_TLBIE_206)
 +  : memory);
   break;
   }
  }
 @@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned lon
   va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
   va |= penc  12;
   va |= ssize  8;
 + va |= 1; /* L */
   asm volatile(.long 0x7c000224 | (%0  11) | (1  21)
: : r(va) : memory);
   break;

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[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

2009-04-24 Thread Michael Neuling

From: Milton Miller milt...@bga.com

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
As they say, better out than in
---

 arch/powerpc/include/asm/cputable.h |3 ++-
 arch/powerpc/mm/hash_native_64.c|   13 +++--
 2 files changed, 13 insertions(+), 3 deletions(-)

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/cputable.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/cputable.h
@@ -195,6 +195,7 @@ extern const char *powerpc_base_platform
 #define CPU_FTR_SAOLONG_ASM_CONST(0x0020)
 #define CPU_FTR_CP_USE_DCBTZ   LONG_ASM_CONST(0x0040)
 #define CPU_FTR_UNALIGNED_LD_STD   LONG_ASM_CONST(0x0080)
+#define CPU_FTR_TLBIE_206  LONG_ASM_CONST(0x0100)
 
 #ifndef __ASSEMBLY__
 
@@ -409,7 +410,7 @@ extern const char *powerpc_base_platform
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-   CPU_FTR_DSCR | CPU_FTR_SAO)
+   CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_TLBIE_206)
 #define CPU_FTRS_CELL  (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -38,6 +38,9 @@
 
 static DEFINE_SPINLOCK(native_tlbie_lock);
 
+#define TLBIE(lp,a) \
+   stringify_in_c(.long 0x7c000264 | ((a)  11) | ((lp)  21))
+
 static inline void __tlbie(unsigned long va, int psize, int ssize)
 {
unsigned int penc;
@@ -49,14 +52,19 @@ static inline void __tlbie(unsigned long
case MMU_PAGE_4K:
va = ~0xffful;
va |= ssize  8;
-   asm volatile(tlbie %0,0 : : r (va) : memory);
+   asm volatile(ASM_FTR_IFCLR(tlbie %0,0, TLBIE(%1,%0), %2)
+: : r (va), r(0), i (CPU_FTR_TLBIE_206)
+: memory);
break;
default:
penc = mmu_psize_defs[psize].penc;
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
-   asm volatile(tlbie %0,1 : : r (va) : memory);
+   va |= 1; /* L */
+   asm volatile(ASM_FTR_IFCLR(tlbie %0,1, TLBIE(%1,%0), %2)
+: : r (va), r(0), i (CPU_FTR_TLBIE_206)
+: memory);
break;
}
 }
@@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned lon
va = ~((1ul  mmu_psize_defs[psize].shift) - 1);
va |= penc  12;
va |= ssize  8;
+   va |= 1; /* L */
asm volatile(.long 0x7c000224 | (%0  11) | (1  21)
 : : r(va) : memory);
break;
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[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

Re: [PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

[PATCH 2/2] powerpc: Add 2.06 tlbie mnemonics

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