Re: [PATCH 8/9] mpc82xx: Update mpc8272ads, and factor out PCI and reset.

2007-08-30 Thread Scott Wood 
On Thu, Aug 30, 2007 at 09:56:16AM -0500, Kumar Gala wrote:
 It don't feel its a mishmash of crap its just how things are  
 defined.  Maybe the SOC node was a mistake, but I think we are past  
 the point of return on that.

The node itself wasn't a mistake -- the IMMR is relocatable, so it should
be under a bus node.  The mistake was assuming the PCI ranges went
straight to the CPU space, rather than getting translated through the
parent bus's ranges.  We got away with that mistake because of a similar
bug in the 32-bit PCI code.

In the past few months, this issue began to be addressed in a handful of
device trees.  In the device trees I prepared, I used separate bus and
control nodes.  In the 8544, 8548, and 8641 device trees, extra ranges
were hacked into the soc node.  All other PCI-bearing Freescale device
tree files are still broken.

I don't think a few months is an unrecoverable legacy.

 Having one platform's device tree be different just creates confusion  
 to our customers.

The intent isn't for 82xx to be different from everything else -- it's
simply the first one to get fixed in this way.  Incremental changes, and
what not.

Note that it would be quite easy to make the code accept either type of
device tree.

 While there isn't anything technically wrong with what your proposing
 it will cause support issues down the line which I want to avoid.

Such as?

-Scott
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Re: [PATCH 8/9] mpc82xx: Update mpc8272ads, and factor out PCI and reset.

2007-08-29 Thread Scott Wood 
On Wed, Aug 29, 2007 at 05:41:17PM -0500, Kumar Gala wrote:
 NACK.
 
 I don't want pq2 to be the only platform that has the PCI bus  
 separate from the PCI controller.

Could you articulate the reasons why you'd rather have a mishmash of crap
in the soc node's ranges property?

-Scott
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[PATCH 8/9] mpc82xx: Update mpc8272ads, and factor out PCI and reset.

2007-08-28 Thread Scott Wood 
1. PCI and reset are factored out into pq2.c.  I renamed them from m82xx
to pq2 because they won't work on the Integrated Host Processor line of
82xx chips (i.e. 8240, 8245, and such).

2. The PCI PIC, which is nominally board-specific, is used on multiple
boards, and thus is used into pq2ads-pci-pic.c.

3. The new CPM binding is used.

4. General cleanup.

Signed-off-by: Scott Wood [EMAIL PROTECTED]
---
 arch/powerpc/Kconfig |2 +-
 arch/powerpc/boot/dts/mpc8272ads.dts |  321 +++--
 arch/powerpc/configs/mpc8272_ads_defconfig   |  380 ---
 arch/powerpc/platforms/82xx/Kconfig  |5 +
 arch/powerpc/platforms/82xx/Makefile |2 +
 arch/powerpc/platforms/82xx/mpc8272_ads.c|  671 +-
 arch/powerpc/platforms/82xx/pq2.c|   93 
 arch/powerpc/platforms/82xx/pq2.h|   20 +
 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c |  202 
 arch/powerpc/platforms/82xx/pq2ads.h |2 -
 10 files changed, 816 insertions(+), 882 deletions(-)
 create mode 100644 arch/powerpc/platforms/82xx/pq2.c
 create mode 100644 arch/powerpc/platforms/82xx/pq2.h
 create mode 100644 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 00099ef..d800d52 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -465,7 +465,7 @@ config PCI_8260
 
 config 8260_PCI9
bool Enable workaround for MPC826x erratum PCI 9
-   depends on PCI_8260  !ADS8272
+   depends on PCI_8260  !8272
default y
 
 choice
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts 
b/arch/powerpc/boot/dts/mpc8272ads.dts
index 4d09dca..bd751d7 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -11,7 +11,7 @@
 
 / {
model = MPC8272ADS;
-   compatible = MPC8260ADS;
+   compatible = fsl,mpc8272ads;
#address-cells = 1;
#size-cells = 1;
 
@@ -22,192 +22,219 @@
PowerPC,[EMAIL PROTECTED] {
device_type = cpu;
reg = 0;
-   d-cache-line-size = 20;   // 32 bytes
-   i-cache-line-size = 20;   // 32 bytes
-   d-cache-size = 4000;  // L1, 16K
-   i-cache-size = 4000;  // L1, 16K
+   d-cache-line-size = d#32;
+   i-cache-line-size = d#32;
+   d-cache-size = d#16384;
+   i-cache-size = d#16384;
timebase-frequency = 0;
bus-frequency = 0;
clock-frequency = 0;
-   32-bit;
};
};
 
-   pci_pic: [EMAIL PROTECTED] {
-   #address-cells = 0;
-   #interrupt-cells = 2;
-   interrupt-controller;
-   reg = f820 f824;
-   built-in;
-   device_type = pci-pic;
+   CS: chipselect {
+   compatible = fsl,mpc8272ads-chipselect,
+fsl,mpc8272-chipselect,
+fsl,pq2-chipselect;
+   #address-cells = 2;
+   #size-cells = 1;
+   fsl,ctrl = CSCTRL;
+
+   ranges = 0 0 fe00 0200
+ 1 0 f450 8000
+ 3 0 f820 8000;
+
+   [EMAIL PROTECTED],0 {
+   device_type = rom;
+   compatible = direct-mapped;
+   reg = 0 0 200;
+   probe-type = JEDEC;
+   bank-width = 4;
+   };
+
+   [EMAIL PROTECTED],0 {
+   reg = 1 0 20;
+   compatible = fsl,mpc8272ads-bcsr;
+   };
+
+   PCI_PIC: [EMAIL PROTECTED],0 {
+   compatible = fsl,mpc8272ads-pci-pic,
+fsl,pq2ads-pci-pic;
+   #interrupt-cells = 1;
+   interrupt-controller;
+   reg = 3 0 8;
+   interrupt-parent = PIC;
+   interrupts = 14 8;
+   };
};
 
-   memory {
-   device_type = memory;
-   reg =  400 f450 0020;
+   PCI: [EMAIL PROTECTED] {
+   #interrupt-cells = 1;
+   #size-cells = 2;
+   #address-cells = 3;
+   device_type = pci;
+   fsl,ctrl = PCICTRL;
+   clock-frequency = d#;
+   interrupt-map-mask = f800 0 0 7;
+   interrupt-map = 
+   /* IDSEL 0x16 */
+b000 0 0 1 PCI_PIC 0
+b000 0 0 2 PCI_PIC 1
+b000 0 0 3 PCI_PIC 2
+