答复: [PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
Regards Thanks
Haijun.
发件人: Wood Scott-B07421
发送时间: 2013年7月8日 17:10
收件人: Zhang Haijun-B42677
抄送: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Fleming
Andy-AFLEMING; Zhang Haijun-B42677; Huang Changming-R66093
主题: Re: [PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
On 07/04/2013 07:05:00 PM, Haijun Zhang wrote:
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
index c952cd3..9d24501 100644
--- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -131,9 +131,7 @@
};
cpld@3,0 {
- #address-cells = 1;
- #size-cells = 1;
- compatible = cpld;
+ compatible = fsl, p1020rdb-cpld;
No space after fsl,.
I'll change it thanks.
+ partition@fs {
+ /* 4MB for Compressed RFS Image */
+ reg = 0x0050 0x0040;
+ label = file system;
+ };
+
+ partition@jffs-fs {
+ /* 7MB for JFFS2 based RFS */
+ reg = 0x0090 0x0070;
+ label = file system jffs2;
+ };
+ };
+ slic@0 {
+ compatible = zarlink,le88266;
+ reg = 1;
+ spi-max-frequency = 800;
+ };
+ slic@1 {
+ compatible = zarlink,le88266;
+ reg = 2;
+ spi-max-frequency = 800;
+ };
+
+ };
Remove that last blank line, and insert a blank line before each
slic@... (like you do between the partition nodes).
I'll change it thanks.
+ /* USB2 is shared with localbus, so it must be disabled
+by default. We can't put 'status = disabled;' here
+since U-Boot doesn't clear the status property when
+it enables USB2. OTOH, U-Boot does create a new node
+when there isn't any. So, just comment it out.
+ */
/*
* Linux multi-line
* comment style
* is like this.
*/
+ usb@23000 {
+ status = disabled;
+ phy_type = ulpi;
+ };
Didn't you just say above that you can't use status = disabled?
And can U-Boot be fixed to set status = disabled on whichever I/O is
not usable?
I had checked with ip owner, this node is not needed. I'll mask it.
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash and L2 switch */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
If you're going to have a comment here about what is mapped by the
ranges, why exclude the CPLD?
I'll add it.
-Scott
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Re: [PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
On 07/04/2013 07:05:00 PM, Haijun Zhang wrote:
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
index c952cd3..9d24501 100644
--- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -131,9 +131,7 @@
};
cpld@3,0 {
- #address-cells = 1;
- #size-cells = 1;
- compatible = cpld;
+ compatible = fsl, p1020rdb-cpld;
No space after fsl,.
+ partition@fs {
+ /* 4MB for Compressed RFS Image */
+ reg = 0x0050 0x0040;
+ label = file system;
+ };
+
+ partition@jffs-fs {
+ /* 7MB for JFFS2 based RFS */
+ reg = 0x0090 0x0070;
+ label = file system jffs2;
+ };
+ };
+ slic@0 {
+ compatible = zarlink,le88266;
+ reg = 1;
+ spi-max-frequency = 800;
+ };
+ slic@1 {
+ compatible = zarlink,le88266;
+ reg = 2;
+ spi-max-frequency = 800;
+ };
+
+ };
Remove that last blank line, and insert a blank line before each
slic@... (like you do between the partition nodes).
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = disabled;' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ */
/*
* Linux multi-line
* comment style
* is like this.
*/
+ usb@23000 {
+ status = disabled;
+ phy_type = ulpi;
+ };
Didn't you just say above that you can't use status = disabled?
And can U-Boot be fixed to set status = disabled on whichever I/O is
not usable?
+/include/ fsl/p1020si-pre.dtsi
+/ {
+ model = fsl,P1020RDB-PD;
+ compatible = fsl,P1020RDB-PD;
+
+ memory {
+ device_type = memory;
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = 0x0 0xffe05000 0x0 0x1000;
+
+ /* NOR, NAND flash and L2 switch */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400
+ 0x1 0x0 0x0 0xff80 0x0004
+ 0x2 0x0 0x0 0xffa0 0x0002
+ 0x3 0x0 0x0 0xffb0 0x0002;
If you're going to have a comment here about what is mapped by the
ranges, why exclude the CPLD?
-Scott
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[PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
changes for v2:
- Remove address cells and size cells for pc/pd board
arch/powerpc/boot/dts/p1020rdb-pc.dtsi| 4 +-
arch/powerpc/boot/dts/p1020rdb-pd.dtsi| 253 ++
arch/powerpc/boot/dts/p1020rdb-pd_32b.dts | 90 +++
3 files changed, 344 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
index c952cd3..9d24501 100644
--- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -131,9 +131,7 @@
};
cpld@3,0 {
- #address-cells = 1;
- #size-cells = 1;
- compatible = cpld;
+ compatible = fsl, p1020rdb-cpld;
reg = 0x3 0x0 0x2;
read-only;
};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
new file mode 100644
index 000..03b308d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
@@ -0,0 +1,253 @@
+/*
+ * P1020RDB-PD Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lbc {
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR DTB Image;
+ };
+
+ partition@2 {
+ /* 3.875 MB for Linux Kernel Image */
+ reg = 0x0002 0x003e;
+ label = NOR Linux Kernel Image;
+ };
+
+ partition@40 {
+ /* 58MB for Root file System */
+ reg = 0x0040 0x03a0;
+ label = NOR Root File System;
+ };
+
+ partition@3e0 {
+ /* This location must not be altered */
+ /* 1M for Vitesse 7385 Switch firmware */
+ reg = 0x3e0 0x0010;
+ label = NOR Vitesse-7385 Firmware;
+ read-only;
+ };
+
+ partition@3f0 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = 0x03f0 0x0010;
+
