Re: [PATCH v4 2/4] powerpc/sstep: Support VSX vector paired storage access instructions
Hi Ravi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.9-rc8 next-20201007]
[cannot apply to mpe/next scottwood/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Ravi-Bangoria/powerpc-sstep-VSX-32-byte-vector-paired-load-store-instructions/20201008-153614
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-g5_defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/55def6779849f9aec057f405abf1cd98a8674b4f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Ravi-Bangoria/powerpc-sstep-VSX-32-byte-vector-paired-load-store-instructions/20201008-153614
git checkout 55def6779849f9aec057f405abf1cd98a8674b4f
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross
ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
arch/powerpc/lib/sstep.c: In function 'analyse_instr':
>> arch/powerpc/lib/sstep.c:2901:15: error: implicit declaration of function
>> 'VSX_REGISTER_XTP'; did you mean 'H_REGISTER_SMR'?
>> [-Werror=implicit-function-declaration]
2901 | op->reg = VSX_REGISTER_XTP(rd);
| ^~~~
| H_REGISTER_SMR
cc1: all warnings being treated as errors
vim +2901 arch/powerpc/lib/sstep.c
2815
2816 #ifdef __powerpc64__
2817 case 62:/* std[u] */
2818 op->ea = dsform_ea(word, regs);
2819 switch (word & 3) {
2820 case 0: /* std */
2821 op->type = MKOP(STORE, 0, 8);
2822 break;
2823 case 1: /* stdu */
2824 op->type = MKOP(STORE, UPDATE, 8);
2825 break;
2826 case 2: /* stq */
2827 if (!(rd & 1))
2828 op->type = MKOP(STORE, 0, 16);
2829 break;
2830 }
2831 break;
2832 case 1: /* Prefixed instructions */
2833 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2834 return -1;
2835
2836 prefix_r = GET_PREFIX_R(word);
2837 ra = GET_PREFIX_RA(suffix);
2838 op->update_reg = ra;
2839 rd = (suffix >> 21) & 0x1f;
2840 op->reg = rd;
2841 op->val = regs->gpr[rd];
2842
2843 suffixopcode = get_op(suffix);
2844 prefixtype = (word >> 24) & 0x3;
2845 switch (prefixtype) {
2846 case 0: /* Type 00 Eight-Byte Load/Store */
2847 if (prefix_r && ra)
2848 break;
2849 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2850 switch (suffixopcode) {
2851 case 41:/* plwa */
2852 op->type = MKOP(LOAD, PREFIXED |
SIGNEXT, 4);
2853 break;
2854 case 42:/* plxsd */
2855 op->reg = rd + 32;
2856 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2857 op->element_size = 8;
2858 op->vsx_flags = VSX_CHECK_VEC;
2859 break;
2860 case 43:/* plxssp */
2861 op->reg = rd + 32;
2862 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2863 op->element_size = 8;
2864 op->vsx_flags = VSX_FPCONV |
VSX_CHECK_VEC;
2865 break;
2866 case 46:/* pstxsd */
2867 op->reg = rd + 32;
2868 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2869 op->element_size = 8;
2870 op->vsx_flags = VSX_CHECK_VEC;
2871 break;
2872
[PATCH v4 2/4] powerpc/sstep: Support VSX vector paired storage access instructions
From: Balamuruhan S
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add emulation support
for these new instructions:
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
* Prefixed Store VSX Vector Paired (pstxvp)
Suggested-by: Naveen N. Rao
Signed-off-by: Balamuruhan S
Signed-off-by: Ravi Bangoria
---
arch/powerpc/lib/sstep.c | 146 +--
1 file changed, 125 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index e6242744c71b..e39ee1651636 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -32,6 +32,10 @@ extern char system_call_vectored_emulate[];
#define XER_OV32 0x0008U
#define XER_CA32 0x0004U
+#ifdef CONFIG_VSX
+#define VSX_REGISTER_XTP(rd) rd) & 1) << 5) | ((rd) & 0xfe))
+#endif
+
#ifdef CONFIG_PPC_FPU
/*
* Functions in ldstfp.S
@@ -279,6 +283,19 @@ static nokprobe_inline void do_byte_reverse(void *ptr, int
nb)
up[1] = tmp;
break;
}
+ case 32: {
+ unsigned long *up = (unsigned long *)ptr;
+ unsigned long tmp;
+
+ tmp = byterev_8(up[0]);
+ up[0] = byterev_8(up[3]);
+ up[3] = tmp;
+ tmp = byterev_8(up[2]);
+ up[2] = byterev_8(up[1]);
+ up[1] = tmp;
+ break;
+ }
+
#endif
default:
WARN_ON_ONCE(1);
@@ -709,6 +726,8 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
reg->d[0] = reg->d[1] = 0;
switch (op->element_size) {
+ case 32:
+ /* [p]lxvp[x] */
case 16:
/* whole vector; lxv[x] or lxvl[l] */
if (size == 0)
@@ -717,7 +736,7 @@ void emulate_vsx_load(struct instruction_op *op, union
vsx_reg *reg,
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev)
- do_byte_reverse(reg, 16);
+ do_byte_reverse(reg, size);
break;
case 8:
/* scalar loads, lxvd2x, lxvdsx */
@@ -793,6 +812,20 @@ void emulate_vsx_store(struct instruction_op *op, const
union vsx_reg *reg,
size = GETSIZE(op->type);
switch (op->element_size) {
+ case 32:
+ /* [p]stxvp[x] */
+ if (size == 0)
+ break;
+ if (rev) {
+ /* reverse 32 bytes */
+ buf.d[0] = byterev_8(reg->d[3]);
+ buf.d[1] = byterev_8(reg->d[2]);
+ buf.d[2] = byterev_8(reg->d[1]);
+ buf.d[3] = byterev_8(reg->d[0]);
+ reg = &buf;
+ }
+ memcpy(mem, reg, size);
+ break;
case 16:
/* stxv, stxvx, stxvl, stxvll */
if (size == 0)
@@ -861,28 +894,43 @@ static nokprobe_inline int do_vsx_load(struct
instruction_op *op,
bool cross_endian)
{
int reg = op->reg;
- u8 mem[16];
- union vsx_reg buf;
+ int i, j, nr_vsx_regs;
+ u8 mem[32];
+ union vsx_reg buf[2];
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
return -EFAULT;
- emulate_vsx_load(op, &buf, mem, cross_endian);
+ nr_vsx_regs = size / sizeof(__vector128);
+ emulate_vsx_load(op, buf, mem, cross_endian);
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
- load_vsrn(reg, &buf);
+ for (i = 0; i < nr_vsx_regs; i++) {
+ j = IS_LE ? nr_vsx_regs - i - 1 : i;
+ load_vsrn(reg + i, &buf[j].v);
+ }
} else {
- current->thread.fp_state.fpr[reg][0] = buf.d[0];
- current->thread.fp_state.fpr[reg][1] = buf.d[1];
+ for (i = 0; i < nr_vsx_regs; i++) {
+ j = IS_LE ? nr_vsx_regs - i - 1 : i;
+ current->thread.fp_state.fpr[reg + i][0] =
buf[j].d[0];
+ current->thread.fp_state.fpr[reg + i][1] =
buf[j].d[1];
+ }
}
} else {
- if (regs->msr & MSR_VEC)
- load_vsrn(reg, &buf);
- else
- current->thread.vr_state.vr[reg - 32] = buf.v;
+ if (regs->msr & MSR_VEC) {
+ for (i
