RE: [PATCH v7 3/9] add Freescale SerDes PHY support
> I'm ok for it to be taken care of in u-boot for now. However, if we > later plan to add power management support to this block. We probably > have to do it in kernel. In that case, can't it be just saving/restoring ? That's easier than supporting full configuration of random user setups Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v7 3/9] add Freescale SerDes PHY support
On Nov 20, 2007, at 10:01 PM, Kumar Gala wrote: >>> Upon further review of all this I don't think this belongs in >>> the kernel at all. This is one time setup and should be done >>> in firmware. >> >> I'm ok for it to be taken care of in u-boot for now. However, if we >> later plan to add power management support to this block. We >> probably >> have to do it in kernel. > > How does pwr mgmt come into play w/SerDes? Never mind, if we do add pwr mgmt it looks like all we need to know is what SerDes is associated with the device. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v7 3/9] add Freescale SerDes PHY support
>> Upon further review of all this I don't think this belongs in >> the kernel at all. This is one time setup and should be done >> in firmware. > > I'm ok for it to be taken care of in u-boot for now. However, if we > later plan to add power management support to this block. We probably > have to do it in kernel. How does pwr mgmt come into play w/SerDes? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: [PATCH v7 3/9] add Freescale SerDes PHY support
> On Oct 19, 2007, at 10:35 AM, Grant Likely wrote: > > > On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote: > >> The SerDes(serializer/deserializer) PHY block is a new SoC > block used > >> in Freescale chips to support multiple serial interfaces, > such as PCI > >> Express, SGMII, SATA. > > > > This looks like board setup behaviour. Shouldn't setting this up be > > the responsibility firmware? And failing that, I think it should be > > done directly by the platform setup function (in other > words; make it > > a helper function and call it at board setup time). > Besides, you want > > to provide guarantees that the board is setup correctly before the > > device driver that uses it gets probed. > > > > Cheers, > > g. > > Upon further review of all this I don't think this belongs in the > kernel at all. This is one time setup and should be done in firmware. The latest u-boot supports the serdes initialization for 837x. So, it can be dropped from kernel for now. Dave ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: [PATCH v7 3/9] add Freescale SerDes PHY support
> -Original Message- > From: Kumar Gala [mailto:[EMAIL PROTECTED] > Sent: Wednesday, November 21, 2007 11:32 AM > To: Li Yang > Cc: Paul Mackerras; linuxppc-dev@ozlabs.org; Grant Likely > Subject: Re: [PATCH v7 3/9] add Freescale SerDes PHY support > > > On Oct 19, 2007, at 10:35 AM, Grant Likely wrote: > > > On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote: > >> The SerDes(serializer/deserializer) PHY block is a new SoC > block used > >> in Freescale chips to support multiple serial interfaces, > such as PCI > >> Express, SGMII, SATA. > > > > This looks like board setup behaviour. Shouldn't setting > this up be > > the responsibility firmware? And failing that, I think it > should be > > done directly by the platform setup function (in other > words; make it > > a helper function and call it at board setup time). > Besides, you want > > to provide guarantees that the board is setup correctly before the > > device driver that uses it gets probed. > > > > Cheers, > > g. > > Upon further review of all this I don't think this belongs in > the kernel at all. This is one time setup and should be done > in firmware. I'm ok for it to be taken care of in u-boot for now. However, if we later plan to add power management support to this block. We probably have to do it in kernel. - Leo ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v7 3/9] add Freescale SerDes PHY support
On Oct 19, 2007, at 10:35 AM, Grant Likely wrote: > On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote: >> The SerDes(serializer/deserializer) PHY block is a new SoC block used >> in Freescale chips to support multiple serial interfaces, such as PCI >> Express, SGMII, SATA. > > This looks like board setup behaviour. Shouldn't setting this up be > the responsibility firmware? And failing that, I think it should be > done directly by the platform setup function (in other words; make it > a helper function and call it at board setup time). Besides, you want > to provide guarantees that the board is setup correctly before the > device driver that uses it gets probed. > > Cheers, > g. Upon further review of all this I don't think this belongs in the kernel at all. This is one time setup and should be done in firmware. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v7 3/9] add Freescale SerDes PHY support
On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote:
> The SerDes(serializer/deserializer) PHY block is a new SoC block used
> in Freescale chips to support multiple serial interfaces, such as PCI
> Express, SGMII, SATA.
This looks like board setup behaviour. Shouldn't setting this up be
the responsibility firmware? And failing that, I think it should be
done directly by the platform setup function (in other words; make it
a helper function and call it at board setup time). Besides, you want
to provide guarantees that the board is setup correctly before the
device driver that uses it gets probed.
Cheers,
g.
>
> Signed-off-by: Li Yang <[EMAIL PROTECTED]>
> ---
> arch/powerpc/platforms/Kconfig |7 ++
> arch/powerpc/sysdev/Makefile |1 +
> arch/powerpc/sysdev/fsl_serdes.c | 195
> ++
> 3 files changed, 203 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
>
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
> index 229d355..5d64f84 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -315,6 +315,13 @@ config FSL_ULI1575
> config CPM
> bool
>
> +config FSL_SERDES
> + bool
> + help
> + The SerDes(serializer/deserializer) PHY block is a new SoC block
> + used in Freescale chips to support multiple serial interfaces,
> + such as PCI Express, SGMII, SATA.
> +
> source "arch/powerpc/sysdev/bestcomm/Kconfig"
>
> endmenu
> diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
> index 99a77d7..2343ea4 100644
> --- a/arch/powerpc/sysdev/Makefile
> +++ b/arch/powerpc/sysdev/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o
> mv64x60_dev.o \
>mv64x60_udbg.o
> obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
> obj-$(CONFIG_AXON_RAM) += axonram.o
> +obj-$(CONFIG_FSL_SERDES) += fsl_serdes.o
>
> ifeq ($(CONFIG_PPC_MERGE),y)
> obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
> diff --git a/arch/powerpc/sysdev/fsl_serdes.c
> b/arch/powerpc/sysdev/fsl_serdes.c
> new file mode 100644
> index 000..670015d
> --- /dev/null
> +++ b/arch/powerpc/sysdev/fsl_serdes.c
> @@ -0,0 +1,195 @@
> +/*
> + * arch/powerpc/sysdev/fsl_serdes.c
> + *
> + * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
> + *
> + * Author: Li Yang <[EMAIL PROTECTED]>
> + *
> + * Freescale SerDes initialization routines
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +#define FSL_SRDSCR0_OFFS 0x0
> +#define FSL_SRDSCR0_DPP_1V20x8800
> +#define FSL_SRDSCR1_OFFS 0x4
> +#define FSL_SRDSCR1_PLLBW 0x0040
> +#define FSL_SRDSCR2_OFFS 0x8
> +#define FSL_SRDSCR2_VDD_1V20x0080
> +#define FSL_SRDSCR2_SEIC_MASK 0x1c1c
> +#define FSL_SRDSCR2_SEIC_SATA 0x1414
> +#define FSL_SRDSCR2_SEIC_PEX 0x1010
> +#define FSL_SRDSCR2_SEIC_SGMII 0x0101
> +#define FSL_SRDSCR3_OFFS 0xc
> +#define FSL_SRDSCR3_KFR_SATA 0x1010
> +#define FSL_SRDSCR3_KPH_SATA 0x0404
> +#define FSL_SRDSCR3_SDFM_SATA_PEX 0x0101
> +#define FSL_SRDSCR3_SDTXL_SATA 0x0505
> +#define FSL_SRDSCR4_OFFS 0x10
> +#define FSL_SRDSCR4_PROT_SATA 0x0808
> +#define FSL_SRDSCR4_PROT_PEX 0x0101
> +#define FSL_SRDSCR4_PROT_SGMII 0x0505
> +#define FSL_SRDSCR4_PLANE_X2 0x0100
> +#define FSL_SRDSCR4_RFCKS_100 0x
> +#define FSL_SRDSCR4_RFCKS_125 0x1000
> +#define FSL_SRDSCR4_RFCKS_150 0x3000
> +#define FSL_SRDSRSTCTL_OFFS0x20
> +#define FSL_SRDSRSTCTL_RST 0x8000
> +#define FSL_SRDSRSTCTL_SATA_RESET 0xf
> +
> +static int fsl_serdes_probe(struct of_device *ofdev,
> + const struct of_device_id *match)
> +{
> + struct device_node *np = ofdev->node;
> + void __iomem *regs;
> + const char *prot;
> + const unsigned int *freq;
> + u32 rfcks;
> +
> + regs = of_iomap(np, 0);
> + if (!regs)
> + return -ENOMEM;
> +
> + prot = of_get_property(np, "protocol", NULL);
> + if (!prot)
> + goto out;
> + freq = of_get_property(np, "clock", NULL);
> + if (!freq)
> + goto out;
> + switch (*freq) {
> + case 100:
> + rfcks = FSL_SRDSCR4_RFCKS_100;
> + break;
>
[PATCH v7 3/9] add Freescale SerDes PHY support
The SerDes(serializer/deserializer) PHY block is a new SoC block used
in Freescale chips to support multiple serial interfaces, such as PCI
Express, SGMII, SATA.
Signed-off-by: Li Yang <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/Kconfig |7 ++
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_serdes.c | 195 ++
3 files changed, 203 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 229d355..5d64f84 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -315,6 +315,13 @@ config FSL_ULI1575
config CPM
bool
+config FSL_SERDES
+ bool
+ help
+ The SerDes(serializer/deserializer) PHY block is a new SoC block
+ used in Freescale chips to support multiple serial interfaces,
+ such as PCI Express, SGMII, SATA.
+
source "arch/powerpc/sysdev/bestcomm/Kconfig"
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..2343ea4 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o
mv64x60_dev.o \
mv64x60_udbg.o
obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_AXON_RAM) += axonram.o
+obj-$(CONFIG_FSL_SERDES) += fsl_serdes.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
diff --git a/arch/powerpc/sysdev/fsl_serdes.c b/arch/powerpc/sysdev/fsl_serdes.c
new file mode 100644
index 000..670015d
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_serdes.c
@@ -0,0 +1,195 @@
+/*
+ * arch/powerpc/sysdev/fsl_serdes.c
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Li Yang <[EMAIL PROTECTED]>
+ *
+ * Freescale SerDes initialization routines
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define FSL_SRDSCR0_OFFS 0x0
+#define FSL_SRDSCR0_DPP_1V20x8800
+#define FSL_SRDSCR1_OFFS 0x4
+#define FSL_SRDSCR1_PLLBW 0x0040
+#define FSL_SRDSCR2_OFFS 0x8
+#define FSL_SRDSCR2_VDD_1V20x0080
+#define FSL_SRDSCR2_SEIC_MASK 0x1c1c
+#define FSL_SRDSCR2_SEIC_SATA 0x1414
+#define FSL_SRDSCR2_SEIC_PEX 0x1010
+#define FSL_SRDSCR2_SEIC_SGMII 0x0101
+#define FSL_SRDSCR3_OFFS 0xc
+#define FSL_SRDSCR3_KFR_SATA 0x1010
+#define FSL_SRDSCR3_KPH_SATA 0x0404
+#define FSL_SRDSCR3_SDFM_SATA_PEX 0x0101
+#define FSL_SRDSCR3_SDTXL_SATA 0x0505
+#define FSL_SRDSCR4_OFFS 0x10
+#define FSL_SRDSCR4_PROT_SATA 0x0808
+#define FSL_SRDSCR4_PROT_PEX 0x0101
+#define FSL_SRDSCR4_PROT_SGMII 0x0505
+#define FSL_SRDSCR4_PLANE_X2 0x0100
+#define FSL_SRDSCR4_RFCKS_100 0x
+#define FSL_SRDSCR4_RFCKS_125 0x1000
+#define FSL_SRDSCR4_RFCKS_150 0x3000
+#define FSL_SRDSRSTCTL_OFFS0x20
+#define FSL_SRDSRSTCTL_RST 0x8000
+#define FSL_SRDSRSTCTL_SATA_RESET 0xf
+
+static int fsl_serdes_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ void __iomem *regs;
+ const char *prot;
+ const unsigned int *freq;
+ u32 rfcks;
+
+ regs = of_iomap(np, 0);
+ if (!regs)
+ return -ENOMEM;
+
+ prot = of_get_property(np, "protocol", NULL);
+ if (!prot)
+ goto out;
+ freq = of_get_property(np, "clock", NULL);
+ if (!freq)
+ goto out;
+ switch (*freq) {
+ case 100:
+ rfcks = FSL_SRDSCR4_RFCKS_100;
+ break;
+ case 125:
+ rfcks = FSL_SRDSCR4_RFCKS_125;
+ break;
+ case 150:
+ rfcks = FSL_SRDSCR4_RFCKS_150;
+ break;
+ default:
+ printk(KERN_ERR "SerDes: Wrong frequency\n");
+ goto out;
+ }
+
+ /* Use default prescale and counter */
+
+ /* 1.0V corevdd */
+ if (of_get_property(np, "vdd-1v", NULL)) {
+ /* DPPE/DPPA = 0 */
+ clrbits32(regs + FSL_SRDSCR0_OFFS, FSL_SRDSCR0_DPP_1V2);
+
+ /* VDD = 0 */
+ clrbits32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_VDD_1V2);
+ }
+
+ /* protocol specific configuration */
+
