Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.
This should work with both EP405 and EP405PC.
I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.
Also, the flash, nvram, rtc and temp control still have to be wired.
Signed-off-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
Note about IRQ routing: The doc is very obscure in that area.
I _think_ the SB interrupt on the CPLD is actually the Windond's
8259 output and the NB interrupt is the PCI_A...PCI_D mux in
there (which can be implemented as a cascaded controller) but
I haven't sorted that out yet. If anybody from Embedded Planet
is around, I could use some advice there.
If my deductions are correct, then we would need to wire up the
8259 driver to SB, which should be trivial provided I stick the
windbond bridge in the device-tree, or at least part of it,
and probably implement a cascaded controller for the PCI IRQ
A...D mux thingy, which should also be trivial.
Note also that it tends to lockup during the transition from
the boot wrapper to the kernel, before udbg is started. I didn't
have a RiscWatch at hand so I haven't yet been able to track that
down. It's random though, quite weird. Maybe some stale TLB entries
or cache content that isn't cleared properly...
arch/powerpc/boot/4xx.c | 55 +-
arch/powerpc/boot/4xx.h |1
arch/powerpc/boot/Makefile |3
arch/powerpc/boot/dts/ep405.dts | 221
arch/powerpc/boot/ep405.c| 74 ++
arch/powerpc/boot/treeboot-walnut.c | 49 -
arch/powerpc/boot/wrapper|2
arch/powerpc/configs/ep405_defconfig | 951 +++
arch/powerpc/platforms/40x/Kconfig | 21
arch/powerpc/platforms/40x/Makefile |1
arch/powerpc/platforms/40x/ep405.c | 127
11 files changed, 1439 insertions(+), 66 deletions(-)
Index: linux-work/arch/powerpc/boot/Makefile
===
--- linux-work.orig/arch/powerpc/boot/Makefile 2007-11-21 16:19:01.0
+1100
+++ linux-work/arch/powerpc/boot/Makefile 2007-11-21 16:23:03.0
+1100
@@ -56,7 +56,7 @@ src-plat := of.c cuboot-52xx.c cuboot-83
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c
\
- fixed-head.S ep88xc.c cuboot-hpc2.c
+ fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -150,6 +150,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag
ifneq ($(CONFIG_DEVICE_TREE),)
image-$(CONFIG_PPC_8xx)+= cuImage.8xx
image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
+image-$(CONFIG_EP405) += zImage.ep405
image-$(CONFIG_8260) += cuImage.pq2
image-$(CONFIG_PPC_MPC52xx)+= cuImage.52xx
image-$(CONFIG_PPC_83xx) += cuImage.83xx
Index: linux-work/arch/powerpc/boot/ep405.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ linux-work/arch/powerpc/boot/ep405.c2007-11-21 16:23:03.0
+1100
@@ -0,0 +1,74 @@
+/*
+ * Embedded Planet EP405 with PlanetCore firmware
+ *
+ * (c) Benjamin Herrenschmidt [EMAIL PROTECTED], IBM Corp,\
+ *
+ * Based on ep88xc.c by
+ *
+ * Scott Wood [EMAIL PROTECTED]
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include ops.h
+#include stdio.h
+#include planetcore.h
+#include dcr.h
+#include 4xx.h
+#include io.h
+
+static char *table;
+static u64 mem_size;
+
+static void platform_fixups(void)
+{
+ u64 val;
+ void *nvrtc;
+
+ dt_fixup_memory(0, mem_size);
+ planetcore_set_mac_addrs(table);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, val)) {
+ printf(No PlanetCore crystal frequency key.\r\n);
+ return;
+ }
+ ibm405gp_fixup_clocks(val, 0xa8c000);
+ ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
+ ibm4xx_fixup_ebc_ranges(/plb/ebc);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_KB_NVRAM, val)) {
+ printf(No PlanetCore NVRAM size key.\r\n);
+ return;
+ }
+ nvrtc = finddevice(/plb/ebc/[EMAIL PROTECTED],20);
+ if (nvrtc != NULL) {
+ u32 reg[3] = { 4, 0x20, 0};
+
