RE: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
On 20/04/2016 12:22AM, Christophe Leroy <christophe.le...@c-s.fr> wrote > -Original Message- > From: Christophe Leroy [mailto:christophe.le...@c-s.fr] > Sent: Wednesday, April 20, 2016 12:22 AM > To: Qiang Zhao <qiang.z...@nxp.com>; da...@davemloft.net > Cc: gre...@linuxfoundation.org; Xiaobo Xie <xiaobo@nxp.com>; linux- > ker...@vger.kernel.org; o...@buserror.net; net...@vger.kernel.org; > a...@linux-foundation.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC > > Le 30/03/2016 10:50, Zhao Qiang a écrit : > > The driver add hdlc support for Freescale QUICC Engine. > > It support NMSI and TSA mode. > When using TSA, how does the TSA gets configured ? Especially how do you > describe which Timeslot is switched to HDLC channels ? the TSA is configured statically according to device tree node. For " which Timeslot is switched to HDLC channels ", there is a property "fsl,tx-timeslot-mask" in device tree to describe it. > Is it possible to route some Timeslots to one UCC for HDLC, and route some > others to another UCC for an ALSA sound driver ? The feature you describe is not supported at present. > The QE also have a QMC which allows to split all timeslots to a given UCC into > independant channels that can either be used with HDLC or transparents (for > audio for instance). Do you intent to also support QMC ? new QE use UMCC instead of QMC in old QE, we have started to develop UMCC. > According to the compatible property, it looks like your driver is for > freescale > T1040. The MPC83xx also has a Quick Engine, would it work on it too ? The driver is common, but tested on t1040, it is needed to add node to MPC83xx If you want to test on mpc83xx. -Zhao Qiang ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
Le 30/03/2016 10:50, Zhao Qiang a écrit : The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. When using TSA, how does the TSA gets configured ? Especially how do you describe which Timeslot is switched to HDLC channels ? Is it possible to route some Timeslots to one UCC for HDLC, and route some others to another UCC for an ALSA sound driver ? The QE also have a QMC which allows to split all timeslots to a given UCC into independant channels that can either be used with HDLC or transparents (for audio for instance). Do you intent to also support QMC ? According to the compatible property, it looks like your driver is for freescale T1040. The MPC83xx also has a Quick Engine, would it work on it too ? Christophe Signed-off-by: Zhao Qiang--- MAINTAINERS|6 + drivers/net/wan/Kconfig| 12 + drivers/net/wan/Makefile |1 + drivers/net/wan/fsl_ucc_hdlc.c | 1339 drivers/net/wan/fsl_ucc_hdlc.h | 140 + include/soc/fsl/qe/ucc_fast.h |4 + 6 files changed, 1502 insertions(+) create mode 100644 drivers/net/wan/fsl_ucc_hdlc.c create mode 100644 drivers/net/wan/fsl_ucc_hdlc.h diff --git a/MAINTAINERS b/MAINTAINERS index 74bbff3..428d6ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4572,6 +4572,12 @@ F: drivers/net/ethernet/freescale/gianfar* X:drivers/net/ethernet/freescale/gianfar_ptp.c F:Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +FREESCALE QUICC ENGINE UCC HDLC DRIVER +M: Zhao Qiang +L: linuxppc-dev@lists.ozlabs.org +S: Maintained +F: drivers/net/wan/fsl_ucc_hdlc* + FREESCALE QUICC ENGINE UCC UART DRIVER M:Timur Tabi L:linuxppc-dev@lists.ozlabs.org diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index a2fdd15..cc424b2 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig @@ -280,6 +280,18 @@ config DSCC4 To compile this driver as a module, choose M here: the module will be called dscc4. +config FSL_UCC_HDLC + tristate "Freescale QUICC Engine HDLC support" + depends on HDLC + select QE_TDM + select QUICC_ENGINE + help + Driver for Freescale QUICC Engine HDLC controller. The driver + support HDLC run on NMSI and TDM mode. + + To compile this driver as a module, choose M here: the + module will be called fsl_ucc_hdlc. + config DSCC4_PCISYNC bool "Etinc PCISYNC features" depends on DSCC4 diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile index c135ef4..25fec40 100644 --- a/drivers/net/wan/Makefile +++ b/drivers/net/wan/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_WANXL) += wanxl.o obj-$(CONFIG_PCI200SYN) += pci200syn.o obj-$(CONFIG_PC300TOO)+= pc300too.o obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o +obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o clean-files := wanxlfw.inc $(obj)/wanxl.o: $(obj)/wanxlfw.inc diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c new file mode 100644 index 000..9958ec1 --- /dev/null +++ b/drivers/net/wan/fsl_ucc_hdlc.c @@ -0,0 +1,1339 @@ +/* Freescale QUICC Engine HDLC Device Driver + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsl_ucc_hdlc.h" + +#define DRV_DESC "Freescale QE UCC HDLC Driver" +#define DRV_NAME "ucc_hdlc" + +#define TDM_PPPOHT_SLIC_MAXIN +/* #define DEBUG */ +/* #define QE_HDLC_TEST */ +#define BROKEN_FRAME_INFO + +static struct ucc_tdm_info utdm_primary_info = { + .uf_info = { + .tsa = 0, + .cdp = 0, + .cds = 1, + .ctsp = 1, + .ctss = 1, + .revd = 0, + .urfs = 256, + .utfs = 256, + .urfet = 128, + .urfset = 192, + .utfet = 128, + .utftt = 0x40, + .ufpt = 256, + .mode = UCC_FAST_PROTOCOL_MODE_HDLC, + .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, + .tenc = UCC_FAST_TX_ENCODING_NRZ, + .renc = UCC_FAST_RX_ENCODING_NRZ, + .tcrc = UCC_FAST_16_BIT_CRC, + .synl = UCC_FAST_SYNC_LEN_NOT_USED, + }, + + .si_info = { +#ifdef CONFIG_FSL_PQ_MDS_T1 + .simr_rfsd = 1,
Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
Hi Zhao, [auto build test ERROR on net/master] [also build test ERROR on v4.6-rc1 next-20160330] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Zhao-Qiang/fsl-qe-add-rx_sync-and-tx_sync-for-TDM-mode/20160330-170411 config: i386-allmodconfig (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=i386 All error/warnings (new ones prefixed by >>): In file included from include/soc/fsl/qe/ucc_slow.h:21:0, from drivers/tty/serial/ucc_uart.c:34: >> include/soc/fsl/qe/qe.h:24:21: fatal error: asm/cpm.h: No such file or >> directory compilation terminated. -- >> drivers/net/ethernet/freescale/gianfar_ptp.c:75:0: warning: "FS" redefined #define FS(1<<28) /* FIPER start indication */ ^ In file included from arch/x86/include/uapi/asm/ptrace.h:5:0, from arch/x86/include/asm/ptrace.h:6, from arch/x86/include/asm/alternative.h:8, from arch/x86/include/asm/bitops.h:16, from include/linux/bitops.h:36, from include/linux/kernel.h:10, from include/linux/list.h:8, from include/linux/kobject.h:20, from include/linux/device.h:17, from drivers/net/ethernet/freescale/gianfar_ptp.c:23: arch/x86/include/uapi/asm/ptrace-abi.h:15:0: note: this is the location of the previous definition #define FS 9 ^ -- In file included from drivers/soc/fsl/qe/qe_ic.c:31:0: include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic': >> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in >> this function) if (cascade_irq != NO_IRQ) ^ include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is reported only once for each function it appears in include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic': include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in this function) if (cascade_irq != NO_IRQ) ^ include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic': include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in this function) if (cascade_irq != NO_IRQ) ^ include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic': include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in this function) if (cascade_irq != NO_IRQ) ^ include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic': include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in this function) if (cascade_irq == NO_IRQ) ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read': >> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function >> 'in_be32' [-Werror=implicit-function-declaration] return in_be32(base + (reg >> 2)); ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write': >> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function >> 'out_be32' [-Werror=implicit-function-declaration] out_be32(base + (reg >> 2), value); ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq': >> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in >> this function) return NO_IRQ; ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq': drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use in this function) return NO_IRQ; ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init': drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use in this function) if (qe_ic->virq_low == NO_IRQ) { ^ drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority': >> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function >> 'virq_to_hw' [-Werror=implicit-function-declaration] unsigned int src = virq_to_hw(virq); ^ cc1: some warnings being treated as errors vim +24 include/soc/fsl/qe/qe.h 98658538 include/asm-powerpc/qe.h Li Yang 2006-10-03 18 1291e49e arch/powerpc/include/asm/qe.h Zhao Qiang 2015-11-30 19 #include 1291e49e arch/powerpc/include/asm/qe.h Zhao Qiang 2015-11-30 20 #include 5e41486c include/asm-powerpc/qe.h Anton Vorontsov 2008-05-23 21 #include 1b9e8904 arch/powerpc/include/asm/qe.h Anton Vorontsov 2008-12-03 22 #include 1b9e8904 arch/powerpc/include/asm/qe.h Anton Vorontsov 2008-12-03 23 #include 5093bb96 include/asm-powerpc/qe.h Anton Vorontsov 2008-05-23 @24 #include 7aa1aa6e include/soc/fsl/qe/qe.h Zhao Qiang 2015-11-30 25
Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
Hi Zhao, [auto build test WARNING on net/master] [also build test WARNING on v4.6-rc1 next-20160330] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Zhao-Qiang/fsl-qe-add-rx_sync-and-tx_sync-for-TDM-mode/20160330-170411 config: powerpc-allyesconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=powerpc All warnings (new ones prefixed by >>): warning: (KMETER1 && FSL_UCC_HDLC) selects QUICC_ENGINE which has unmet direct dependencies (FSL_SOC && PPC32) --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: Binary data ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 5/5] drivers/net: support hdlc function for QE-UCC
Hi Zhao, [auto build test WARNING on net/master] [also build test WARNING on v4.6-rc1 next-20160330] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Zhao-Qiang/fsl-qe-add-rx_sync-and-tx_sync-for-TDM-mode/20160330-170411 config: xtensa-allyesconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=xtensa All warnings (new ones prefixed by >>): warning: (FSL_UCC_HDLC) selects QUICC_ENGINE which has unmet direct dependencies (FSL_SOC && PPC32) --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: Binary data ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev