On Mon, Jul 9, 2018 at 7:08 PM, Michael Ellerman wrote:
> Document the support for spec_store_bypass_disable that was added for
> powerpc in commit a048a07d7f45 ("powerpc/64s: Add support for a store
> forwarding barrier at kernel entry/exit").
>
> Signed-off-by: Michael Ellerman
Reviewed-by: Kees Cook
-Kees
> ---
> Documentation/admin-guide/kernel-parameters.txt | 16 +---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> I tried documenting the differences between the PPC options and X86 ones in
> one
> section, but it got quite messy, so I went with this instead. Happy to take
> advice on how better to structure it if anyone has opinions.
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt
> b/Documentation/admin-guide/kernel-parameters.txt
> index efc7aa7a0670..f320c7168b04 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -4060,6 +4060,8 @@
> This parameter controls whether the Speculative Store
> Bypass optimization is used.
>
> + On x86 the options are:
> +
> on - Unconditionally disable Speculative Store
> Bypass
> off - Unconditionally enable Speculative Store
> Bypass
> auto- Kernel detects whether the CPU model
> contains an
> @@ -4075,12 +4077,20 @@
> seccomp - Same as "prctl" above, but all seccomp
> threads
> will disable SSB unless they explicitly opt
> out.
>
> - Not specifying this option is equivalent to
> - spec_store_bypass_disable=auto.
> -
> Default mitigations:
> X86:If CONFIG_SECCOMP=y "seccomp", otherwise
> "prctl"
>
> + On powerpc the options are:
> +
> + on,auto - On Power8 and Power9 insert a
> store-forwarding
> + barrier on kernel entry and exit. On Power7
> + perform a software flush on kernel entry and
> + exit.
> + off - No action.
> +
> + Not specifying this option is equivalent to
> + spec_store_bypass_disable=auto.
> +
> spia_io_base= [HW,MTD]
> spia_fio_base=
> spia_pedr=
> --
> 2.14.1
>
--
Kees Cook
Pixel Security
