Re: [PATCH] ndfc driver
On Tue, Dec 16, 2008 at 11:14:00PM -0500, Sean MacLennan wrote: On Wed, 10 Dec 2008 18:16:34 -0500 Sean MacLennan sean.maclen...@ottawa.kanatek.ca wrote: Here is an updated patch. Doc has been moved to 4xx and amcc changed to ibm. Anybody? Even if it is not perfect, it would be better to have a driver that at least compiles ;) Reviewing it today. Looked pretty good at first glance. It would be nice to get David or Thomas to Ack it. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
On Wed, Dec 10, 2008 at 06:16:34PM -0500, Sean MacLennan wrote:
Here is an updated patch. Doc has been moved to 4xx and amcc changed to
ibm.
Arnd: I removed your acked-by just in case you don't approve of the new
flash layout. Feel free to ack again.
Cheers,
Sean
Port of the ndfc driver to an OF platform driver.
Signed-off-by: Sean MacLennan smaclen...@pikatech.com
Acked-By: Josh Boyer jwbo...@linux.vnet.ibm.com
David, if you have no objections I'd like to take this patch
through my tree. I'll fixup the subject and commit log when
I do.
josh
---
diff --git a/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
b/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
new file mode 100644
index 000..869f0b5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
@@ -0,0 +1,39 @@
+AMCC NDFC (NanD Flash Controller)
+
+Required properties:
+- compatible : ibm,ndfc.
+- reg : should specify chip select and size used for the chip (0x2000).
+
+Optional properties:
+- ccr : NDFC config and control register value (default 0).
+- bank-settings : NDFC bank configuration register value (default 0).
+
+Notes:
+- partition(s) - follows the OF MTD standard for partitions
+
+Example:
+
+n...@1,0 {
+ compatible = ibm,ndfc;
+ reg = 0x0001 0x 0x2000;
+ ccr = 0x1000;
+ bank-settings = 0x8000;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ nand {
+ #address-cells = 1;
+ #size-cells = 1;
+
+ partit...@0 {
+ label = kernel;
+ reg = 0x 0x0020;
+ };
+ partit...@20 {
+ label = root;
+ reg = 0x0020 0x03E0;
+ };
+ };
+};
+
+
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 1c2e945..5705f85 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -163,6 +163,13 @@ config MTD_NAND_S3C2410_HWECC
incorrect ECC generation, and if using these, the default of
software ECC is preferable.
+config MTD_NAND_NDFC
+ tristate NDFC NanD Flash Controller
+ depends on 4xx
+ select MTD_NAND_ECC_SMC
+ help
+ NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
+
config MTD_NAND_S3C2410_CLKSTOP
bool S3C2410 NAND IDLE clock stop
depends on MTD_NAND_S3C2410
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 955959e..582cf80 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -2,12 +2,20 @@
* drivers/mtd/ndfc.c
*
* Overview:
- * Platform independend driver for NDFC (NanD Flash Controller)
+ * Platform independent driver for NDFC (NanD Flash Controller)
* integrated into EP440 cores
*
+ * Ported to an OF platform driver by Sean MacLennan
+ *
+ * The NDFC supports multiple chips, but this driver only supports a
+ * single chip since I do not have access to any boards with
+ * multiple chips.
+ *
* Author: Thomas Gleixner
*
* Copyright 2006 IBM
+ * Copyright 2008 PIKA Technologies
+ *Sean MacLennan smaclen...@pikatech.com
*
* This program is free software; you can redistributeit and/or
modify it
* under the terms ofthe GNU General Public License as published
by the
@@ -21,27 +29,20 @@
#include linux/mtd/partitions.h
#include linux/mtd/ndfc.h
#include linux/mtd/mtd.h
-#include linux/platform_device.h
-
+#include linux/of_platform.h
#include asm/io.h
-#ifdef CONFIG_40x
-#include asm/ibm405.h
-#else
-#include asm/ibm44x.h
-#endif
-
-struct ndfc_nand_mtd {
- struct mtd_info mtd;
- struct nand_chipchip;
- struct platform_nand_chip *pl_chip;
-};
-static struct ndfc_nand_mtd ndfc_mtd[NDFC_MAX_BANKS];
struct ndfc_controller {
- void __iomem*ndfcbase;
- struct nand_hw_control ndfc_control;
- atomic_tchilds_active;
+ struct of_device *ofdev;
+ void __iomem *ndfcbase;
+ struct mtd_info mtd;
+ struct nand_chip chip;
+ int chip_select;
+ struct nand_hw_control ndfc_control;
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *parts;
+#endif
};
static struct ndfc_controller ndfc_ctrl;
@@ -50,17 +51,14 @@ static void ndfc_select_chip(struct mtd_info *mtd, int
chip)
{
uint32_t ccr;
struct ndfc_controller *ndfc = ndfc_ctrl;
- struct nand_chip *nandchip = mtd-priv;
- struct ndfc_nand_mtd *nandmtd = nandchip-priv;
- struct platform_nand_chip *pchip = nandmtd-pl_chip;
- ccr = __raw_readl(ndfc-ndfcbase + NDFC_CCR);
+ ccr = in_be32(ndfc-ndfcbase + NDFC_CCR);
if (chip = 0) {
ccr = ~NDFC_CCR_BS_MASK;
- ccr |= NDFC_CCR_BS(chip + pchip-chip_offset);
+ ccr |= NDFC_CCR_BS(chip + ndfc-chip_select);
} else
ccr |= NDFC_CCR_RESET_CE;
- __raw_writel(ccr,
Re: [PATCH] ndfc driver
On Wed, 10 Dec 2008 18:16:34 -0500 Sean MacLennan sean.maclen...@ottawa.kanatek.ca wrote: Here is an updated patch. Doc has been moved to 4xx and amcc changed to ibm. Anybody? Even if it is not perfect, it would be better to have a driver that at least compiles ;) Cheers, Sean ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
n Mon, 08 Dec 2008 21:57:12 -1000
Mitch Bradley [EMAIL PROTECTED] wrote:
One address/size cell isn't enough for the next generation of NAND
FLASH chips.
I am no dts expert, but I thought I could put:
nand {
#address-cells = 1;
#size-cells = 1;
in my dts and you could put:
nand {
#address-cells = 2;
#size-cells = 2;
and, assuming we specified the reg entry right, everything would just
work. Is that assumption wrong?
And if the assumption is true, should I make a note in the doc that you
can make the address and size bigger?
Cheers,
Sean
In principle that is correct, but the device tree partition parser in
the Linux kernel assumes one address cell and one size cell, or at least
it did the last time I looked.
I wrote a patch to fix that and circulated it on the linuxppc list, but
since lost interest. OLPC (my main focus) is probably going to switch to
managed NAND (SSD, LBA-NAND, eMMC, or some such thing with a built-in
Flash Translation Layer) at some point. Raw NAND is starting to go by
the wayside.
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Re: [PATCH] ndfc driver
Here is an updated patch. Doc has been moved to 4xx and amcc changed to
ibm.
Arnd: I removed your acked-by just in case you don't approve of the new
flash layout. Feel free to ack again.
Cheers,
Sean
Port of the ndfc driver to an OF platform driver.
Signed-off-by: Sean MacLennan [EMAIL PROTECTED]
---
diff --git a/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
b/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
new file mode 100644
index 000..869f0b5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/4xx/ndfc.txt
@@ -0,0 +1,39 @@
+AMCC NDFC (NanD Flash Controller)
+
+Required properties:
+- compatible : ibm,ndfc.
+- reg : should specify chip select and size used for the chip (0x2000).
+
+Optional properties:
+- ccr : NDFC config and control register value (default 0).
+- bank-settings : NDFC bank configuration register value (default 0).
+
+Notes:
+- partition(s) - follows the OF MTD standard for partitions
+
+Example:
+
[EMAIL PROTECTED],0 {
+ compatible = ibm,ndfc;
+ reg = 0x0001 0x 0x2000;
+ ccr = 0x1000;
+ bank-settings = 0x8000;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ nand {
+ #address-cells = 1;
+ #size-cells = 1;
+
+ [EMAIL PROTECTED] {
+ label = kernel;
+ reg = 0x 0x0020;
+ };
+ [EMAIL PROTECTED] {
+ label = root;
+ reg = 0x0020 0x03E0;
+ };
+ };
+};
+
+
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 1c2e945..5705f85 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -163,6 +163,13 @@ config MTD_NAND_S3C2410_HWECC
incorrect ECC generation, and if using these, the default of
software ECC is preferable.
+config MTD_NAND_NDFC
+ tristate NDFC NanD Flash Controller
+ depends on 4xx
+ select MTD_NAND_ECC_SMC
+ help
+NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
+
config MTD_NAND_S3C2410_CLKSTOP
bool S3C2410 NAND IDLE clock stop
depends on MTD_NAND_S3C2410
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 955959e..582cf80 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -2,12 +2,20 @@
* drivers/mtd/ndfc.c
*
* Overview:
- * Platform independend driver for NDFC (NanD Flash Controller)
+ * Platform independent driver for NDFC (NanD Flash Controller)
* integrated into EP440 cores
*
+ * Ported to an OF platform driver by Sean MacLennan
+ *
+ * The NDFC supports multiple chips, but this driver only supports a
+ * single chip since I do not have access to any boards with
+ * multiple chips.
+ *
* Author: Thomas Gleixner
*
* Copyright 2006 IBM
+ * Copyright 2008 PIKA Technologies
+ *Sean MacLennan [EMAIL PROTECTED]
*
* This program is free software; you can redistribute it and/or
modify it
* under the terms of the GNU General Public License as published
by the
@@ -21,27 +29,20 @@
#include linux/mtd/partitions.h
#include linux/mtd/ndfc.h
#include linux/mtd/mtd.h
-#include linux/platform_device.h
-
+#include linux/of_platform.h
#include asm/io.h
-#ifdef CONFIG_40x
-#include asm/ibm405.h
-#else
-#include asm/ibm44x.h
-#endif
-
-struct ndfc_nand_mtd {
- struct mtd_info mtd;
- struct nand_chipchip;
- struct platform_nand_chip *pl_chip;
-};
-static struct ndfc_nand_mtd ndfc_mtd[NDFC_MAX_BANKS];
struct ndfc_controller {
- void __iomem*ndfcbase;
- struct nand_hw_control ndfc_control;
- atomic_tchilds_active;
+ struct of_device *ofdev;
+ void __iomem *ndfcbase;
+ struct mtd_info mtd;
+ struct nand_chip chip;
+ int chip_select;
+ struct nand_hw_control ndfc_control;
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *parts;
+#endif
};
static struct ndfc_controller ndfc_ctrl;
@@ -50,17 +51,14 @@ static void ndfc_select_chip(struct mtd_info *mtd, int chip)
{
uint32_t ccr;
struct ndfc_controller *ndfc = ndfc_ctrl;
- struct nand_chip *nandchip = mtd-priv;
- struct ndfc_nand_mtd *nandmtd = nandchip-priv;
- struct platform_nand_chip *pchip = nandmtd-pl_chip;
- ccr = __raw_readl(ndfc-ndfcbase + NDFC_CCR);
+ ccr = in_be32(ndfc-ndfcbase + NDFC_CCR);
if (chip = 0) {
ccr = ~NDFC_CCR_BS_MASK;
- ccr |= NDFC_CCR_BS(chip + pchip-chip_offset);
+ ccr |= NDFC_CCR_BS(chip + ndfc-chip_select);
} else
ccr |= NDFC_CCR_RESET_CE;
- __raw_writel(ccr, ndfc-ndfcbase + NDFC_CCR);
+ out_be32(ndfc-ndfcbase + NDFC_CCR, ccr);
}
static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -80,7 +78,7 @@ static int
Re: [PATCH] ndfc driver
One address/size cell isn't enough for the next generation of NAND FLASH chips. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
On Tue, 9 Dec 2008 07:10:27 +0100 Stefan Roese [EMAIL PROTECTED] wrote: On Tuesday 09 December 2008, Sean MacLennan wrote: On Thu, 4 Dec 2008 09:01:07 -0500 Josh Boyer [EMAIL PROTECTED] wrote: In addition to an example DTS patch (probably to warp itself), could you briefly write up a binding and put it in Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC the devicetree-discuss list on that part. Here is a start at the doc. I have sent it as a patch, but could just as easily send raw text. The example comes from the warp dts, just with less partitions, so I have not included a warp dts patch here. Cheers, Sean diff --git a/Documentation/powerpc/dts-bindings/amcc/ndfc.txt b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt new file mode 100644 index 000..668f4a9 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt @@ -0,0 +1,31 @@ +AMCC NDFC (NanD Flash Controller) + +Required properties: +- compatible : amcc,ndfc. The 4xx NAND controller was first implemented on the 440EP, IIRC. So I'm pretty sure that this controller is an IBM core and not am AMCC core. So this should be ibm,ndfc. That is true. It's an IBM blue logic core. And with this change it makes no sense to put this file ndfc.txt into the amcc directory. Josh, where should this go then? I declare it to be: dts-bindings/4xx/ mostly because I don't want the bindings scattered across two directories simply because of the timeframe they showed up in the marketplace. If there are better ideas, I'm all ears. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
On Mon, 08 Dec 2008 21:57:12 -1000
Mitch Bradley [EMAIL PROTECTED] wrote:
One address/size cell isn't enough for the next generation of NAND
FLASH chips.
I am no dts expert, but I thought I could put:
nand {
#address-cells = 1;
#size-cells = 1;
in my dts and you could put:
nand {
#address-cells = 2;
#size-cells = 2;
and, assuming we specified the reg entry right, everything would just
work. Is that assumption wrong?
And if the assumption is true, should I make a note in the doc that you
can make the address and size bigger?
Cheers,
Sean
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Re: [PATCH] ndfc driver
On Thu, 4 Dec 2008 09:01:07 -0500
Josh Boyer [EMAIL PROTECTED] wrote:
In addition to an example DTS patch (probably to warp itself), could
you briefly write up a binding and put it in
Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC
the devicetree-discuss list on that part.
Here is a start at the doc. I have sent it as a patch, but could just
as easily send raw text.
The example comes from the warp dts, just with less partitions, so I
have not included a warp dts patch here.
Cheers,
Sean
diff --git a/Documentation/powerpc/dts-bindings/amcc/ndfc.txt
b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt new file mode 100644
index 000..668f4a9
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt
@@ -0,0 +1,31 @@
+AMCC NDFC (NanD Flash Controller)
+
+Required properties:
+- compatible : amcc,ndfc.
+- reg : should specify chip select and size used for the chip (0x2000).
+
+Optional properties:
+- ccr : NDFC config and control register value (default 0).
+- bank-settings : NDFC bank configuration register value (default 0).
+- partition(s) - follows the OF MTD standard for partitions
+
+Example:
+
[EMAIL PROTECTED],0 {
+ compatible = amcc,ndfc;
+ reg = 0x0001 0x 0x2000;
+ ccr = 0x1000;
+ bank-settings = 0x8000;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ [EMAIL PROTECTED] {
+ label = kernel;
+ reg = 0x 0x0020;
+ };
+ [EMAIL PROTECTED] {
+ label = root;
+ reg = 0x0020 0x03E0;
+ };
+};
+
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Re: [PATCH] ndfc driver
On Thu, 4 Dec 2008 09:01:07 -0500 Josh Boyer [EMAIL PROTECTED] wrote: You also seem to only support a single NAND chip, however the NDFC can support multiple chips. Have you looked at how the the fsl_elbc_nand driver does multiple chip support? If not, could you at least document the limitation in the patch? Signed-off-by: Sean MacLennan [EMAIL PROTECTED] --- diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0352d5c..3dd85e8 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -2,11 +2,15 @@ * drivers/mtd/ndfc.c * * Overview: - * Platform independend driver for NDFC (NanD Flash Controller) + * Platform independent driver for NDFC (NanD Flash Controller) * integrated into EP440 cores * * Ported to an OF platform driver by Sean MacLennan * + * The NDFC supports multiple chips, but this driver only supports a + * single chip since I do not have access to any boards with + * multiple chips. + * * Author: Thomas Gleixner * * Copyright 2006 IBM ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
Hi Sean,
On Mon, Dec 08, 2008 at 07:34:46PM -0500, Sean MacLennan wrote:
On Thu, 4 Dec 2008 09:01:07 -0500
Josh Boyer [EMAIL PROTECTED] wrote:
In addition to an example DTS patch (probably to warp itself), could
you briefly write up a binding and put it in
Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC
the devicetree-discuss list on that part.
Here is a start at the doc. I have sent it as a patch, but could just
as easily send raw text.
The example comes from the warp dts, just with less partitions, so I
have not included a warp dts patch here.
Cheers,
Sean
diff --git a/Documentation/powerpc/dts-bindings/amcc/ndfc.txt
b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt new file mode 100644
index 000..668f4a9
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/amcc/ndfc.txt
@@ -0,0 +1,31 @@
+AMCC NDFC (NanD Flash Controller)
+
+Required properties:
+- compatible : amcc,ndfc.
+- reg : should specify chip select and size used for the chip (0x2000).
+
+Optional properties:
+- ccr : NDFC config and control register value (default 0).
+- bank-settings : NDFC bank configuration register value (default 0).
+- partition(s) - follows the OF MTD standard for partitions
+
+Example:
+
[EMAIL PROTECTED],0 {
+ compatible = amcc,ndfc;
The first line in this file says that this is a controller...
+ reg = 0x0001 0x 0x2000;
+ ccr = 0x1000;
+ bank-settings = 0x8000;
+ #address-cells = 1;
+ #size-cells = 1;
+ [EMAIL PROTECTED] {
So this is a controller with partitions? ;-)
Recalling my own mistakes with the FSL UPM NAND controller bindings,
and Josh's comment:
http://www.mail-archive.com/linuxppc-dev@ozlabs.org/msg16572.html
I think the bindings should look like this:
[EMAIL PROTECTED] {
...controller's properties...
[EMAIL PROTECTED] {
...chip's properties...
[EMAIL PROTECTED] {
...partition's properties...
};
};
[EMAIL PROTECTED] {
...
};
};
Sure, I understand that there are plenty of boards with the old
scheme flashed into the firmware... Just something you might
want to consider for the future updates for the driver/bindings.
Thanks,
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [PATCH] ndfc driver
On Tue, 9 Dec 2008 05:11:15 +0300
Anton Vorontsov [EMAIL PROTECTED] wrote:
So this is a controller with partitions? ;-)
Actually, I did it this way to mimic the look of the NOR. Really, we
shouldn't care about the NAND chip.
Here is the complete NOR and NAND DTS:
[EMAIL PROTECTED],0 {
compatible = amd,s29gl032a, cfi-flash;
bank-width = 2;
reg = 0x 0x 0x0040;
#address-cells = 1;
#size-cells = 1;
[EMAIL PROTECTED] {
label = splash;
reg = 0x 0x0002;
};
[EMAIL PROTECTED] {
label = fpga;
reg = 0x030 0x0004;
};
[EMAIL PROTECTED] {
label = env;
reg = 0x034 0x0004;
};
[EMAIL PROTECTED] {
label = u-boot;
reg = 0x038 0x0008;
};
};
[EMAIL PROTECTED],0 {
compatible = amcc,ndfc;
reg = 0x0001 0x 0x2000;
ccr = 0x1000;
bank-settings = 0x8000;
#address-cells = 1;
#size-cells = 1;
[EMAIL PROTECTED] {
label = kernel;
reg = 0x 0x0020;
};
[EMAIL PROTECTED] {
label = root;
reg = 0x0020 0x03E0;
};
[EMAIL PROTECTED] {
label = persistent;
reg = 0x0400 0x0400;
};
[EMAIL PROTECTED] {
label = persistent1;
reg = 0x0800 0x0400;
};
[EMAIL PROTECTED] {
label = persistent2;
reg = 0x0C00 0x0400;
};
};
Now I know I am cheating a bit but it does make it *look*
consistent.
But comments are welcome. I also could remove the partitions for now. A
partially supported NDFC is better than none at all.
Cheers,
Sean
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Re: [PATCH] ndfc driver
On Mon, 8 Dec 2008 21:45:12 -0500 Sean MacLennan [EMAIL PROTECTED] wrote: On Tue, 9 Dec 2008 05:11:15 +0300 Anton Vorontsov [EMAIL PROTECTED] wrote: So this is a controller with partitions? ;-) Actually, I did it this way to mimic the look of the NOR. Really, we shouldn't care about the NAND chip. Except there is no controller in front of the NOR. It's all just MMIOs. With NDFC, there is a controller, you have to do things to it to talk to different chips, etc. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
On Mon, 8 Dec 2008 22:32:27 -0500
Josh Boyer [EMAIL PROTECTED] wrote:
Except there is no controller in front of the NOR. It's all just
MMIOs. With NDFC, there is a controller, you have to do things to it
to talk to different chips, etc.
Ok, I have the following dts working... would this be better? It
basically follows the fsl,upm-nand model. I can produce a new patch to
ndfc.c for this:
[EMAIL PROTECTED],0 {
compatible = amcc,ndfc;
reg = 0x0001 0x 0x2000;
ccr = 0x1000;
bank-settings = 0x8000;
#address-cells = 1;
#size-cells = 1;
nand {
#address-cells = 1;
#size-cells = 1;
[EMAIL PROTECTED] {
label = kernel;
reg = 0x 0x0020;
};
[EMAIL PROTECTED] {
label = root;
reg = 0x0020 0x03E0;
};
[EMAIL PROTECTED] {
label = persistent;
reg = 0x0400 0x0400;
};
[EMAIL PROTECTED] {
label = persistent1;
reg = 0x0800 0x0400;
};
[EMAIL PROTECTED] {
label = persistent2;
reg = 0x0C00 0x0400;
};
};
};
Here is the boot output for both the NOR and the NAND (just for
comparison):
ffc0.nor: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
ffc0.nor: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
RedBoot partition parsing not available
Creating 4 MTD partitions on ffc0.nor:
0x-0x0002 : splash
0x0030-0x0034 : fpga
0x0034-0x0038 : env
0x0038-0x0040 : u-boot
NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 3,3V
8-bit)
Scanning device for bad blocks
Creating 5 MTD partitions on d000.ndfc.nand:
0x-0x0020 : kernel
0x0020-0x0400 : root
0x0400-0x0800 : persistent
0x0800-0x0c00 : persistent1
0x0c00-0x1000 : persistent2
If everybody likes this better, I can produce a code patch.
Cheers,
Sean
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Re: [PATCH] ndfc driver
On Wed, 3 Dec 2008 22:28:32 -0500 Sean MacLennan [EMAIL PROTECTED] wrote: Hi Sean, A couple of comments/requests below. The current ndfc driver only compiles under arch/ppc. This arch was removed from the kernel. I notice the event entry for the ndfc in Kconfig has been removed in 2.6.28. This patch converts the ndfc to a proper OF (OpenFirmware) driver. I can give a working example of the DTS if needed. In addition to an example DTS patch (probably to warp itself), could you briefly write up a binding and put it in Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC the devicetree-discuss list on that part. The patch has been in production use on the PIKA Warp Appliance and is in use by others. The Warp basically boots from NAND, so the ndfc driver is very important to us. Looking over the patch it seems pretty straight-forward and I don't see anything immediately wrong with it. You do have a number of semi-unrelated changes to the actual port to of_platform though, like the s/__raw_writel/out_be32 stuff, the addition of partition parsing, etc. I'm wondering if you could do those fixups separately from the actual port. Also, could you document why the data structures changed as they did in the changelog or perhaps in a summary email. You also seem to only support a single NAND chip, however the NDFC can support multiple chips. Have you looked at how the the fsl_elbc_nand driver does multiple chip support? If not, could you at least document the limitation in the patch? This is a bi-monthly posting ;) Keep at it Sean. Your work is appreciated, even if the rest of us are slow to review. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
On Thu, 4 Dec 2008 09:01:07 -0500 Josh Boyer [EMAIL PROTECTED] wrote: On Wed, 3 Dec 2008 22:28:32 -0500 Sean MacLennan [EMAIL PROTECTED] wrote: Hi Sean, A couple of comments/requests below. In addition to an example DTS patch (probably to warp itself), could you briefly write up a binding and put it in Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC the devicetree-discuss list on that part. The DTS patch was a separate email to the linuxppc-dev list. I'll try to find it. I will look into writing up the binding. Looking over the patch it seems pretty straight-forward and I don't see anything immediately wrong with it. You do have a number of semi-unrelated changes to the actual port to of_platform though, like the s/__raw_writel/out_be32 stuff, the addition of partition parsing, etc. I'm wondering if you could do those fixups separately from the actual port. Also, could you document why the data structures changed as they did in the changelog or perhaps in a summary email. The __raw_writel changes where from feedback from this list. I will try to find the email. This patch originally goes back to January... so I have problems remembering why all the changes where made ;) Believe it or not, we have gone through 3 or 4 repositories since then. Finding history is basically impossible :( So I have to try to rely on an email trail. You also seem to only support a single NAND chip, however the NDFC can support multiple chips. Have you looked at how the the fsl_elbc_nand driver does multiple chip support? If not, could you at least document the limitation in the patch? I will document the limitation. I do not have access to a board with multiple chips and I don't like submitting something I can't test. Cheers, Sean ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] ndfc driver
Hi, I can confirm that this driver works fine on custom 4060EX board. The NAND is 256MiB Samsumg, with 2K page size. I had to modify U-boot to provide EBC ranges property for NAND, but otherwise it worked from the beginning. I didn't see any reaction to Sean's post, but this driver is important IMHO, since several in-tree 44X boards (e.g Canyonlands and Glacier) lack NAND support, and Warp uses old platform device model for its NAND. Felix Radensky Embedded Solutions Ltd. http://www.embedded-sol.com ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: OF NDFC
Is anybody working on the device-tree-aware ppc 44x NAND flash controller (ndfc) driver? Not to my knowledge. We sort of need a decent binding for NAND flash in general first. Not really. You can put the NAND controller in the device tree without describing the NAND flash itself -- and for that, you only need a name, compatible, reg, and maybe some interrupt stuff. Segher ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: OF NDFC
On Thu, 6 Sep 2007 15:06:03 +0200 Segher Boessenkool [EMAIL PROTECTED] wrote: Is anybody working on the device-tree-aware ppc 44x NAND flash controller (ndfc) driver? Not to my knowledge. We sort of need a decent binding for NAND flash in general first. Not really. You can put the NAND controller in the device tree without describing the NAND flash itself -- and for that, you only need a name, compatible, reg, and maybe some interrupt stuff. He said driver. To test a driver, you'd need the binding for both the controller, and the NAND flash it controls. Otherwise, the driver isn't going to do much :). josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: OF NDFC
Josh Boyer wrote: On Thu, 6 Sep 2007 15:06:03 +0200 Segher Boessenkool [EMAIL PROTECTED] wrote: Is anybody working on the device-tree-aware ppc 44x NAND flash controller (ndfc) driver? Not to my knowledge. We sort of need a decent binding for NAND flash in general first. Not really. You can put the NAND controller in the device tree without describing the NAND flash itself -- and for that, you only need a name, compatible, reg, and maybe some interrupt stuff. He said driver. To test a driver, you'd need the binding for both the controller, and the NAND flash it controls. Otherwise, the driver isn't going to do much :). josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev AFAIK, NAND flash is autodetected by reading it's ID at runtime, so there should be no need for flash bindings. Thanks, Valentine. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: OF NDFC
On Thu, 06 Sep 2007 17:30:08 +0400 Valentine Barshak [EMAIL PROTECTED] wrote: AFAIK, NAND flash is autodetected by reading it's ID at runtime, so there should be no need for flash bindings. Well, I'm not really sure. CFI and JEDEC can both be probed as well, and we're working on a binding there. But if you think you can come up with a driver for NDFC that doesn't require some kind of device tree description of the devices it controls, then by all means go for it. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: OF NDFC
On Wed, 5 Sep 2007 22:17:03 +0400 Valentine Barshak [EMAIL PROTECTED] wrote: Is anybody working on the device-tree-aware ppc 44x NAND flash controller (ndfc) driver? Not to my knowledge. We sort of need a decent binding for NAND flash in general first. And David's recent flash binding doesn't address NAND flash. It's on my list of things to do, but if someone gets there first then great. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
