re: PPC405 system slow boot
hi! i've recently had a similar situation with a XC2VP50-based custom board. There was no SystemACE involved, we load the FPGA via a CPLD/serial flash. the problem resided in the interrupt controller, which was not able to enable interrupts due to an error in the MHS file. you should check that your interrupt controller section includes the following parameters: PARAMETER C_HAS_IPR = 1 PARAMETER C_HAS_SIE = 1 PARAMETER C_HAS_CIE = 1 PARAMETER C_HAS_IVR = 1 the intc driver uses SIE and CIE to atomically enable and disable interrupts. when the uartlite interrupt was not enabled, the uartlite driver encountered timeouts which caused single characters to appear at the serial console, similar to what you described. hope that helps, arvid staub Von: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Im Auftrag von Clint Thomas Gesendet: Montag, 28. August 2006 21:57 An: linuxppc-embedded@ozlabs.org Betreff: PPC405 system slow boot Hey guys, I've run through the loops to try and figure what could be wrong with this system. The board in question is modeled after the Xilinx ML300 board. It uses a Xilinx System ACE chip to load a FPGA / Kernel image from compact flash. Originally, I was trying to use the CompactFlash as the root file system, but because of issues in either the design or software, this would only work if SysAce was in polled I/O mode. To circumvent this, I built my root filesystem into an initrd image and built a single ELF file with the Kernel and RFS, then strapped that to the FPGA bit file to make a single FPGA/Kernel/RFS SysAce file. Upon decompression, the Linux kernel boots quickly and loads all of the device drivers. However when it gets to the prompt, it starts slowing down. Output and input to and from the board becomes very very slow (it displays 2 characters roughly every 20 seconds). Originally I believed this to be the CPU still polling SystemAce, so I disabled the Linux System ACE drivers to remove that as a possibility, however after doing this, the problem still persists, even with the RFS in ram! Has anybody encountered a similar situation to this before, with possible insight towards a solution? Thank you for your time. Clinton Thomas [EMAIL PROTECTED] ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
2 Ethernet port operating in a PPC405EP system
Hi all, Sorry for such long e-mail. I am now working on a STB project, and our board is a IBM PPC405EP with 2 ethernet ports. U-Boot 1.0.0 and linux 2.4.20 (from MontaVista) is used and update is not recommended. Each ethernet port has a RTL8021CP PHY connected. Under u-boot environment, only 1 ethernet port is operating. But sometimes the port is not able to PING other PCs within the same subnet. Also some modifications are made (under bd_t) to let linux kernel fetch 2 different MAC address when boot into linux kernel. Error log (U-Boot): ## snip ## Hit any key to stop autoboot: 0 = setenv ipaddr 10.6.64.343 = setenv ipaddr 10.6.64.34 = ping 10.6.64.128 ENET Speed is 100 Mbps - FULL duplex connection the board holds here about several seconds ping failed; host 10.6.64.128 is not alive ## snip ## Under linux environment, 2 ethernet ports are operating. But sometimes only ethernet 1 is operating (by running a udhcpc, from busybox-v1.00-pre8); sometimes both are not operating. When ethernet 1 is operating (can fetch a IP address from DHCP server, say 10.6.64.111), then I assigned a static IP address (say, 192.168.1.120) and let the board PING to different subnets at the same time. But the ethernet 2 cannot PING out while ethernet 1 is operating ... Error log (Linux): ## snip ## Press CTRL-C to enter shell within 1 sec ~ # udhcpc -i eth0 -s /etc/udhcpc.sh info, udhcpc (v0.9.9-pre) started debug, Sending discover... debug, Sending discover... the ethernet port 1 goes wrong and cannot get IP from DHCP server, until I plug and unplug the ethernet cable several times, it works again debug, Sending discover... debug, Sending select for 10.6.64.197... info, Lease of 10.6.64.197 obtained, lease time 691200 deleting routers SIOCDELRT: No such process adding dns 10.6.2.11 adding dns 10.6.2.12 ~ # ping 10.6.64.128 PING 10.6.64.128 (10.6.64.128): 56 data bytes 64 bytes from 10.6.64.128: icmp_seq=0 ttl=64 time=9.4 ms 64 bytes from 10.6.64.128: icmp_seq=1 ttl=64 time=0.3 ms 64 bytes from 10.6.64.128: icmp_seq=2 ttl=64 time=0.3 ms --- 10.6.64.128 ping statistics --- 3 packets transmitted, 3 packets received, 0% packet loss round-trip min/avg/max = 0.3/3.3/9.4 ms ~ # ifconfig eth1 192.168.1.120 EMAC1 open, with PHY @ 0x13 ibm_ocp_phy.c: cclo - fep-link = 1 -- phy: RTL8201CP, mii_parse_anar(0x01e1), phy=0x13 -- eth1: IBM EMAC: link up, 100 Mbps Full Duplex, auto-negotiation complete. eth1: IBM EMAC: MAC cc:0b:20:08:21:b2. ~ # ping 192.168.1.123 PING 192.168.1.123 (192.168.1.123): 56 data bytes --- 192.168.1.123 ping statistics --- 3 packets transmitted, 0 packets received, 100% packet loss ~ # ## snip ## I also serached something about this issue on internet, I found something: http://ozlabs.org/pipermail/linuxppc-embedded/2003-December/012802.html Are there any updates about this issue? Or my problem is not related to this? Please help. Thanks. Best regards, Lo Chun Chung This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: DS1302 driver for powerpc
On Wed, Aug 30, 2006 at 07:54:16PM +0800, Chun Chung Lo wrote: Hi all, I am now doing a STB project and the development board uses a DS1302 (trickle charge timekeeping chip) as a RTC. Our board is a IBM PPC405EP with a linux kernel 2.4.20 running on it. And the DS1302 is controlled by 2 GPIO pins instead of I2C. I would like to ask are there any porting of DS1302 support under ppc architecture? (I can only find DS1302 is supported under cris architecture.) There doesn't seem to be any DS1302 support for ppc available. However, even if there were a platform with DS1302 support you'd be in the same boat as the low-level support for cris. Support for DS1302 has a glue layer that's board-specific based on what GPIO pins are used to drive it. So if you had this driver for another PPC system like 83xx you'd still have no better starting point than the cris ds1302 driver glue since the GPIO mechanism/connection is different. Porting the board-specific glue from arch/cris/drivers/ds1302.c to 4xx GPIO is trivial to do though. -Matt ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [CFT:PATCH] Removing possible wrong asm/serial.h inclusions
From: Russell King [EMAIL PROTECTED]
Subject: [CFT:PATCH] Removing possible wrong asm/serial.h inclusions
Date: Mon, 28 Aug 2006 09:52:44 +0100
diff --git a/drivers/serial/m32r_sio.c b/drivers/serial/m32r_sio.c
--- a/drivers/serial/m32r_sio.c
+++ b/drivers/serial/m32r_sio.c
@@ -76,17 +76,16 @@
*/
#define is_real_interrupt(irq) ((irq) != 0)
-#include asm/serial.h
+#define BASE_BAUD115200
/* Standard COM flags */
#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
/*
* SERIAL_PORT_DFNS tells us about built-in ports that have no
* standard enumeration mechanism. Platforms that can find all
* serial ports via mechanisms like ACPI or PCI need not supply it.
*/
-#undef SERIAL_PORT_DFNS
#if defined(CONFIG_PLAT_USRV)
#define SERIAL_PORT_DFNS \
@@ -109,7 +108,7 @@
#endif /* !CONFIG_PLAT_USRV */
static struct old_serial_port old_serial_port[] = {
- SERIAL_PORT_DFNS/* defined in asm/serial.h */
+ SERIAL_PORT_DFNS
};
#define UART_NR ARRAY_SIZE(old_serial_port)
Acked-by: Hirokazu Takata [EMAIL PROTECTED]
Thank you.
-- Takata
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Some problem about code reading
Hi, I met some problems when reading sourcecode of u-boot 1.1.4 (for mpc85xx) file /cpu/mpc85xx/start.s line 276 276. #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)277. /* Special sequence needed to update CCSRBAR itself */278. lisr4, [EMAIL PROTECTED]279. orir4, r4, [EMAIL PROTECTED] 280. 281. lisr5, [EMAIL PROTECTED]282. orir5, r5, [EMAIL PROTECTED]283. srwir6,r5,12284. stwr6, 0(r4)285. isync 286. 287. lisr5, 0x288. orir5,r5,0xf000289. lwzr5, 0(r5)290. isync 291. 292. lisr3, [EMAIL PROTECTED]293. lwzr5, [EMAIL PROTECTED](r3)294. isync295. #endif I think it means if we don't use default CCSRBAR, we put the CCSRBAR addr actually used to the proper place in default CCSRBAR, so that it can jump to the addr we want to automatically.(line 276-286). But, I don't know what line 287-294 does.Can some one tell me pls? Thanks for your help. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
RE: Some problem about code reading
Hi, please read the following from MPC85xx UM about the sequence on how to write CCSRBAR: * When the e500 core is writing to CCSRBAR, it should use the following sequence: Read the current value of CCSRBAR using a load word instruction followed by an isync. This forces all accesses to configuration space to complete. Write the new value to CCSRBAR. Perform a load of an address that does not access configuration space or the on-chip SRAM, but has an address mapping already in effect (for example, boot ROM). Follow this load with an isync. Read the contents of CCSRBAR from its new location, followed by another isync instruction. Thecodesbetween line 287-294 complete the third step above. Haiying From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of enormSent: Wednesday, August 30, 2006 9:46 AMTo: linuxppc-embedded@ozlabs.orgSubject: Some problem about code reading Hi, I met some problems when reading sourcecode of u-boot 1.1.4 (for mpc85xx) file /cpu/mpc85xx/start.s line 276 276. #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)277. /* Special sequence needed to update CCSRBAR itself */278. lisr4, [EMAIL PROTECTED]279. orir4, r4, [EMAIL PROTECTED] 280. 281. lisr5, [EMAIL PROTECTED]282. orir5, r5, [EMAIL PROTECTED]283. srwir6,r5,12284. stwr6, 0(r4)285. isync 286. 287. lisr5, 0x288. orir5,r5,0xf000289. lwzr5, 0(r5)290. isync 291. 292. lisr3, [EMAIL PROTECTED]293. lwzr5, [EMAIL PROTECTED](r3)294. isync295. #endif I think it means if we don't use default CCSRBAR, we put the CCSRBAR addr actually used to the proper place in default CCSRBAR, so that it can jump to the addr we want to automatically.(line 276-286). But, I don't know what line 287-294 does.Can some one tell me pls? Thanks for your help. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: 2 Ethernet port operating in a PPC405EP system
On Wed, Aug 30, 2006 at 09:17:20PM +0800, Chun Chung Lo wrote: I know my source code is vert old. But since there are lots of applications developed base on this 2 sets of source code, if the kernel and U-Boot needs to change, the above applications (tons of codes) also need to revise ... (lots of multimedia players, drivers, and other supporting tools). My team cannot afford such great change. So I say update is not recommended ... Hopefully your product will say: buy this product is not recommended :) Don't repeat the same mistake as the MediaMVP, it uses the same processor and same kernel version, it sucks badly... -otto ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
RE: 2 Ethernet port operating in a PPC405EP system
Hi, I really do not know what happened about MediaMVP, could you mind giving me a review? Thanks. Best regards, Lo Chun Chung -Original Message- From: Otto Solares [mailto:[EMAIL PROTECTED] Sent: Thursday, 31 August, 2006 2:23 AM To: Chun Chung Lo Cc: linuxppc-embedded@ozlabs.org Subject: Re: 2 Ethernet port operating in a PPC405EP system On Wed, Aug 30, 2006 at 09:17:20PM +0800, Chun Chung Lo wrote: I know my source code is vert old. But since there are lots of applications developed base on this 2 sets of source code, if the kernel and U-Boot needs to change, the above applications (tons of codes) also need to revise ... (lots of multimedia players, drivers, and other supporting tools). My team cannot afford such great change. So I say update is not recommended ... Hopefully your product will say: buy this product is not recommended :) Don't repeat the same mistake as the MediaMVP, it uses the same processor and same kernel version, it sucks badly... -otto This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: DS1302 driver for powerpc
On Thu, Aug 31, 2006 at 08:51:22AM +0800, Chun Chung Lo wrote: Hi, Thanks for your help. But I also do not have this driver for 83xx. (as my linux is comes from Montavista) The 83xx reference was a hypothetical. There is no 83xx driver for the ds1302. Could you mind providing me a link / or a source of such driver for me to reference ? My advice is to port the cris DS1302 driver to your board-specific GPIO configuration. -Matt ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
RE: DS1302 driver for powerpc
Hi, That's good. I also started to work on it. Thanks for your quick reply. Best regards, Lo Chun Chung -Original Message- From: Matt Porter [mailto:[EMAIL PROTECTED] Sent: Thursday, 31 August, 2006 9:12 AM To: Chun Chung Lo Cc: linuxppc-embedded@ozlabs.org Subject: Re: DS1302 driver for powerpc On Thu, Aug 31, 2006 at 08:51:22AM +0800, Chun Chung Lo wrote: Hi, Thanks for your help. But I also do not have this driver for 83xx. (as my linux is comes from Montavista) The 83xx reference was a hypothetical. There is no 83xx driver for the ds1302. Could you mind providing me a link / or a source of such driver for me to reference ? My advice is to port the cris DS1302 driver to your board-specific GPIO configuration. -Matt This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
atomic operations in user space
On 8/30/06, Esben Nielsen nielsen.esben at gogglemail.com wrote: On Tue, 29 Aug 2006, Li Yang wrote: This is exactly how it is supposed to work! That's why there is a loop in the atomic increment - you check if you still had the reservation after the transaction by checking the result from the stwcx, and if not, retry. I surely know all the theories you mentioned clearly. But please do look at the case I gave. Correct me if I missed anything. Thanks All the lwarx and stwcx operate on the same address. Task A Task B lwarx // Get RESERVATION .. lwarx stwcx // RESERVATION cleared . . lwarx // Get RESERVATION again Now we do a task switch involving atomic operations, and thus an reservation on another address. This makes sense for me.
Help for building linux 2.6.15
In message 20060829171138.y9uuwvfi4gs48ws4 at webmail.mcgill.ca you wrote: I am working on ELDK 4.0 package with my evaluation board: AM MPC875, after configuration for my board, and do 'make zImage', I got the following errors: I cannot find any board support for this board in the 2.6 kernel trees. Who ported Linux to this hardware? Please go and ask these guys. CC arch/ppc/syslib/m8xx_setup.o arch/ppc/syslib/m8xx_setup.c:56: error: 'bd_t' undeclared here (not in a function) Broken code, and/or a broken configuration, if you ask me. Can anyone help me? Thanks. Which board configration are you using? And where is the board support coming from? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Change is the essential process of all existence. -- Spock, Let That Be Your Last Battlefield, stardate 5730.2
atomic operations in user space
-Original Message- From: Liu Dave-r63238 Sent: Wednesday, August 30, 2006 10:17 AM To: Li Yang-r58472; linuxppc-embedded at ozlabs.org; linuxppc-dev at ozlabs.org Subject: RE: atomic operations in user space [snip] I surely know all the theories you mentioned clearly. But please do look at the case I gave. Correct me if I missed anything. Thanks All the lwarx and stwcx operate on the same address. Task ATask B lwarx // Get RESERVATION .. lwarx stwcx // RESERVATION cleared . . lwarx // Get RESERVATION again stwcx //Note here: RESERVATION is valid, address is the same. So the result is commited, no retry for task A . stwcx //RESERVATION is cleared, retry atomic op for task B Please be noted that reservation is only identified by reservation bit and address operated on. So different lwarx's on the same address, may be considered as the same reservation. Is this your reason we cannot do atomic operation in user space? How about the kernel space? You can image it. The context switching as above also happen in kernel space, Why we can do atomic operation in kernel space, not do in user space? There are substantial different between kernel and user control path. First, interrupt can't be interrupted by user process. Second, context switch can be explicitly controlled in kernel, but not in user space. You are assuming the context switching cause the reservation broken. but we can do atomic operation in kernel space. The context switching really is the execption of processor, If we can clear the wrong RESERVATION before exception return, I think we can solve this problem. We can dummy stwcx. before exception return or the processor automaticly clear the reservation in exception. I assume stwcx is a costing instruction, and I don't see such code indeed. - Leo
atomic operations in user space
-Original Message- From: Liu Dave-r63238 Sent: Wednesday, August 30, 2006 10:27 AM To: Liu Dave-r63238; Li Yang-r58472; linuxppc-embedded at ozlabs.org; linuxppc-dev at ozlabs.org Subject: RE: atomic operations in user space [snip] I surely know all the theories you mentioned clearly. But please do look at the case I gave. Correct me if I missed anything. Thanks All the lwarx and stwcx operate on the same address. Task A Task B lwarx // Get RESERVATION .. lwarx stwcx // RESERVATION cleared . . lwarx // Get RESERVATION again stwcx //Note here: RESERVATION is valid, address is the same. So the result is commited, no retry for task A . stwcx //RESERVATION is cleared, retry atomic op for task B Please be noted that reservation is only identified by reservation bit and address operated on. So different lwarx's on the same address, may be considered as the same reservation. Is this your reason we cannot do atomic operation in user space? How about the kernel space? You can image it. The context switching as above also happen in kernel space, Why we can do atomic operation in kernel space, not do in user space? You are assuming the context switching cause the reservation broken. but we can do atomic operation in kernel space. The context switching really is the execption of processor, If we can clear the wrong RESERVATION before exception return, I think we can solve this problem. We can dummy stwcx. before exception return or the processor automaticly clear the reservation in exception. Are you missing these important things? -DAve I got it. I noticed that all of execption return in kernel did stwcx. to clear the wrong reserved bit. See the source code. .globl ret_from_except_full ret_from_except_full: REST_NVGPRS(r1) /* fall through */ .globl ret_from_except ret_from_except: .. restore: lwz r0,GPR0(r1) lwz r2,GPR2(r1) REST_4GPRS(3, r1) REST_2GPRS(7, r1) lwz r10,_XER(r1) lwz r11,_CTR(r1) mtspr SPRN_XER,r10 mtctr r11 PPC405_ERR77(0,r1) stwcx. r0,0,r1 /* to clear the reservation */ Ya, you found the point. There is no problem for me about this question. - Leo
atomic operations in user space
[snip] Is this your reason we cannot do atomic operation in user space? How about the kernel space? You can image it. The context switching as above also happen in kernel space, Why we can do atomic operation in kernel space, not do in user space? There are substantial different between kernel and user control path. First, interrupt can't be interrupted by user process. Second, context switch can be explicitly controlled in kernel, but not in user space. I agree this, but from the processor's view, the context switch is the same to user space and kernel space. The exception control flow only happen at exception interrupt. What is different you point ? You are assuming the context switching cause the reservation broken. but we can do atomic operation in kernel space. The context switching really is the execption of processor, If we can clear the wrong RESERVATION before exception return, I think we can solve this problem. We can dummy stwcx. before exception return or the processor automaticly clear the reservation in exception. I assume stwcx is a costing instruction, and I don't see such code indeed.
atomic operations in user space
-Original Message- From: Liu Dave-r63238 Sent: Wednesday, August 30, 2006 10:43 AM To: Li Yang-r58472; 'linuxppc-embedded at ozlabs.org'; 'linuxppc-dev at ozlabs.org' Subject: RE: RE: atomic operations in user space [snip] Is this your reason we cannot do atomic operation in user space? How about the kernel space? You can image it. The context switching as above also happen in kernel space, Why we can do atomic operation in kernel space, not do in user space? There are substantial different between kernel and user control path. First, interrupt can't be interrupted by user process. Second, context switch can be explicitly controlled in kernel, but not in user space. I agree this, but from the processor's view, the context switch is the same to user space and kernel space. The exception control flow only happen at exception interrupt. Exception is special and tiny part of the kernel, which should be programmed carefully not to break any thing. Anyway, as you found, clear reservation in exception do solve all the problems. What is different you point ? You are assuming the context switching cause the reservation broken. but we can do atomic operation in kernel space. The context switching really is the execption of processor, If we can clear the wrong RESERVATION before exception return, I think we can solve this problem. We can dummy stwcx. before exception return or the processor automaticly clear the reservation in exception. I assume stwcx is a costing instruction, and I don't see such code indeed.
atomic operations in user space
[snip] Is this your reason we cannot do atomic operation in user space? How about the kernel space? You can image it. The context switching as above also happen in kernel space, Why we can do atomic operation in kernel space, not do in user space? There are substantial different between kernel and user control path. First, interrupt can't be interrupted by user process. Second, context switch can be explicitly controlled in kernel, but not in user space. I agree this, but from the processor's view, the context switch is the same to user space and kernel space. The exception control flow only happen at exception interrupt. What is different you point ? Exception is special and tiny part of the kernel, which should be programmed carefully not to break any thing. Anyway, as you found, clear reservation in exception do solve all the problems. Can we do atomic operation in user space as kernel space? You are assuming the context switching cause the reservation broken. but we can do atomic operation in kernel space. The context switching really is the execption of processor, If we can clear the wrong RESERVATION before exception return, I think we can solve this problem. We can dummy stwcx. before exception return or the processor automaticly clear the reservation in exception. I assume stwcx is a costing instruction, and I don't see such code indeed.
How to turn off MMU in MPC8540
Hi Can anyone know how to turn off MMU in MPC8540? Thanksregards Suneel -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/8473ba00/attachment.htm
Gabe Johnson is out of the office.
I will be out of the office starting 08/30/2006 and will not return until 09/05/2006. I will respond to your message when I return.
How to turn off MMU in MPC8540
-Original Message- From: linuxppc-embedded-bounces+leoli=freescale.com at ozlabs.org [mailto:linuxppc-embedded-bounces+leoli=freescale.com at ozlabs.o rg] On Behalf Of Reddy Suneel-ASR125 Sent: Wednesday, August 30, 2006 2:25 PM To: linuxppc-embedded at ozlabs.org Subject: How to turn off MMU in MPC8540 Hi Can anyone know how to turn off MMU in MPC8540? I heard that it can't be turned off on e500.
How to turn off MMU in MPC8540
Turn off MMU of e500? hmmm... Do you want to get real address space? You can emulate this. -DAve From: linuxppc-embedded-bounces+daveliu=freescale.com at ozlabs.org [mailto:linuxppc-embedded-bounces+daveliu=freescale.com at ozlabs.org] On Behalf Of Reddy Suneel-ASR125 Sent: Wednesday, August 30, 2006 2:25 PM To: linuxppc-embedded at ozlabs.org Subject: How to turn off MMU in MPC8540 Hi Can anyone know how to turn off MMU in MPC8540? Thanksregards Suneel -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/45818ea6/attachment.htm
atomic operations in user space
On Wed, Aug 30, 2006 at 10:55:39AM +0800, Liu Dave-r63238 wrote: Can we do atomic operation in user space as kernel space? Yes. -Olof
Atomic operations in user space: Yes but No
On Wed, 2006-08-30 at 01:33 -0500, Olof Johansson wrote: On Wed, Aug 30, 2006 at 10:55:39AM +0800, Liu Dave-r63238 wrote: Can we do atomic operation in user space as kernel space? Ok, let's hope that clarifies it for everybody. Atomic operations in user space are possible using reservations (lwarx/stwcx. or their 64 bits counterpart). However they are very much not recommended. The reason they work is that the kernel always clears all pending reservations in the exception path, thus if there is a task switch, an interrupt or anything that can break the user program flow in the middle of it's lwarx/stwcx. loop, the kernel will return to userspace with all reservations cleared, thus causing stwcx. to fail. However, they are not recommended unless you know VERY WELL what you are doing. When I say, VERY WELL in all uppercases, I really mean it. That is examples in books etc... are usually not enough to know very well what you are doing :) There are three issues at hand at least that I know about use of lwarx/stwcx, from the less to the most important: - Processor erratas. For example, the 405 requires a sync in an atomic loop. The kernel has a mecanism to have those sync's in and eventually comment them out at runtime. Future processors might have different erratas regarding those instructions. It's better to keep their usage local to the kernel and/or glibc to avoid having to fix too much userland problems when that happens. - Performance issues and possible livelocks. There are both processor and bus starvation issues related to the use of atomics. On some processors, it's very recommended for example, when a lock operation fails, to go do something else for a while (intentional branch mispredict for example) before trying again. In general, there are issues with cache lines used for lwarx/stwcx. ping-ponging all over the fabric on some heavy duty SMP machines if great care isn't taken with the way atomics or locks are laid out in memory and shared among threads. - Correctness vs. storage ordering. That's the biggest one. Almost every time I've seen userland code try to do their own atomic stuffs, it was done without full understanding of the out of order storage model of the PowerPC architecture and thus without appropriate barriers. This is a complicated topic and thus I won't get into a long explanation here, but let's say that outside of pure atomic counters that have no specific ordering requirements or no locking/exclusion semantics vs. the execution flow, you should _not_ try to do it yourself with atomics, but instead use some of the primitives provided by glibc. With NPTL, nowadays, glibc provides pretty fast implementations that do not use the kernel unless there is contention. So yes, you can, but most of the time, you should not. Cheers, Ben.
booting Linux in Linux using kexec tools
Hi I am trying to boot Linux (zImage.elf) in Linux using kexec tools. I am getting the folling crash sh-2.05b# sh-2.05b# kexec -e Shutting down gianfar ethernet Shutting down gianfar ethernet Shutting down gianfar ethernet Starting new kernel Bye! Oops: kernel access of bad area, sig: 11 [#1] PREEMPT NIP: 2E5C0020 LR: C000A3CC SP: C8D97DF0 REGS: c8d97d40 TRAP: 0400Not taintedMSR: 1000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 TASK = c82f84a0[665] 'kexec' THREAD: c8d96000 Last syscall: 88 GPR00: C8D97DF0 C82F84A0 2E5C1002 2E5C 0F35 C0307DBC GPR08: 2E5C0020 C035 C8D96000 10030450 0220 100CBD88 GPR16: 42202442 GPR24: 100D71C8 100D7508 2E5C1002 C0A8DC80 EE5C 2E5C C0A8DC80 Call trace: [c000a2fc] [c00302d0] [c000206c] Segmentation fault sh-2.05b# I am working on MPC8540 processor. can any one help me. Thanksregards Suneel -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/9a0e1a44/attachment.htm
PPC405 system slow boot
hi! i've recently had a similar situation with a XC2VP50-based custom board. There was no SystemACE involved, we load the FPGA via a CPLD/serial flash. the problem resided in the interrupt controller, which was not able to enable interrupts due to an error in the MHS file. you should check that your interrupt controller section includes the following parameters: PARAMETER C_HAS_IPR = 1 PARAMETER C_HAS_SIE = 1 PARAMETER C_HAS_CIE = 1 PARAMETER C_HAS_IVR = 1 the intc driver uses SIE and CIE to atomically enable and disable interrupts. when the uartlite interrupt was not enabled, the uartlite driver encountered timeouts which caused single characters to appear at the serial console, similar to what you described. hope that helps, arvid staub Von: linuxppc-embedded-bounces+arvid.staub=mediornet.com at ozlabs.org [mailto:linuxppc-embedded-bounces+arvid.staub=mediornet.com at ozlabs.org] Im Auftrag von Clint Thomas Gesendet: Montag, 28. August 2006 21:57 An: linuxppc-embedded at ozlabs.org Betreff: PPC405 system slow boot Hey guys, I've run through the loops to try and figure what could be wrong with this system. The board in question is modeled after the Xilinx ML300 board. It uses a Xilinx System ACE chip to load a FPGA / Kernel image from compact flash. Originally, I was trying to use the CompactFlash as the root file system, but because of issues in either the design or software, this would only work if SysAce was in polled I/O mode. To circumvent this, I built my root filesystem into an initrd image and built a single ELF file with the Kernel and RFS, then strapped that to the FPGA bit file to make a single FPGA/Kernel/RFS SysAce file. Upon decompression, the Linux kernel boots quickly and loads all of the device drivers. However when it gets to the prompt, it starts slowing down. Output and input to and from the board becomes very very slow (it displays 2 characters roughly every 20 seconds). Originally I believed this to be the CPU still polling SystemAce, so I disabled the Linux System ACE drivers to remove that as a possibility, however after doing this, the problem still persists, even with the RFS in ram! Has anybody encountered a similar situation to this before, with possible insight towards a solution? Thank you for your time. ? Clinton Thomas cthomas at soneticom.com ?
DS1302 driver for powerpc
Hi all, I am now doing a STB project and the development board uses a DS1302 (trickle charge timekeeping chip) as a RTC. Our board is a IBM PPC405EP with a linux kernel 2.4.20 running on it. And the DS1302 is controlled by 2 GPIO pins instead of I2C. I would like to ask are there any porting of DS1302 support under ppc architecture? (I can only find DS1302 is supported under cris architecture.) Thanks all. Best regards, Lo Chun Chung This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
2 Ethernet port operating in a PPC405EP system
Hi all, Sorry for such long e-mail. I am now working on a STB project, and our board is a IBM PPC405EP with 2 ethernet ports. U-Boot 1.0.0 and linux 2.4.20 (from MontaVista) is used and update is not recommended. Each ethernet port has a RTL8021CP PHY connected. Under u-boot environment, only 1 ethernet port is operating. But sometimes the port is not able to PING other PCs within the same subnet. Also some modifications are made (under bd_t) to let linux kernel fetch 2 different MAC address when boot into linux kernel. Error log (U-Boot): ## snip ## Hit any key to stop autoboot: 0 = setenv ipaddr 10.6.64.343 = setenv ipaddr 10.6.64.34 = ping 10.6.64.128 ENET Speed is 100 Mbps - FULL duplex connection the board holds here about several seconds ping failed; host 10.6.64.128 is not alive ## snip ## Under linux environment, 2 ethernet ports are operating. But sometimes only ethernet 1 is operating (by running a udhcpc, from busybox-v1.00-pre8); sometimes both are not operating. When ethernet 1 is operating (can fetch a IP address from DHCP server, say 10.6.64.111), then I assigned a static IP address (say, 192.168.1.120) and let the board PING to different subnets at the same time. But the ethernet 2 cannot PING out while ethernet 1 is operating ... Error log (Linux): ## snip ## Press CTRL-C to enter shell within 1 sec ~ # udhcpc -i eth0 -s /etc/udhcpc.sh info, udhcpc (v0.9.9-pre) started debug, Sending discover... debug, Sending discover... the ethernet port 1 goes wrong and cannot get IP from DHCP server, until I plug and unplug the ethernet cable several times, it works again debug, Sending discover... debug, Sending select for 10.6.64.197... info, Lease of 10.6.64.197 obtained, lease time 691200 deleting routers SIOCDELRT: No such process adding dns 10.6.2.11 adding dns 10.6.2.12 ~ # ping 10.6.64.128 PING 10.6.64.128 (10.6.64.128): 56 data bytes 64 bytes from 10.6.64.128: icmp_seq=0 ttl=64 time=9.4 ms 64 bytes from 10.6.64.128: icmp_seq=1 ttl=64 time=0.3 ms 64 bytes from 10.6.64.128: icmp_seq=2 ttl=64 time=0.3 ms --- 10.6.64.128 ping statistics --- 3 packets transmitted, 3 packets received, 0% packet loss round-trip min/avg/max = 0.3/3.3/9.4 ms ~ # ifconfig eth1 192.168.1.120 EMAC1 open, with PHY @ 0x13 ibm_ocp_phy.c: cclo - fep-link = 1 -- phy: RTL8201CP, mii_parse_anar(0x01e1), phy=0x13 -- eth1: IBM EMAC: link up, 100 Mbps Full Duplex, auto-negotiation complete. eth1: IBM EMAC: MAC cc:0b:20:08:21:b2. ~ # ping 192.168.1.123 PING 192.168.1.123 (192.168.1.123): 56 data bytes --- 192.168.1.123 ping statistics --- 3 packets transmitted, 0 packets received, 100% packet loss ~ # ## snip ## I also serached something about this issue on internet, I found something: http://ozlabs.org/pipermail/linuxppc-embedded/2003-December/012802.html Are there any updates about this issue? Or my problem is not related to this? Please help. Thanks. Best regards, Lo Chun Chung This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
[CFT:PATCH] Removing possible wrong asm/serial.h inclusions
Russell King rmk+lkml at arm.linux.org.uk wrote: --- a/arch/frv/kernel/setup.c +++ b/arch/frv/kernel/setup.c @@ -31,7 +31,6 @@ #include linux/serial_reg.h #include asm/setup.h -#include asm/serial.h #include asm/irq.h #include asm/sections.h #include asm/pgalloc.h Acked-By: David Howells dhowells at redhat.com
2 Ethernet port operating in a PPC405EP system
In message A7B1E4DD46AA7046A4398F745240F29402737D5C at ASPROEXG.astri.local you wrote: Sorry for such long e-mail. Actually it's not so long... I am now working on a STB project, and our board is a IBM PPC405EP with 2 ethernet ports. U-Boot 1.0.0 and linux 2.4.20 (from MontaVista) is used and update is not recommended. Each ethernet port has a RTL8021CP PHY connected. ... as reading stops here. Both U-Boot 1.0.0 and Linux 2.4.20 are not only old, they are ancient. Zillions of smaller and bigger bugs have been fixed since. Do yourself a favour and use current code. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de The software required `Windows 95 or better', so I installed Linux.
2 Ethernet port operating in a PPC405EP system
Hi, I know my source code is vert old. But since there are lots of applications developed base on this 2 sets of source code, if the kernel and U-Boot needs to change, the above applications (tons of codes) also need to revise ... (lots of multimedia players, drivers, and other supporting tools). My team cannot afford such great change. So I say update is not recommended ... Thanks for your quick reply. Best regards, Lo Chun Chung -Original Message- From: wd at denx.de [mailto:[EMAIL PROTECTED] Sent: Wednesday, 30 August, 2006 9:07 PM To: Chun Chung Lo Cc: linuxppc-embedded at ozlabs.org Subject: Re: 2 Ethernet port operating in a PPC405EP system In message A7B1E4DD46AA7046A4398F745240F29402737D5C at ASPROEXG.astri.local you wrote: Sorry for such long e-mail. Actually it's not so long... I am now working on a STB project, and our board is a IBM PPC405EP with 2 ethernet ports. U-Boot 1.0.0 and linux 2.4.20 (from MontaVista) is used and update is not recommended. Each ethernet port has a RTL8021CP PHY connected. ... as reading stops here. Both U-Boot 1.0.0 and Linux 2.4.20 are not only old, they are ancient. Zillions of smaller and bigger bugs have been fixed since. Do yourself a favour and use current code. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de The software required `Windows 95 or better', so I installed Linux. This message (including any attachments) is for the named addressee(s)'s use only. It may contain sensitive, confidential, private proprietary or legally privileged information intended for a specific individual and purpose, and is protected by law. If you are not the intended recipient, please immediately delete it and all copies of it from your system, destroy any hard copies of it and notify the sender. Any use, disclosure, copying, or distribution of this message and/or any attachments is strictly prohibited.
How to turn off MMU in MPC8540
On Aug 30, 2006, at 1:25 AM, Reddy Suneel-ASR125 wrote: Hi Can anyone know how to turn off MMU in MPC8540? You can not turn the MMU off on the MPC8540 or any e500 based product. You can emulate a 1:1 mapping if you so desire by preloading TLBs. - kumar
DS1302 driver for powerpc
On Wed, Aug 30, 2006 at 07:54:16PM +0800, Chun Chung Lo wrote: Hi all, I am now doing a STB project and the development board uses a DS1302 (trickle charge timekeeping chip) as a RTC. Our board is a IBM PPC405EP with a linux kernel 2.4.20 running on it. And the DS1302 is controlled by 2 GPIO pins instead of I2C. I would like to ask are there any porting of DS1302 support under ppc architecture? (I can only find DS1302 is supported under cris architecture.) There doesn't seem to be any DS1302 support for ppc available. However, even if there were a platform with DS1302 support you'd be in the same boat as the low-level support for cris. Support for DS1302 has a glue layer that's board-specific based on what GPIO pins are used to drive it. So if you had this driver for another PPC system like 83xx you'd still have no better starting point than the cris ds1302 driver glue since the GPIO mechanism/connection is different. Porting the board-specific glue from arch/cris/drivers/ds1302.c to 4xx GPIO is trivial to do though. -Matt
[CFT:PATCH] Removing possible wrong asm/serial.h inclusions
From: Russell King [EMAIL PROTECTED]
Subject: [CFT:PATCH] Removing possible wrong asm/serial.h inclusions
Date: Mon, 28 Aug 2006 09:52:44 +0100
diff --git a/drivers/serial/m32r_sio.c b/drivers/serial/m32r_sio.c
--- a/drivers/serial/m32r_sio.c
+++ b/drivers/serial/m32r_sio.c
@@ -76,17 +76,16 @@
*/
#define is_real_interrupt(irq) ((irq) != 0)
-#include asm/serial.h
+#define BASE_BAUD115200
/* Standard COM flags */
#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
/*
* SERIAL_PORT_DFNS tells us about built-in ports that have no
* standard enumeration mechanism. Platforms that can find all
* serial ports via mechanisms like ACPI or PCI need not supply it.
*/
-#undef SERIAL_PORT_DFNS
#if defined(CONFIG_PLAT_USRV)
#define SERIAL_PORT_DFNS \
@@ -109,7 +108,7 @@
#endif /* !CONFIG_PLAT_USRV */
static struct old_serial_port old_serial_port[] = {
- SERIAL_PORT_DFNS/* defined in asm/serial.h */
+ SERIAL_PORT_DFNS
};
#define UART_NR ARRAY_SIZE(old_serial_port)
Acked-by: Hirokazu Takata takata at linux-m32r.org
Thank you.
-- Takata
could not access the address in linux-System ace driver
. Xilinx BSP for linux 2.6 3. Kernel hangs after Now booting the kernel. cheers, -Ameet Raja Chidambaram wrote: Hi all, We are working on customized board with amcc 440SPe processor xilinx System Ace controller. The System Ace controller is connected to compact flash driver. We use u-boot 1.2 as bootloader linux kernel 2.6.16-2. On the process the u-boot is able to detect compact flash through Xilinx SystemAce controller able to load the kernel image into compact flash.But when the linux boot's up it not able to detect the System Ace controller or compact flash. Note:we need to have the root file system in compact flash. Is their any drivers available for SystemAce controller on linux 2.6,if their how to get it.please help me in this with regards raja __ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded ___ Linuxppc-embedded mailing list Linuxppc-embedded at ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/2d847dbe/attachment.htm
Some problem about code reading
Hi, I met some problems when reading sourcecode of u-boot 1.1.4 (for mpc85xx) file /cpu/mpc85xx/start.s line 276 276.#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) 277./* Special sequence needed to update CCSRBAR itself */ 278.lis r4, CFG_CCSRBAR_DEFAULT at h 279.ori r4, r4, CFG_CCSRBAR_DEFAULT at l 280. 281.lis r5, CFG_CCSRBAR at h 282.ori r5, r5, CFG_CCSRBAR at l 283.srwi r6,r5,12 284.stw r6, 0(r4) 285.isync 286. 287. lis r5, 0x 288. ori r5,r5,0xf000 289. lwz r5, 0(r5) 290. isync 291. 292.lis r3, CFG_CCSRBAR at h 293.lwz r5, CFG_CCSRBAR at l(r3) 294. isync 295.#endif I think it means if we don't use default CCSRBAR, we put the CCSRBAR addr actually used to the proper place in default CCSRBAR, so that it can jump to the addr we want to automatically.(line 276-286). But, I don't know what line 287-294 does. Can some one tell me pls? Thanks for your help. -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/37fb136c/attachment.htm
Some problem about code reading
Hi, please read the following from MPC85xx UM about the sequence on how to write CCSRBAR: * When the e500 core is writing to CCSRBAR, it should use the following sequence: - Read the current value of CCSRBAR using a load word instruction followed by an isync. This forces all accesses to configuration space to complete. - Write the new value to CCSRBAR. - Perform a load of an address that does not access configuration space or the on-chip SRAM, but has an address mapping already in effect (for example, boot ROM). Follow this load with an isync. - Read the contents of CCSRBAR from its new location, followed by another isync instruction. The codes between line 287-294 complete the third step above. Haiying From: linuxppc-embedded-bounces+haiying.wang=freescale.com at ozlabs.org [mailto:linuxppc-embedded-bounces+haiying.wang=freescale.com at ozlabs.org] On Behalf Of enorm Sent: Wednesday, August 30, 2006 9:46 AM To: linuxppc-embedded at ozlabs.org Subject: Some problem about code reading Hi, I met some problems when reading sourcecode of u-boot 1.1.4 (for mpc85xx) file /cpu/mpc85xx/start.s line 276 276.#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) 277./* Special sequence needed to update CCSRBAR itself */ 278.lis r4, CFG_CCSRBAR_DEFAULT at h 279.ori r4, r4, CFG_CCSRBAR_DEFAULT at l 280. 281.lis r5, CFG_CCSRBAR at h 282.ori r5, r5, CFG_CCSRBAR at l 283.srwi r6,r5,12 284.stw r6, 0(r4) 285.isync 286. 287. lis r5, 0x 288. ori r5,r5,0xf000 289. lwz r5, 0(r5) 290. isync 291. 292.lis r3, CFG_CCSRBAR at h 293.lwz r5, CFG_CCSRBAR at l(r3) 294. isync 295.#endif I think it means if we don't use default CCSRBAR, we put the CCSRBAR addr actually used to the proper place in default CCSRBAR, so that it can jump to the addr we want to automatically.(line 276-286). But, I don't know what line 287-294 does. Can some one tell me pls? Thanks for your help. -- next part -- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060830/9c392533/attachment.htm
Driver for OCP Driver for PPC405
Hi, I need a OCP IDE driver for IBM PPC405 redwood6 platform for 2.6 kernel. Any pointer for same or similar driver would be highly appreciated. regards, Akhilesh
Driver for OCP Driver for PPC405
On Wed, Aug 30, 2006 at 09:42:05PM +0530, akhilesh at innomedia.soft.net wrote: Hi, I need a OCP IDE driver for IBM PPC405 redwood6 platform for 2.6 kernel. Any pointer for same or similar driver would be highly appreciated. List archives are your friend. http://ozlabs.org/pipermail/linuxppc-embedded/2005-February/016715.html Read the whole thread...there's a patch that applies to linuxppc-2.5 (and the location to rsync that old tree) in a later mail. It didn't go upstream because the author didn't clean up some minor things needed for upstream inclusion. -Matt
2 Ethernet port operating in a PPC405EP system
On Wed, Aug 30, 2006 at 09:17:20PM +0800, Chun Chung Lo wrote: I know my source code is vert old. But since there are lots of applications developed base on this 2 sets of source code, if the kernel and U-Boot needs to change, the above applications (tons of codes) also need to revise ... (lots of multimedia players, drivers, and other supporting tools). My team cannot afford such great change. So I say update is not recommended ... Hopefully your product will say: buy this product is not recommended :) Don't repeat the same mistake as the MediaMVP, it uses the same processor and same kernel version, it sucks badly... -otto
DS1302 driver for powerpc
On Thu, Aug 31, 2006 at 08:51:22AM +0800, Chun Chung Lo wrote: Hi, Thanks for your help. But I also do not have this driver for 83xx. (as my linux is comes from Montavista) The 83xx reference was a hypothetical. There is no 83xx driver for the ds1302. Could you mind providing me a link / or a source of such driver for me to reference ? My advice is to port the cris DS1302 driver to your board-specific GPIO configuration. -Matt
2 Ethernet port operating in a PPC405EP system
On Wed, Aug 30, 2006 at 01:23:03PM -0500, Otto Solares wrote: Don't repeat the same mistake as the MediaMVP, it uses the same processor and same kernel version, it sucks badly... FWIW, MediaMVP doesn't use the same processor. It has an STBx25xx which is quite different from a 405EP. It is the same 405 core at least. -Matt
