[PATCH] lite5200b: flash definition in dts
Add flash definition for to lite5200b dts, and while at it
fix ranges for soc node.
Signed-off-by: Domen Puncer [EMAIL PROTECTED]
---
Hi!
Sylvain, it would be nice to have this merged.
# cat /proc/mtd
dev:size erasesize name
mtd0: 0100 0002 data0
mtd1: 00f0 0002 data1
mtd2: 0010 0002 u-boot
Some benchmarks:
read: 2.3 MB/s
erase: 168 kB/s
write: 7.3 kB/s
arch/powerpc/boot/dts/lite5200b.dts | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
Index: work-powerpc.git/arch/powerpc/boot/dts/lite5200b.dts
===
--- work-powerpc.git.orig/arch/powerpc/boot/dts/lite5200b.dts
+++ work-powerpc.git/arch/powerpc/boot/dts/lite5200b.dts
@@ -52,7 +52,8 @@
revision = ; // from bootloader
#interrupt-cells = 3;
device_type = soc;
- ranges = 0 f000 f001;
+ ranges = f000 0001
+ fe00 fe00 0200;
reg = f000 0001;
bus-frequency = 0;// from bootloader
system-frequency = 0; // from bootloader
@@ -403,5 +404,26 @@
compatible = mpc5200b-sram\0mpc5200-sram\0sram;
reg = 8000 4000;
};
+
+ [EMAIL PROTECTED] {
+ device_type = rom;
+ compatible = direct-mapped;
+ probe-type = CFI;
+ reg = fe00 0100;
+ bank-width = 1;
+ partitions = 0100;
+ partition-names = data0;
+ };
+
+ [EMAIL PROTECTED] {
+ device_type = rom;
+ compatible = direct-mapped;
+ probe-type = CFI;
+ reg = ff00 0100;
+ bank-width = 1;
+ partitions = 00f0
+ 00f0 0010;
+ partition-names = data1, u-boot;
+ };
};
};
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] [POWERPC] Typo fixes interrrupt - interrupt
Stephen Rothwell wrote: On Wed, 01 Aug 2007 05:16:27 +0200 Gabriel C [EMAIL PROTECTED] wrote: arch/powerpc/platforms/iseries/it_lp_naca.h | 87 +++-- NAK this part as it just makes a lot of the lines more than 80 characters for no real gain on a platform that is moving on ... Well some were there before but with the wrong comment style. I'll send an new patch in a bit without the comments fixes. Gabriel ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] [POWERPC] Typo fixes interrrupt - interrupt ( try 2 )
This patch fixes some interrrupt - interrupt typos
Signed-off-by: Gabriel Craciunescu [EMAIL PROTECTED]
---
arch/powerpc/platforms/embedded6xx/holly.c|2 +-
arch/powerpc/platforms/embedded6xx/linkstation.c |2 +-
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c |2 +-
arch/powerpc/platforms/iseries/it_lp_naca.h |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c
b/arch/powerpc/platforms/embedded6xx/holly.c
index 6292e36..fda16e8 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -147,7 +147,7 @@ static void __init holly_setup_arch(void)
}
/*
- * Interrupt setup and service. Interrrupts on the holly come
+ * Interrupt setup and service. Interrupts on the holly come
* from the four external INT pins, PCI interrupts are routed via
* PCI interrupt control registers, it generates internal IRQ23
*
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c
b/arch/powerpc/platforms/embedded6xx/linkstation.c
index bd5ca58..8c60e02 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -99,7 +99,7 @@ static void __init linkstation_setup_arch(void)
}
/*
- * Interrupt setup and service. Interrrupts on the linkstation come
+ * Interrupt setup and service. Interrupts on the linkstation come
* from the four PCI slots plus onboard 8241 devices: I2C, DUART.
*/
static void __init linkstation_init_IRQ(void)
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 1e3cc69..25c29bc 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -91,7 +91,7 @@ static void __init mpc7448_hpc2_setup_arch(void)
}
/*
- * Interrupt setup and service. Interrrupts on the mpc7448_hpc2 come
+ * Interrupt setup and service. Interrupts on the mpc7448_hpc2 come
* from the four external INT pins, PCI interrupts are routed via
* PCI interrupt control registers, it generates internal IRQ23
*
diff --git a/arch/powerpc/platforms/iseries/it_lp_naca.h
b/arch/powerpc/platforms/iseries/it_lp_naca.h
index 9bbf589..cf6dcf6 100644
--- a/arch/powerpc/platforms/iseries/it_lp_naca.h
+++ b/arch/powerpc/platforms/iseries/it_lp_naca.h
@@ -60,7 +60,7 @@ struct ItLpNaca {
u8 xRsvd2_0[128]; // Reserved x00-x7F
// CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators
-// NB: Padding required to keep xInterrruptHdlr at x300 which is required
+// NB: Padding required to keep xInterruptHdlr at x300 which is required
// for v4r4 PLIC.
u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F
u8 xRsvd3_0[384]; // Reserved 180-2FF
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: Embedded linux FTP Server
khollan schrieb: Hey Im looking for a basic ftp server to run on my ML410 Xilinx board, I was looking on the net and couldn't find anything that stands out. Does anyone have suggestions, or know of something that works well. Thanks kholland netkit-ftp seems to be standard. I am using vsftp because it seems to be good for production. The http://vsftpd.beasts.org http://www.proftpd.org http://www.wu-ftpd.org are propably the well known/often used ones. And there are also tftp servers (trivial ftp)... if that's what you mean with basic. Just choose one from: http://crux.nu/portdb/?q=ftpa=search Regards, -- Clemens Koller __ RD Imaging Devices Anagramm GmbH Rupert-Mayer-Straße 45/1 Linhof Werksgelände D-81379 München Tel.089-741518-50 Fax 089-741518-19 http://www.anagramm-technology.com ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
GPIO interrupts on mpc8313e
I want to receive interrupt from 1 GPIO port (for example 14) I changed the GPIMR to 0x (so I need to get interrupts from all GPIO ports) And then request the irq by : irq_create_mapping(NULL,74); request_irq(74,handler,IRQF_DISABLED,GPIO,NULL); the return value is 0 (OK) but I cant receive any interrupt. do I need to do something else? ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] lite5200b: flash definition in dts
On 8/1/07, Domen Puncer [EMAIL PROTECTED] wrote:
Add flash definition for to lite5200b dts, and while at it
fix ranges for soc node.
Signed-off-by: Domen Puncer [EMAIL PROTECTED]
---
Hi!
Sylvain, it would be nice to have this merged.
# cat /proc/mtd
dev:size erasesize name
mtd0: 0100 0002 data0
mtd1: 00f0 0002 data1
mtd2: 0010 0002 u-boot
Some benchmarks:
read: 2.3 MB/s
erase: 168 kB/s
write: 7.3 kB/s
arch/powerpc/boot/dts/lite5200b.dts | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
Index: work-powerpc.git/arch/powerpc/boot/dts/lite5200b.dts
===
--- work-powerpc.git.orig/arch/powerpc/boot/dts/lite5200b.dts
+++ work-powerpc.git/arch/powerpc/boot/dts/lite5200b.dts
@@ -52,7 +52,8 @@
revision = ; // from bootloader
#interrupt-cells = 3;
device_type = soc;
- ranges = 0 f000 f001;
+ ranges = f000 0001
+ fe00 fe00 0200;
I don't think this is the right approach. I think the SoC node is
intended for describing the on-chip devices, and the ranges property
reflects that. Shouldn't flash nodes be up 1 level?
Cheers,
g.
reg = f000 0001;
bus-frequency = 0;// from bootloader
system-frequency = 0; // from bootloader
@@ -403,5 +404,26 @@
compatible = mpc5200b-sram\0mpc5200-sram\0sram;
reg = 8000 4000;
};
+
+ [EMAIL PROTECTED] {
+ device_type = rom;
+ compatible = direct-mapped;
+ probe-type = CFI;
+ reg = fe00 0100;
+ bank-width = 1;
+ partitions = 0100;
+ partition-names = data0;
+ };
+
+ [EMAIL PROTECTED] {
+ device_type = rom;
+ compatible = direct-mapped;
+ probe-type = CFI;
+ reg = ff00 0100;
+ bank-width = 1;
+ partitions = 00f0
+ 00f0 0010;
+ partition-names = data1, u-boot;
+ };
};
};
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] Add support for Wind River SBC8641D board
On Jul 31, 2007, at 7:36 PM, Joe Hamman wrote:
Add support for Wind River's SBC8641D reference board.
Is this a single core or dual core chip?
Signed-off by: Joe Hamman [EMAIL PROTECTED]
diff -purN -X dontdiff linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts
linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts
--- linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts 1969-12-31
18:00:00.0 -0600
+++ linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts 2007-07-31
13:15:15.0 -0500
@@ -0,0 +1,160 @@
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman [EMAIL PROTECTED]
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = SBC8641D;
+ compatible = mpc86xx;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 20; // 32 bytes
+ i-cache-line-size = 20; // 32 bytes
+ d-cache-size = 8000; // L1, 32K
+ i-cache-size = 8000; // L1, 32K
+ timebase-frequency = 0; // 33 MHz, from uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ 32-bit;
+ };
if this is really an 8641D I'd expect a 2nd cpu node.
+ };
+
+ memory {
+ device_type = memory;
+ reg = 2000; // 512M at 0x0
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ #interrupt-cells = 2;
+ device_type = soc;
+ ranges = 0 f800 0010;
+ reg = f800 0010; // CCSRBAR 1M
+ bus-frequency = 0;
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = mdio;
+ compatible = gianfar;
+ reg = 24520 20;
+ phy1f: [EMAIL PROTECTED] {
+ reg = 1f;
+ device_type = ethernet-phy;
+ };
+ phy0: [EMAIL PROTECTED] {
+ reg = 0;
+ device_type = ethernet-phy;
+ };
+ phy1: [EMAIL PROTECTED] {
+ reg = 1;
+ device_type = ethernet-phy;
+ };
+ phy2: [EMAIL PROTECTED] {
+ reg = 2;
+ device_type = ethernet-phy;
+ };
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 24000 1000;
+ mac-address = [ 00 E0 0C 00 73 00 ];
+ interrupts = 1d 2 1e 2 22 2;
+ interrupt-parent = mpic;
+ phy-handle = phy1f;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 25000 1000;
+ mac-address = [ 00 E0 0C 00 73 01 ];
+ interrupts = 23 2 24 2 28 2;
+ interrupt-parent = mpic;
+ phy-handle = phy0;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 26000 1000;
+ mac-address = [ 00 E0 0C 00 02 FD ];
+ interrupts = 1F 2 20 2 21 2;
+ interrupt-parent = mpic;
+ phy-handle = phy1;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type =
RE: [PATCH] Add support for Wind River SBC8641D board
Sorry, I replied to only the first question.
-Original Message-
From: Kumar Gala [mailto:[EMAIL PROTECTED]
Sent: Wednesday, August 01, 2007 9:18 AM
To: [EMAIL PROTECTED]
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: [PATCH] Add support for Wind River SBC8641D board
On Jul 31, 2007, at 7:36 PM, Joe Hamman wrote:
Add support for Wind River's SBC8641D reference board.
Is this a single core or dual core chip?
The board I have is single core. I would have to see if I could get access
to a dual core board.
Signed-off by: Joe Hamman [EMAIL PROTECTED]
diff -purN -X dontdiff linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts
linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts
--- linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts1969-12-31
18:00:00.0 -0600
+++ linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts2007-07-31
13:15:15.0 -0500
@@ -0,0 +1,160 @@
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman [EMAIL PROTECTED]
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = SBC8641D;
+ compatible = mpc86xx;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 20; // 32 bytes
+ i-cache-line-size = 20; // 32 bytes
+ d-cache-size = 8000; // L1, 32K
+ i-cache-size = 8000; // L1, 32K
+ timebase-frequency = 0; // 33 MHz, from
uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ 32-bit;
+ };
if this is really an 8641D I'd expect a 2nd cpu node.
+ };
+
+ memory {
+ device_type = memory;
+ reg = 2000; // 512M at 0x0
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ #interrupt-cells = 2;
+ device_type = soc;
+ ranges = 0 f800 0010;
+ reg = f800 0010; // CCSRBAR 1M
+ bus-frequency = 0;
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = mdio;
+ compatible = gianfar;
+ reg = 24520 20;
+ phy1f: [EMAIL PROTECTED] {
+ reg = 1f;
+ device_type = ethernet-phy;
+ };
+ phy0: [EMAIL PROTECTED] {
+ reg = 0;
+ device_type = ethernet-phy;
+ };
+ phy1: [EMAIL PROTECTED] {
+ reg = 1;
+ device_type = ethernet-phy;
+ };
+ phy2: [EMAIL PROTECTED] {
+ reg = 2;
+ device_type = ethernet-phy;
+ };
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 24000 1000;
+ mac-address = [ 00 E0 0C 00 73 00 ];
+ interrupts = 1d 2 1e 2 22 2;
+ interrupt-parent = mpic;
+ phy-handle = phy1f;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 25000 1000;
+ mac-address = [ 00 E0 0C 00 73 01 ];
+ interrupts = 23 2 24 2 28 2;
+ interrupt-parent = mpic;
+ phy-handle = phy0;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 26000 1000;
+ mac-address = [ 00 E0 0C 00 02 FD
RE: [PATCH] Add support for Wind River SBC8641D board
The board supports both single and dual core parts. The board I have is
single core.
-Original Message-
From: Kumar Gala [mailto:[EMAIL PROTECTED]
Sent: Wednesday, August 01, 2007 9:18 AM
To: [EMAIL PROTECTED]
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: [PATCH] Add support for Wind River SBC8641D board
On Jul 31, 2007, at 7:36 PM, Joe Hamman wrote:
Add support for Wind River's SBC8641D reference board.
Is this a single core or dual core chip?
Signed-off by: Joe Hamman [EMAIL PROTECTED]
diff -purN -X dontdiff linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts
linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts
--- linux-2.6/arch/powerpc/boot/dts/sbc8641d.dts1969-12-31
18:00:00.0 -0600
+++ linux-2.6-esi/arch/powerpc/boot/dts/sbc8641d.dts2007-07-31
13:15:15.0 -0500
@@ -0,0 +1,160 @@
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman [EMAIL PROTECTED]
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = SBC8641D;
+ compatible = mpc86xx;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 20; // 32 bytes
+ i-cache-line-size = 20; // 32 bytes
+ d-cache-size = 8000; // L1, 32K
+ i-cache-size = 8000; // L1, 32K
+ timebase-frequency = 0; // 33 MHz, from
uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ 32-bit;
+ };
if this is really an 8641D I'd expect a 2nd cpu node.
+ };
+
+ memory {
+ device_type = memory;
+ reg = 2000; // 512M at 0x0
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ #interrupt-cells = 2;
+ device_type = soc;
+ ranges = 0 f800 0010;
+ reg = f800 0010; // CCSRBAR 1M
+ bus-frequency = 0;
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = mdio;
+ compatible = gianfar;
+ reg = 24520 20;
+ phy1f: [EMAIL PROTECTED] {
+ reg = 1f;
+ device_type = ethernet-phy;
+ };
+ phy0: [EMAIL PROTECTED] {
+ reg = 0;
+ device_type = ethernet-phy;
+ };
+ phy1: [EMAIL PROTECTED] {
+ reg = 1;
+ device_type = ethernet-phy;
+ };
+ phy2: [EMAIL PROTECTED] {
+ reg = 2;
+ device_type = ethernet-phy;
+ };
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 24000 1000;
+ mac-address = [ 00 E0 0C 00 73 00 ];
+ interrupts = 1d 2 1e 2 22 2;
+ interrupt-parent = mpic;
+ phy-handle = phy1f;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 25000 1000;
+ mac-address = [ 00 E0 0C 00 73 01 ];
+ interrupts = 23 2 24 2 28 2;
+ interrupt-parent = mpic;
+ phy-handle = phy0;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ device_type = network;
+ model = eTSEC;
+ compatible = gianfar;
+ reg = 26000 1000;
+ mac-address = [ 00 E0 0C 00 02 FD ];
+ interrupts = 1F 2 20 2 21 2;
+
Re: a question about mpc8xx linux
how do you know execution stop at rfi instruction.i think it seems it stop at rfi instruction when debugging through debugger, but it does n't . you check it by putting break point in the later functions e.g start_here, machine_init etc. - 5, 50, 500, 5000. Store N number of mails in your inbox. Click here.___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: GPIO interrupts on mpc8313e
Is the interrupt configured properly for whatever it is you connect to it? (level vs edge triggered, rising vs falling) Best regards, Florian On Wed, 1 Aug 2007 14:45:05 +0300 Yoni Levin [EMAIL PROTECTED] wrote: I want to receive interrupt from 1 GPIO port (for example 14) I changed the GPIMR to 0x (so I need to get interrupts from all GPIO ports) And then request the irq by : irq_create_mapping(NULL,74); request_irq(74,handler,IRQF_DISABLED,GPIO,NULL); the return value is 0 (OK) but I cant receive any interrupt. do I need to do something else? ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] Add support for Wind River SBC8641D board
On Aug 1, 2007, at 9:53 AM, Joe Hamman wrote:
Sorry, I replied to only the first question.
-Original Message-
From: Kumar Gala [mailto:[EMAIL PROTECTED]
Sent: Wednesday, August 01, 2007 9:18 AM
To: [EMAIL PROTECTED]
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: [PATCH] Add support for Wind River SBC8641D board
On Jul 31, 2007, at 7:36 PM, Joe Hamman wrote:
Add support for Wind River's SBC8641D reference board.
Is this a single core or dual core chip?
The board I have is single core. I would have to see if I could
get access
to a dual core board.
You may want to think about having both core's in the .dts and build
with !CONFIG_SMP for single and CONFIG_SMP for dual.
+void
+sbc8641d_show_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ uint memsize = total_memory;
+ const char *model = ;
+ uint svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, Vendor\t\t: Wind River Systems\n);
+
+ root = of_find_node_by_path(/);
+ if (root)
+ model = get_property(root, model, NULL);
+ seq_printf(m, Machine\t\t: %s\n, model);
+ of_node_put(root);
+
+ seq_printf(m, SVR\t\t: 0x%x\n, svid);
+ seq_printf(m, Memory\t\t: %d MB\n, memsize / (1024 * 1024));
+}
+
This is mostly redundant with the basic show cpu info, do you need
your own?
The plan is to add code to read the EEPROM device and show more info.
Ok thats fine than.
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init sbc8641d_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, mpc86xx))
+ return 1; /* Looks good */
the check you have is too generic, you probably need something more
specific in the top level compatible property.
Will do.
+
+ return 0;
+}
+
+
+void
+sbc8641d_restart(char *cmd)
+{
+ void __iomem *rstcr;
+
+ rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
+
+ local_irq_disable();
+
+ /* Assert reset request to Reset Control Register */
+ out_be32(rstcr, 0x2);
+
+ /* not reached */
+}
+
+
+long __init
+sbc8641d_time_init(void)
+{
+ unsigned int temp;
+
+ /* Set the time base to zero */
+ mtspr(SPRN_TBWL, 0);
+ mtspr(SPRN_TBWU, 0);
+
+ temp = mfspr(SPRN_HID0);
+ temp |= HID0_TBEN;
+ mtspr(SPRN_HID0, temp);
+ asm volatile(isync);
+
+ return 0;
+}
+
+
+define_machine(sbc8641d) {
+ .name = SBC8641D,
+ .probe = sbc8641d_probe,
+ .setup_arch = sbc8641d_setup_arch,
+ .init_IRQ = sbc8641d_init_irq,
+ .show_cpuinfo = sbc8641d_show_cpuinfo,
+ .get_irq= mpic_get_irq,
+ .restart= sbc8641d_restart,
+ .time_init = sbc8641d_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+
+#ifdef CONFIG_GEN_RTC
+ /* RTC interface, using functions in include/asm-generic/rtc.h */
+ .get_rtc_time = get_rtc_time,
+ .set_rtc_time = set_rtc_time,
+#endif
+};
Noticed you didn't have an PCIe support. Is that something that
exists on the board? is wired to anything?
diff -purN -X dontdiff linux-2.6/drivers/net/gianfar.h linux-2.6-
esi/drivers/net/gianfar.h
--- linux-2.6/drivers/net/gianfar.h 2007-07-31 10:15:39.0
-0500
+++ linux-2.6-esi/drivers/net/gianfar.h 2007-07-31
10:39:10.0 -0500
@@ -131,7 +131,7 @@ extern const char gfar_driver_version[];
#define DEFAULT_RXCOUNT16
#define DEFAULT_RXTIME 4
-#define TBIPA_VALUE0x1f
+#define TBIPA_VALUE0x1e
we need to turn this into a config option or something.
I was a little concerned when I saw a hard-coded address. I never
would
have found the conflict with the QUAD PHY (it starts at 0x1f and
increments
for each device) without your help.
Let me know what you think and I'll put something together.
I'll talk to someone here and see. I think a simple thing would be
to make it a Kconfig'ble option to what the value is for TBIPA_VALUE
and default to 0x1f but changeable in your defconfig.
#define MIIMCFG_INIT_VALUE 0x0007
#define MIIMCFG_RESET 0x8000
#define MIIMIND_BUSY0x0001
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: GPIO interrupts on mpc8313e
On Wed, Aug 01, 2007 at 02:45:05PM +0300, Yoni Levin wrote: request_irq(74,handler,IRQF_DISABLED,GPIO,NULL); ^ Did you try removing that flag (or calling enable_irq())? -Scott ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] lite5200b: flash definition in dts
On 01/08/07 06:41 -0600, Grant Likely wrote:
On 8/1/07, Domen Puncer [EMAIL PROTECTED] wrote:
Add flash definition for to lite5200b dts, and while at it
fix ranges for soc node.
...
+++ work-powerpc.git/arch/powerpc/boot/dts/lite5200b.dts
@@ -52,7 +52,8 @@
revision = ; // from bootloader
#interrupt-cells = 3;
device_type = soc;
- ranges = 0 f000 f001;
+ ranges = f000 0001
+ fe00 fe00 0200;
I don't think this is the right approach. I think the SoC node is
intended for describing the on-chip devices, and the ranges property
reflects that. Shouldn't flash nodes be up 1 level?
That would make sense, however, it does not work, probably because:
arch/powerpc/kernel/of_platform.c:
32 /*
33 * The list of OF IDs below is used for matching bus types in the
34 * system whose devices are to be exposed as of_platform_devices.
35 *
36 * This is the default list valid for most platforms. This file provides
37 * functions who can take an explicit list if necessary though
38 *
39 * The search is always performed recursively looking for children of
40 * the provided device_node and recursively if such a children matches
41 * a bus type in the list
42 */
43
44 static struct of_device_id of_default_bus_ids[] = {
45 { .type = soc, },
46 { .compatible = soc, },
47 { .type = spider, },
48 { .type = axon, },
49 { .type = plb5, },
50 { .type = plb4, },
51 { .type = opb, },
52 { .type = ebc, },
53 {},
54 };
Suggestions?
BTW. phy's are also not on chip, but are usualy listed under soc
(ie. mpc885ads.dts). Or rtc chip connected to i2c in kuroboxHD.dts.
Domen
___
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
