Re: Try to Disable PPC Interrupt
On Mar 28, 2007, at 11:20 PM, Zhou Rui wrote:
Hi
Sorry for my silly mistake, and I modify it like this:
#ifndef MODULE
#define MODULE
#endif
#ifndef __KERNEL__
#define __KERNEL__
#endif
#include linux/module.h
#include linux/kernel.h
#include linux/types.h
#include linux/errno.h
void hw_disable_irq (void) {
int c;
__asm__ __volatile__(
mfmsr %%r0; \
wrteei 0; \
mfmsr %0;:=r(c) : );
Why don't use use local_irq_disable() ?
printk(%x\n,c);
}
int init_module(void)
{
hw_disable_irq();
}
void cleanup_module(void)
{
}
MODULE_LICENSE(GPL);
I can get the output is 0x21030. But I also use BDI2000 here and
when I halt the board from BDI2000, I get
405EPhalt
Core number: 0
Core state : debug mode
Debug entry cause : JTAG stop request
Current PC : 0xc00042d8
Current CR : 0x22004082
Current MSR : 0x00029030
Current LR : 0xc00042d8
Hope my understanding for big endian is right. It seems 0x00029030
in MSR is
0010 1001 0011, but 0x21030 is
0010 0001 0011.
It seems the 16th bit (EE) has been set to 0, but what should I do
to make sure whether the external interrupt is disabled or not?
Thank you very much.
What exactly are you asking? If MSR[EE] = 0, interrupts are disabled.
- k
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Re: Try to Disable PPC Interrupt
On Thu, 2007-03-29 at 13:41 -0500, Kumar Gala wrote: It seems the 16th bit (EE) has been set to 0, but what should I do to make sure whether the external interrupt is disabled or not? Thank you very much. What exactly are you asking? If MSR[EE] = 0, interrupts are disabled. Since you're on a 405, you can actually test this from within your code still. Use the SRS bits in the UICs to generate a spurious interrupt at the UIC level for something that is currently enabled in the ER register. If you still get an interrupt at the CPU with MSR[EE] == 0, then you've found a very odd bug indeed. But as Kumar says, if MSR[EE] == 0, external interrupts are disabled. Of course, that doesn't mean that debug, machine check, or critical interrupts are. (How to use the SRS bits in the UICs is an exercise left up to the reader.) josh ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
