Hi Aditya,
-> Is it enough if I supply functions to gettime64, settime64 functions of
ptp_clock_info structure?-> What functions does ptp4l expect to be implemented
in the driver for above said ptp configuration(master,two step timestamp,
ethernet protocol) if I use HW timestamping? -> Can you please point me to
where exactly the HW timestamping is happening in the ptp4l code?HW
timestamping must happen in the HW level (MAC layer or PHY layer of your FPGA).
And this timestamp in general will get stored in some HW FIFO and an interrupt
would be generated to the driver. The driver should read this timestamp from
the HW, and keep it ready for ptp4l to use. To match the timestamp with certain
PTP event frames, the PTPFrameType & the seqID is also logged into FIFO with
the timestamp. In some HW, instead of using interrupts & FW FIFO, they use
in-band timestamping, where the PTPEvnetFrame's unused field could be used to
carry the ingress timestamps.
Thanks!
On Monday, 17 October, 2022 at 03:30:04 am GMT-4, Aditya Venu via
Linuxptp-users wrote:
Hi,
Can you please resolve my following queries. Below are the steps I've followed.
-> I have a FPGA card(PCIe based) on which I've implemented a network driver(on
x86, linux) so that ptp4l messages flow to and from the NIC card.-> I have
implemented software timestamping. skb_tx_timestamp() in the transmit function
and skb_defer_rx_timestamp() in the bottom half of the receive interrupt
handler. -> I'm running my system as a PTP master (two step timestamping, raw
ethernet protocol) and connected to a link partner which runs a ptp slave. With
the sw timestamping, the slave's offset from master is very high(100s of us).
But I need ns level offset.-> To achieve that level of offset accuracy, I think
I'll have to implement HW timestamping. -> But then, I have to implement a PHC
in my FPGA and add support for that PHC in my linux driver.My query is on the
driver side.
-> Is it enough if I supply functions to gettime64, settime64 functions of
ptp_clock_info structure?-> What functions does ptp4l expect to be implemented
in the driver for above said ptp configuration(master,two step timestamp,
ethernet protocol) if I use HW timestamping? -> Can you please point me to
where exactly the HW timestamping is happening in the ptp4l code?
Thanks,Aditya.
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