[Lldb-commits] Moderator needed
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Re: [Lldb-commits] [PATCH] D12083: [LLGS] Avoid misrepresenting log lines as inferior output
ovyalov accepted this revision. ovyalov added a comment. LGTM http://reviews.llvm.org/D12083 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12092: [ValueObjectSynthetic and ValueObjectDynamicValue] Override GetDeclaration
granata.enrico accepted this revision. granata.enrico added a comment. This revision is now accepted and ready to land. Assuming it passes the test suite, LGTM http://reviews.llvm.org/D12092 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] r245261 - Remove unintentional ;'s.
Author: jmolenda Date: Mon Aug 17 19:21:24 2015 New Revision: 245261 URL: http://llvm.org/viewvc/llvm-project?rev=245261view=rev Log: Remove unintentional ;'s. Modified: lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp Modified: lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp?rev=245261r1=245260r2=245261view=diff == --- lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp (original) +++ lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp Mon Aug 17 19:21:24 2015 @@ -328,9 +328,9 @@ DynamicRegisterInfo::SetRegisterInfo(con reg_info.kinds[lldb::eRegisterKindStabs] = i; uint32_t eh_frame_regno = LLDB_INVALID_REGNUM; reg_info_dict-GetValueForKeyAsInteger(gcc, eh_frame_regno, LLDB_INVALID_REGNUM); -if (eh_frame_regno == LLDB_INVALID_REGNUM); +if (eh_frame_regno == LLDB_INVALID_REGNUM) reg_info_dict-GetValueForKeyAsInteger(ehframe, eh_frame_regno, LLDB_INVALID_REGNUM); -if (eh_frame_regno == LLDB_INVALID_REGNUM); +if (eh_frame_regno == LLDB_INVALID_REGNUM) reg_info_dict-GetValueForKeyAsInteger(eh_frame, eh_frame_regno, LLDB_INVALID_REGNUM); reg_info.kinds[lldb::eRegisterKindEHFrame] = eh_frame_regno; reg_info_dict-GetValueForKeyAsInteger(dwarf, reg_info.kinds[lldb::eRegisterKindDWARF], LLDB_INVALID_REGNUM); ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D12083: [LLGS] Avoid misrepresenting log lines as inferior output
labath created this revision.
labath added reviewers: clayborg, ovyalov.
labath added subscribers: lldb-commits, dean.
in case we are logging to stdout, any log lines from the forked child can be
misconstrued to be
inferior output. To avoid this, we disable all logging immediately after
forking.
I also fix the implementatoion of DisableAllLogChannels, which was a no-op
before this commit.
http://reviews.llvm.org/D12083
Files:
source/Core/Log.cpp
source/Plugins/Process/Linux/NativeProcessLinux.cpp
Index: source/Plugins/Process/Linux/NativeProcessLinux.cpp
===
--- source/Plugins/Process/Linux/NativeProcessLinux.cpp
+++ source/Plugins/Process/Linux/NativeProcessLinux.cpp
@@ -560,8 +560,11 @@
// Child process.
if (pid == 0)
{
+// First, make sure we disable all logging. If we are logging to
stdout, our logs can be
+// mistaken for interior output.
+Log::DisableAllLogChannels(nullptr);
// FIXME consider opening a pipe between parent/child and have this
forked child
-// send log info to parent re: launch status, in place of the log
lines removed here.
+// send log info to parent re: launch status.
// Start tracing this child that is about to exec.
error = PtraceWrapper(PTRACE_TRACEME, 0);
Index: source/Core/Log.cpp
===
--- source/Core/Log.cpp
+++ source/Core/Log.cpp
@@ -449,7 +449,7 @@
{
CallbackMap callback_map = GetCallbackMap ();
CallbackMapIter pos, end = callback_map.end();
-const char *categories[1] = {NULL};
+const char *categories[] = {all, nullptr};
for (pos = callback_map.begin(); pos != end; ++pos)
pos-second.disable (categories, feedback_strm);
Index: source/Plugins/Process/Linux/NativeProcessLinux.cpp
===
--- source/Plugins/Process/Linux/NativeProcessLinux.cpp
+++ source/Plugins/Process/Linux/NativeProcessLinux.cpp
@@ -560,8 +560,11 @@
// Child process.
if (pid == 0)
{
+// First, make sure we disable all logging. If we are logging to stdout, our logs can be
+// mistaken for interior output.
+Log::DisableAllLogChannels(nullptr);
// FIXME consider opening a pipe between parent/child and have this forked child
-// send log info to parent re: launch status, in place of the log lines removed here.
+// send log info to parent re: launch status.
// Start tracing this child that is about to exec.
error = PtraceWrapper(PTRACE_TRACEME, 0);
Index: source/Core/Log.cpp
===
--- source/Core/Log.cpp
+++ source/Core/Log.cpp
@@ -449,7 +449,7 @@
{
CallbackMap callback_map = GetCallbackMap ();
CallbackMapIter pos, end = callback_map.end();
-const char *categories[1] = {NULL};
+const char *categories[] = {all, nullptr};
for (pos = callback_map.begin(); pos != end; ++pos)
pos-second.disable (categories, feedback_strm);
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[Lldb-commits] [PATCH] D12077: [MIPS] Move is 'or' instead of 'addu'.
sdardis created this revision. sdardis added a reviewer: clayborg. sdardis added a subscriber: lldb-commits. Change move encoding in PLTs and tests to be 'or' instead of 'addu'. http://reviews.llvm.org/D12077 Files: lib/ReaderWriter/ELF/Mips/MipsRelocationPass.cpp test/elf/Mips/plt-entry-mixed-1.test test/elf/Mips/plt-entry-r6-be.test test/elf/Mips/plt-entry-r6.test test/elf/Mips/plt-header-be.test test/elf/Mips/plt-header-mixed.test test/elf/Mips/plt-header.test test/elf/Mips/rel-dynamic-01.test test/elf/Mips/rel-dynamic-03.test Index: test/elf/Mips/rel-dynamic-03.test === --- test/elf/Mips/rel-dynamic-03.test +++ test/elf/Mips/rel-dynamic-03.test @@ -24,7 +24,7 @@ # PLT-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # PLT-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # PLT-NEXT: 40016c: 23 c0 1c 03 subu$24, $24, $gp -# PLT-NEXT: 400170: 21 78 e0 03 move$15, $ra +# PLT-NEXT: 400170: 25 78 e0 03 move$15, $ra # PLT-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # PLT-NEXT: 400178: 09 f8 20 03 jalr$25 # PLT-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 Index: test/elf/Mips/rel-dynamic-01.test === --- test/elf/Mips/rel-dynamic-01.test +++ test/elf/Mips/rel-dynamic-01.test @@ -23,7 +23,7 @@ # PLT-NEXT: 4001f4: 00 20 99 8f lw $25, 8192($gp) # PLT-NEXT: 4001f8: 00 20 9c 27 addiu $gp, $gp, 8192 # PLT-NEXT: 4001fc: 23 c0 1c 03 subu$24, $24, $gp -# PLT-NEXT: 400200: 21 78 e0 03 move$15, $ra +# PLT-NEXT: 400200: 25 78 e0 03 move$15, $ra # PLT-NEXT: 400204: 82 c0 18 00 srl $24, $24, 2 # PLT-NEXT: 400208: 09 f8 20 03 jalr$25 # PLT-NEXT: 40020c: fe ff 18 27 addiu $24, $24, -2 Index: test/elf/Mips/plt-header.test === --- test/elf/Mips/plt-header.test +++ test/elf/Mips/plt-header.test @@ -19,7 +19,7 @@ # EXE-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # EXE-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # EXE-NEXT: 40016c: 23 c0 1c 03 subu$24, $24, $gp -# EXE-NEXT: 400170: 21 78 e0 03 move$15, $ra +# EXE-NEXT: 400170: 25 78 e0 03 move$15, $ra # EXE-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # EXE-NEXT: 400178: 09 f8 20 03 jalr$25 # EXE-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 Index: test/elf/Mips/plt-header-mixed.test === --- test/elf/Mips/plt-header-mixed.test +++ test/elf/Mips/plt-header-mixed.test @@ -20,7 +20,7 @@ # DIS-NEXT: 400174: 00 20 99 8f lw $25, 8192($gp) # DIS-NEXT: 400178: 00 20 9c 27 addiu $gp, $gp, 8192 # DIS-NEXT: 40017c: 23 c0 1c 03 subu$24, $24, $gp -# DIS-NEXT: 400180: 21 78 e0 03 move $15, $ra +# DIS-NEXT: 400180: 25 78 e0 03 move$15, $ra # DIS-NEXT: 400184: 82 c0 18 00 srl $24, $24, 2 # DIS-NEXT: 400188: 09 f8 20 03 jalr$25 # DIS-NEXT: 40018c: fe ff 18 27 addiu $24, $24, -2 Index: test/elf/Mips/plt-header-be.test === --- test/elf/Mips/plt-header-be.test +++ test/elf/Mips/plt-header-be.test @@ -17,7 +17,7 @@ # CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp) # CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192 # CHECK-NEXT: 40016c: 03 1c c0 23 subu$24, $24, $gp -# CHECK-NEXT: 400170: 03 e0 78 21 move $15, $ra +# CHECK-NEXT: 400170: 03 e0 78 25 move$15, $ra # CHECK-NEXT: 400174: 00 18 c0 82 srl $24, $24, 2 # CHECK-NEXT: 400178: 03 20 f8 09 jalr$25 # CHECK-NEXT: 40017c: 27 18 ff fe addiu $24, $24, -2 Index: test/elf/Mips/plt-entry-r6.test === --- test/elf/Mips/plt-entry-r6.test +++ test/elf/Mips/plt-entry-r6.test @@ -17,7 +17,7 @@ # CHECK-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # CHECK-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # CHECK-NEXT: 40016c: 23 c0 1c 03 subu$24, $24, $gp -# CHECK-NEXT: 400170: 21 78 e0 03 move$15, $ra +# CHECK-NEXT: 400170: 25 78 e0 03 move$15, $ra # CHECK-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # CHECK-NEXT: 400178: 09 f8 20 03 jalr$25 # CHECK-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 Index: test/elf/Mips/plt-entry-r6-be.test === --- test/elf/Mips/plt-entry-r6-be.test +++ test/elf/Mips/plt-entry-r6-be.test @@ -17,7 +17,7 @@ # CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp) # CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192 # CHECK-NEXT: 40016c: 03 1c c0 23 subu$24, $24, $gp -# CHECK-NEXT: 400170: 03 e0 78 21 move
Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses
clayborg requested changes to this revision.
clayborg added a comment.
This revision now requires changes to proceed.
Many changes. See inlined comments.
Comment at: source/Core/Disassembler.cpp:1169-1187
@@ +1168,21 @@
+
+/*
+ * MIPS:
+ * The bit #0 of an address is used for ISA mode (1 for microMIPS, 0
for MIPS).
+ * This allows processer to switch between microMIPS and MIPS without
any need
+ * for special mode-control register. If the address specified in the
'range'
+ * is a microMIPS address then clear bit #0 and fetch opcode from the
memory.
+*/
+Address compressed_addr = range.GetBaseAddress();
+if (m_arch.GetMachine() == llvm::Triple::mips64
+|| m_arch.GetMachine() == llvm::Triple::mips64el
+|| m_arch.GetMachine() == llvm::Triple::mips
+|| m_arch.GetMachine() == llvm::Triple::mipsel)
+{
+if ((m_arch.GetFlags() | ArchSpec::eMIPSAse_micromips) ==
ArchSpec::eMIPSAse_micromips
+|| (m_arch.GetFlags() | ArchSpec::eMIPSAse_mips16) ==
ArchSpec::eMIPSAse_mips16)
+{
+compressed_addr.SetOffset (compressed_addr.GetOffset() (~1));
+}
+}
+
This kind of address snipping is going to be needed in many different places
and this should be done in:
lldb::addr_t
Target::GetOpcodeLoadAddress (lldb::addr_t load_addr, AddressClass addr_class)
const;
You will note there is already similar functionality for ARM:
```
lldb::addr_t
Target::GetOpcodeLoadAddress (lldb::addr_t load_addr, AddressClass addr_class)
const
{
addr_t opcode_addr = load_addr;
switch (m_arch.GetMachine())
{
case llvm::Triple::arm:
case llvm::Triple::thumb:
switch (addr_class)
{
case eAddressClassData:
case eAddressClassDebug:
return LLDB_INVALID_ADDRESS;
case eAddressClassInvalid:
case eAddressClassUnknown:
case eAddressClassCode:
case eAddressClassCodeAlternateISA:
case eAddressClassRuntime:
opcode_addr = ~(1ull);
break;
}
break;
default:
break;
}
return opcode_addr;
}
```
Then you would typically access this via Address::GetCallableLoadAddress
(Target *target, bool is_indirect) const.
We should probably add a new method to Address:
```
Address
Address::GetCallableAddress(Target *target, bool is_indirect) const
{
SectionSP section_sp (GetSection());
if (section_sp)
{
ModuleSP module_sp = section_sp-GetModule();
if (module_sp)
{
lldb::addr_t callable_file_addr = target-GetCallableLoadAddress
(GetFileAddress(), GetAddressClass());
Address callable_addr;
if (module_sp-ResolveFileAddress (callable_file_addr,
callable_addr))
return callable_addr;
}
}
return *this;
}
```
Then you should use this here:
```
const size_t bytes_read = target-ReadMemory
(range.GetBaseAddress().GetCallableAddress(target, false),
```
Comment at: source/Core/Disassembler.cpp:1189
@@ -1169,1 +1188,3 @@
+
+const size_t bytes_read = target-ReadMemory
(compressed_addr.GetFileAddress(),
prefer_file_cache,
This is incorrect. You can't pass a file address to target-ReadMemory(...) as
this will do the wrong thing if you are running. The story goes like this:
lldb_private::Address is a section offset based address that says an address is
.text + 0x1000. When target-ReadMemory() tries to read memory from this
address, it can see if prefer_file_cache is set and if so, it will grab the
section from the the address that is passed as the first parameter and then be
able to get the module from that section and read data from the cached .text
section contents from the object file in the module.
If you call Target::ReadMemory() with compressed_addr.GetFileAddress(), it
will get the file address (the unslid address) of 0x1000 and convert that to a
Address object.
So just pass your fixed up address, in this case it will be compressed_addr.
Comment at: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp:2098-2112
@@ -2093,1 +2097,17 @@
+/*
+ * MIPS:
+ * The bit #0 of an address is used for ISA mode (1 for microMIPS, 0
for MIPS).
+ * This allows processer to switch between microMIPS and MIPS without
any need
+ * for special mode-control register. However, apart from .debug_line,
none of
+ * the ELF/DWARF sections set the ISA bit (for symbol or section). Use
st_other
+ * flag to check whether the symbol is microMIPS and then set the ISA
bit
+ * accordingly.
+*/
+if (IS_MICROMIPS(symbol.st_other)
+(arch.GetMachine() == llvm::Triple::mips64
+
Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses
clayborg added a comment. The main thing is, we don't want to be like other debuggers that have all this code in many many places that check address bits by checking the Architecture and litter the code with bit strips and adding bits where needed. We want to support addresses correctly by knowing that a Address has a special address class. So we use: addr_t Address::GetCallableLoadAddress (Target *target, bool is_indirect) const and lldb::addr_t Target::GetOpcodeLoadAddress (lldb::addr_t load_addr, AddressClass addr_class) const Target also has a counterpart that does the actual check since the target has the ArchSpec that tells us the architecture. Also if you ever need make a special address that needs to have bit zero set, there is: lldb::addr_t Target::GetCallableLoadAddress (lldb::addr_t load_addr, AddressClass addr_class) const Repository: rL LLVM http://reviews.llvm.org/D12079 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12083: [LLGS] Avoid misrepresenting log lines as inferior output
clayborg accepted this revision. clayborg added a comment. This revision is now accepted and ready to land. Looks good. http://reviews.llvm.org/D12083 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12044: Fix resolution conflict between global and class static variables in C++.
clayborg added a comment.
Please make sure that the following works after your changes:
(lldb) r
Process 35421 launched: '/private/tmp/a.out' (x86_64)
Process 35421 stopped
* thread #1: tid = 0xb659be, 0x00010f9d a.out main + 13, stop reason
= breakpoint 1.1, queue = com.apple.main-thread
frame #0: 0x00010f9d a.out main + 13 at main.cpp:24
21
22 int main()
23 {
- 24 return 0; // break here
25 }
(lldb) target variable
Global variables for /tmp/main.cpp in /private/tmp/a.out:
(int) A::a =
(int) B::a =
(int) C::a =
(int) ::a =
http://reviews.llvm.org/D12044
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Re: [Lldb-commits] [lldb] r245217 - [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
Merged to 3.7 in r245240. There was a conflicts because r245141 isn't on the branch. Please check that I got it right: http://llvm.org/viewvc/llvm-project?rev=245240view=rev Thanks, Hans On Mon, Aug 17, 2015 at 1:28 PM, Greg Clayton clayb...@gmail.com wrote: Ok to merge. On Aug 17, 2015, at 1:26 PM, Hans Wennborg h...@chromium.org wrote: I'm OK with it if Greg approves. - Hans On Mon, Aug 17, 2015 at 7:07 AM, sagar.tha...@imgtec.com wrote: Hi Hans, Could you please also merge r245217 in the release branch. Thanks, Sagar -Original Message- From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of Sagar Thakur via lldb-commits Sent: 17 August 2015 19:10 To: lldb-commits@lists.llvm.org Subject: [Lldb-commits] [lldb] r245217 - [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support Author: slthakur Date: Mon Aug 17 08:40:17 2015 New Revision: 245217 URL: http://llvm.org/viewvc/llvm-project?rev=245217view=rev Log: [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D12077: [MIPS] Move is 'or' instead of 'addu'.
clayborg resigned from this revision. clayborg removed a reviewer: clayborg. clayborg added a comment. I don't think I am the right person to review this as this is in LLVM. http://reviews.llvm.org/D12077 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r245217 - [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
I'm OK with it if Greg approves. - Hans On Mon, Aug 17, 2015 at 7:07 AM, sagar.tha...@imgtec.com wrote: Hi Hans, Could you please also merge r245217 in the release branch. Thanks, Sagar -Original Message- From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of Sagar Thakur via lldb-commits Sent: 17 August 2015 19:10 To: lldb-commits@lists.llvm.org Subject: [Lldb-commits] [lldb] r245217 - [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support Author: slthakur Date: Mon Aug 17 08:40:17 2015 New Revision: 245217 URL: http://llvm.org/viewvc/llvm-project?rev=245217view=rev Log: [LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r245216 - [LLDB] Use llvm::APInt and llvm::APFloat in Scalar and RegisterValue
+lldb-commits On Mon, Aug 17, 2015 at 1:25 PM, Hans Wennborg h...@chromium.org wrote: I'm OK with it if Greg approves. - Hans On Mon, Aug 17, 2015 at 7:06 AM, sagar.tha...@imgtec.com wrote: Hi Hans, Could you please merge r245216 in the release branch? Thanks, Sagar -Original Message- From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of Sagar Thakur via lldb-commits Sent: 17 August 2015 17:36 To: lldb-commits@lists.llvm.org Subject: [Lldb-commits] [lldb] r245216 - [LLDB] Use llvm::APInt and llvm::APFloat in Scalar and RegisterValue Author: slthakur Date: Mon Aug 17 07:05:31 2015 New Revision: 245216 URL: http://llvm.org/viewvc/llvm-project?rev=245216view=rev Log: [LLDB] Use llvm::APInt and llvm::APFloat in Scalar and RegisterValue ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
