[Lldb-commits] [lldb] r265931 - Remove unintentional return
Author: bhushan.attarde
Date: Mon Apr 11 06:19:37 2016
New Revision: 265931
URL: http://llvm.org/viewvc/llvm-project?rev=265931=rev
Log:
Remove unintentional return
Modified:
lldb/trunk/source/Core/ArchSpec.cpp
Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=265931=265930=265931=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Mon Apr 11 06:19:37 2016
@@ -1344,7 +1344,6 @@ cores_match (const ArchSpec::Core core1,
{
if (core2 == ArchSpec::eCore_mips32el || core2 ==
ArchSpec::eCore_mips32r6el)
return true;
-return true;
}
break;
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[Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
Author: bhushan.attarde
Date: Thu Feb 18 05:53:28 2016
New Revision: 261206
URL: http://llvm.org/viewvc/llvm-project?rev=261206=rev
Log:
[LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for
MIPS
SUMMARY:
This patch implements ArchSpec::GetClangTargetCPU() that provides string
representing current architecture as a target CPU.
This string is then passed to tools like clang so that they generate
correct code for that target.
Reviewers: clayborg, zturner
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D17022
Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Core/ArchSpec.cpp
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=261206=261205=261206=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Thu Feb 18 05:53:28 2016
@@ -288,6 +288,16 @@ public:
GetArchitectureName () const;
//--
+/// Returns a string representing current architecture as a target CPU
+/// for tools like compiler, disassembler etc.
+///
+/// @return A string representing target CPU for the current
+/// architecture.
+//--
+std::string
+GetClangTargetCPU ();
+
+//--
/// Clears the object state.
///
/// Clears the object state back to a default invalid state.
Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=261206=261205=261206=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Thu Feb 18 05:53:28 2016
@@ -511,6 +511,56 @@ ArchSpec::GetArchitectureName () const
return "unknown";
}
+std::string
+ArchSpec::GetClangTargetCPU ()
+{
+std::string cpu;
+const llvm::Triple::ArchType machine = GetMachine();
+
+if (machine == llvm::Triple::mips ||
+machine == llvm::Triple::mipsel ||
+machine == llvm::Triple::mips64 ||
+machine == llvm::Triple::mips64el)
+{
+switch (m_core)
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+break;
+}
+}
+return cpu;
+}
+
uint32_t
ArchSpec::GetMachOCPUType () const
{
Modified:
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp?rev=261206=261205=261206=diff
==
--- lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
(original)
+++ lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Thu Feb 18 05:53:28 2016
@@ -179,6 +179,12 @@ ClangExpressionParser::ClangExpressionPa
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec target_arch;
+if (target_sp)
+target_arch = target_sp->GetArchitecture();
+
+const auto target_machine = target_arch.GetMachine();
+
// If the expression is being evaluated in the context of an existing
// stack frame, we introspect to see if the language runtime is available.
auto frame = exe_scope->CalculateStackFrame();
@@ -197,9 +203,9 @@
[Lldb-commits] [lldb] r258919 - [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
Author: bhushan.attarde
Date: Wed Jan 27 04:16:30 2016
New Revision: 258919
URL: http://llvm.org/viewvc/llvm-project?rev=258919=rev
Log:
[LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
SUMMARY:
Get the load address for the address given by symbol and function.
Earlier, this was done for function only, this patch does it for symbol too.
This patch also adds TestAvoidBreakpointInDelaySlot.py to test this change.
Reviewers: clayborg
Subscribers: labath, zturner, mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D16049
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
Modified:
lldb/trunk/include/lldb/API/SBInstruction.h
lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py
lldb/trunk/scripts/interface/SBInstruction.i
lldb/trunk/source/API/SBInstruction.cpp
lldb/trunk/source/Target/Target.cpp
Modified: lldb/trunk/include/lldb/API/SBInstruction.h
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/API/SBInstruction.h?rev=258919=258918=258919=diff
==
--- lldb/trunk/include/lldb/API/SBInstruction.h (original)
+++ lldb/trunk/include/lldb/API/SBInstruction.h Wed Jan 27 04:16:30 2016
@@ -60,6 +60,9 @@ public:
bool
DoesBranch ();
+bool
+HasDelaySlot ();
+
void
Print (FILE *out);
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile?rev=258919=auto
==
---
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
(added)
+++
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
Wed Jan 27 04:16:30 2016
@@ -0,0 +1,6 @@
+LEVEL = ../../../make
+
+C_SOURCES := main.c
+
+include $(LEVEL)/Makefile.rules
+
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py?rev=258919=auto
==
---
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
(added)
+++
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
Wed Jan 27 04:16:30 2016
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil
+from lldbsuite.test.lldbtest import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessArch(archs=re.compile('mips*'))
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None,
self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+sc = list.GetContextAtIndex(0)
+self.assertTrue(sc.GetSymbol().GetName() == "foo")
+function = sc.GetFunction()
+self.assertTrue(function)
+self.function(function, target)
+
+def function (self, function, target):
+"""Iterate over instructions in function and place a breakpoint on
delay slot instruction"""
+# Get the list of all instructions in the function
+insts = function.GetInstructions(target)
+print insts
+i = 0
+for inst in
[Lldb-commits] [lldb] r258485 - Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
Author: bhushan.attarde
Date: Thu Jan 21 23:02:02 2016
New Revision: 258485
URL: http://llvm.org/viewvc/llvm-project?rev=258485=rev
Log:
Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB
during expression evaluation
SUMMARY:
The symbol "$" has a special meaning for MIPS i.e it is marker for
temporary symbols for MIPS.
So this patch uses additional _ prefix for "$__lldb_valid_pointer_check" so
that it wont be marked as temporary symbol in case of MIPS.
Reviewers: clayborg, spyffe
Subscribers: dean, emaste, mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential http://reviews.llvm.org/D14111
Modified:
lldb/trunk/source/Expression/IRDynamicChecks.cpp
Modified: lldb/trunk/source/Expression/IRDynamicChecks.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Expression/IRDynamicChecks.cpp?rev=258485=258484=258485=diff
==
--- lldb/trunk/source/Expression/IRDynamicChecks.cpp (original)
+++ lldb/trunk/source/Expression/IRDynamicChecks.cpp Thu Jan 21 23:02:02 2016
@@ -35,12 +35,12 @@ using namespace lldb_private;
static char ID;
-#define VALID_POINTER_CHECK_NAME "$__lldb_valid_pointer_check"
+#define VALID_POINTER_CHECK_NAME "_$__lldb_valid_pointer_check"
#define VALID_OBJC_OBJECT_CHECK_NAME "$__lldb_objc_object_check"
static const char g_valid_pointer_check_text[] =
"extern \"C\" void\n"
-"$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
+"_$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
"{\n"
"unsigned char $__lldb_local_val = *$__lldb_arg_ptr;\n"
"}";
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[Lldb-commits] [lldb] r257442 - [LLDB][MIPS] Merge emulation of similar instructions for MIPS64
Author: bhushan.attarde
Date: Mon Jan 11 21:56:58 2016
New Revision: 257442
URL: http://llvm.org/viewvc/llvm-project?rev=257442=rev
Log:
[LLDB][MIPS] Merge emulation of similar instructions for MIPS64
SUMMARY:
This patch merges emulation of similar instructions into a single function
(wherever possible) to remove code duplication.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D16051
Modified:
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Modified:
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=257442=257441=257442=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
Mon Jan 11 21:56:58 2016
@@ -549,45 +549,45 @@ EmulateInstructionMIPS64::GetOpcodeForIn
//--
// Branch instructions
//--
-{ "BEQ",::Emulate_BEQ, "BEQ
rs,rt,offset" },
-{ "BNE",::Emulate_BNE, "BNE
rs,rt,offset" },
-{ "BEQL", ::Emulate_BEQL,"BEQL
rs,rt,offset" },
-{ "BNEL", ::Emulate_BNEL,"BNEL
rs,rt,offset" },
-{ "BGEZALL",::Emulate_BGEZALL,
"BGEZALL rt,offset" },
+{ "BEQ",::Emulate_BXX_3ops,"BEQ
rs,rt,offset" },
+{ "BNE",::Emulate_BXX_3ops,"BNE
rs,rt,offset" },
+{ "BEQL", ::Emulate_BXX_3ops,"BEQL
rs,rt,offset" },
+{ "BNEL", ::Emulate_BXX_3ops,"BNEL
rs,rt,offset" },
+{ "BGEZALL",::Emulate_Bcond_Link,
"BGEZALL rt,offset" },
{ "BAL",::Emulate_BAL, "BAL
offset"},
-{ "BGEZAL", ::Emulate_BGEZAL,
"BGEZAL rs,offset" },
+{ "BGEZAL", ::Emulate_Bcond_Link,
"BGEZAL rs,offset" },
{ "BALC", ::Emulate_BALC,"BALC
offset" },
{ "BC", ::Emulate_BC, "BC
offset" },
-{ "BGEZ", ::Emulate_BGEZ,"BGEZ
rs,offset"},
-{ "BLEZALC",::Emulate_BLEZALC,
"BLEZALC rs,offset" },
-{ "BGEZALC",::Emulate_BGEZALC,
"BGEZALC rs,offset" },
-{ "BLTZALC",::Emulate_BLTZALC,
"BLTZALC rs,offset" },
-{ "BGTZALC",::Emulate_BGTZALC,
"BGTZALC rs,offset" },
-{ "BEQZALC",::Emulate_BEQZALC,
"BEQZALC rs,offset" },
-{ "BNEZALC",::Emulate_BNEZALC,
"BNEZALC rs,offset" },
-{ "BEQC", ::Emulate_BEQC,"BEQC
rs,rt,offset" },
-{ "BNEC", ::Emulate_BNEC,"BNEC
rs,rt,offset" },
-{ "BLTC", ::Emulate_BLTC,"BLTC
rs,rt,offset" },
-{ "BGEC", ::Emulate_BGEC,"BGEC
rs,rt,offset" },
-{ "BLTUC", ::Emulate_BLTUC, "BLTUC
rs,rt,offset"},
-{ "BGEUC", ::Emulate_BGEUC, "BGEUC
rs,rt,offset"},
-{ "BLTZC", ::Emulate_BLTZC, "BLTZC
rt,offset" },
-{ "BLEZC", ::Emulate_BLEZC, "BLEZC
rt,offset" },
-{ "BGEZC", ::Emulate_BGEZC, "BGEZC
rt,offset" },
-{ "BGTZC", ::Emulate_BGTZC, "BGTZC
rt,offset" },
-{ "BEQZC", ::Emulate_BEQZC, "BEQZC
rt,offset" },
-{ "BNEZC", ::Emulate_BNEZC, "BNEZC
rt,offset" },
-{ "BGEZL", ::Emulate_BGEZL, "BGEZL
rt,offset" },
-{ "BGTZ", ::Emulate_BGTZ,"BGTZ
rt,offset"},
-{ "BGTZL", ::Emulate_BGTZL, "BGTZL
rt,offset" },
-{ "BLEZ", ::Emulate_BLEZ,"BLEZ
rt,offset"},
-{ "BLEZL", ::Emulate_BLEZL, "BLEZL
rt,offset" },
-{ "BLTZ", ::Emulate_BLTZ,"BLTZ
rt,offset"},
-{ "BLTZAL", ::Emulate_BLTZAL,
"BLTZAL rt,offset" },
-{ "BLTZALL",::Emulate_BLTZALL,
"BLTZALL rt,offset" },
-{ "BLTZL", ::Emulate_BLTZL, "BLTZL
rt,offset" },
-{ "BOVC", ::Emulate_BOVC,"BOVC
rs,rt,offset" },
-{ "BNVC", ::Emulate_BNVC,
[Lldb-commits] [lldb] r257441 - [LLDB][MIPS] Handle PIC calling convention for MIPS64
Author: bhushan.attarde
Date: Mon Jan 11 21:48:43 2016
New Revision: 257441
URL: http://llvm.org/viewvc/llvm-project?rev=257441=rev
Log:
[LLDB][MIPS] Handle PIC calling convention for MIPS64
SUMMARY:
This patch sets up register r25 with the address of function to be called
in PrepareTrivialCall().
This is required as per MIPS PIC calling convention.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D16046
Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp?rev=257441=257440=257441=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp Mon Jan 11
21:48:43 2016
@@ -206,6 +206,7 @@ ABISysV_mips64::PrepareTrivialCall (Thre
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -228,6 +229,13 @@ ABISysV_mips64::PrepareTrivialCall (Thre
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of
the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
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[Lldb-commits] [lldb] r256929 - Fix build warnings after rL256915
Author: bhushan.attarde
Date: Wed Jan 6 06:08:22 2016
New Revision: 256929
URL: http://llvm.org/viewvc/llvm-project?rev=256929=rev
Log:
Fix build warnings after rL256915
Modified:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=256929=256928=256929=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Wed
Jan 6 06:08:22 2016
@@ -1404,7 +1404,7 @@ EmulateInstructionMIPS::Emulate_BXX_3ops
{
bool success = false;
uint32_t rs, rt;
-int32_t offset, pc, target, rs_val, rt_val;
+int32_t offset, pc, target = 0, rs_val, rt_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
@@ -1459,7 +1459,7 @@ EmulateInstructionMIPS::Emulate_BXX_3ops
{
bool success = false;
uint32_t rs, rt;
-int32_t offset, pc, target, rs_val, rt_val;
+int32_t offset, pc, target = 0, rs_val, rt_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
@@ -1555,7 +1555,7 @@ EmulateInstructionMIPS::Emulate_Bcond_Li
{
bool success = false;
uint32_t rs;
-int32_t offset, pc, target;
+int32_t offset, pc, target = 0;
int32_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
@@ -1634,7 +1634,7 @@ EmulateInstructionMIPS::Emulate_Bcond_Li
{
bool success = false;
uint32_t rs;
-int32_t offset, pc, target;
+int32_t offset, pc, target = 0;
int32_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
@@ -1687,7 +1687,7 @@ EmulateInstructionMIPS::Emulate_BXX_2ops
{
bool success = false;
uint32_t rs;
-int32_t offset, pc, target;
+int32_t offset, pc, target = 0;
int32_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
@@ -1754,7 +1754,7 @@ EmulateInstructionMIPS::Emulate_BXX_2ops
{
bool success = false;
uint32_t rs;
-int32_t offset, pc, target;
+int32_t offset, pc, target = 0;
int32_t rs_val;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
@@ -2363,7 +2363,7 @@ EmulateInstructionMIPS::Emulate_FP_branc
{
bool success = false;
uint32_t cc, fcsr;
-int32_t target, pc, offset;
+int32_t pc, offset, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
@@ -2492,7 +2492,7 @@ EmulateInstructionMIPS::Emulate_3D_branc
{
bool success = false;
uint32_t cc, fcsr;
-int32_t target, pc, offset;
+int32_t pc, offset, target = 0;
const char *op_name = m_insn_info->getName (insn.getOpcode ());
cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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[Lldb-commits] [lldb] r256915 - [LLDB][MIPS32]Merge emulation of similar instructions
Author: bhushan.attarde
Date: Tue Jan 5 23:44:02 2016
New Revision: 256915
URL: http://llvm.org/viewvc/llvm-project?rev=256915=rev
Log:
[LLDB][MIPS32]Merge emulation of similar instructions
SUMMARY:
This patch merges emulation of similar instructions into a single function
(wherever possible) to remove code duplication.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D15886
Modified:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=256915=256914=256915=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Tue
Jan 5 23:44:02 2016
@@ -591,45 +591,45 @@ EmulateInstructionMIPS::GetOpcodeForInst
//--
// Branch instructions
//--
-{ "BEQ",::Emulate_BEQ, "BEQ
rs,rt,offset" },
-{ "BNE",::Emulate_BNE, "BNE
rs,rt,offset" },
-{ "BEQL", ::Emulate_BEQL,"BEQL
rs,rt,offset" },
-{ "BNEL", ::Emulate_BNEL,"BNEL
rs,rt,offset" },
-{ "BGEZALL",::Emulate_BGEZALL, "BGEZALL
rt,offset" },
+{ "BEQ",::Emulate_BXX_3ops,"BEQ
rs,rt,offset" },
+{ "BNE",::Emulate_BXX_3ops,"BNE
rs,rt,offset" },
+{ "BEQL", ::Emulate_BXX_3ops,"BEQL
rs,rt,offset" },
+{ "BNEL", ::Emulate_BXX_3ops,"BNEL
rs,rt,offset" },
+{ "BGEZALL",::Emulate_Bcond_Link, "BGEZALL
rt,offset" },
{ "BAL",::Emulate_BAL, "BAL
offset"},
-{ "BGEZAL", ::Emulate_BGEZAL, "BGEZAL
rs,offset" },
+{ "BGEZAL", ::Emulate_Bcond_Link, "BGEZAL
rs,offset" },
{ "BALC", ::Emulate_BALC,"BALC
offset" },
{ "BC", ::Emulate_BC, "BC
offset" },
-{ "BGEZ", ::Emulate_BGEZ,"BGEZ
rs,offset"},
-{ "BLEZALC",::Emulate_BLEZALC, "BLEZALC
rs,offset" },
-{ "BGEZALC",::Emulate_BGEZALC, "BGEZALC
rs,offset" },
-{ "BLTZALC",::Emulate_BLTZALC, "BLTZALC
rs,offset" },
-{ "BGTZALC",::Emulate_BGTZALC, "BGTZALC
rs,offset" },
-{ "BEQZALC",::Emulate_BEQZALC, "BEQZALC
rs,offset" },
-{ "BNEZALC",::Emulate_BNEZALC, "BNEZALC
rs,offset" },
-{ "BEQC", ::Emulate_BEQC,"BEQC
rs,rt,offset" },
-{ "BNEC", ::Emulate_BNEC,"BNEC
rs,rt,offset" },
-{ "BLTC", ::Emulate_BLTC,"BLTC
rs,rt,offset" },
-{ "BGEC", ::Emulate_BGEC,"BGEC
rs,rt,offset" },
-{ "BLTUC", ::Emulate_BLTUC, "BLTUC
rs,rt,offset"},
-{ "BGEUC", ::Emulate_BGEUC, "BGEUC
rs,rt,offset"},
-{ "BLTZC", ::Emulate_BLTZC, "BLTZC
rt,offset" },
-{ "BLEZC", ::Emulate_BLEZC, "BLEZC
rt,offset" },
-{ "BGEZC", ::Emulate_BGEZC, "BGEZC
rt,offset" },
-{ "BGTZC", ::Emulate_BGTZC, "BGTZC
rt,offset" },
-{ "BEQZC", ::Emulate_BEQZC, "BEQZC
rt,offset" },
-{ "BNEZC", ::Emulate_BNEZC, "BNEZC
rt,offset" },
-{ "BGEZL", ::Emulate_BGEZL, "BGEZL
rt,offset" },
-{ "BGTZ", ::Emulate_BGTZ,"BGTZ
rt,offset"},
-{ "BGTZL", ::Emulate_BGTZL, "BGTZL
rt,offset" },
-{ "BLEZ", ::Emulate_BLEZ,"BLEZ
rt,offset"},
-{ "BLEZL", ::Emulate_BLEZL, "BLEZL
rt,offset" },
-{ "BLTZ", ::Emulate_BLTZ,"BLTZ
rt,offset"},
-{ "BLTZAL", ::Emulate_BLTZAL, "BLTZAL
rt,offset" },
-{ "BLTZALL",::Emulate_BLTZALL, "BLTZALL
rt,offset" },
-{ "BLTZL", ::Emulate_BLTZL, "BLTZL
rt,offset" },
-{ "BOVC", ::Emulate_BOVC,"BOVC
rs,rt,offset" },
-{ "BNVC", ::Emulate_BNVC,"BNVC
rs,rt,offset" },
+
[Lldb-commits] [lldb] r255005 - [LLDB][MIPS] Handle PIC calling convention for MIPS32
Author: bhushan.attarde
Date: Tue Dec 8 00:05:57 2015
New Revision: 255005
URL: http://llvm.org/viewvc/llvm-project?rev=255005=rev
Log:
[LLDB][MIPS] Handle PIC calling convention for MIPS32
SUMMARY:
- PrepareTrivialCall() to setup register r25 with the address of function
to be called.
- RegisterIsCalleeSaved() to use name of a register instead of its
byte_offset.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D15273
Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp?rev=255005=255004=255005=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp Tue Dec 8
00:05:57 2015
@@ -241,6 +241,7 @@ ABISysV_mips::PrepareTrivialCall (Thread
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -262,7 +263,14 @@ ABISysV_mips::PrepareTrivialCall (Thread
// Set pc to the address of the called function.
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
-
+
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of
the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
@@ -546,13 +554,36 @@ ABISysV_mips::RegisterIsCalleeSaved (con
{
// Preserved registers are :
// r16-r23, r28, r29, r30, r31
+const char *name = reg_info->name;
-int reg = ((reg_info->byte_offset) / 4);
-
-bool save = (reg >= 16) && (reg <= 23);
- save |= (reg >= 28) && (reg <= 31);
+if (name[0] == 'r')
+{
+switch (name[1])
+{
+case '1':
+if (name[2] == '6' || name[2] == '7' || name[2] == '8' ||
name[2] == '9') // r16-r19
+return name[3] == '\0';
+break;
+case '2':
+if (name[2] == '0' || name[2] == '1' || name[2] == '2' ||
name[2] == '3' // r20-r23
+|| name[2] == '8' || name[2] == '9')
// r28 and r29
+return name[3] == '\0';
+break;
+case '3':
+if (name[2] == '0' || name[2] == '1') // r30 and r31
+return name[3] == '\0';
+break;
+}
-return save;
+if (name[0] == 'g' && name[1] == 'p' && name[2] == '\0') // gp
(r28)
+return true;
+if (name[0] == 's' && name[1] == 'p' && name[2] == '\0') // sp
(r29)
+return true;
+if (name[0] == 'f' && name[1] == 'p' && name[2] == '\0') // fp
(r30)
+return true;
+if (name[0] == 'r' && name[1] == 'a' && name[2] == '\0') // ra
(r31)
+return true;
+}
}
return false;
}
___
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[Lldb-commits] [lldb] r249381 - [MIPS] Emulate microMIPS instructions
Author: bhushan.attarde
Date: Tue Oct 6 03:52:08 2015
New Revision: 249381
URL: http://llvm.org/viewvc/llvm-project?rev=249381=rev
Log:
[MIPS] Emulate microMIPS instructions
SUMMARY:
This patch includes:
1. Emulation of prologue/epilogue and branch instructions for microMIPS.
2. Setting up alternate disassembler (to be used for microMIPS).
So there will be two disassembler instances, one for microMIPS and other
for MIPS.
Appropriate disassembler will be used based on the address class of
instruction address.
3. Some of the branch instructions does not have fixed sized delay slot,
that means delay slot instruction can be of 2-byte or 4-byte.
For this "m_next_inst_size" has been introduced which stores the size of
next instruction (i.e size of delay slot instruction in case of branch).
This can be used wherever the size of next instruction is required.
4. A minor change to use mips32 register names instead of mips64 names.
Reviewers: clayborg, tberghammer
Subscribers: mohit.bhakkad, sagar, jaydeep, nitesh.jain, lldb-commits
Differential Revision: http://reviews.llvm.org/D13282
Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h?rev=249381=249380=249381=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h Tue Oct 6 03:52:08
2015
@@ -74,13 +74,11 @@ public:
}
virtual bool
-CodeAddressIsValid (lldb::addr_t pc)//must- check
+CodeAddressIsValid (lldb::addr_t pc)
{
- if (pc & (4ull - 1ull))
- return false; // Not 4 byte aligned
-
-// Anything else if fair game..
-return true;
+// Just make sure the address is a valid 32 bit address. Bit zero
+// might be set due to MicroMIPS function calls, so don't enforce
alignment.
+return (pc <= UINT32_MAX);
}
virtual const lldb_private::RegisterInfo *
Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=249381=249380=249381=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Tue
Oct 6 03:52:08 2015
@@ -29,6 +29,7 @@
#include "lldb/Core/DataExtractor.h"
#include "lldb/Core/Stream.h"
#include "lldb/Symbol/UnwindPlan.h"
+#include "lldb/Target/Target.h"
#include "llvm/ADT/STLExtras.h"
@@ -132,10 +133,6 @@ EmulateInstructionMIPS::EmulateInstructi
features += "+dsp,";
if (arch_flags & ArchSpec::eMIPSAse_dspr2)
features += "+dspr2,";
-if (arch_flags & ArchSpec::eMIPSAse_mips16)
-features += "+mips16,";
-if (arch_flags & ArchSpec::eMIPSAse_micromips)
-features += "+micromips,";
m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
assert (m_reg_info.get());
@@ -152,6 +149,21 @@ EmulateInstructionMIPS::EmulateInstructi
m_disasm.reset (target->createMCDisassembler (*m_subtype_info,
*m_context));
assert (m_disasm.get());
+
+/* Create alternate disassembler for microMIPS */
+if (arch_flags & ArchSpec::eMIPSAse_mips16)
+features += "+mips16,";
+else if (arch_flags & ArchSpec::eMIPSAse_micromips)
+features += "+micromips,";
+
+m_alt_subtype_info.reset (target->createMCSubtargetInfo
(triple.getTriple(), cpu, features));
+assert (m_alt_subtype_info.get());
+
+m_alt_disasm.reset (target->createMCDisassembler (*m_alt_subtype_info,
*m_context));
+assert (m_alt_disasm.get());
+
+m_next_inst_size = 0;
+m_use_alt_disaasm = false;
}
void
@@ -485,8 +497,22 @@ EmulateInstructionMIPS::GetOpcodeForInst
{ "ADDiu", ::Emulate_ADDiu, "ADDIU
rt,rs,immediate"},
{ "SW", ::Emulate_SW, "SW
rt,offset(rs)" },
{ "LW", ::Emulate_LW, "LW
rt,offset(base)" },
-
//--
+// MicroMIPS Prologue/Epilogue instructions
+
//--
+{ "ADDIUSP_MM", ::Emulate_ADDIUSP, "ADDIU
immediate"},
+{ "ADDIUS5_MM", ::Emulate_ADDIUS5, "ADDIUS5
rd,immediate" },
+{ "SWSP_MM",::Emulate_SWSP,
[Lldb-commits] [lldb] r247666 - [LLDB][MIPS] Add support for DT_MIPS_RLD_MAP_REL
Author: bhushan.attarde
Date: Tue Sep 15 00:45:29 2015
New Revision: 247666
URL: http://llvm.org/viewvc/llvm-project?rev=247666=rev
Log:
[LLDB][MIPS] Add support for DT_MIPS_RLD_MAP_REL
SUMMARY:
This patch provides support for MIPS specific DT_MIPS_RLD_MAP_REL tag in
LLDB.
This tag allows debugging of MIPS position independent executables and
provides access to shared library information.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D12794
Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=247666=247665=247666=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Tue Sep 15
00:45:29 2015
@@ -1097,16 +1097,35 @@ ObjectFileELF::GetImageInfoAddress(Targe
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
return Address(dynsym_section_sp, offset);
}
-else if (symbol.d_tag == DT_MIPS_RLD_MAP && target)
+// MIPS executables uses DT_MIPS_RLD_MAP_REL to support PIE.
DT_MIPS_RLD_MAP exists in non-PIE.
+else if ((symbol.d_tag == DT_MIPS_RLD_MAP || symbol.d_tag ==
DT_MIPS_RLD_MAP_REL) && target)
{
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
addr_t dyn_base = dynsym_section_sp->GetLoadBaseAddress(target);
if (dyn_base == LLDB_INVALID_ADDRESS)
return Address();
-Address addr;
+
Error error;
-if (target->ReadPointerFromMemory(dyn_base + offset, false, error,
addr))
-return addr;
+if (symbol.d_tag == DT_MIPS_RLD_MAP)
+{
+// DT_MIPS_RLD_MAP tag stores an absolute address of the debug
pointer.
+Address addr;
+if (target->ReadPointerFromMemory(dyn_base + offset, false,
error, addr))
+return addr;
+}
+if (symbol.d_tag == DT_MIPS_RLD_MAP_REL)
+{
+// DT_MIPS_RLD_MAP_REL tag stores the offset to the debug
pointer, relative to the address of the tag.
+uint64_t rel_offset;
+rel_offset = target->ReadUnsignedIntegerFromMemory(dyn_base +
offset, false, GetAddressByteSize(), UINT64_MAX, error);
+if (error.Success() && rel_offset != UINT64_MAX)
+{
+Address addr;
+addr_t debug_ptr_address = dyn_base + (offset -
GetAddressByteSize()) + rel_offset;
+addr.SetOffset (debug_ptr_address);
+return addr;
+}
+}
}
}
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